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drm: bridge/dw_hdmi: clean up HDMI vs DVI mode handling
[linux-2.6-block.git] / drivers / gpu / drm / bridge / dw_hdmi.c
CommitLineData
9aaf880e
FE		 1/*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
b21f4b65 9 * Designware High-Definition Multimedia Interface (HDMI) driver
9aaf880e
FE		 10 *
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
12 */
b21f4b65 13#include <linux/module.h>
9aaf880e
FE		 14#include <linux/irq.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
5a819ed6 18#include <linux/hdmi.h>
6bcf4953 19#include <linux/mutex.h>
9aaf880e 20#include <linux/of_device.h>
b90120a9 21#include <linux/spinlock.h>
9aaf880e 22
3d1b35a3 23#include <drm/drm_of.h>
9aaf880e
FE		 24#include <drm/drmP.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_edid.h>
27#include <drm/drm_encoder_slave.h>
b21f4b65 28#include <drm/bridge/dw_hdmi.h>
9aaf880e 29
b21f4b65 30#include "dw_hdmi.h"
9aaf880e
FE		 31
32#define HDMI_EDID_LEN 512
33
34#define RGB 0
35#define YCBCR444 1
36#define YCBCR422_16BITS 2
37#define YCBCR422_8BITS 3
38#define XVYCC444 4
39
40enum hdmi_datamap {
41 RGB444_8B = 0x01,
42 RGB444_10B = 0x03,
43 RGB444_12B = 0x05,
44 RGB444_16B = 0x07,
45 YCbCr444_8B = 0x09,
46 YCbCr444_10B = 0x0B,
47 YCbCr444_12B = 0x0D,
48 YCbCr444_16B = 0x0F,
49 YCbCr422_8B = 0x16,
50 YCbCr422_10B = 0x14,
51 YCbCr422_12B = 0x12,
52};
53
9aaf880e
FE		 54static const u16 csc_coeff_default[3][4] = {
55 { 0x2000, 0x0000, 0x0000, 0x0000 },
56 { 0x0000, 0x2000, 0x0000, 0x0000 },
57 { 0x0000, 0x0000, 0x2000, 0x0000 }
58};
59
60static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
61 { 0x2000, 0x6926, 0x74fd, 0x010e },
62 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
63 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
64};
65
66static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
67 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
68 { 0x2000, 0x3264, 0x0000, 0x7e6d },
69 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
70};
71
72static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
73 { 0x2591, 0x1322, 0x074b, 0x0000 },
74 { 0x6535, 0x2000, 0x7acc, 0x0200 },
75 { 0x6acd, 0x7534, 0x2000, 0x0200 }
76};
77
78static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
79 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
80 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
81 { 0x6756, 0x78ab, 0x2000, 0x0200 }
82};
83
84struct hdmi_vmode {
9aaf880e
FE		 85 bool mdataenablepolarity;
86
87 unsigned int mpixelclock;
88 unsigned int mpixelrepetitioninput;
89 unsigned int mpixelrepetitionoutput;
90};
91
92struct hdmi_data_info {
93 unsigned int enc_in_format;
94 unsigned int enc_out_format;
95 unsigned int enc_color_depth;
96 unsigned int colorimetry;
97 unsigned int pix_repet_factor;
98 unsigned int hdcp_enable;
99 struct hdmi_vmode video_mode;
100};
101
b21f4b65 102struct dw_hdmi {
9aaf880e 103 struct drm_connector connector;
3d1b35a3
AY		 104 struct drm_encoder *encoder;
105 struct drm_bridge *bridge;
9aaf880e 106
b21f4b65 107 enum dw_hdmi_devtype dev_type;
9aaf880e
FE		 108 struct device *dev;
109 struct clk *isfr_clk;
110 struct clk *iahb_clk;
111
112 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 113 const struct dw_hdmi_plat_data *plat_data;
114
9aaf880e
FE		 115 int vic;
116
117 u8 edid[HDMI_EDID_LEN];
118 bool cable_plugin;
119
120 bool phy_enabled;
121 struct drm_display_mode previous_mode;
122
9aaf880e
FE		 123 struct i2c_adapter *ddc;
124 void __iomem *regs;
05b1342f 125 bool sink_is_hdmi;
9aaf880e 126
b90120a9 127 spinlock_t audio_lock;
6bcf4953 128 struct mutex audio_mutex;
9aaf880e 129 unsigned int sample_rate;
b90120a9
RK		 130 unsigned int audio_cts;
131 unsigned int audio_n;
132 bool audio_enable;
9aaf880e 133 int ratio;
0cd9d142
AY		 134
135 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
136 u8 (*read)(struct dw_hdmi *hdmi, int offset);
9aaf880e
FE		 137};
138
0cd9d142
AY		 139static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
140{
141 writel(val, hdmi->regs + (offset << 2));
142}
143
144static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
145{
146 return readl(hdmi->regs + (offset << 2));
147}
148
149static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
9aaf880e
FE		 150{
151 writeb(val, hdmi->regs + offset);
152}
153
0cd9d142 154static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
9aaf880e
FE		 155{
156 return readb(hdmi->regs + offset);
157}
158
0cd9d142
AY		 159static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
160{
161 hdmi->write(hdmi, val, offset);
162}
163
164static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
165{
166 return hdmi->read(hdmi, offset);
167}
168
b21f4b65 169static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615
RK		 170{
171 u8 val = hdmi_readb(hdmi, reg) & ~mask;
b44ab1b0 172
812bc615
RK		 173 val |= data & mask;
174 hdmi_writeb(hdmi, val, reg);
175}
176
b21f4b65 177static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 178 u8 shift, u8 mask)
9aaf880e 179{
812bc615 180 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 181}
182
351e1354
RK		 183static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
184 unsigned int n)
9aaf880e 185{
622494a3
RK		 186 /* Must be set/cleared first */
187 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 188
189 /* nshift factor = 0 */
812bc615 190 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e 191
9aaf880e
FE		 192 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
193 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
622494a3
RK		 194 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
195 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
196
197 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
198 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
199 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
9aaf880e
FE		 200}
201
202static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
203 unsigned int ratio)
204{
205 unsigned int n = (128 * freq) / 1000;
206
207 switch (freq) {
208 case 32000:
209 if (pixel_clk == 25170000)
210 n = (ratio == 150) ? 9152 : 4576;
211 else if (pixel_clk == 27020000)
212 n = (ratio == 150) ? 8192 : 4096;
213 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
214 n = 11648;
215 else
216 n = 4096;
217 break;
218
219 case 44100:
220 if (pixel_clk == 25170000)
221 n = 7007;
222 else if (pixel_clk == 74170000)
223 n = 17836;
224 else if (pixel_clk == 148350000)
225 n = (ratio == 150) ? 17836 : 8918;
226 else
227 n = 6272;
228 break;
229
230 case 48000:
231 if (pixel_clk == 25170000)
232 n = (ratio == 150) ? 9152 : 6864;
233 else if (pixel_clk == 27020000)
234 n = (ratio == 150) ? 8192 : 6144;
235 else if (pixel_clk == 74170000)
236 n = 11648;
237 else if (pixel_clk == 148350000)
238 n = (ratio == 150) ? 11648 : 5824;
239 else
240 n = 6144;
241 break;
242
243 case 88200:
244 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
245 break;
246
247 case 96000:
248 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
249 break;
250
251 case 176400:
252 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
253 break;
254
255 case 192000:
256 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
257 break;
258
259 default:
260 break;
261 }
262
263 return n;
264}
265
266static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
267 unsigned int ratio)
268{
269 unsigned int cts = 0;
270
271 pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
272 pixel_clk, ratio);
273
274 switch (freq) {
275 case 32000:
276 if (pixel_clk == 297000000) {
277 cts = 222750;
278 break;
279 }
280 case 48000:
281 case 96000:
282 case 192000:
283 switch (pixel_clk) {
284 case 25200000:
285 case 27000000:
286 case 54000000:
287 case 74250000:
288 case 148500000:
289 cts = pixel_clk / 1000;
290 break;
291 case 297000000:
292 cts = 247500;
293 break;
294 /*
295 * All other TMDS clocks are not supported by
296 * DWC_hdmi_tx. The TMDS clocks divided or
297 * multiplied by 1,001 coefficients are not
298 * supported.
299 */
300 default:
301 break;
302 }
303 break;
304 case 44100:
305 case 88200:
306 case 176400:
307 switch (pixel_clk) {
308 case 25200000:
309 cts = 28000;
310 break;
311 case 27000000:
312 cts = 30000;
313 break;
314 case 54000000:
315 cts = 60000;
316 break;
317 case 74250000:
318 cts = 82500;
319 break;
320 case 148500000:
321 cts = 165000;
322 break;
323 case 297000000:
324 cts = 247500;
325 break;
326 default:
327 break;
328 }
329 break;
330 default:
331 break;
332 }
333 if (ratio == 100)
334 return cts;
7557b6e1 335 return (cts * ratio) / 100;
9aaf880e
FE		 336}
337
b21f4b65 338static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
f879b38f 339 unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio)
9aaf880e 340{
f879b38f
RK		 341 unsigned int n, cts;
342
343 n = hdmi_compute_n(sample_rate, pixel_clk, ratio);
344 cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio);
345 if (!cts) {
346 dev_err(hdmi->dev,
347 "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
348 __func__, pixel_clk, sample_rate);
9aaf880e
FE		 349 }
350
f879b38f
RK		 351 dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n",
352 __func__, sample_rate, ratio, pixel_clk, n, cts);
9aaf880e 353
b90120a9
RK		 354 spin_lock_irq(&hdmi->audio_lock);
355 hdmi->audio_n = n;
356 hdmi->audio_cts = cts;
357 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
358 spin_unlock_irq(&hdmi->audio_lock);
9aaf880e
FE		 359}
360
b21f4b65 361static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 362{
6bcf4953 363 mutex_lock(&hdmi->audio_mutex);
f879b38f
RK		 364 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate,
365 hdmi->ratio);
6bcf4953 366 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 367}
368
b21f4b65 369static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 370{
6bcf4953 371 mutex_lock(&hdmi->audio_mutex);
f879b38f
RK		 372 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
373 hdmi->sample_rate, hdmi->ratio);
6bcf4953 374 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 375}
376
b5814fff
RK		 377void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
378{
379 mutex_lock(&hdmi->audio_mutex);
380 hdmi->sample_rate = rate;
381 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
382 hdmi->sample_rate, hdmi->ratio);
383 mutex_unlock(&hdmi->audio_mutex);
384}
385EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
386
b90120a9
RK		 387void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
388{
389 unsigned long flags;
390
391 spin_lock_irqsave(&hdmi->audio_lock, flags);
392 hdmi->audio_enable = true;
393 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
394 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
395}
396EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
397
398void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
399{
400 unsigned long flags;
401
402 spin_lock_irqsave(&hdmi->audio_lock, flags);
403 hdmi->audio_enable = false;
404 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
405 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
406}
407EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
408
9aaf880e
FE		 409/*
410 * this submodule is responsible for the video data synchronization.
411 * for example, for RGB 4:4:4 input, the data map is defined as
412 * pin{47~40} <==> R[7:0]
413 * pin{31~24} <==> G[7:0]
414 * pin{15~8} <==> B[7:0]
415 */
b21f4b65 416static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 417{
418 int color_format = 0;
419 u8 val;
420
421 if (hdmi->hdmi_data.enc_in_format == RGB) {
422 if (hdmi->hdmi_data.enc_color_depth == 8)
423 color_format = 0x01;
424 else if (hdmi->hdmi_data.enc_color_depth == 10)
425 color_format = 0x03;
426 else if (hdmi->hdmi_data.enc_color_depth == 12)
427 color_format = 0x05;
428 else if (hdmi->hdmi_data.enc_color_depth == 16)
429 color_format = 0x07;
430 else
431 return;
432 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
433 if (hdmi->hdmi_data.enc_color_depth == 8)
434 color_format = 0x09;
435 else if (hdmi->hdmi_data.enc_color_depth == 10)
436 color_format = 0x0B;
437 else if (hdmi->hdmi_data.enc_color_depth == 12)
438 color_format = 0x0D;
439 else if (hdmi->hdmi_data.enc_color_depth == 16)
440 color_format = 0x0F;
441 else
442 return;
443 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
444 if (hdmi->hdmi_data.enc_color_depth == 8)
445 color_format = 0x16;
446 else if (hdmi->hdmi_data.enc_color_depth == 10)
447 color_format = 0x14;
448 else if (hdmi->hdmi_data.enc_color_depth == 12)
449 color_format = 0x12;
450 else
451 return;
452 }
453
454 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
455 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
456 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
457 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
458
459 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
460 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
461 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
462 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
463 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
464 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
465 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
466 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
467 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
468 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
469 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
470}
471
b21f4b65 472static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 473{
ba92b225 474 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
9aaf880e
FE		 475}
476
b21f4b65 477static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 478{
ba92b225
FE		 479 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
480 return 0;
481 if (hdmi->hdmi_data.enc_in_format == RGB ||
482 hdmi->hdmi_data.enc_in_format == YCBCR444)
483 return 1;
484 return 0;
9aaf880e
FE		 485}
486
b21f4b65 487static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 488{
ba92b225
FE		 489 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
490 return 0;
491 if (hdmi->hdmi_data.enc_out_format == RGB ||
492 hdmi->hdmi_data.enc_out_format == YCBCR444)
493 return 1;
494 return 0;
9aaf880e
FE		 495}
496
b21f4b65 497static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 498{
499 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 500 unsigned i;
9aaf880e 501 u32 csc_scale = 1;
9aaf880e
FE		 502
503 if (is_color_space_conversion(hdmi)) {
504 if (hdmi->hdmi_data.enc_out_format == RGB) {
256a38b0
GK		 505 if (hdmi->hdmi_data.colorimetry ==
506 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 507 csc_coeff = &csc_coeff_rgb_out_eitu601;
508 else
509 csc_coeff = &csc_coeff_rgb_out_eitu709;
510 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
256a38b0
GK		 511 if (hdmi->hdmi_data.colorimetry ==
512 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 513 csc_coeff = &csc_coeff_rgb_in_eitu601;
514 else
515 csc_coeff = &csc_coeff_rgb_in_eitu709;
516 csc_scale = 0;
517 }
518 }
519
c082f9d7
RK		 520 /* The CSC registers are sequential, alternating MSB then LSB */
521 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
522 u16 coeff_a = (*csc_coeff)[0][i];
523 u16 coeff_b = (*csc_coeff)[1][i];
524 u16 coeff_c = (*csc_coeff)[2][i];
525
b5878339 526 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 527 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
528 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
529 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 530 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 531 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
532 }
9aaf880e 533
812bc615
RK		 534 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
535 HDMI_CSC_SCALE);
9aaf880e
FE		 536}
537
b21f4b65 538static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 539{
540 int color_depth = 0;
541 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
542 int decimation = 0;
9aaf880e
FE		 543
544 /* YCC422 interpolation to 444 mode */
545 if (is_color_space_interpolation(hdmi))
546 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
547 else if (is_color_space_decimation(hdmi))
548 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
549
550 if (hdmi->hdmi_data.enc_color_depth == 8)
551 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
552 else if (hdmi->hdmi_data.enc_color_depth == 10)
553 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
554 else if (hdmi->hdmi_data.enc_color_depth == 12)
555 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
556 else if (hdmi->hdmi_data.enc_color_depth == 16)
557 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
558 else
559 return;
560
561 /* Configure the CSC registers */
562 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 563 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
564 HDMI_CSC_SCALE);
9aaf880e 565
b21f4b65 566 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 567}
568
569/*
570 * HDMI video packetizer is used to packetize the data.
571 * for example, if input is YCC422 mode or repeater is used,
572 * data should be repacked this module can be bypassed.
573 */
b21f4b65 574static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 575{
576 unsigned int color_depth = 0;
577 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
578 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
579 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 580 u8 val, vp_conf;
9aaf880e 581
b5878339
AY		 582 if (hdmi_data->enc_out_format == RGB ||
583 hdmi_data->enc_out_format == YCBCR444) {
584 if (!hdmi_data->enc_color_depth) {
9aaf880e 585 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 586 } else if (hdmi_data->enc_color_depth == 8) {
9aaf880e
FE		 587 color_depth = 4;
588 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 589 } else if (hdmi_data->enc_color_depth == 10) {
9aaf880e 590 color_depth = 5;
b5878339 591 } else if (hdmi_data->enc_color_depth == 12) {
9aaf880e 592 color_depth = 6;
b5878339 593 } else if (hdmi_data->enc_color_depth == 16) {
9aaf880e 594 color_depth = 7;
b5878339 595 } else {
9aaf880e 596 return;
b5878339 597 }
9aaf880e
FE		 598 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
599 if (!hdmi_data->enc_color_depth ||
600 hdmi_data->enc_color_depth == 8)
601 remap_size = HDMI_VP_REMAP_YCC422_16bit;
602 else if (hdmi_data->enc_color_depth == 10)
603 remap_size = HDMI_VP_REMAP_YCC422_20bit;
604 else if (hdmi_data->enc_color_depth == 12)
605 remap_size = HDMI_VP_REMAP_YCC422_24bit;
606 else
607 return;
608 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 609 } else {
9aaf880e 610 return;
b5878339 611 }
9aaf880e
FE		 612
613 /* set the packetizer registers */
614 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
615 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
616 ((hdmi_data->pix_repet_factor <<
617 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
618 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
619 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
620
812bc615
RK		 621 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
622 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 623
624 /* Data from pixel repeater block */
625 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 626 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
627 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 628 } else { /* data from packetizer block */
bebdf664
RK		 629 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
630 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 631 }
632
bebdf664
RK		 633 hdmi_modb(hdmi, vp_conf,
634 HDMI_VP_CONF_PR_EN_MASK |
635 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
636
812bc615
RK		 637 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
638 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 639
640 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
641
642 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 643 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
644 HDMI_VP_CONF_PP_EN_ENABLE |
645 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 646 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 647 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
648 HDMI_VP_CONF_PP_EN_DISABLE |
649 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 650 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 651 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
652 HDMI_VP_CONF_PP_EN_DISABLE |
653 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 654 } else {
655 return;
656 }
657
bebdf664
RK		 658 hdmi_modb(hdmi, vp_conf,
659 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
660 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
661
812bc615
RK		 662 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
663 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
664 HDMI_VP_STUFF_PP_STUFFING_MASK |
665 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 666
812bc615
RK		 667 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
668 HDMI_VP_CONF);
9aaf880e
FE		 669}
670
b21f4b65 671static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 672 unsigned char bit)
9aaf880e 673{
812bc615
RK		 674 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
675 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 676}
677
b21f4b65 678static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
b5878339 679 unsigned char bit)
9aaf880e 680{
812bc615
RK		 681 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
682 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 683}
684
b21f4b65 685static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
b5878339 686 unsigned char bit)
9aaf880e 687{
812bc615
RK		 688 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
689 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 690}
691
b21f4b65 692static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
b5878339 693 unsigned char bit)
9aaf880e
FE		 694{
695 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
696}
697
b21f4b65 698static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
b5878339 699 unsigned char bit)
9aaf880e
FE		 700{
701 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
702}
703
b21f4b65 704static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 705{
a4d3b8b0
AY		 706 u32 val;
707
708 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 709 if (msec-- == 0)
710 return false;
0e6bcf3a 711 udelay(1000);
9aaf880e 712 }
a4d3b8b0
AY		 713 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
714
9aaf880e
FE		 715 return true;
716}
717
b21f4b65 718static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 719 unsigned char addr)
9aaf880e
FE		 720{
721 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
722 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
723 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 724 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 725 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 726 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 727 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 728 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 729 hdmi_phy_wait_i2c_done(hdmi, 1000);
730}
731
b21f4b65 732static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 733 unsigned char addr)
9aaf880e
FE		 734{
735 __hdmi_phy_i2c_write(hdmi, data, addr);
736 return 0;
737}
738
b21f4b65 739static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 740{
741 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
742 HDMI_PHY_CONF0_PDZ_OFFSET,
743 HDMI_PHY_CONF0_PDZ_MASK);
744}
745
b21f4b65 746static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 747{
748 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
749 HDMI_PHY_CONF0_ENTMDS_OFFSET,
750 HDMI_PHY_CONF0_ENTMDS_MASK);
751}
752
d346c14e
AY		 753static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
754{
755 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
756 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
757 HDMI_PHY_CONF0_SPARECTRL_MASK);
758}
759
b21f4b65 760static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 761{
762 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
763 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
764 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
765}
766
b21f4b65 767static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 768{
769 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
770 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
771 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
772}
773
b21f4b65 774static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 775{
776 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
777 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
778 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
779}
780
b21f4b65 781static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 782{
783 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
784 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
785 HDMI_PHY_CONF0_SELDIPIF_MASK);
786}
787
b21f4b65 788static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
9aaf880e
FE		 789 unsigned char res, int cscon)
790{
39cc1535 791 unsigned res_idx;
9aaf880e 792 u8 val, msec;
39cc1535
RK		 793 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
794 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
795 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
796 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
9aaf880e 797
9aaf880e
FE		 798 if (prep)
799 return -EINVAL;
3e46f152
RK		 800
801 switch (res) {
802 case 0: /* color resolution 0 is 8 bit colour depth */
803 case 8:
b21f4b65 804 res_idx = DW_HDMI_RES_8;
3e46f152
RK		 805 break;
806 case 10:
b21f4b65 807 res_idx = DW_HDMI_RES_10;
3e46f152
RK		 808 break;
809 case 12:
b21f4b65 810 res_idx = DW_HDMI_RES_12;
3e46f152
RK		 811 break;
812 default:
9aaf880e 813 return -EINVAL;
3e46f152 814 }
9aaf880e 815
39cc1535
RK		 816 /* PLL/MPLL Cfg - always match on final entry */
817 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
818 if (hdmi->hdmi_data.video_mode.mpixelclock <=
819 mpll_config->mpixelclock)
820 break;
821
822 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
823 if (hdmi->hdmi_data.video_mode.mpixelclock <=
824 curr_ctrl->mpixelclock)
825 break;
826
827 for (; phy_config->mpixelclock != ~0UL; phy_config++)
828 if (hdmi->hdmi_data.video_mode.mpixelclock <=
829 phy_config->mpixelclock)
830 break;
831
832 if (mpll_config->mpixelclock == ~0UL ||
833 curr_ctrl->mpixelclock == ~0UL ||
834 phy_config->mpixelclock == ~0UL) {
835 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
836 hdmi->hdmi_data.video_mode.mpixelclock);
837 return -EINVAL;
838 }
839
9aaf880e
FE		 840 /* Enable csc path */
841 if (cscon)
842 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
843 else
844 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
845
846 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
847
848 /* gen2 tx power off */
b21f4b65 849 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
9aaf880e
FE		 850
851 /* gen2 pddq */
b21f4b65 852 dw_hdmi_phy_gen2_pddq(hdmi, 1);
9aaf880e
FE		 853
854 /* PHY reset */
855 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
856 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
857
858 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
859
860 hdmi_phy_test_clear(hdmi, 1);
861 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
b5878339 862 HDMI_PHY_I2CM_SLAVE_ADDR);
9aaf880e
FE		 863 hdmi_phy_test_clear(hdmi, 0);
864
39cc1535
RK		 865 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
866 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
9aaf880e 867
3e46f152 868 /* CURRCTRL */
39cc1535 869 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
3e46f152 870
9aaf880e
FE		 871 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
872 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
aaa757a0 873
39cc1535
RK		 874 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
875 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
876 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
034705a4 877
9aaf880e
FE		 878 /* REMOVE CLK TERM */
879 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
880
b21f4b65 881 dw_hdmi_phy_enable_power(hdmi, 1);
9aaf880e
FE		 882
883 /* toggle TMDS enable */
b21f4b65
AY		 884 dw_hdmi_phy_enable_tmds(hdmi, 0);
885 dw_hdmi_phy_enable_tmds(hdmi, 1);
9aaf880e
FE		 886
887 /* gen2 tx power on */
b21f4b65
AY		 888 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
889 dw_hdmi_phy_gen2_pddq(hdmi, 0);
9aaf880e 890
12b9f204
AY		 891 if (hdmi->dev_type == RK3288_HDMI)
892 dw_hdmi_phy_enable_spare(hdmi, 1);
893
9aaf880e
FE		 894 /*Wait for PHY PLL lock */
895 msec = 5;
896 do {
897 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
898 if (!val)
899 break;
900
901 if (msec == 0) {
902 dev_err(hdmi->dev, "PHY PLL not locked\n");
903 return -ETIMEDOUT;
904 }
905
906 udelay(1000);
907 msec--;
908 } while (1);
909
910 return 0;
911}
912
b21f4b65 913static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
9aaf880e
FE		 914{
915 int i, ret;
05b1342f 916 bool cscon;
9aaf880e
FE		 917
918 /*check csc whether needed activated in HDMI mode */
05b1342f 919 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
9aaf880e
FE		 920
921 /* HDMI Phy spec says to do the phy initialization sequence twice */
922 for (i = 0; i < 2; i++) {
b21f4b65
AY		 923 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
924 dw_hdmi_phy_sel_interface_control(hdmi, 0);
925 dw_hdmi_phy_enable_tmds(hdmi, 0);
926 dw_hdmi_phy_enable_power(hdmi, 0);
9aaf880e
FE		 927
928 /* Enable CSC */
929 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
930 if (ret)
931 return ret;
932 }
933
934 hdmi->phy_enabled = true;
935 return 0;
936}
937
b21f4b65 938static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 939{
812bc615 940 u8 de;
9aaf880e
FE		 941
942 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
943 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
944 else
945 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
946
947 /* disable rx detect */
812bc615
RK		 948 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
949 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 950
812bc615 951 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 952
812bc615
RK		 953 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
954 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 955}
956
d4ac4cb6 957static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e 958{
d4ac4cb6
RK		 959 struct hdmi_avi_infoframe frame;
960 u8 val;
9aaf880e 961
d4ac4cb6
RK		 962 /* Initialise info frame from DRM mode */
963 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
9aaf880e 964
9aaf880e 965 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
d4ac4cb6 966 frame.colorspace = HDMI_COLORSPACE_YUV444;
9aaf880e 967 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
d4ac4cb6 968 frame.colorspace = HDMI_COLORSPACE_YUV422;
9aaf880e 969 else
d4ac4cb6 970 frame.colorspace = HDMI_COLORSPACE_RGB;
9aaf880e
FE		 971
972 /* Set up colorimetry */
973 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
d4ac4cb6 974 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
5a819ed6 975 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
d4ac4cb6
RK		 976 frame.extended_colorimetry =
977 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
5a819ed6 978 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
d4ac4cb6
RK		 979 frame.extended_colorimetry =
980 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
9aaf880e 981 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
d083c312 982 frame.colorimetry = hdmi->hdmi_data.colorimetry;
d4ac4cb6 983 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
9aaf880e 984 } else { /* Carries no data */
d4ac4cb6
RK		 985 frame.colorimetry = HDMI_COLORIMETRY_NONE;
986 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
9aaf880e
FE		 987 }
988
d4ac4cb6
RK		 989 frame.scan_mode = HDMI_SCAN_MODE_NONE;
990
991 /*
992 * The Designware IP uses a different byte format from standard
993 * AVI info frames, though generally the bits are in the correct
994 * bytes.
995 */
996
997 /*
998 * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
999 * active aspect present in bit 6 rather than 4.
1000 */
1001 val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1002 if (frame.active_aspect & 15)
1003 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1004 if (frame.top_bar || frame.bottom_bar)
1005 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1006 if (frame.left_bar || frame.right_bar)
1007 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1008 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1009
1010 /* AVI data byte 2 differences: none */
1011 val = ((frame.colorimetry & 0x3) << 6) |
1012 ((frame.picture_aspect & 0x3) << 4) |
1013 (frame.active_aspect & 0xf);
9aaf880e
FE		 1014 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1015
d4ac4cb6
RK		 1016 /* AVI data byte 3 differences: none */
1017 val = ((frame.extended_colorimetry & 0x7) << 4) |
1018 ((frame.quantization_range & 0x3) << 2) |
1019 (frame.nups & 0x3);
1020 if (frame.itc)
1021 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
9aaf880e
FE		 1022 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1023
d4ac4cb6
RK		 1024 /* AVI data byte 4 differences: none */
1025 val = frame.video_code & 0x7f;
1026 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
9aaf880e
FE		 1027
1028 /* AVI Data Byte 5- set up input and output pixel repetition */
1029 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1030 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1031 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1032 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1033 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1034 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1035 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1036
d4ac4cb6
RK		 1037 /*
1038 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1039 * ycc range in bits 2,3 rather than 6,7
1040 */
1041 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1042 (frame.content_type & 0x3);
9aaf880e
FE		 1043 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1044
1045 /* AVI Data Bytes 6-13 */
d4ac4cb6
RK		 1046 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1047 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1048 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1049 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1050 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1051 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1052 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1053 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
9aaf880e
FE		 1054}
1055
b21f4b65 1056static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1057 const struct drm_display_mode *mode)
1058{
1059 u8 inv_val;
1060 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1061 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1062
9aaf880e
FE		 1063 vmode->mpixelclock = mode->clock * 1000;
1064
1065 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1066
1067 /* Set up HDMI_FC_INVIDCONF */
1068 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1069 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1070 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1071
b91eee8c 1072 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
9aaf880e 1073 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1074 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e 1075
b91eee8c 1076 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
9aaf880e 1077 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1078 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e
FE		 1079
1080 inv_val |= (vmode->mdataenablepolarity ?
1081 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1082 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1083
1084 if (hdmi->vic == 39)
1085 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1086 else
b91eee8c 1087 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1088 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
b91eee8c 1089 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
9aaf880e 1090
b91eee8c 1091 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1092 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
b91eee8c 1093 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
9aaf880e 1094
05b1342f
RK		 1095 inv_val |= hdmi->sink_is_hdmi ?
1096 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1097 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
9aaf880e
FE		 1098
1099 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1100
1101 /* Set up horizontal active pixel width */
1102 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1103 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1104
1105 /* Set up vertical active lines */
1106 hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1107 hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1108
1109 /* Set up horizontal blanking pixel region width */
1110 hblank = mode->htotal - mode->hdisplay;
1111 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1112 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1113
1114 /* Set up vertical blanking pixel region width */
1115 vblank = mode->vtotal - mode->vdisplay;
1116 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1117
1118 /* Set up HSYNC active edge delay width (in pixel clks) */
1119 h_de_hs = mode->hsync_start - mode->hdisplay;
1120 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1121 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1122
1123 /* Set up VSYNC active edge delay (in lines) */
1124 v_de_vs = mode->vsync_start - mode->vdisplay;
1125 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1126
1127 /* Set up HSYNC active pulse width (in pixel clks) */
1128 hsync_len = mode->hsync_end - mode->hsync_start;
1129 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1130 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1131
1132 /* Set up VSYNC active edge delay (in lines) */
1133 vsync_len = mode->vsync_end - mode->vsync_start;
1134 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1135}
1136
b21f4b65 1137static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
9aaf880e
FE		 1138{
1139 if (!hdmi->phy_enabled)
1140 return;
1141
b21f4b65
AY		 1142 dw_hdmi_phy_enable_tmds(hdmi, 0);
1143 dw_hdmi_phy_enable_power(hdmi, 0);
9aaf880e
FE		 1144
1145 hdmi->phy_enabled = false;
1146}
1147
1148/* HDMI Initialization Step B.4 */
b21f4b65 1149static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e
FE		 1150{
1151 u8 clkdis;
1152
1153 /* control period minimum duration */
1154 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1155 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1156 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1157
1158 /* Set to fill TMDS data channels */
1159 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1160 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1161 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1162
1163 /* Enable pixel clock and tmds data path */
1164 clkdis = 0x7F;
1165 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1166 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1167
1168 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1169 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1170
1171 /* Enable csc path */
1172 if (is_color_space_conversion(hdmi)) {
1173 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1174 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1175 }
1176}
1177
b21f4b65 1178static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
9aaf880e 1179{
812bc615 1180 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
9aaf880e
FE		 1181}
1182
1183/* Workaround to clear the overflow condition */
b21f4b65 1184static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e
FE		 1185{
1186 int count;
1187 u8 val;
1188
1189 /* TMDS software reset */
1190 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1191
1192 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1193 if (hdmi->dev_type == IMX6DL_HDMI) {
1194 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1195 return;
1196 }
1197
1198 for (count = 0; count < 4; count++)
1199 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1200}
1201
b21f4b65 1202static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1203{
1204 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1205 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1206}
1207
b21f4b65 1208static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1209{
1210 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1211 HDMI_IH_MUTE_FC_STAT2);
1212}
1213
b21f4b65 1214static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1215{
1216 int ret;
1217
1218 hdmi_disable_overflow_interrupts(hdmi);
1219
1220 hdmi->vic = drm_match_cea_mode(mode);
1221
1222 if (!hdmi->vic) {
1223 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
9aaf880e
FE		 1224 } else {
1225 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
9aaf880e
FE		 1226 }
1227
1228 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 1229 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1230 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1231 (hdmi->vic == 17) || (hdmi->vic == 18))
5a819ed6 1232 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
9aaf880e 1233 else
5a819ed6 1234 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
9aaf880e 1235
d10ca826 1236 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
9aaf880e
FE		 1237 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1238
1239 /* TODO: Get input format from IPU (via FB driver interface) */
1240 hdmi->hdmi_data.enc_in_format = RGB;
1241
1242 hdmi->hdmi_data.enc_out_format = RGB;
1243
1244 hdmi->hdmi_data.enc_color_depth = 8;
1245 hdmi->hdmi_data.pix_repet_factor = 0;
1246 hdmi->hdmi_data.hdcp_enable = 0;
1247 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1248
1249 /* HDMI Initialization Step B.1 */
1250 hdmi_av_composer(hdmi, mode);
1251
1252 /* HDMI Initializateion Step B.2 */
b21f4b65 1253 ret = dw_hdmi_phy_init(hdmi);
9aaf880e
FE		 1254 if (ret)
1255 return ret;
1256
1257 /* HDMI Initialization Step B.3 */
b21f4b65 1258 dw_hdmi_enable_video_path(hdmi);
9aaf880e
FE		 1259
1260 /* not for DVI mode */
05b1342f
RK		 1261 if (hdmi->sink_is_hdmi) {
1262 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
9aaf880e
FE		 1263
1264 /* HDMI Initialization Step E - Configure audio */
1265 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1266 hdmi_enable_audio_clk(hdmi);
1267
1268 /* HDMI Initialization Step F - Configure AVI InfoFrame */
d4ac4cb6 1269 hdmi_config_AVI(hdmi, mode);
05b1342f
RK		 1270 } else {
1271 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
9aaf880e
FE		 1272 }
1273
1274 hdmi_video_packetize(hdmi);
1275 hdmi_video_csc(hdmi);
1276 hdmi_video_sample(hdmi);
1277 hdmi_tx_hdcp_config(hdmi);
1278
b21f4b65 1279 dw_hdmi_clear_overflow(hdmi);
05b1342f 1280 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
9aaf880e
FE		 1281 hdmi_enable_overflow_interrupts(hdmi);
1282
1283 return 0;
1284}
1285
1286/* Wait until we are registered to enable interrupts */
b21f4b65 1287static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
9aaf880e
FE		 1288{
1289 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1290 HDMI_PHY_I2CM_INT_ADDR);
1291
1292 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1293 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1294 HDMI_PHY_I2CM_CTLINT_ADDR);
1295
1296 /* enable cable hot plug irq */
1297 hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1298
1299 /* Clear Hotplug interrupts */
1300 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1301
9aaf880e
FE		 1302 return 0;
1303}
1304
b21f4b65 1305static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 1306{
1307 u8 ih_mute;
1308
1309 /*
1310 * Boot up defaults are:
1311 * HDMI_IH_MUTE = 0x03 (disabled)
1312 * HDMI_IH_MUTE_* = 0x00 (enabled)
1313 *
1314 * Disable top level interrupt bits in HDMI block
1315 */
1316 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1317 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1318 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1319
1320 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1321
1322 /* by default mask all interrupts */
1323 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1324 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1325 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1326 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1327 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1328 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1329 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1330 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1331 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1332 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1333 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1334 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1335 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1336 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1337 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1338
1339 /* Disable interrupts in the IH_MUTE_* registers */
1340 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1341 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1342 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1343 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1344 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1345 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1346 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1347 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1348 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1349 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1350
1351 /* Enable top level interrupt bits in HDMI block */
1352 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1353 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1354 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1355}
1356
b21f4b65 1357static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 1358{
b21f4b65 1359 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 1360}
1361
b21f4b65 1362static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 1363{
b21f4b65 1364 dw_hdmi_phy_disable(hdmi);
9aaf880e
FE		 1365}
1366
b21f4b65 1367static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
eb10d635
SL		 1368 struct drm_display_mode *orig_mode,
1369 struct drm_display_mode *mode)
3d1b35a3 1370{
b21f4b65 1371 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1372
b21f4b65 1373 dw_hdmi_setup(hdmi, mode);
3d1b35a3
AY		 1374
1375 /* Store the display mode for plugin/DKMS poweron events */
1376 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1377}
1378
b21f4b65
AY		 1379static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1380 const struct drm_display_mode *mode,
1381 struct drm_display_mode *adjusted_mode)
3d1b35a3
AY		 1382{
1383 return true;
1384}
1385
b21f4b65 1386static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
3d1b35a3 1387{
b21f4b65 1388 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1389
b21f4b65 1390 dw_hdmi_poweroff(hdmi);
3d1b35a3
AY		 1391}
1392
b21f4b65 1393static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
3d1b35a3 1394{
b21f4b65 1395 struct dw_hdmi *hdmi = bridge->driver_private;
3d1b35a3 1396
b21f4b65 1397 dw_hdmi_poweron(hdmi);
3d1b35a3
AY		 1398}
1399
b21f4b65 1400static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
3d1b35a3
AY		 1401{
1402 /* do nothing */
1403}
1404
b21f4b65
AY		 1405static enum drm_connector_status
1406dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 1407{
b21f4b65 1408 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 1409 connector);
98dbeada
RK		 1410
1411 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1412 connector_status_connected : connector_status_disconnected;
9aaf880e
FE		 1413}
1414
b21f4b65 1415static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 1416{
b21f4b65 1417 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1418 connector);
1419 struct edid *edid;
1420 int ret;
1421
1422 if (!hdmi->ddc)
1423 return 0;
1424
1425 edid = drm_get_edid(connector, hdmi->ddc);
1426 if (edid) {
1427 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1428 edid->width_cm, edid->height_cm);
1429
05b1342f 1430 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
9aaf880e
FE		 1431 drm_mode_connector_update_edid_property(connector, edid);
1432 ret = drm_add_edid_modes(connector, edid);
1433 kfree(edid);
1434 } else {
1435 dev_dbg(hdmi->dev, "failed to get edid\n");
1436 }
1437
1438 return 0;
1439}
1440
632d035b
AY		 1441static enum drm_mode_status
1442dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1443 struct drm_display_mode *mode)
1444{
1445 struct dw_hdmi *hdmi = container_of(connector,
1446 struct dw_hdmi, connector);
1447 enum drm_mode_status mode_status = MODE_OK;
1448
8add4190
RK		 1449 /* We don't support double-clocked modes */
1450 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1451 return MODE_BAD;
1452
632d035b
AY		 1453 if (hdmi->plat_data->mode_valid)
1454 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1455
1456 return mode_status;
1457}
1458
b21f4b65 1459static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
9aaf880e
FE		 1460 *connector)
1461{
b21f4b65 1462 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1463 connector);
1464
3d1b35a3 1465 return hdmi->encoder;
9aaf880e
FE		 1466}
1467
b21f4b65 1468static void dw_hdmi_connector_destroy(struct drm_connector *connector)
9aaf880e 1469{
3d1b35a3
AY		 1470 drm_connector_unregister(connector);
1471 drm_connector_cleanup(connector);
9aaf880e
FE		 1472}
1473
b21f4b65 1474static struct drm_connector_funcs dw_hdmi_connector_funcs = {
9aaf880e
FE		 1475 .dpms = drm_helper_connector_dpms,
1476 .fill_modes = drm_helper_probe_single_connector_modes,
b21f4b65
AY		 1477 .detect = dw_hdmi_connector_detect,
1478 .destroy = dw_hdmi_connector_destroy,
9aaf880e
FE		 1479};
1480
b21f4b65
AY		 1481static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1482 .get_modes = dw_hdmi_connector_get_modes,
632d035b 1483 .mode_valid = dw_hdmi_connector_mode_valid,
b21f4b65 1484 .best_encoder = dw_hdmi_connector_best_encoder,
9aaf880e
FE		 1485};
1486
b21f4b65
AY		 1487struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1488 .enable = dw_hdmi_bridge_enable,
1489 .disable = dw_hdmi_bridge_disable,
1490 .pre_enable = dw_hdmi_bridge_nop,
1491 .post_disable = dw_hdmi_bridge_nop,
1492 .mode_set = dw_hdmi_bridge_mode_set,
1493 .mode_fixup = dw_hdmi_bridge_mode_fixup,
3d1b35a3
AY		 1494};
1495
b21f4b65 1496static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 1497{
b21f4b65 1498 struct dw_hdmi *hdmi = dev_id;
d94905e0
RK		 1499 u8 intr_stat;
1500
1501 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1502 if (intr_stat)
1503 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1504
1505 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1506}
1507
b21f4b65 1508static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 1509{
b21f4b65 1510 struct dw_hdmi *hdmi = dev_id;
9aaf880e
FE		 1511 u8 intr_stat;
1512 u8 phy_int_pol;
9aaf880e
FE		 1513
1514 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1515
1516 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1517
1518 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1519 if (phy_int_pol & HDMI_PHY_HPD) {
1520 dev_dbg(hdmi->dev, "EVENT=plugin\n");
1521
812bc615 1522 hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
9aaf880e 1523
b21f4b65 1524 dw_hdmi_poweron(hdmi);
9aaf880e
FE		 1525 } else {
1526 dev_dbg(hdmi->dev, "EVENT=plugout\n");
1527
256a38b0 1528 hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
b5878339 1529 HDMI_PHY_POL0);
9aaf880e 1530
b21f4b65 1531 dw_hdmi_poweroff(hdmi);
9aaf880e 1532 }
4b9bcaa7 1533 drm_helper_hpd_irq_event(hdmi->bridge->dev);
9aaf880e
FE		 1534 }
1535
1536 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
d94905e0 1537 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 1538
1539 return IRQ_HANDLED;
1540}
1541
b21f4b65 1542static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
9aaf880e 1543{
3d1b35a3
AY		 1544 struct drm_encoder *encoder = hdmi->encoder;
1545 struct drm_bridge *bridge;
9aaf880e
FE		 1546 int ret;
1547
3d1b35a3
AY		 1548 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1549 if (!bridge) {
1550 DRM_ERROR("Failed to allocate drm bridge\n");
1551 return -ENOMEM;
1552 }
9aaf880e 1553
3d1b35a3
AY		 1554 hdmi->bridge = bridge;
1555 bridge->driver_private = hdmi;
b5217bf4
FE		 1556 bridge->funcs = &dw_hdmi_bridge_funcs;
1557 ret = drm_bridge_attach(drm, bridge);
3d1b35a3
AY		 1558 if (ret) {
1559 DRM_ERROR("Failed to initialize bridge with drm\n");
1560 return -EINVAL;
1561 }
9aaf880e 1562
3d1b35a3
AY		 1563 encoder->bridge = bridge;
1564 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
9aaf880e
FE		 1565
1566 drm_connector_helper_add(&hdmi->connector,
b21f4b65
AY		 1567 &dw_hdmi_connector_helper_funcs);
1568 drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1b3f7675 1569 DRM_MODE_CONNECTOR_HDMIA);
9aaf880e 1570
3d1b35a3 1571 hdmi->connector.encoder = encoder;
9aaf880e 1572
3d1b35a3 1573 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
9aaf880e
FE		 1574
1575 return 0;
1576}
1577
b21f4b65 1578int dw_hdmi_bind(struct device *dev, struct device *master,
3d1b35a3
AY		 1579 void *data, struct drm_encoder *encoder,
1580 struct resource *iores, int irq,
1581 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 1582{
1b3f7675 1583 struct drm_device *drm = data;
17b5001b 1584 struct device_node *np = dev->of_node;
9aaf880e 1585 struct device_node *ddc_node;
b21f4b65 1586 struct dw_hdmi *hdmi;
3d1b35a3 1587 int ret;
0cd9d142 1588 u32 val = 1;
9aaf880e 1589
17b5001b 1590 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e
FE		 1591 if (!hdmi)
1592 return -ENOMEM;
1593
3d1b35a3 1594 hdmi->plat_data = plat_data;
17b5001b 1595 hdmi->dev = dev;
3d1b35a3 1596 hdmi->dev_type = plat_data->dev_type;
40678388
RK		 1597 hdmi->sample_rate = 48000;
1598 hdmi->ratio = 100;
3d1b35a3 1599 hdmi->encoder = encoder;
9aaf880e 1600
6bcf4953 1601 mutex_init(&hdmi->audio_mutex);
b90120a9 1602 spin_lock_init(&hdmi->audio_lock);
6bcf4953 1603
0cd9d142
AY		 1604 of_property_read_u32(np, "reg-io-width", &val);
1605
1606 switch (val) {
1607 case 4:
1608 hdmi->write = dw_hdmi_writel;
1609 hdmi->read = dw_hdmi_readl;
1610 break;
1611 case 1:
1612 hdmi->write = dw_hdmi_writeb;
1613 hdmi->read = dw_hdmi_readb;
1614 break;
1615 default:
1616 dev_err(dev, "reg-io-width must be 1 or 4\n");
1617 return -EINVAL;
1618 }
1619
b5d45901 1620 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e
FE		 1621 if (ddc_node) {
1622 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 1623 of_node_put(ddc_node);
1624 if (!hdmi->ddc) {
9aaf880e 1625 dev_dbg(hdmi->dev, "failed to read ddc node\n");
c2c38488
AY		 1626 return -EPROBE_DEFER;
1627 }
9aaf880e 1628
9aaf880e
FE		 1629 } else {
1630 dev_dbg(hdmi->dev, "no ddc property found\n");
1631 }
1632
17b5001b 1633 hdmi->regs = devm_ioremap_resource(dev, iores);
9aaf880e
FE		 1634 if (IS_ERR(hdmi->regs))
1635 return PTR_ERR(hdmi->regs);
1636
9aaf880e
FE		 1637 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1638 if (IS_ERR(hdmi->isfr_clk)) {
1639 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 1640 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9aaf880e
FE		 1641 return ret;
1642 }
1643
1644 ret = clk_prepare_enable(hdmi->isfr_clk);
1645 if (ret) {
b5878339 1646 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9aaf880e
FE		 1647 return ret;
1648 }
1649
1650 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1651 if (IS_ERR(hdmi->iahb_clk)) {
1652 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 1653 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 1654 goto err_isfr;
1655 }
1656
1657 ret = clk_prepare_enable(hdmi->iahb_clk);
1658 if (ret) {
b5878339 1659 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 1660 goto err_isfr;
1661 }
1662
1663 /* Product and revision IDs */
17b5001b 1664 dev_info(dev,
b5878339
AY		 1665 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1666 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1667 hdmi_readb(hdmi, HDMI_REVISION_ID),
1668 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1669 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
9aaf880e
FE		 1670
1671 initialize_hdmi_ih_mutes(hdmi);
1672
639a202c
PZ		 1673 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1674 dw_hdmi_irq, IRQF_SHARED,
1675 dev_name(dev), hdmi);
1676 if (ret)
b33ef619 1677 goto err_iahb;
639a202c 1678
9aaf880e
FE		 1679 /*
1680 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1681 * N and cts values before enabling phy
1682 */
1683 hdmi_init_clk_regenerator(hdmi);
1684
1685 /*
1686 * Configure registers related to HDMI interrupt
1687 * generation before registering IRQ.
1688 */
1689 hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1690
1691 /* Clear Hotplug interrupts */
1692 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1693
b21f4b65 1694 ret = dw_hdmi_fb_registered(hdmi);
9aaf880e
FE		 1695 if (ret)
1696 goto err_iahb;
1697
b21f4b65 1698 ret = dw_hdmi_register(drm, hdmi);
9aaf880e
FE		 1699 if (ret)
1700 goto err_iahb;
1701
d94905e0
RK		 1702 /* Unmute interrupts */
1703 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
9aaf880e 1704
17b5001b 1705 dev_set_drvdata(dev, hdmi);
9aaf880e
FE		 1706
1707 return 0;
1708
1709err_iahb:
1710 clk_disable_unprepare(hdmi->iahb_clk);
1711err_isfr:
1712 clk_disable_unprepare(hdmi->isfr_clk);
1713
1714 return ret;
1715}
b21f4b65 1716EXPORT_SYMBOL_GPL(dw_hdmi_bind);
9aaf880e 1717
b21f4b65 1718void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
9aaf880e 1719{
b21f4b65 1720 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
9aaf880e 1721
d94905e0
RK		 1722 /* Disable all interrupts */
1723 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1724
1b3f7675 1725 hdmi->connector.funcs->destroy(&hdmi->connector);
3d1b35a3 1726 hdmi->encoder->funcs->destroy(hdmi->encoder);
9aaf880e
FE		 1727
1728 clk_disable_unprepare(hdmi->iahb_clk);
1729 clk_disable_unprepare(hdmi->isfr_clk);
1730 i2c_put_adapter(hdmi->ddc);
17b5001b 1731}
b21f4b65 1732EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e
FE		 1733
1734MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 1735MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1736MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
b21f4b65 1737MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 1738MODULE_LICENSE("GPL");
b21f4b65 1739MODULE_ALIAS("platform:dw-hdmi");
Linux 6.x block layer and io_uring tree(s)