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drm: bridge: dw-hdmi: Fix the PHY power up sequence
[linux-2.6-block.git] / drivers / gpu / drm / bridge / dw-hdmi.c
CommitLineData
9aaf880e 1/*
3efc2fa3
VZ		 2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
3 *
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
9aaf880e 5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3efc2fa3 6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
9aaf880e
FE		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
9aaf880e 13 */
b21f4b65 14#include <linux/module.h>
9aaf880e
FE		 15#include <linux/irq.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/clk.h>
5a819ed6 19#include <linux/hdmi.h>
6bcf4953 20#include <linux/mutex.h>
9aaf880e 21#include <linux/of_device.h>
b90120a9 22#include <linux/spinlock.h>
9aaf880e 23
3d1b35a3 24#include <drm/drm_of.h>
9aaf880e 25#include <drm/drmP.h>
2c5b2ccc 26#include <drm/drm_atomic_helper.h>
9aaf880e
FE		 27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_edid.h>
29#include <drm/drm_encoder_slave.h>
b21f4b65 30#include <drm/bridge/dw_hdmi.h>
9aaf880e 31
248a86fc
TR		 32#include "dw-hdmi.h"
33#include "dw-hdmi-audio.h"
9aaf880e
FE		 34
35#define HDMI_EDID_LEN 512
36
37#define RGB 0
38#define YCBCR444 1
39#define YCBCR422_16BITS 2
40#define YCBCR422_8BITS 3
41#define XVYCC444 4
42
43enum hdmi_datamap {
44 RGB444_8B = 0x01,
45 RGB444_10B = 0x03,
46 RGB444_12B = 0x05,
47 RGB444_16B = 0x07,
48 YCbCr444_8B = 0x09,
49 YCbCr444_10B = 0x0B,
50 YCbCr444_12B = 0x0D,
51 YCbCr444_16B = 0x0F,
52 YCbCr422_8B = 0x16,
53 YCbCr422_10B = 0x14,
54 YCbCr422_12B = 0x12,
55};
56
9aaf880e
FE		 57static const u16 csc_coeff_default[3][4] = {
58 { 0x2000, 0x0000, 0x0000, 0x0000 },
59 { 0x0000, 0x2000, 0x0000, 0x0000 },
60 { 0x0000, 0x0000, 0x2000, 0x0000 }
61};
62
63static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
64 { 0x2000, 0x6926, 0x74fd, 0x010e },
65 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
66 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
67};
68
69static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
70 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
71 { 0x2000, 0x3264, 0x0000, 0x7e6d },
72 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
73};
74
75static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
76 { 0x2591, 0x1322, 0x074b, 0x0000 },
77 { 0x6535, 0x2000, 0x7acc, 0x0200 },
78 { 0x6acd, 0x7534, 0x2000, 0x0200 }
79};
80
81static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
82 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
83 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
84 { 0x6756, 0x78ab, 0x2000, 0x0200 }
85};
86
87struct hdmi_vmode {
9aaf880e
FE		 88 bool mdataenablepolarity;
89
90 unsigned int mpixelclock;
91 unsigned int mpixelrepetitioninput;
92 unsigned int mpixelrepetitionoutput;
93};
94
95struct hdmi_data_info {
96 unsigned int enc_in_format;
97 unsigned int enc_out_format;
98 unsigned int enc_color_depth;
99 unsigned int colorimetry;
100 unsigned int pix_repet_factor;
101 unsigned int hdcp_enable;
102 struct hdmi_vmode video_mode;
103};
104
3efc2fa3
VZ		 105struct dw_hdmi_i2c {
106 struct i2c_adapter adap;
107
108 struct mutex lock; /* used to serialize data transfers */
109 struct completion cmp;
110 u8 stat;
111
112 u8 slave_reg;
113 bool is_regaddr;
114};
115
faba6c3c
LP		 116struct dw_hdmi_phy_data {
117 enum dw_hdmi_phy_type type;
118 const char *name;
b0e583e5 119 unsigned int gen;
faba6c3c
LP		 120 bool has_svsret;
121};
122
b21f4b65 123struct dw_hdmi {
9aaf880e 124 struct drm_connector connector;
70c963ec 125 struct drm_bridge bridge;
9aaf880e 126
b21f4b65 127 enum dw_hdmi_devtype dev_type;
be41fc55
LP		 128 unsigned int version;
129
130 struct platform_device *audio;
9aaf880e
FE		 131 struct device *dev;
132 struct clk *isfr_clk;
133 struct clk *iahb_clk;
3efc2fa3 134 struct dw_hdmi_i2c *i2c;
9aaf880e
FE		 135
136 struct hdmi_data_info hdmi_data;
b21f4b65
AY		 137 const struct dw_hdmi_plat_data *plat_data;
138
9aaf880e
FE		 139 int vic;
140
141 u8 edid[HDMI_EDID_LEN];
142 bool cable_plugin;
143
faba6c3c 144 const struct dw_hdmi_phy_data *phy;
9aaf880e 145 bool phy_enabled;
faba6c3c 146
9aaf880e
FE		 147 struct drm_display_mode previous_mode;
148
9aaf880e
FE		 149 struct i2c_adapter *ddc;
150 void __iomem *regs;
05b1342f 151 bool sink_is_hdmi;
f709ec07 152 bool sink_has_audio;
9aaf880e 153
b872a8e1 154 struct mutex mutex; /* for state below and previous_mode */
381f05a7 155 enum drm_connector_force force; /* mutex-protected force state */
b872a8e1 156 bool disabled; /* DRM has disabled our bridge */
381f05a7 157 bool bridge_is_on; /* indicates the bridge is on */
aeac23bd
RK		 158 bool rxsense; /* rxsense state */
159 u8 phy_mask; /* desired phy int mask settings */
b872a8e1 160
b90120a9 161 spinlock_t audio_lock;
6bcf4953 162 struct mutex audio_mutex;
9aaf880e 163 unsigned int sample_rate;
b90120a9
RK		 164 unsigned int audio_cts;
165 unsigned int audio_n;
166 bool audio_enable;
0cd9d142
AY		 167
168 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
169 u8 (*read)(struct dw_hdmi *hdmi, int offset);
9aaf880e
FE		 170};
171
aeac23bd
RK		 172#define HDMI_IH_PHY_STAT0_RX_SENSE \
173 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
174 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
175
176#define HDMI_PHY_RX_SENSE \
177 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
178 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
179
0cd9d142
AY		 180static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
181{
182 writel(val, hdmi->regs + (offset << 2));
183}
184
185static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
186{
187 return readl(hdmi->regs + (offset << 2));
188}
189
190static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
9aaf880e
FE		 191{
192 writeb(val, hdmi->regs + offset);
193}
194
0cd9d142 195static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
9aaf880e
FE		 196{
197 return readb(hdmi->regs + offset);
198}
199
0cd9d142
AY		 200static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
201{
202 hdmi->write(hdmi, val, offset);
203}
204
205static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
206{
207 return hdmi->read(hdmi, offset);
208}
209
b21f4b65 210static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
812bc615
RK		 211{
212 u8 val = hdmi_readb(hdmi, reg) & ~mask;
b44ab1b0 213
812bc615
RK		 214 val |= data & mask;
215 hdmi_writeb(hdmi, val, reg);
216}
217
b21f4b65 218static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
b5878339 219 u8 shift, u8 mask)
9aaf880e 220{
812bc615 221 hdmi_modb(hdmi, data << shift, mask, reg);
9aaf880e
FE		 222}
223
3efc2fa3
VZ		 224static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
225{
226 /* Software reset */
227 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
228
229 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
230 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
231
232 /* Set done, not acknowledged and arbitration interrupt polarities */
233 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
234 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
235 HDMI_I2CM_CTLINT);
236
237 /* Clear DONE and ERROR interrupts */
238 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
239 HDMI_IH_I2CM_STAT0);
240
241 /* Mute DONE and ERROR interrupts */
242 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
243 HDMI_IH_MUTE_I2CM_STAT0);
244}
245
246static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
247 unsigned char *buf, unsigned int length)
248{
249 struct dw_hdmi_i2c *i2c = hdmi->i2c;
250 int stat;
251
252 if (!i2c->is_regaddr) {
253 dev_dbg(hdmi->dev, "set read register address to 0\n");
254 i2c->slave_reg = 0x00;
255 i2c->is_regaddr = true;
256 }
257
258 while (length--) {
259 reinit_completion(&i2c->cmp);
260
261 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
262 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
263 HDMI_I2CM_OPERATION);
264
265 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
266 if (!stat)
267 return -EAGAIN;
268
269 /* Check for error condition on the bus */
270 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
271 return -EIO;
272
273 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
274 }
275
276 return 0;
277}
278
279static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
280 unsigned char *buf, unsigned int length)
281{
282 struct dw_hdmi_i2c *i2c = hdmi->i2c;
283 int stat;
284
285 if (!i2c->is_regaddr) {
286 /* Use the first write byte as register address */
287 i2c->slave_reg = buf[0];
288 length--;
289 buf++;
290 i2c->is_regaddr = true;
291 }
292
293 while (length--) {
294 reinit_completion(&i2c->cmp);
295
296 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
297 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
298 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
299 HDMI_I2CM_OPERATION);
300
301 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
302 if (!stat)
303 return -EAGAIN;
304
305 /* Check for error condition on the bus */
306 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
307 return -EIO;
308 }
309
310 return 0;
311}
312
313static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
314 struct i2c_msg *msgs, int num)
315{
316 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
317 struct dw_hdmi_i2c *i2c = hdmi->i2c;
318 u8 addr = msgs[0].addr;
319 int i, ret = 0;
320
321 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
322
323 for (i = 0; i < num; i++) {
324 if (msgs[i].addr != addr) {
325 dev_warn(hdmi->dev,
326 "unsupported transfer, changed slave address\n");
327 return -EOPNOTSUPP;
328 }
329
330 if (msgs[i].len == 0) {
331 dev_dbg(hdmi->dev,
332 "unsupported transfer %d/%d, no data\n",
333 i + 1, num);
334 return -EOPNOTSUPP;
335 }
336 }
337
338 mutex_lock(&i2c->lock);
339
340 /* Unmute DONE and ERROR interrupts */
341 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
342
343 /* Set slave device address taken from the first I2C message */
344 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
345
346 /* Set slave device register address on transfer */
347 i2c->is_regaddr = false;
348
349 for (i = 0; i < num; i++) {
350 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
351 i + 1, num, msgs[i].len, msgs[i].flags);
352
353 if (msgs[i].flags & I2C_M_RD)
354 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
355 else
356 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
357
358 if (ret < 0)
359 break;
360 }
361
362 if (!ret)
363 ret = num;
364
365 /* Mute DONE and ERROR interrupts */
366 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
367 HDMI_IH_MUTE_I2CM_STAT0);
368
369 mutex_unlock(&i2c->lock);
370
371 return ret;
372}
373
374static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
375{
376 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
377}
378
379static const struct i2c_algorithm dw_hdmi_algorithm = {
380 .master_xfer = dw_hdmi_i2c_xfer,
381 .functionality = dw_hdmi_i2c_func,
382};
383
384static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
385{
386 struct i2c_adapter *adap;
387 struct dw_hdmi_i2c *i2c;
388 int ret;
389
390 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
391 if (!i2c)
392 return ERR_PTR(-ENOMEM);
393
394 mutex_init(&i2c->lock);
395 init_completion(&i2c->cmp);
396
397 adap = &i2c->adap;
398 adap->class = I2C_CLASS_DDC;
399 adap->owner = THIS_MODULE;
400 adap->dev.parent = hdmi->dev;
401 adap->algo = &dw_hdmi_algorithm;
402 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
403 i2c_set_adapdata(adap, hdmi);
404
405 ret = i2c_add_adapter(adap);
406 if (ret) {
407 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
408 devm_kfree(hdmi->dev, i2c);
409 return ERR_PTR(ret);
410 }
411
412 hdmi->i2c = i2c;
413
414 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
415
416 return adap;
417}
418
351e1354
RK		 419static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
420 unsigned int n)
9aaf880e 421{
622494a3
RK		 422 /* Must be set/cleared first */
423 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
9aaf880e
FE		 424
425 /* nshift factor = 0 */
812bc615 426 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
9aaf880e 427
9aaf880e
FE		 428 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
429 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
622494a3
RK		 430 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
431 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
432
433 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
434 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
435 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
9aaf880e
FE		 436}
437
b195fbdb 438static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
9aaf880e
FE		 439{
440 unsigned int n = (128 * freq) / 1000;
d0c96d16
RK		 441 unsigned int mult = 1;
442
443 while (freq > 48000) {
444 mult *= 2;
445 freq /= 2;
446 }
9aaf880e
FE		 447
448 switch (freq) {
449 case 32000:
426701d0 450 if (pixel_clk == 25175000)
b195fbdb 451 n = 4576;
426701d0 452 else if (pixel_clk == 27027000)
b195fbdb 453 n = 4096;
426701d0 454 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
9aaf880e
FE		 455 n = 11648;
456 else
457 n = 4096;
d0c96d16 458 n *= mult;
9aaf880e
FE		 459 break;
460
461 case 44100:
426701d0 462 if (pixel_clk == 25175000)
9aaf880e 463 n = 7007;
426701d0 464 else if (pixel_clk == 74176000)
9aaf880e 465 n = 17836;
426701d0 466 else if (pixel_clk == 148352000)
b195fbdb 467 n = 8918;
9aaf880e
FE		 468 else
469 n = 6272;
d0c96d16 470 n *= mult;
9aaf880e
FE		 471 break;
472
473 case 48000:
426701d0 474 if (pixel_clk == 25175000)
b195fbdb 475 n = 6864;
426701d0 476 else if (pixel_clk == 27027000)
b195fbdb 477 n = 6144;
426701d0 478 else if (pixel_clk == 74176000)
9aaf880e 479 n = 11648;
426701d0 480 else if (pixel_clk == 148352000)
b195fbdb 481 n = 5824;
9aaf880e
FE		 482 else
483 n = 6144;
d0c96d16 484 n *= mult;
9aaf880e
FE		 485 break;
486
487 default:
488 break;
489 }
490
491 return n;
492}
493
b21f4b65 494static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
b195fbdb 495 unsigned long pixel_clk, unsigned int sample_rate)
9aaf880e 496{
dfbdaf50 497 unsigned long ftdms = pixel_clk;
f879b38f 498 unsigned int n, cts;
dfbdaf50 499 u64 tmp;
9aaf880e 500
b195fbdb 501 n = hdmi_compute_n(sample_rate, pixel_clk);
9aaf880e 502
dfbdaf50
RK		 503 /*
504 * Compute the CTS value from the N value. Note that CTS and N
505 * can be up to 20 bits in total, so we need 64-bit math. Also
506 * note that our TDMS clock is not fully accurate; it is accurate
507 * to kHz. This can introduce an unnecessary remainder in the
508 * calculation below, so we don't try to warn about that.
509 */
510 tmp = (u64)ftdms * n;
511 do_div(tmp, 128 * sample_rate);
512 cts = tmp;
513
514 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
515 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
516 n, cts);
9aaf880e 517
b90120a9
RK		 518 spin_lock_irq(&hdmi->audio_lock);
519 hdmi->audio_n = n;
520 hdmi->audio_cts = cts;
521 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
522 spin_unlock_irq(&hdmi->audio_lock);
9aaf880e
FE		 523}
524
b21f4b65 525static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
9aaf880e 526{
6bcf4953 527 mutex_lock(&hdmi->audio_mutex);
b195fbdb 528 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
6bcf4953 529 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 530}
531
b21f4b65 532static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
9aaf880e 533{
6bcf4953 534 mutex_lock(&hdmi->audio_mutex);
f879b38f 535 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
b195fbdb 536 hdmi->sample_rate);
6bcf4953 537 mutex_unlock(&hdmi->audio_mutex);
9aaf880e
FE		 538}
539
b5814fff
RK		 540void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
541{
542 mutex_lock(&hdmi->audio_mutex);
543 hdmi->sample_rate = rate;
544 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
b195fbdb 545 hdmi->sample_rate);
b5814fff
RK		 546 mutex_unlock(&hdmi->audio_mutex);
547}
548EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
549
b90120a9
RK		 550void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
551{
552 unsigned long flags;
553
554 spin_lock_irqsave(&hdmi->audio_lock, flags);
555 hdmi->audio_enable = true;
556 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
557 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
558}
559EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
560
561void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
562{
563 unsigned long flags;
564
565 spin_lock_irqsave(&hdmi->audio_lock, flags);
566 hdmi->audio_enable = false;
567 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
568 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
569}
570EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
571
9aaf880e
FE		 572/*
573 * this submodule is responsible for the video data synchronization.
574 * for example, for RGB 4:4:4 input, the data map is defined as
575 * pin{47~40} <==> R[7:0]
576 * pin{31~24} <==> G[7:0]
577 * pin{15~8} <==> B[7:0]
578 */
b21f4b65 579static void hdmi_video_sample(struct dw_hdmi *hdmi)
9aaf880e
FE		 580{
581 int color_format = 0;
582 u8 val;
583
584 if (hdmi->hdmi_data.enc_in_format == RGB) {
585 if (hdmi->hdmi_data.enc_color_depth == 8)
586 color_format = 0x01;
587 else if (hdmi->hdmi_data.enc_color_depth == 10)
588 color_format = 0x03;
589 else if (hdmi->hdmi_data.enc_color_depth == 12)
590 color_format = 0x05;
591 else if (hdmi->hdmi_data.enc_color_depth == 16)
592 color_format = 0x07;
593 else
594 return;
595 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
596 if (hdmi->hdmi_data.enc_color_depth == 8)
597 color_format = 0x09;
598 else if (hdmi->hdmi_data.enc_color_depth == 10)
599 color_format = 0x0B;
600 else if (hdmi->hdmi_data.enc_color_depth == 12)
601 color_format = 0x0D;
602 else if (hdmi->hdmi_data.enc_color_depth == 16)
603 color_format = 0x0F;
604 else
605 return;
606 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
607 if (hdmi->hdmi_data.enc_color_depth == 8)
608 color_format = 0x16;
609 else if (hdmi->hdmi_data.enc_color_depth == 10)
610 color_format = 0x14;
611 else if (hdmi->hdmi_data.enc_color_depth == 12)
612 color_format = 0x12;
613 else
614 return;
615 }
616
617 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
618 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
619 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
620 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
621
622 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
623 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
624 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
625 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
626 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
627 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
628 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
629 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
630 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
631 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
632 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
633}
634
b21f4b65 635static int is_color_space_conversion(struct dw_hdmi *hdmi)
9aaf880e 636{
ba92b225 637 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
9aaf880e
FE		 638}
639
b21f4b65 640static int is_color_space_decimation(struct dw_hdmi *hdmi)
9aaf880e 641{
ba92b225
FE		 642 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
643 return 0;
644 if (hdmi->hdmi_data.enc_in_format == RGB ||
645 hdmi->hdmi_data.enc_in_format == YCBCR444)
646 return 1;
647 return 0;
9aaf880e
FE		 648}
649
b21f4b65 650static int is_color_space_interpolation(struct dw_hdmi *hdmi)
9aaf880e 651{
ba92b225
FE		 652 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
653 return 0;
654 if (hdmi->hdmi_data.enc_out_format == RGB ||
655 hdmi->hdmi_data.enc_out_format == YCBCR444)
656 return 1;
657 return 0;
9aaf880e
FE		 658}
659
b21f4b65 660static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
9aaf880e
FE		 661{
662 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
c082f9d7 663 unsigned i;
9aaf880e 664 u32 csc_scale = 1;
9aaf880e
FE		 665
666 if (is_color_space_conversion(hdmi)) {
667 if (hdmi->hdmi_data.enc_out_format == RGB) {
256a38b0
GK		 668 if (hdmi->hdmi_data.colorimetry ==
669 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 670 csc_coeff = &csc_coeff_rgb_out_eitu601;
671 else
672 csc_coeff = &csc_coeff_rgb_out_eitu709;
673 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
256a38b0
GK		 674 if (hdmi->hdmi_data.colorimetry ==
675 HDMI_COLORIMETRY_ITU_601)
9aaf880e
FE		 676 csc_coeff = &csc_coeff_rgb_in_eitu601;
677 else
678 csc_coeff = &csc_coeff_rgb_in_eitu709;
679 csc_scale = 0;
680 }
681 }
682
c082f9d7
RK		 683 /* The CSC registers are sequential, alternating MSB then LSB */
684 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
685 u16 coeff_a = (*csc_coeff)[0][i];
686 u16 coeff_b = (*csc_coeff)[1][i];
687 u16 coeff_c = (*csc_coeff)[2][i];
688
b5878339 689 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
c082f9d7
RK		 690 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
691 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
692 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
b5878339 693 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
c082f9d7
RK		 694 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
695 }
9aaf880e 696
812bc615
RK		 697 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
698 HDMI_CSC_SCALE);
9aaf880e
FE		 699}
700
b21f4b65 701static void hdmi_video_csc(struct dw_hdmi *hdmi)
9aaf880e
FE		 702{
703 int color_depth = 0;
704 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
705 int decimation = 0;
9aaf880e
FE		 706
707 /* YCC422 interpolation to 444 mode */
708 if (is_color_space_interpolation(hdmi))
709 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
710 else if (is_color_space_decimation(hdmi))
711 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
712
713 if (hdmi->hdmi_data.enc_color_depth == 8)
714 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
715 else if (hdmi->hdmi_data.enc_color_depth == 10)
716 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
717 else if (hdmi->hdmi_data.enc_color_depth == 12)
718 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
719 else if (hdmi->hdmi_data.enc_color_depth == 16)
720 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
721 else
722 return;
723
724 /* Configure the CSC registers */
725 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
812bc615
RK		 726 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
727 HDMI_CSC_SCALE);
9aaf880e 728
b21f4b65 729 dw_hdmi_update_csc_coeffs(hdmi);
9aaf880e
FE		 730}
731
732/*
733 * HDMI video packetizer is used to packetize the data.
734 * for example, if input is YCC422 mode or repeater is used,
735 * data should be repacked this module can be bypassed.
736 */
b21f4b65 737static void hdmi_video_packetize(struct dw_hdmi *hdmi)
9aaf880e
FE		 738{
739 unsigned int color_depth = 0;
740 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
741 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
742 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
bebdf664 743 u8 val, vp_conf;
9aaf880e 744
b5878339
AY		 745 if (hdmi_data->enc_out_format == RGB ||
746 hdmi_data->enc_out_format == YCBCR444) {
747 if (!hdmi_data->enc_color_depth) {
9aaf880e 748 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 749 } else if (hdmi_data->enc_color_depth == 8) {
9aaf880e
FE		 750 color_depth = 4;
751 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
b5878339 752 } else if (hdmi_data->enc_color_depth == 10) {
9aaf880e 753 color_depth = 5;
b5878339 754 } else if (hdmi_data->enc_color_depth == 12) {
9aaf880e 755 color_depth = 6;
b5878339 756 } else if (hdmi_data->enc_color_depth == 16) {
9aaf880e 757 color_depth = 7;
b5878339 758 } else {
9aaf880e 759 return;
b5878339 760 }
9aaf880e
FE		 761 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
762 if (!hdmi_data->enc_color_depth ||
763 hdmi_data->enc_color_depth == 8)
764 remap_size = HDMI_VP_REMAP_YCC422_16bit;
765 else if (hdmi_data->enc_color_depth == 10)
766 remap_size = HDMI_VP_REMAP_YCC422_20bit;
767 else if (hdmi_data->enc_color_depth == 12)
768 remap_size = HDMI_VP_REMAP_YCC422_24bit;
769 else
770 return;
771 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
b5878339 772 } else {
9aaf880e 773 return;
b5878339 774 }
9aaf880e
FE		 775
776 /* set the packetizer registers */
777 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
778 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
779 ((hdmi_data->pix_repet_factor <<
780 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
781 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
782 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
783
812bc615
RK		 784 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
785 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 786
787 /* Data from pixel repeater block */
788 if (hdmi_data->pix_repet_factor > 1) {
bebdf664
RK		 789 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
790 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
9aaf880e 791 } else { /* data from packetizer block */
bebdf664
RK		 792 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
793 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
9aaf880e
FE		 794 }
795
bebdf664
RK		 796 hdmi_modb(hdmi, vp_conf,
797 HDMI_VP_CONF_PR_EN_MASK |
798 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
799
812bc615
RK		 800 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
801 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
9aaf880e
FE		 802
803 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
804
805 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
bebdf664
RK		 806 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
807 HDMI_VP_CONF_PP_EN_ENABLE |
808 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e 809 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
bebdf664
RK		 810 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
811 HDMI_VP_CONF_PP_EN_DISABLE |
812 HDMI_VP_CONF_YCC422_EN_ENABLE;
9aaf880e 813 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
bebdf664
RK		 814 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
815 HDMI_VP_CONF_PP_EN_DISABLE |
816 HDMI_VP_CONF_YCC422_EN_DISABLE;
9aaf880e
FE		 817 } else {
818 return;
819 }
820
bebdf664
RK		 821 hdmi_modb(hdmi, vp_conf,
822 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
823 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
824
812bc615
RK		 825 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
826 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
827 HDMI_VP_STUFF_PP_STUFFING_MASK |
828 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
9aaf880e 829
812bc615
RK		 830 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
831 HDMI_VP_CONF);
9aaf880e
FE		 832}
833
b21f4b65 834static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
b5878339 835 unsigned char bit)
9aaf880e 836{
812bc615
RK		 837 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
838 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
9aaf880e
FE		 839}
840
b21f4b65 841static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
9aaf880e 842{
a4d3b8b0
AY		 843 u32 val;
844
845 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
9aaf880e
FE		 846 if (msec-- == 0)
847 return false;
0e6bcf3a 848 udelay(1000);
9aaf880e 849 }
a4d3b8b0
AY		 850 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
851
9aaf880e
FE		 852 return true;
853}
854
cc7e9623 855static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
b5878339 856 unsigned char addr)
9aaf880e
FE		 857{
858 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
859 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
860 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
b5878339 861 HDMI_PHY_I2CM_DATAO_1_ADDR);
9aaf880e 862 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
b5878339 863 HDMI_PHY_I2CM_DATAO_0_ADDR);
9aaf880e 864 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
b5878339 865 HDMI_PHY_I2CM_OPERATION_ADDR);
9aaf880e
FE		 866 hdmi_phy_wait_i2c_done(hdmi, 1000);
867}
868
2fada109 869static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
9aaf880e 870{
2fada109 871 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
9aaf880e
FE		 872 HDMI_PHY_CONF0_PDZ_OFFSET,
873 HDMI_PHY_CONF0_PDZ_MASK);
874}
875
b21f4b65 876static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 877{
878 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
879 HDMI_PHY_CONF0_ENTMDS_OFFSET,
880 HDMI_PHY_CONF0_ENTMDS_MASK);
881}
882
f4104e8f 883static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
d346c14e
AY		 884{
885 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
f4104e8f
LP		 886 HDMI_PHY_CONF0_SVSRET_OFFSET,
887 HDMI_PHY_CONF0_SVSRET_MASK);
d346c14e
AY		 888}
889
b21f4b65 890static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 891{
892 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
893 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
894 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
895}
896
b21f4b65 897static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 898{
899 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
900 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
901 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
902}
903
b21f4b65 904static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 905{
906 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
907 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
908 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
909}
910
b21f4b65 911static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
9aaf880e
FE		 912{
913 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
914 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
915 HDMI_PHY_CONF0_SELDIPIF_MASK);
916}
917
b0e583e5
LP		 918static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
919{
920 const struct dw_hdmi_phy_data *phy = hdmi->phy;
921 unsigned int i;
922 u16 val;
923
924 if (phy->gen == 1) {
925 dw_hdmi_phy_enable_tmds(hdmi, 0);
926 dw_hdmi_phy_enable_powerdown(hdmi, true);
927 return;
928 }
929
930 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
931
932 /*
933 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
934 * to low power mode.
935 */
936 for (i = 0; i < 5; ++i) {
937 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
938 if (!(val & HDMI_PHY_TX_PHY_LOCK))
939 break;
940
941 usleep_range(1000, 2000);
942 }
943
944 if (val & HDMI_PHY_TX_PHY_LOCK)
945 dev_warn(hdmi->dev, "PHY failed to power down\n");
946 else
947 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
948
949 dw_hdmi_phy_gen2_pddq(hdmi, 1);
950}
951
181e0ef0
LP		 952static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
953{
954 const struct dw_hdmi_phy_data *phy = hdmi->phy;
955 unsigned int i;
956 u8 val;
957
958 if (phy->gen == 1) {
959 dw_hdmi_phy_enable_powerdown(hdmi, false);
960
961 /* Toggle TMDS enable. */
962 dw_hdmi_phy_enable_tmds(hdmi, 0);
963 dw_hdmi_phy_enable_tmds(hdmi, 1);
964 return 0;
965 }
966
967 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
968 dw_hdmi_phy_gen2_pddq(hdmi, 0);
969
970 /* Wait for PHY PLL lock */
971 for (i = 0; i < 5; ++i) {
972 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
973 if (val)
974 break;
975
976 usleep_range(1000, 2000);
977 }
978
979 if (!val) {
980 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
981 return -ETIMEDOUT;
982 }
983
984 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
985 return 0;
986}
987
8b9e1c0d 988static int hdmi_phy_configure(struct dw_hdmi *hdmi)
9aaf880e 989{
39cc1535
RK		 990 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
991 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
992 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
993 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
9aaf880e 994
39cc1535
RK		 995 /* PLL/MPLL Cfg - always match on final entry */
996 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
997 if (hdmi->hdmi_data.video_mode.mpixelclock <=
998 mpll_config->mpixelclock)
999 break;
1000
1001 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1002 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1003 curr_ctrl->mpixelclock)
1004 break;
1005
1006 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1007 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1008 phy_config->mpixelclock)
1009 break;
1010
1011 if (mpll_config->mpixelclock == ~0UL ||
1012 curr_ctrl->mpixelclock == ~0UL ||
1013 phy_config->mpixelclock == ~0UL) {
1014 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1015 hdmi->hdmi_data.video_mode.mpixelclock);
1016 return -EINVAL;
1017 }
1018
b0e583e5 1019 dw_hdmi_phy_power_off(hdmi);
9aaf880e 1020
2668db37
LP		 1021 /* Leave low power consumption mode by asserting SVSRET. */
1022 if (hdmi->phy->has_svsret)
1023 dw_hdmi_phy_enable_svsret(hdmi, 1);
1024
54d72737
LP		 1025 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1026 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1027 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
9aaf880e
FE		 1028
1029 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1030
1031 hdmi_phy_test_clear(hdmi, 1);
1032 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
b5878339 1033 HDMI_PHY_I2CM_SLAVE_ADDR);
9aaf880e
FE		 1034 hdmi_phy_test_clear(hdmi, 0);
1035
f0e7f2f3
LP		 1036 hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1037 HDMI_3D_TX_PHY_CPCE_CTRL);
1038 hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1039 HDMI_3D_TX_PHY_GMPCTRL);
1040 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1041 HDMI_3D_TX_PHY_CURRCTRL);
1042
1043 hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1044 hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1045 HDMI_3D_TX_PHY_MSM_CTRL);
1046
1047 hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1048 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1049 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1050 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1051 HDMI_3D_TX_PHY_VLEVCTRL);
1052
1053 /* Override and disable clock termination. */
1054 hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1055 HDMI_3D_TX_PHY_CKCALCTRL);
9aaf880e 1056
181e0ef0 1057 return dw_hdmi_phy_power_on(hdmi);
9aaf880e
FE		 1058}
1059
b21f4b65 1060static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
9aaf880e
FE		 1061{
1062 int i, ret;
9aaf880e
FE		 1063
1064 /* HDMI Phy spec says to do the phy initialization sequence twice */
1065 for (i = 0; i < 2; i++) {
b21f4b65
AY		 1066 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1067 dw_hdmi_phy_sel_interface_control(hdmi, 0);
9aaf880e 1068
8b9e1c0d 1069 ret = hdmi_phy_configure(hdmi);
9aaf880e
FE		 1070 if (ret)
1071 return ret;
1072 }
1073
1074 hdmi->phy_enabled = true;
1075 return 0;
1076}
1077
b21f4b65 1078static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
9aaf880e 1079{
812bc615 1080 u8 de;
9aaf880e
FE		 1081
1082 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1083 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1084 else
1085 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1086
1087 /* disable rx detect */
812bc615
RK		 1088 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1089 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
9aaf880e 1090
812bc615 1091 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
9aaf880e 1092
812bc615
RK		 1093 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1094 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
9aaf880e
FE		 1095}
1096
d4ac4cb6 1097static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e 1098{
d4ac4cb6
RK		 1099 struct hdmi_avi_infoframe frame;
1100 u8 val;
9aaf880e 1101
d4ac4cb6
RK		 1102 /* Initialise info frame from DRM mode */
1103 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
9aaf880e 1104
9aaf880e 1105 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
d4ac4cb6 1106 frame.colorspace = HDMI_COLORSPACE_YUV444;
9aaf880e 1107 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
d4ac4cb6 1108 frame.colorspace = HDMI_COLORSPACE_YUV422;
9aaf880e 1109 else
d4ac4cb6 1110 frame.colorspace = HDMI_COLORSPACE_RGB;
9aaf880e
FE		 1111
1112 /* Set up colorimetry */
1113 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
d4ac4cb6 1114 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
5a819ed6 1115 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
d4ac4cb6
RK		 1116 frame.extended_colorimetry =
1117 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
5a819ed6 1118 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
d4ac4cb6
RK		 1119 frame.extended_colorimetry =
1120 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
9aaf880e 1121 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
d083c312 1122 frame.colorimetry = hdmi->hdmi_data.colorimetry;
d4ac4cb6 1123 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
9aaf880e 1124 } else { /* Carries no data */
d4ac4cb6
RK		 1125 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1126 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
9aaf880e
FE		 1127 }
1128
d4ac4cb6
RK		 1129 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1130
1131 /*
1132 * The Designware IP uses a different byte format from standard
1133 * AVI info frames, though generally the bits are in the correct
1134 * bytes.
1135 */
1136
1137 /*
b0118e7d
JA		 1138 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1139 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1140 * bit 6 rather than 4.
d4ac4cb6 1141 */
b0118e7d 1142 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
d4ac4cb6
RK		 1143 if (frame.active_aspect & 15)
1144 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1145 if (frame.top_bar || frame.bottom_bar)
1146 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1147 if (frame.left_bar || frame.right_bar)
1148 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1149 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1150
1151 /* AVI data byte 2 differences: none */
1152 val = ((frame.colorimetry & 0x3) << 6) |
1153 ((frame.picture_aspect & 0x3) << 4) |
1154 (frame.active_aspect & 0xf);
9aaf880e
FE		 1155 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1156
d4ac4cb6
RK		 1157 /* AVI data byte 3 differences: none */
1158 val = ((frame.extended_colorimetry & 0x7) << 4) |
1159 ((frame.quantization_range & 0x3) << 2) |
1160 (frame.nups & 0x3);
1161 if (frame.itc)
1162 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
9aaf880e
FE		 1163 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1164
d4ac4cb6
RK		 1165 /* AVI data byte 4 differences: none */
1166 val = frame.video_code & 0x7f;
1167 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
9aaf880e
FE		 1168
1169 /* AVI Data Byte 5- set up input and output pixel repetition */
1170 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1171 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1172 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1173 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1174 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1175 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1176 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1177
d4ac4cb6
RK		 1178 /*
1179 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1180 * ycc range in bits 2,3 rather than 6,7
1181 */
1182 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1183 (frame.content_type & 0x3);
9aaf880e
FE		 1184 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1185
1186 /* AVI Data Bytes 6-13 */
d4ac4cb6
RK		 1187 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1188 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1189 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1190 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1191 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1192 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1193 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1194 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
9aaf880e
FE		 1195}
1196
b21f4b65 1197static void hdmi_av_composer(struct dw_hdmi *hdmi,
9aaf880e
FE		 1198 const struct drm_display_mode *mode)
1199{
1200 u8 inv_val;
1201 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1202 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
e80b9f4e 1203 unsigned int vdisplay;
9aaf880e 1204
9aaf880e
FE		 1205 vmode->mpixelclock = mode->clock * 1000;
1206
1207 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1208
1209 /* Set up HDMI_FC_INVIDCONF */
1210 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1211 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1212 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1213
b91eee8c 1214 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
9aaf880e 1215 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1216 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e 1217
b91eee8c 1218 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
9aaf880e 1219 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
b91eee8c 1220 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
9aaf880e
FE		 1221
1222 inv_val |= (vmode->mdataenablepolarity ?
1223 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1224 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1225
1226 if (hdmi->vic == 39)
1227 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1228 else
b91eee8c 1229 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1230 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
b91eee8c 1231 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
9aaf880e 1232
b91eee8c 1233 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
9aaf880e 1234 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
b91eee8c 1235 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
9aaf880e 1236
05b1342f
RK		 1237 inv_val |= hdmi->sink_is_hdmi ?
1238 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1239 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
9aaf880e
FE		 1240
1241 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1242
e80b9f4e
RK		 1243 vdisplay = mode->vdisplay;
1244 vblank = mode->vtotal - mode->vdisplay;
1245 v_de_vs = mode->vsync_start - mode->vdisplay;
1246 vsync_len = mode->vsync_end - mode->vsync_start;
1247
1248 /*
1249 * When we're setting an interlaced mode, we need
1250 * to adjust the vertical timing to suit.
1251 */
1252 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1253 vdisplay /= 2;
1254 vblank /= 2;
1255 v_de_vs /= 2;
1256 vsync_len /= 2;
1257 }
1258
9aaf880e
FE		 1259 /* Set up horizontal active pixel width */
1260 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1261 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1262
1263 /* Set up vertical active lines */
e80b9f4e
RK		 1264 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1265 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
9aaf880e
FE		 1266
1267 /* Set up horizontal blanking pixel region width */
1268 hblank = mode->htotal - mode->hdisplay;
1269 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1270 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1271
1272 /* Set up vertical blanking pixel region width */
9aaf880e
FE		 1273 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1274
1275 /* Set up HSYNC active edge delay width (in pixel clks) */
1276 h_de_hs = mode->hsync_start - mode->hdisplay;
1277 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1278 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1279
1280 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1281 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1282
1283 /* Set up HSYNC active pulse width (in pixel clks) */
1284 hsync_len = mode->hsync_end - mode->hsync_start;
1285 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1286 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1287
1288 /* Set up VSYNC active edge delay (in lines) */
9aaf880e
FE		 1289 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1290}
1291
b21f4b65 1292static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
9aaf880e
FE		 1293{
1294 if (!hdmi->phy_enabled)
1295 return;
1296
b0e583e5 1297 dw_hdmi_phy_power_off(hdmi);
9aaf880e
FE		 1298
1299 hdmi->phy_enabled = false;
1300}
1301
1302/* HDMI Initialization Step B.4 */
b21f4b65 1303static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
9aaf880e
FE		 1304{
1305 u8 clkdis;
1306
1307 /* control period minimum duration */
1308 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1309 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1310 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1311
1312 /* Set to fill TMDS data channels */
1313 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1314 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1315 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1316
1317 /* Enable pixel clock and tmds data path */
1318 clkdis = 0x7F;
1319 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1320 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1321
1322 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1323 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1324
1325 /* Enable csc path */
1326 if (is_color_space_conversion(hdmi)) {
1327 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1328 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1329 }
8b9e1c0d 1330
14247d7c
NA		 1331 /* Enable color space conversion if needed */
1332 if (is_color_space_conversion(hdmi))
8b9e1c0d
LP		 1333 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1334 HDMI_MC_FLOWCTRL);
1335 else
1336 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1337 HDMI_MC_FLOWCTRL);
9aaf880e
FE		 1338}
1339
b21f4b65 1340static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
9aaf880e 1341{
812bc615 1342 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
9aaf880e
FE		 1343}
1344
1345/* Workaround to clear the overflow condition */
b21f4b65 1346static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
9aaf880e 1347{
be41fc55
LP		 1348 unsigned int count;
1349 unsigned int i;
9aaf880e
FE		 1350 u8 val;
1351
be41fc55
LP		 1352 /*
1353 * Under some circumstances the Frame Composer arithmetic unit can miss
1354 * an FC register write due to being busy processing the previous one.
1355 * The issue can be worked around by issuing a TMDS software reset and
1356 * then write one of the FC registers several times.
1357 *
1358 * The number of iterations matters and depends on the HDMI TX revision
1359 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1360 * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1361 * 4 and 1 iterations respectively.
1362 */
9aaf880e 1363
be41fc55
LP		 1364 switch (hdmi->version) {
1365 case 0x130a:
1366 count = 4;
1367 break;
1368 case 0x131a:
1369 count = 1;
1370 break;
1371 default:
9aaf880e
FE		 1372 return;
1373 }
1374
be41fc55
LP		 1375 /* TMDS software reset */
1376 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1377
1378 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1379 for (i = 0; i < count; i++)
9aaf880e
FE		 1380 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1381}
1382
b21f4b65 1383static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1384{
1385 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1386 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1387}
1388
b21f4b65 1389static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
9aaf880e
FE		 1390{
1391 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1392 HDMI_IH_MUTE_FC_STAT2);
1393}
1394
b21f4b65 1395static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
9aaf880e
FE		 1396{
1397 int ret;
1398
1399 hdmi_disable_overflow_interrupts(hdmi);
1400
1401 hdmi->vic = drm_match_cea_mode(mode);
1402
1403 if (!hdmi->vic) {
1404 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
9aaf880e
FE		 1405 } else {
1406 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
9aaf880e
FE		 1407 }
1408
1409 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
b5878339
AY		 1410 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1411 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1412 (hdmi->vic == 17) || (hdmi->vic == 18))
5a819ed6 1413 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
9aaf880e 1414 else
5a819ed6 1415 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
9aaf880e 1416
d10ca826 1417 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
9aaf880e
FE		 1418 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1419
1420 /* TODO: Get input format from IPU (via FB driver interface) */
1421 hdmi->hdmi_data.enc_in_format = RGB;
1422
1423 hdmi->hdmi_data.enc_out_format = RGB;
1424
1425 hdmi->hdmi_data.enc_color_depth = 8;
1426 hdmi->hdmi_data.pix_repet_factor = 0;
1427 hdmi->hdmi_data.hdcp_enable = 0;
1428 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1429
1430 /* HDMI Initialization Step B.1 */
1431 hdmi_av_composer(hdmi, mode);
1432
1433 /* HDMI Initializateion Step B.2 */
b21f4b65 1434 ret = dw_hdmi_phy_init(hdmi);
9aaf880e
FE		 1435 if (ret)
1436 return ret;
1437
1438 /* HDMI Initialization Step B.3 */
b21f4b65 1439 dw_hdmi_enable_video_path(hdmi);
9aaf880e 1440
f709ec07
RK		 1441 if (hdmi->sink_has_audio) {
1442 dev_dbg(hdmi->dev, "sink has audio support\n");
9aaf880e
FE		 1443
1444 /* HDMI Initialization Step E - Configure audio */
1445 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1446 hdmi_enable_audio_clk(hdmi);
f709ec07
RK		 1447 }
1448
1449 /* not for DVI mode */
1450 if (hdmi->sink_is_hdmi) {
1451 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
9aaf880e
FE		 1452
1453 /* HDMI Initialization Step F - Configure AVI InfoFrame */
d4ac4cb6 1454 hdmi_config_AVI(hdmi, mode);
05b1342f
RK		 1455 } else {
1456 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
9aaf880e
FE		 1457 }
1458
1459 hdmi_video_packetize(hdmi);
1460 hdmi_video_csc(hdmi);
1461 hdmi_video_sample(hdmi);
1462 hdmi_tx_hdcp_config(hdmi);
1463
b21f4b65 1464 dw_hdmi_clear_overflow(hdmi);
05b1342f 1465 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
9aaf880e
FE		 1466 hdmi_enable_overflow_interrupts(hdmi);
1467
1468 return 0;
1469}
1470
1471/* Wait until we are registered to enable interrupts */
b21f4b65 1472static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
9aaf880e
FE		 1473{
1474 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1475 HDMI_PHY_I2CM_INT_ADDR);
1476
1477 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1478 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1479 HDMI_PHY_I2CM_CTLINT_ADDR);
1480
1481 /* enable cable hot plug irq */
aeac23bd 1482 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
9aaf880e
FE		 1483
1484 /* Clear Hotplug interrupts */
aeac23bd
RK		 1485 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1486 HDMI_IH_PHY_STAT0);
9aaf880e 1487
9aaf880e
FE		 1488 return 0;
1489}
1490
b21f4b65 1491static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
9aaf880e
FE		 1492{
1493 u8 ih_mute;
1494
1495 /*
1496 * Boot up defaults are:
1497 * HDMI_IH_MUTE = 0x03 (disabled)
1498 * HDMI_IH_MUTE_* = 0x00 (enabled)
1499 *
1500 * Disable top level interrupt bits in HDMI block
1501 */
1502 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1503 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1504 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1505
1506 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1507
1508 /* by default mask all interrupts */
1509 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1510 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1511 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1512 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1513 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1514 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1515 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1516 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1517 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1518 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1519 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1520 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1521 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1522 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1523 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1524
1525 /* Disable interrupts in the IH_MUTE_* registers */
1526 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1527 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1528 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1529 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1530 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1531 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1532 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1533 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1534 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1535 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1536
1537 /* Enable top level interrupt bits in HDMI block */
1538 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1539 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1540 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1541}
1542
b21f4b65 1543static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
9aaf880e 1544{
381f05a7 1545 hdmi->bridge_is_on = true;
b21f4b65 1546 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
9aaf880e
FE		 1547}
1548
b21f4b65 1549static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
9aaf880e 1550{
b21f4b65 1551 dw_hdmi_phy_disable(hdmi);
381f05a7
RK		 1552 hdmi->bridge_is_on = false;
1553}
1554
1555static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1556{
1557 int force = hdmi->force;
1558
1559 if (hdmi->disabled) {
1560 force = DRM_FORCE_OFF;
1561 } else if (force == DRM_FORCE_UNSPECIFIED) {
aeac23bd 1562 if (hdmi->rxsense)
381f05a7
RK		 1563 force = DRM_FORCE_ON;
1564 else
1565 force = DRM_FORCE_OFF;
1566 }
1567
1568 if (force == DRM_FORCE_OFF) {
1569 if (hdmi->bridge_is_on)
1570 dw_hdmi_poweroff(hdmi);
1571 } else {
1572 if (!hdmi->bridge_is_on)
1573 dw_hdmi_poweron(hdmi);
1574 }
9aaf880e
FE		 1575}
1576
aeac23bd
RK		 1577/*
1578 * Adjust the detection of RXSENSE according to whether we have a forced
1579 * connection mode enabled, or whether we have been disabled. There is
1580 * no point processing RXSENSE interrupts if we have a forced connection
1581 * state, or DRM has us disabled.
1582 *
1583 * We also disable rxsense interrupts when we think we're disconnected
1584 * to avoid floating TDMS signals giving false rxsense interrupts.
1585 *
1586 * Note: we still need to listen for HPD interrupts even when DRM has us
1587 * disabled so that we can detect a connect event.
1588 */
1589static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1590{
1591 u8 old_mask = hdmi->phy_mask;
1592
1593 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1594 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1595 else
1596 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1597
1598 if (old_mask != hdmi->phy_mask)
1599 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1600}
1601
b21f4b65
AY		 1602static enum drm_connector_status
1603dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
9aaf880e 1604{
b21f4b65 1605 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
d94905e0 1606 connector);
98dbeada 1607
381f05a7
RK		 1608 mutex_lock(&hdmi->mutex);
1609 hdmi->force = DRM_FORCE_UNSPECIFIED;
1610 dw_hdmi_update_power(hdmi);
aeac23bd 1611 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 1612 mutex_unlock(&hdmi->mutex);
1613
98dbeada
RK		 1614 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1615 connector_status_connected : connector_status_disconnected;
9aaf880e
FE		 1616}
1617
b21f4b65 1618static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
9aaf880e 1619{
b21f4b65 1620 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
9aaf880e
FE		 1621 connector);
1622 struct edid *edid;
6c7e66e6 1623 int ret = 0;
9aaf880e
FE		 1624
1625 if (!hdmi->ddc)
1626 return 0;
1627
1628 edid = drm_get_edid(connector, hdmi->ddc);
1629 if (edid) {
1630 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1631 edid->width_cm, edid->height_cm);
1632
05b1342f 1633 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
f709ec07 1634 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
9aaf880e
FE		 1635 drm_mode_connector_update_edid_property(connector, edid);
1636 ret = drm_add_edid_modes(connector, edid);
f5ce4057
RK		 1637 /* Store the ELD */
1638 drm_edid_to_eld(connector, edid);
9aaf880e
FE		 1639 kfree(edid);
1640 } else {
1641 dev_dbg(hdmi->dev, "failed to get edid\n");
1642 }
1643
6c7e66e6 1644 return ret;
9aaf880e
FE		 1645}
1646
632d035b
AY		 1647static enum drm_mode_status
1648dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1649 struct drm_display_mode *mode)
1650{
1651 struct dw_hdmi *hdmi = container_of(connector,
1652 struct dw_hdmi, connector);
1653 enum drm_mode_status mode_status = MODE_OK;
1654
8add4190
RK		 1655 /* We don't support double-clocked modes */
1656 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1657 return MODE_BAD;
1658
632d035b
AY		 1659 if (hdmi->plat_data->mode_valid)
1660 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1661
1662 return mode_status;
1663}
1664
381f05a7
RK		 1665static void dw_hdmi_connector_force(struct drm_connector *connector)
1666{
1667 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1668 connector);
1669
1670 mutex_lock(&hdmi->mutex);
1671 hdmi->force = connector->force;
1672 dw_hdmi_update_power(hdmi);
aeac23bd 1673 dw_hdmi_update_phy_mask(hdmi);
381f05a7
RK		 1674 mutex_unlock(&hdmi->mutex);
1675}
1676
dae91e4d 1677static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2c5b2ccc
MY		 1678 .dpms = drm_atomic_helper_connector_dpms,
1679 .fill_modes = drm_helper_probe_single_connector_modes,
1680 .detect = dw_hdmi_connector_detect,
fdd8326a 1681 .destroy = drm_connector_cleanup,
2c5b2ccc
MY		 1682 .force = dw_hdmi_connector_force,
1683 .reset = drm_atomic_helper_connector_reset,
1684 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1685 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1686};
1687
dae91e4d 1688static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
b21f4b65 1689 .get_modes = dw_hdmi_connector_get_modes,
632d035b 1690 .mode_valid = dw_hdmi_connector_mode_valid,
c2a441fe 1691 .best_encoder = drm_atomic_helper_best_encoder,
9aaf880e
FE		 1692};
1693
d2ae94ae
LP		 1694static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1695{
1696 struct dw_hdmi *hdmi = bridge->driver_private;
1697 struct drm_encoder *encoder = bridge->encoder;
1698 struct drm_connector *connector = &hdmi->connector;
1699
1700 connector->interlace_allowed = 1;
1701 connector->polled = DRM_CONNECTOR_POLL_HPD;
1702
1703 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1704
1705 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1706 DRM_MODE_CONNECTOR_HDMIA);
1707
1708 drm_mode_connector_attach_encoder(connector, encoder);
1709
1710 return 0;
1711}
1712
fd30b38c
LP		 1713static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1714 struct drm_display_mode *orig_mode,
1715 struct drm_display_mode *mode)
1716{
1717 struct dw_hdmi *hdmi = bridge->driver_private;
1718
1719 mutex_lock(&hdmi->mutex);
1720
1721 /* Store the display mode for plugin/DKMS poweron events */
1722 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1723
1724 mutex_unlock(&hdmi->mutex);
1725}
1726
1727static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1728{
1729 struct dw_hdmi *hdmi = bridge->driver_private;
1730
1731 mutex_lock(&hdmi->mutex);
1732 hdmi->disabled = true;
1733 dw_hdmi_update_power(hdmi);
1734 dw_hdmi_update_phy_mask(hdmi);
1735 mutex_unlock(&hdmi->mutex);
1736}
1737
1738static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1739{
1740 struct dw_hdmi *hdmi = bridge->driver_private;
1741
1742 mutex_lock(&hdmi->mutex);
1743 hdmi->disabled = false;
1744 dw_hdmi_update_power(hdmi);
1745 dw_hdmi_update_phy_mask(hdmi);
1746 mutex_unlock(&hdmi->mutex);
1747}
1748
dae91e4d 1749static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
d2ae94ae 1750 .attach = dw_hdmi_bridge_attach,
b21f4b65
AY		 1751 .enable = dw_hdmi_bridge_enable,
1752 .disable = dw_hdmi_bridge_disable,
b21f4b65 1753 .mode_set = dw_hdmi_bridge_mode_set,
3d1b35a3
AY		 1754};
1755
3efc2fa3
VZ		 1756static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1757{
1758 struct dw_hdmi_i2c *i2c = hdmi->i2c;
1759 unsigned int stat;
1760
1761 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1762 if (!stat)
1763 return IRQ_NONE;
1764
1765 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1766
1767 i2c->stat = stat;
1768
1769 complete(&i2c->cmp);
1770
1771 return IRQ_HANDLED;
1772}
1773
b21f4b65 1774static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
d94905e0 1775{
b21f4b65 1776 struct dw_hdmi *hdmi = dev_id;
d94905e0 1777 u8 intr_stat;
3efc2fa3
VZ		 1778 irqreturn_t ret = IRQ_NONE;
1779
1780 if (hdmi->i2c)
1781 ret = dw_hdmi_i2c_irq(hdmi);
d94905e0
RK		 1782
1783 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3efc2fa3 1784 if (intr_stat) {
d94905e0 1785 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3efc2fa3
VZ		 1786 return IRQ_WAKE_THREAD;
1787 }
d94905e0 1788
3efc2fa3 1789 return ret;
d94905e0
RK		 1790}
1791
b21f4b65 1792static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
9aaf880e 1793{
b21f4b65 1794 struct dw_hdmi *hdmi = dev_id;
aeac23bd 1795 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
9aaf880e
FE		 1796
1797 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
9aaf880e 1798 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
aeac23bd
RK		 1799 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1800
1801 phy_pol_mask = 0;
1802 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1803 phy_pol_mask |= HDMI_PHY_HPD;
1804 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1805 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1806 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1807 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1808 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1809 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1810 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1811 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1812
1813 if (phy_pol_mask)
1814 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
9aaf880e 1815
aeac23bd
RK		 1816 /*
1817 * RX sense tells us whether the TDMS transmitters are detecting
1818 * load - in other words, there's something listening on the
1819 * other end of the link. Use this to decide whether we should
1820 * power on the phy as HPD may be toggled by the sink to merely
1821 * ask the source to re-read the EDID.
1822 */
1823 if (intr_stat &
1824 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
b872a8e1 1825 mutex_lock(&hdmi->mutex);
aeac23bd
RK		 1826 if (!hdmi->disabled && !hdmi->force) {
1827 /*
1828 * If the RX sense status indicates we're disconnected,
1829 * clear the software rxsense status.
1830 */
1831 if (!(phy_stat & HDMI_PHY_RX_SENSE))
1832 hdmi->rxsense = false;
1833
1834 /*
1835 * Only set the software rxsense status when both
1836 * rxsense and hpd indicates we're connected.
1837 * This avoids what seems to be bad behaviour in
1838 * at least iMX6S versions of the phy.
1839 */
1840 if (phy_stat & HDMI_PHY_HPD)
1841 hdmi->rxsense = true;
1842
1843 dw_hdmi_update_power(hdmi);
1844 dw_hdmi_update_phy_mask(hdmi);
9aaf880e 1845 }
b872a8e1 1846 mutex_unlock(&hdmi->mutex);
aeac23bd
RK		 1847 }
1848
1849 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1850 dev_dbg(hdmi->dev, "EVENT=%s\n",
1851 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
ba5d7e61
LP		 1852 if (hdmi->bridge.dev)
1853 drm_helper_hpd_irq_event(hdmi->bridge.dev);
9aaf880e
FE		 1854 }
1855
1856 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
aeac23bd
RK		 1857 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1858 HDMI_IH_MUTE_PHY_STAT0);
9aaf880e
FE		 1859
1860 return IRQ_HANDLED;
1861}
1862
faba6c3c
LP		 1863static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
1864 {
1865 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
1866 .name = "DWC HDMI TX PHY",
b0e583e5 1867 .gen = 1,
faba6c3c
LP		 1868 }, {
1869 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
1870 .name = "DWC MHL PHY + HEAC PHY",
b0e583e5 1871 .gen = 2,
faba6c3c
LP		 1872 .has_svsret = true,
1873 }, {
1874 .type = DW_HDMI_PHY_DWC_MHL_PHY,
1875 .name = "DWC MHL PHY",
b0e583e5 1876 .gen = 2,
faba6c3c
LP		 1877 .has_svsret = true,
1878 }, {
1879 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
1880 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
b0e583e5 1881 .gen = 2,
faba6c3c
LP		 1882 }, {
1883 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
1884 .name = "DWC HDMI 3D TX PHY",
b0e583e5 1885 .gen = 2,
faba6c3c
LP		 1886 }, {
1887 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
1888 .name = "DWC HDMI 2.0 TX PHY",
b0e583e5 1889 .gen = 2,
faba6c3c
LP		 1890 .has_svsret = true,
1891 }
1892};
1893
1894static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
1895{
1896 unsigned int i;
1897 u8 phy_type;
1898
1899 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
1900
1901 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
1902 if (dw_hdmi_phys[i].type == phy_type) {
1903 hdmi->phy = &dw_hdmi_phys[i];
1904 return 0;
1905 }
1906 }
1907
1908 if (phy_type == DW_HDMI_PHY_VENDOR_PHY)
1909 dev_err(hdmi->dev, "Unsupported vendor HDMI PHY\n");
1910 else
1911 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n",
1912 phy_type);
1913
1914 return -ENODEV;
1915}
1916
69497eb9
LP		 1917static struct dw_hdmi *
1918__dw_hdmi_probe(struct platform_device *pdev,
1919 const struct dw_hdmi_plat_data *plat_data)
9aaf880e 1920{
c608119d 1921 struct device *dev = &pdev->dev;
17b5001b 1922 struct device_node *np = dev->of_node;
7ed6c665 1923 struct platform_device_info pdevinfo;
9aaf880e 1924 struct device_node *ddc_node;
b21f4b65 1925 struct dw_hdmi *hdmi;
c608119d
LP		 1926 struct resource *iores;
1927 int irq;
3d1b35a3 1928 int ret;
0cd9d142 1929 u32 val = 1;
0527e12e
LP		 1930 u8 prod_id0;
1931 u8 prod_id1;
2761ba6c 1932 u8 config0;
0c674948 1933 u8 config3;
9aaf880e 1934
17b5001b 1935 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
9aaf880e 1936 if (!hdmi)
69497eb9 1937 return ERR_PTR(-ENOMEM);
9aaf880e 1938
3d1b35a3 1939 hdmi->plat_data = plat_data;
17b5001b 1940 hdmi->dev = dev;
3d1b35a3 1941 hdmi->dev_type = plat_data->dev_type;
40678388 1942 hdmi->sample_rate = 48000;
b872a8e1 1943 hdmi->disabled = true;
aeac23bd
RK		 1944 hdmi->rxsense = true;
1945 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
9aaf880e 1946
b872a8e1 1947 mutex_init(&hdmi->mutex);
6bcf4953 1948 mutex_init(&hdmi->audio_mutex);
b90120a9 1949 spin_lock_init(&hdmi->audio_lock);
6bcf4953 1950
0cd9d142
AY		 1951 of_property_read_u32(np, "reg-io-width", &val);
1952
1953 switch (val) {
1954 case 4:
1955 hdmi->write = dw_hdmi_writel;
1956 hdmi->read = dw_hdmi_readl;
1957 break;
1958 case 1:
1959 hdmi->write = dw_hdmi_writeb;
1960 hdmi->read = dw_hdmi_readb;
1961 break;
1962 default:
1963 dev_err(dev, "reg-io-width must be 1 or 4\n");
69497eb9 1964 return ERR_PTR(-EINVAL);
0cd9d142
AY		 1965 }
1966
b5d45901 1967 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
9aaf880e 1968 if (ddc_node) {
9f04a1f2 1969 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
c2c38488
AY		 1970 of_node_put(ddc_node);
1971 if (!hdmi->ddc) {
9aaf880e 1972 dev_dbg(hdmi->dev, "failed to read ddc node\n");
69497eb9 1973 return ERR_PTR(-EPROBE_DEFER);
c2c38488 1974 }
9aaf880e 1975
9aaf880e
FE		 1976 } else {
1977 dev_dbg(hdmi->dev, "no ddc property found\n");
1978 }
1979
c608119d 1980 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17b5001b 1981 hdmi->regs = devm_ioremap_resource(dev, iores);
9f04a1f2
VZ		 1982 if (IS_ERR(hdmi->regs)) {
1983 ret = PTR_ERR(hdmi->regs);
1984 goto err_res;
1985 }
9aaf880e 1986
9aaf880e
FE		 1987 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1988 if (IS_ERR(hdmi->isfr_clk)) {
1989 ret = PTR_ERR(hdmi->isfr_clk);
b5878339 1990 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
9f04a1f2 1991 goto err_res;
9aaf880e
FE		 1992 }
1993
1994 ret = clk_prepare_enable(hdmi->isfr_clk);
1995 if (ret) {
b5878339 1996 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
9f04a1f2 1997 goto err_res;
9aaf880e
FE		 1998 }
1999
2000 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2001 if (IS_ERR(hdmi->iahb_clk)) {
2002 ret = PTR_ERR(hdmi->iahb_clk);
b5878339 2003 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
9aaf880e
FE		 2004 goto err_isfr;
2005 }
2006
2007 ret = clk_prepare_enable(hdmi->iahb_clk);
2008 if (ret) {
b5878339 2009 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
9aaf880e
FE		 2010 goto err_isfr;
2011 }
2012
2013 /* Product and revision IDs */
be41fc55
LP		 2014 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2015 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
0527e12e
LP		 2016 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2017 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2018
2019 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2020 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2021 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
be41fc55 2022 hdmi->version, prod_id0, prod_id1);
0527e12e
LP		 2023 ret = -ENODEV;
2024 goto err_iahb;
2025 }
2026
faba6c3c
LP		 2027 ret = dw_hdmi_detect_phy(hdmi);
2028 if (ret < 0)
2029 goto err_iahb;
2030
2031 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
be41fc55 2032 hdmi->version >> 12, hdmi->version & 0xfff,
faba6c3c
LP		 2033 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2034 hdmi->phy->name);
9aaf880e
FE		 2035
2036 initialize_hdmi_ih_mutes(hdmi);
2037
c608119d 2038 irq = platform_get_irq(pdev, 0);
69497eb9
LP		 2039 if (irq < 0) {
2040 ret = irq;
c608119d 2041 goto err_iahb;
69497eb9 2042 }
c608119d 2043
639a202c
PZ		 2044 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2045 dw_hdmi_irq, IRQF_SHARED,
2046 dev_name(dev), hdmi);
2047 if (ret)
b33ef619 2048 goto err_iahb;
639a202c 2049
9aaf880e
FE		 2050 /*
2051 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2052 * N and cts values before enabling phy
2053 */
2054 hdmi_init_clk_regenerator(hdmi);
2055
3efc2fa3
VZ		 2056 /* If DDC bus is not specified, try to register HDMI I2C bus */
2057 if (!hdmi->ddc) {
2058 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2059 if (IS_ERR(hdmi->ddc))
2060 hdmi->ddc = NULL;
2061 }
2062
9aaf880e
FE		 2063 /*
2064 * Configure registers related to HDMI interrupt
2065 * generation before registering IRQ.
2066 */
aeac23bd 2067 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
9aaf880e
FE		 2068
2069 /* Clear Hotplug interrupts */
aeac23bd
RK		 2070 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
2071 HDMI_IH_PHY_STAT0);
9aaf880e 2072
69497eb9
LP		 2073 hdmi->bridge.driver_private = hdmi;
2074 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
d5ad7843 2075#ifdef CONFIG_OF
69497eb9 2076 hdmi->bridge.of_node = pdev->dev.of_node;
d5ad7843 2077#endif
9aaf880e 2078
69497eb9 2079 ret = dw_hdmi_fb_registered(hdmi);
9aaf880e
FE		 2080 if (ret)
2081 goto err_iahb;
2082
d94905e0 2083 /* Unmute interrupts */
aeac23bd
RK		 2084 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2085 HDMI_IH_MUTE_PHY_STAT0);
9aaf880e 2086
7ed6c665
RK		 2087 memset(&pdevinfo, 0, sizeof(pdevinfo));
2088 pdevinfo.parent = dev;
2089 pdevinfo.id = PLATFORM_DEVID_AUTO;
2090
2761ba6c 2091 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
0c674948 2092 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2761ba6c 2093
0c674948 2094 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
2761ba6c
KM		 2095 struct dw_hdmi_audio_data audio;
2096
7ed6c665
RK		 2097 audio.phys = iores->start;
2098 audio.base = hdmi->regs;
2099 audio.irq = irq;
2100 audio.hdmi = hdmi;
f5ce4057 2101 audio.eld = hdmi->connector.eld;
7ed6c665
RK		 2102
2103 pdevinfo.name = "dw-hdmi-ahb-audio";
2104 pdevinfo.data = &audio;
2105 pdevinfo.size_data = sizeof(audio);
2106 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2107 hdmi->audio = platform_device_register_full(&pdevinfo);
2761ba6c
KM		 2108 } else if (config0 & HDMI_CONFIG0_I2S) {
2109 struct dw_hdmi_i2s_audio_data audio;
2110
2111 audio.hdmi = hdmi;
2112 audio.write = hdmi_writeb;
2113 audio.read = hdmi_readb;
2114
2115 pdevinfo.name = "dw-hdmi-i2s-audio";
2116 pdevinfo.data = &audio;
2117 pdevinfo.size_data = sizeof(audio);
2118 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2119 hdmi->audio = platform_device_register_full(&pdevinfo);
7ed6c665
RK		 2120 }
2121
3efc2fa3
VZ		 2122 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2123 if (hdmi->i2c)
2124 dw_hdmi_i2c_init(hdmi);
2125
c608119d 2126 platform_set_drvdata(pdev, hdmi);
9aaf880e 2127
69497eb9 2128 return hdmi;
9aaf880e
FE		 2129
2130err_iahb:
3efc2fa3
VZ		 2131 if (hdmi->i2c) {
2132 i2c_del_adapter(&hdmi->i2c->adap);
2133 hdmi->ddc = NULL;
2134 }
2135
9aaf880e
FE		 2136 clk_disable_unprepare(hdmi->iahb_clk);
2137err_isfr:
2138 clk_disable_unprepare(hdmi->isfr_clk);
9f04a1f2
VZ		 2139err_res:
2140 i2c_put_adapter(hdmi->ddc);
9aaf880e 2141
69497eb9 2142 return ERR_PTR(ret);
9aaf880e
FE		 2143}
2144
69497eb9 2145static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
9aaf880e 2146{
7ed6c665
RK		 2147 if (hdmi->audio && !IS_ERR(hdmi->audio))
2148 platform_device_unregister(hdmi->audio);
2149
d94905e0
RK		 2150 /* Disable all interrupts */
2151 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2152
9aaf880e
FE		 2153 clk_disable_unprepare(hdmi->iahb_clk);
2154 clk_disable_unprepare(hdmi->isfr_clk);
3efc2fa3
VZ		 2155
2156 if (hdmi->i2c)
2157 i2c_del_adapter(&hdmi->i2c->adap);
2158 else
2159 i2c_put_adapter(hdmi->ddc);
17b5001b 2160}
69497eb9
LP		 2161
2162/* -----------------------------------------------------------------------------
2163 * Probe/remove API, used from platforms based on the DRM bridge API.
2164 */
2165int dw_hdmi_probe(struct platform_device *pdev,
2166 const struct dw_hdmi_plat_data *plat_data)
2167{
2168 struct dw_hdmi *hdmi;
2169 int ret;
2170
2171 hdmi = __dw_hdmi_probe(pdev, plat_data);
2172 if (IS_ERR(hdmi))
2173 return PTR_ERR(hdmi);
2174
2175 ret = drm_bridge_add(&hdmi->bridge);
2176 if (ret < 0) {
2177 __dw_hdmi_remove(hdmi);
2178 return ret;
2179 }
2180
2181 return 0;
2182}
2183EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2184
2185void dw_hdmi_remove(struct platform_device *pdev)
2186{
2187 struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
2188
2189 drm_bridge_remove(&hdmi->bridge);
2190
2191 __dw_hdmi_remove(hdmi);
2192}
2193EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2194
2195/* -----------------------------------------------------------------------------
2196 * Bind/unbind API, used from platforms based on the component framework.
2197 */
2198int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2199 const struct dw_hdmi_plat_data *plat_data)
2200{
2201 struct dw_hdmi *hdmi;
2202 int ret;
2203
2204 hdmi = __dw_hdmi_probe(pdev, plat_data);
2205 if (IS_ERR(hdmi))
2206 return PTR_ERR(hdmi);
2207
2208 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2209 if (ret) {
2210 dw_hdmi_remove(pdev);
2211 DRM_ERROR("Failed to initialize bridge with drm\n");
2212 return ret;
2213 }
2214
2215 return 0;
2216}
2217EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2218
2219void dw_hdmi_unbind(struct device *dev)
2220{
2221 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2222
2223 __dw_hdmi_remove(hdmi);
2224}
b21f4b65 2225EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
9aaf880e
FE		 2226
2227MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3d1b35a3
AY		 2228MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2229MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3efc2fa3 2230MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
b21f4b65 2231MODULE_DESCRIPTION("DW HDMI transmitter driver");
9aaf880e 2232MODULE_LICENSE("GPL");
b21f4b65 2233MODULE_ALIAS("platform:dw-hdmi");
Linux 6.x block layer and io_uring tree(s)