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e1923395 BB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright: 2017 Cadence Design Systems, Inc. | |
4 | * | |
5 | * Author: Boris Brezillon <boris.brezillon@bootlin.com> | |
6 | */ | |
7 | ||
8 | #include <drm/drm_atomic_helper.h> | |
9 | #include <drm/drm_bridge.h> | |
6abb4940 | 10 | #include <drm/drm_drv.h> |
e1923395 BB |
11 | #include <drm/drm_mipi_dsi.h> |
12 | #include <drm/drm_panel.h> | |
fcd70cd3 | 13 | #include <drm/drm_probe_helper.h> |
e1923395 BB |
14 | #include <video/mipi_display.h> |
15 | ||
16 | #include <linux/clk.h> | |
6abb4940 | 17 | #include <linux/interrupt.h> |
e1923395 BB |
18 | #include <linux/iopoll.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_graph.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/reset.h> | |
25 | ||
fced5a36 MR |
26 | #include <linux/phy/phy.h> |
27 | #include <linux/phy/phy-mipi-dphy.h> | |
28 | ||
e1923395 BB |
29 | #define IP_CONF 0x0 |
30 | #define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26) | |
31 | #define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21) | |
32 | #define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16) | |
33 | #define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13) | |
34 | #define SDI_IFACE_32 BIT(12) | |
35 | #define INTERNAL_DATAPATH_32 (0 << 10) | |
36 | #define INTERNAL_DATAPATH_16 (1 << 10) | |
37 | #define INTERNAL_DATAPATH_8 (3 << 10) | |
38 | #define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10)) | |
39 | #define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1) | |
40 | #define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6) | |
41 | #define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0)) | |
42 | ||
43 | #define MCTL_MAIN_DATA_CTL 0x4 | |
44 | #define TE_MIPI_POLLING_EN BIT(25) | |
45 | #define TE_HW_POLLING_EN BIT(24) | |
46 | #define DISP_EOT_GEN BIT(18) | |
47 | #define HOST_EOT_GEN BIT(17) | |
48 | #define DISP_GEN_CHECKSUM BIT(16) | |
49 | #define DISP_GEN_ECC BIT(15) | |
50 | #define BTA_EN BIT(14) | |
51 | #define READ_EN BIT(13) | |
52 | #define REG_TE_EN BIT(12) | |
53 | #define IF_TE_EN(x) BIT(8 + (x)) | |
54 | #define TVG_SEL BIT(6) | |
55 | #define VID_EN BIT(5) | |
56 | #define IF_VID_SELECT(x) ((x) << 2) | |
57 | #define IF_VID_SELECT_MASK GENMASK(3, 2) | |
58 | #define IF_VID_MODE BIT(1) | |
59 | #define LINK_EN BIT(0) | |
60 | ||
61 | #define MCTL_MAIN_PHY_CTL 0x8 | |
62 | #define HS_INVERT_DAT(x) BIT(19 + ((x) * 2)) | |
63 | #define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2)) | |
64 | #define HS_INVERT_CLK BIT(17) | |
65 | #define SWAP_PINS_CLK BIT(16) | |
66 | #define HS_SKEWCAL_EN BIT(15) | |
67 | #define WAIT_BURST_TIME(x) ((x) << 10) | |
68 | #define DATA_ULPM_EN(x) BIT(6 + (x)) | |
69 | #define CLK_ULPM_EN BIT(5) | |
70 | #define CLK_CONTINUOUS BIT(4) | |
71 | #define DATA_LANE_EN(x) BIT((x) - 1) | |
72 | ||
73 | #define MCTL_MAIN_EN 0xc | |
74 | #define DATA_FORCE_STOP BIT(17) | |
75 | #define CLK_FORCE_STOP BIT(16) | |
76 | #define IF_EN(x) BIT(13 + (x)) | |
77 | #define DATA_LANE_ULPM_REQ(l) BIT(9 + (l)) | |
78 | #define CLK_LANE_ULPM_REQ BIT(8) | |
79 | #define DATA_LANE_START(x) BIT(4 + (x)) | |
80 | #define CLK_LANE_EN BIT(3) | |
81 | #define PLL_START BIT(0) | |
82 | ||
83 | #define MCTL_DPHY_CFG0 0x10 | |
84 | #define DPHY_C_RSTB BIT(20) | |
85 | #define DPHY_D_RSTB(x) GENMASK(15 + (x), 16) | |
86 | #define DPHY_PLL_PDN BIT(10) | |
87 | #define DPHY_CMN_PDN BIT(9) | |
88 | #define DPHY_C_PDN BIT(8) | |
89 | #define DPHY_D_PDN(x) GENMASK(3 + (x), 4) | |
90 | #define DPHY_ALL_D_PDN GENMASK(7, 4) | |
91 | #define DPHY_PLL_PSO BIT(1) | |
92 | #define DPHY_CMN_PSO BIT(0) | |
93 | ||
94 | #define MCTL_DPHY_TIMEOUT1 0x14 | |
95 | #define HSTX_TIMEOUT(x) ((x) << 4) | |
96 | #define HSTX_TIMEOUT_MAX GENMASK(17, 0) | |
97 | #define CLK_DIV(x) (x) | |
98 | #define CLK_DIV_MAX GENMASK(3, 0) | |
99 | ||
100 | #define MCTL_DPHY_TIMEOUT2 0x18 | |
101 | #define LPRX_TIMEOUT(x) (x) | |
102 | ||
103 | #define MCTL_ULPOUT_TIME 0x1c | |
104 | #define DATA_LANE_ULPOUT_TIME(x) ((x) << 9) | |
105 | #define CLK_LANE_ULPOUT_TIME(x) (x) | |
106 | ||
107 | #define MCTL_3DVIDEO_CTL 0x20 | |
108 | #define VID_VSYNC_3D_EN BIT(7) | |
109 | #define VID_VSYNC_3D_LR BIT(5) | |
110 | #define VID_VSYNC_3D_SECOND_EN BIT(4) | |
111 | #define VID_VSYNC_3DFORMAT_LINE (0 << 2) | |
112 | #define VID_VSYNC_3DFORMAT_FRAME (1 << 2) | |
113 | #define VID_VSYNC_3DFORMAT_PIXEL (2 << 2) | |
114 | #define VID_VSYNC_3DMODE_OFF 0 | |
115 | #define VID_VSYNC_3DMODE_PORTRAIT 1 | |
116 | #define VID_VSYNC_3DMODE_LANDSCAPE 2 | |
117 | ||
118 | #define MCTL_MAIN_STS 0x24 | |
119 | #define MCTL_MAIN_STS_CTL 0x130 | |
120 | #define MCTL_MAIN_STS_CLR 0x150 | |
121 | #define MCTL_MAIN_STS_FLAG 0x170 | |
122 | #define HS_SKEWCAL_DONE BIT(11) | |
123 | #define IF_UNTERM_PKT_ERR(x) BIT(8 + (x)) | |
124 | #define LPRX_TIMEOUT_ERR BIT(7) | |
125 | #define HSTX_TIMEOUT_ERR BIT(6) | |
126 | #define DATA_LANE_RDY(l) BIT(2 + (l)) | |
127 | #define CLK_LANE_RDY BIT(1) | |
128 | #define PLL_LOCKED BIT(0) | |
129 | ||
130 | #define MCTL_DPHY_ERR 0x28 | |
131 | #define MCTL_DPHY_ERR_CTL1 0x148 | |
132 | #define MCTL_DPHY_ERR_CLR 0x168 | |
133 | #define MCTL_DPHY_ERR_FLAG 0x188 | |
134 | #define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l)) | |
135 | #define ERR_CONTROL(l) BIT(14 + (l)) | |
136 | #define ERR_SYNESC(l) BIT(10 + (l)) | |
137 | #define ERR_ESC(l) BIT(6 + (l)) | |
138 | ||
139 | #define MCTL_DPHY_ERR_CTL2 0x14c | |
140 | #define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l)) | |
141 | #define ERR_CONTROL_EDGE(l) BIT(8 + (l)) | |
142 | #define ERR_SYN_ESC_EDGE(l) BIT(4 + (l)) | |
143 | #define ERR_ESC_EDGE(l) BIT(0 + (l)) | |
144 | ||
145 | #define MCTL_LANE_STS 0x2c | |
146 | #define PPI_C_TX_READY_HS BIT(18) | |
147 | #define DPHY_PLL_LOCK BIT(17) | |
148 | #define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12) | |
149 | #define LANE_STATE_START 0 | |
150 | #define LANE_STATE_IDLE 1 | |
151 | #define LANE_STATE_WRITE 2 | |
152 | #define LANE_STATE_ULPM 3 | |
153 | #define LANE_STATE_READ 4 | |
154 | #define DATA_LANE_STATE(l, val) \ | |
155 | (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0)) | |
156 | #define CLK_LANE_STATE_HS 2 | |
157 | #define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0)) | |
158 | ||
159 | #define DSC_MODE_CTL 0x30 | |
160 | #define DSC_MODE_EN BIT(0) | |
161 | ||
162 | #define DSC_CMD_SEND 0x34 | |
163 | #define DSC_SEND_PPS BIT(0) | |
164 | #define DSC_EXECUTE_QUEUE BIT(1) | |
165 | ||
166 | #define DSC_PPS_WRDAT 0x38 | |
167 | ||
168 | #define DSC_MODE_STS 0x3c | |
169 | #define DSC_PPS_DONE BIT(1) | |
170 | #define DSC_EXEC_DONE BIT(2) | |
171 | ||
172 | #define CMD_MODE_CTL 0x70 | |
173 | #define IF_LP_EN(x) BIT(9 + (x)) | |
174 | #define IF_VCHAN_ID(x, c) ((c) << ((x) * 2)) | |
175 | ||
176 | #define CMD_MODE_CTL2 0x74 | |
177 | #define TE_TIMEOUT(x) ((x) << 11) | |
178 | #define FILL_VALUE(x) ((x) << 3) | |
179 | #define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1) | |
180 | #define ARB_ROUND_ROBIN_MODE BIT(0) | |
181 | ||
182 | #define CMD_MODE_STS 0x78 | |
183 | #define CMD_MODE_STS_CTL 0x134 | |
184 | #define CMD_MODE_STS_CLR 0x154 | |
185 | #define CMD_MODE_STS_FLAG 0x174 | |
186 | #define ERR_IF_UNDERRUN(x) BIT(4 + (x)) | |
187 | #define ERR_UNWANTED_READ BIT(3) | |
188 | #define ERR_TE_MISS BIT(2) | |
189 | #define ERR_NO_TE BIT(1) | |
190 | #define CSM_RUNNING BIT(0) | |
191 | ||
192 | #define DIRECT_CMD_SEND 0x80 | |
193 | ||
194 | #define DIRECT_CMD_MAIN_SETTINGS 0x84 | |
195 | #define TRIGGER_VAL(x) ((x) << 25) | |
196 | #define CMD_LP_EN BIT(24) | |
197 | #define CMD_SIZE(x) ((x) << 16) | |
198 | #define CMD_VCHAN_ID(x) ((x) << 14) | |
199 | #define CMD_DATATYPE(x) ((x) << 8) | |
200 | #define CMD_LONG BIT(3) | |
201 | #define WRITE_CMD 0 | |
202 | #define READ_CMD 1 | |
203 | #define TE_REQ 4 | |
204 | #define TRIGGER_REQ 5 | |
205 | #define BTA_REQ 6 | |
206 | ||
207 | #define DIRECT_CMD_STS 0x88 | |
208 | #define DIRECT_CMD_STS_CTL 0x138 | |
209 | #define DIRECT_CMD_STS_CLR 0x158 | |
210 | #define DIRECT_CMD_STS_FLAG 0x178 | |
211 | #define RCVD_ACK_VAL(val) ((val) >> 16) | |
212 | #define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11) | |
213 | #define READ_COMPLETED_WITH_ERR BIT(10) | |
214 | #define BTA_FINISHED BIT(9) | |
215 | #define BTA_COMPLETED BIT(8) | |
216 | #define TE_RCVD BIT(7) | |
217 | #define TRIGGER_RCVD BIT(6) | |
218 | #define ACK_WITH_ERR_RCVD BIT(5) | |
219 | #define ACK_RCVD BIT(4) | |
220 | #define READ_COMPLETED BIT(3) | |
221 | #define TRIGGER_COMPLETED BIT(2) | |
222 | #define WRITE_COMPLETED BIT(1) | |
223 | #define SENDING_CMD BIT(0) | |
224 | ||
225 | #define DIRECT_CMD_STOP_READ 0x8c | |
226 | ||
227 | #define DIRECT_CMD_WRDATA 0x90 | |
228 | ||
229 | #define DIRECT_CMD_FIFO_RST 0x94 | |
230 | ||
231 | #define DIRECT_CMD_RDDATA 0xa0 | |
232 | ||
233 | #define DIRECT_CMD_RD_PROPS 0xa4 | |
234 | #define RD_DCS BIT(18) | |
235 | #define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0)) | |
236 | #define RD_SIZE(val) ((val) & GENMASK(15, 0)) | |
237 | ||
238 | #define DIRECT_CMD_RD_STS 0xa8 | |
239 | #define DIRECT_CMD_RD_STS_CTL 0x13c | |
240 | #define DIRECT_CMD_RD_STS_CLR 0x15c | |
241 | #define DIRECT_CMD_RD_STS_FLAG 0x17c | |
242 | #define ERR_EOT_WITH_ERR BIT(8) | |
243 | #define ERR_MISSING_EOT BIT(7) | |
244 | #define ERR_WRONG_LENGTH BIT(6) | |
245 | #define ERR_OVERSIZE BIT(5) | |
246 | #define ERR_RECEIVE BIT(4) | |
247 | #define ERR_UNDECODABLE BIT(3) | |
248 | #define ERR_CHECKSUM BIT(2) | |
249 | #define ERR_UNCORRECTABLE BIT(1) | |
250 | #define ERR_FIXED BIT(0) | |
251 | ||
252 | #define VID_MAIN_CTL 0xb0 | |
253 | #define VID_IGNORE_MISS_VSYNC BIT(31) | |
254 | #define VID_FIELD_SW BIT(28) | |
255 | #define VID_INTERLACED_EN BIT(27) | |
256 | #define RECOVERY_MODE(x) ((x) << 25) | |
257 | #define RECOVERY_MODE_NEXT_HSYNC 0 | |
258 | #define RECOVERY_MODE_NEXT_STOP_POINT 2 | |
259 | #define RECOVERY_MODE_NEXT_VSYNC 3 | |
260 | #define REG_BLKEOL_MODE(x) ((x) << 23) | |
261 | #define REG_BLKLINE_MODE(x) ((x) << 21) | |
262 | #define REG_BLK_MODE_NULL_PKT 0 | |
263 | #define REG_BLK_MODE_BLANKING_PKT 1 | |
264 | #define REG_BLK_MODE_LP 2 | |
265 | #define SYNC_PULSE_HORIZONTAL BIT(20) | |
266 | #define SYNC_PULSE_ACTIVE BIT(19) | |
267 | #define BURST_MODE BIT(18) | |
268 | #define VID_PIXEL_MODE_MASK GENMASK(17, 14) | |
269 | #define VID_PIXEL_MODE_RGB565 (0 << 14) | |
270 | #define VID_PIXEL_MODE_RGB666_PACKED (1 << 14) | |
271 | #define VID_PIXEL_MODE_RGB666 (2 << 14) | |
272 | #define VID_PIXEL_MODE_RGB888 (3 << 14) | |
273 | #define VID_PIXEL_MODE_RGB101010 (4 << 14) | |
274 | #define VID_PIXEL_MODE_RGB121212 (5 << 14) | |
275 | #define VID_PIXEL_MODE_YUV420 (8 << 14) | |
276 | #define VID_PIXEL_MODE_YUV422_PACKED (9 << 14) | |
277 | #define VID_PIXEL_MODE_YUV422 (10 << 14) | |
278 | #define VID_PIXEL_MODE_YUV422_24B (11 << 14) | |
279 | #define VID_PIXEL_MODE_DSC_COMP (12 << 14) | |
280 | #define VID_DATATYPE(x) ((x) << 8) | |
281 | #define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2)) | |
282 | #define STOP_MODE(x) ((x) << 2) | |
283 | #define START_MODE(x) (x) | |
284 | ||
285 | #define VID_VSIZE1 0xb4 | |
286 | #define VFP_LEN(x) ((x) << 12) | |
287 | #define VBP_LEN(x) ((x) << 6) | |
288 | #define VSA_LEN(x) (x) | |
289 | ||
290 | #define VID_VSIZE2 0xb8 | |
291 | #define VACT_LEN(x) (x) | |
292 | ||
293 | #define VID_HSIZE1 0xc0 | |
294 | #define HBP_LEN(x) ((x) << 16) | |
295 | #define HSA_LEN(x) (x) | |
296 | ||
297 | #define VID_HSIZE2 0xc4 | |
298 | #define HFP_LEN(x) ((x) << 16) | |
299 | #define HACT_LEN(x) (x) | |
300 | ||
301 | #define VID_BLKSIZE1 0xcc | |
302 | #define BLK_EOL_PKT_LEN(x) ((x) << 15) | |
303 | #define BLK_LINE_EVENT_PKT_LEN(x) (x) | |
304 | ||
305 | #define VID_BLKSIZE2 0xd0 | |
306 | #define BLK_LINE_PULSE_PKT_LEN(x) (x) | |
307 | ||
308 | #define VID_PKT_TIME 0xd8 | |
309 | #define BLK_EOL_DURATION(x) (x) | |
310 | ||
311 | #define VID_DPHY_TIME 0xdc | |
312 | #define REG_WAKEUP_TIME(x) ((x) << 17) | |
313 | #define REG_LINE_DURATION(x) (x) | |
314 | ||
315 | #define VID_ERR_COLOR1 0xe0 | |
316 | #define COL_GREEN(x) ((x) << 12) | |
317 | #define COL_RED(x) (x) | |
318 | ||
319 | #define VID_ERR_COLOR2 0xe4 | |
320 | #define PAD_VAL(x) ((x) << 12) | |
321 | #define COL_BLUE(x) (x) | |
322 | ||
323 | #define VID_VPOS 0xe8 | |
324 | #define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2) | |
325 | #define LINE_POS(val) ((val) & GENMASK(1, 0)) | |
326 | ||
327 | #define VID_HPOS 0xec | |
328 | #define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3) | |
329 | #define HORIZ_POS(val) ((val) & GENMASK(2, 0)) | |
330 | ||
331 | #define VID_MODE_STS 0xf0 | |
332 | #define VID_MODE_STS_CTL 0x140 | |
333 | #define VID_MODE_STS_CLR 0x160 | |
334 | #define VID_MODE_STS_FLAG 0x180 | |
335 | #define VSG_RECOVERY BIT(10) | |
336 | #define ERR_VRS_WRONG_LEN BIT(9) | |
337 | #define ERR_LONG_READ BIT(8) | |
338 | #define ERR_LINE_WRITE BIT(7) | |
339 | #define ERR_BURST_WRITE BIT(6) | |
340 | #define ERR_SMALL_HEIGHT BIT(5) | |
341 | #define ERR_SMALL_LEN BIT(4) | |
342 | #define ERR_MISSING_VSYNC BIT(3) | |
343 | #define ERR_MISSING_HSYNC BIT(2) | |
344 | #define ERR_MISSING_DATA BIT(1) | |
345 | #define VSG_RUNNING BIT(0) | |
346 | ||
347 | #define VID_VCA_SETTING1 0xf4 | |
348 | #define BURST_LP BIT(16) | |
349 | #define MAX_BURST_LIMIT(x) (x) | |
350 | ||
351 | #define VID_VCA_SETTING2 0xf8 | |
352 | #define MAX_LINE_LIMIT(x) ((x) << 16) | |
353 | #define EXACT_BURST_LIMIT(x) (x) | |
354 | ||
355 | #define TVG_CTL 0xfc | |
356 | #define TVG_STRIPE_SIZE(x) ((x) << 5) | |
357 | #define TVG_MODE_MASK GENMASK(4, 3) | |
358 | #define TVG_MODE_SINGLE_COLOR (0 << 3) | |
359 | #define TVG_MODE_VSTRIPES (2 << 3) | |
360 | #define TVG_MODE_HSTRIPES (3 << 3) | |
361 | #define TVG_STOPMODE_MASK GENMASK(2, 1) | |
362 | #define TVG_STOPMODE_EOF (0 << 1) | |
363 | #define TVG_STOPMODE_EOL (1 << 1) | |
364 | #define TVG_STOPMODE_NOW (2 << 1) | |
365 | #define TVG_RUN BIT(0) | |
366 | ||
367 | #define TVG_IMG_SIZE 0x100 | |
368 | #define TVG_NBLINES(x) ((x) << 16) | |
369 | #define TVG_LINE_SIZE(x) (x) | |
370 | ||
371 | #define TVG_COLOR1 0x104 | |
372 | #define TVG_COL1_GREEN(x) ((x) << 12) | |
373 | #define TVG_COL1_RED(x) (x) | |
374 | ||
375 | #define TVG_COLOR1_BIS 0x108 | |
376 | #define TVG_COL1_BLUE(x) (x) | |
377 | ||
378 | #define TVG_COLOR2 0x10c | |
379 | #define TVG_COL2_GREEN(x) ((x) << 12) | |
380 | #define TVG_COL2_RED(x) (x) | |
381 | ||
382 | #define TVG_COLOR2_BIS 0x110 | |
383 | #define TVG_COL2_BLUE(x) (x) | |
384 | ||
385 | #define TVG_STS 0x114 | |
386 | #define TVG_STS_CTL 0x144 | |
387 | #define TVG_STS_CLR 0x164 | |
388 | #define TVG_STS_FLAG 0x184 | |
389 | #define TVG_STS_RUNNING BIT(0) | |
390 | ||
391 | #define STS_CTL_EDGE(e) ((e) << 16) | |
392 | ||
393 | #define DPHY_LANES_MAP 0x198 | |
394 | #define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8)) | |
395 | ||
396 | #define DPI_IRQ_EN 0x1a0 | |
397 | #define DPI_IRQ_CLR 0x1a4 | |
398 | #define DPI_IRQ_STS 0x1a8 | |
399 | #define PIXEL_BUF_OVERFLOW BIT(0) | |
400 | ||
401 | #define DPI_CFG 0x1ac | |
402 | #define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16) | |
403 | #define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0)) | |
404 | ||
405 | #define TEST_GENERIC 0x1f0 | |
406 | #define TEST_STATUS(x) ((x) >> 16) | |
407 | #define TEST_CTRL(x) (x) | |
408 | ||
409 | #define ID_REG 0x1fc | |
410 | #define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20) | |
411 | #define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12) | |
412 | #define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8) | |
413 | #define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4) | |
414 | #define REV_MINOR(x) ((x) & GENMASK(3, 0)) | |
415 | ||
416 | #define DSI_OUTPUT_PORT 0 | |
417 | #define DSI_INPUT_PORT(inputid) (1 + (inputid)) | |
418 | ||
419 | #define DSI_HBP_FRAME_OVERHEAD 12 | |
420 | #define DSI_HSA_FRAME_OVERHEAD 14 | |
421 | #define DSI_HFP_FRAME_OVERHEAD 6 | |
422 | #define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4 | |
423 | #define DSI_BLANKING_FRAME_OVERHEAD 6 | |
424 | #define DSI_NULL_FRAME_OVERHEAD 6 | |
425 | #define DSI_EOT_PKT_SIZE 4 | |
426 | ||
e1923395 BB |
427 | struct cdns_dsi_output { |
428 | struct mipi_dsi_device *dev; | |
429 | struct drm_panel *panel; | |
430 | struct drm_bridge *bridge; | |
fced5a36 | 431 | union phy_configure_opts phy_opts; |
e1923395 BB |
432 | }; |
433 | ||
434 | enum cdns_dsi_input_id { | |
435 | CDNS_SDI_INPUT, | |
436 | CDNS_DPI_INPUT, | |
437 | CDNS_DSC_INPUT, | |
438 | }; | |
439 | ||
e1923395 BB |
440 | struct cdns_dsi_cfg { |
441 | unsigned int hfp; | |
442 | unsigned int hsa; | |
443 | unsigned int hbp; | |
444 | unsigned int hact; | |
445 | unsigned int htotal; | |
446 | }; | |
447 | ||
e1923395 BB |
448 | struct cdns_dsi_input { |
449 | enum cdns_dsi_input_id id; | |
450 | struct drm_bridge bridge; | |
451 | }; | |
452 | ||
453 | struct cdns_dsi { | |
454 | struct mipi_dsi_host base; | |
455 | void __iomem *regs; | |
456 | struct cdns_dsi_input input; | |
457 | struct cdns_dsi_output output; | |
458 | unsigned int direct_cmd_fifo_depth; | |
459 | unsigned int rx_fifo_depth; | |
460 | struct completion direct_cmd_comp; | |
461 | struct clk *dsi_p_clk; | |
462 | struct reset_control *dsi_p_rst; | |
463 | struct clk *dsi_sys_clk; | |
464 | bool link_initialized; | |
fced5a36 | 465 | struct phy *dphy; |
e1923395 BB |
466 | }; |
467 | ||
468 | static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input) | |
469 | { | |
470 | return container_of(input, struct cdns_dsi, input); | |
471 | } | |
472 | ||
473 | static inline struct cdns_dsi *to_cdns_dsi(struct mipi_dsi_host *host) | |
474 | { | |
475 | return container_of(host, struct cdns_dsi, base); | |
476 | } | |
477 | ||
478 | static inline struct cdns_dsi_input * | |
479 | bridge_to_cdns_dsi_input(struct drm_bridge *bridge) | |
480 | { | |
481 | return container_of(bridge, struct cdns_dsi_input, bridge); | |
482 | } | |
483 | ||
4dad3e7f MR |
484 | static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode, |
485 | bool mode_valid_check) | |
486 | { | |
487 | if (mode_valid_check) | |
488 | return mode->hsync_start - mode->hdisplay; | |
489 | ||
490 | return mode->crtc_hsync_start - mode->crtc_hdisplay; | |
491 | } | |
492 | ||
e1923395 BB |
493 | static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing, |
494 | unsigned int dpi_bpp, | |
495 | unsigned int dsi_pkt_overhead) | |
496 | { | |
497 | unsigned int dsi_timing = DIV_ROUND_UP(dpi_timing * dpi_bpp, 8); | |
498 | ||
499 | if (dsi_timing < dsi_pkt_overhead) | |
500 | dsi_timing = 0; | |
501 | else | |
502 | dsi_timing -= dsi_pkt_overhead; | |
503 | ||
504 | return dsi_timing; | |
505 | } | |
506 | ||
507 | static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, | |
508 | const struct drm_display_mode *mode, | |
509 | struct cdns_dsi_cfg *dsi_cfg, | |
e1923395 BB |
510 | bool mode_valid_check) |
511 | { | |
e1923395 | 512 | struct cdns_dsi_output *output = &dsi->output; |
4dad3e7f | 513 | unsigned int tmp; |
e1923395 | 514 | bool sync_pulse = false; |
810c7736 | 515 | int bpp; |
e1923395 BB |
516 | |
517 | memset(dsi_cfg, 0, sizeof(*dsi_cfg)); | |
518 | ||
519 | if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
520 | sync_pulse = true; | |
521 | ||
522 | bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); | |
e1923395 BB |
523 | |
524 | if (mode_valid_check) | |
525 | tmp = mode->htotal - | |
526 | (sync_pulse ? mode->hsync_end : mode->hsync_start); | |
527 | else | |
528 | tmp = mode->crtc_htotal - | |
529 | (sync_pulse ? | |
530 | mode->crtc_hsync_end : mode->crtc_hsync_start); | |
531 | ||
532 | dsi_cfg->hbp = dpi_to_dsi_timing(tmp, bpp, DSI_HBP_FRAME_OVERHEAD); | |
e1923395 BB |
533 | |
534 | if (sync_pulse) { | |
535 | if (mode_valid_check) | |
536 | tmp = mode->hsync_end - mode->hsync_start; | |
537 | else | |
538 | tmp = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
539 | ||
540 | dsi_cfg->hsa = dpi_to_dsi_timing(tmp, bpp, | |
541 | DSI_HSA_FRAME_OVERHEAD); | |
e1923395 BB |
542 | } |
543 | ||
544 | dsi_cfg->hact = dpi_to_dsi_timing(mode_valid_check ? | |
545 | mode->hdisplay : mode->crtc_hdisplay, | |
546 | bpp, 0); | |
4dad3e7f MR |
547 | dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check), |
548 | bpp, DSI_HFP_FRAME_OVERHEAD); | |
e1923395 | 549 | |
4dad3e7f MR |
550 | return 0; |
551 | } | |
552 | ||
fced5a36 | 553 | static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi, |
4dad3e7f | 554 | struct cdns_dsi_cfg *dsi_cfg, |
fced5a36 | 555 | struct phy_configure_opts_mipi_dphy *phy_cfg, |
4dad3e7f MR |
556 | const struct drm_display_mode *mode, |
557 | bool mode_valid_check) | |
558 | { | |
559 | struct cdns_dsi_output *output = &dsi->output; | |
fced5a36 MR |
560 | unsigned long long dlane_bps; |
561 | unsigned long adj_dsi_htotal; | |
4dad3e7f | 562 | unsigned long dsi_htotal; |
fced5a36 MR |
563 | unsigned long dpi_htotal; |
564 | unsigned long dpi_hz; | |
565 | unsigned int dsi_hfp_ext; | |
566 | unsigned int lanes = output->dev->lanes; | |
4dad3e7f MR |
567 | |
568 | dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD; | |
569 | if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
570 | dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD; | |
e1923395 | 571 | |
4dad3e7f | 572 | dsi_htotal += dsi_cfg->hact; |
e1923395 BB |
573 | dsi_htotal += dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD; |
574 | ||
fced5a36 MR |
575 | /* |
576 | * Make sure DSI htotal is aligned on a lane boundary when calculating | |
577 | * the expected data rate. This is done by extending HFP in case of | |
578 | * misalignment. | |
579 | */ | |
580 | adj_dsi_htotal = dsi_htotal; | |
581 | if (dsi_htotal % lanes) | |
582 | adj_dsi_htotal += lanes - (dsi_htotal % lanes); | |
583 | ||
584 | dpi_hz = (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000; | |
585 | dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal; | |
586 | ||
587 | /* data rate in bytes/sec is not an integer, refuse the mode. */ | |
588 | dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal; | |
589 | if (do_div(dlane_bps, lanes * dpi_htotal)) | |
590 | return -EINVAL; | |
e1923395 | 591 | |
fced5a36 MR |
592 | /* data rate was in bytes/sec, convert to bits/sec. */ |
593 | phy_cfg->hs_clk_rate = dlane_bps * 8; | |
594 | ||
595 | dsi_hfp_ext = adj_dsi_htotal - dsi_htotal; | |
e1923395 | 596 | dsi_cfg->hfp += dsi_hfp_ext; |
4dad3e7f MR |
597 | dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext; |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | static int cdns_dsi_check_conf(struct cdns_dsi *dsi, | |
603 | const struct drm_display_mode *mode, | |
604 | struct cdns_dsi_cfg *dsi_cfg, | |
4dad3e7f MR |
605 | bool mode_valid_check) |
606 | { | |
607 | struct cdns_dsi_output *output = &dsi->output; | |
fced5a36 | 608 | struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy; |
4dad3e7f MR |
609 | unsigned long dsi_hss_hsa_hse_hbp; |
610 | unsigned int nlanes = output->dev->lanes; | |
611 | int ret; | |
612 | ||
613 | ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check); | |
614 | if (ret) | |
615 | return ret; | |
616 | ||
fced5a36 MR |
617 | phy_mipi_dphy_get_default_config(mode->crtc_clock * 1000, |
618 | mipi_dsi_pixel_format_to_bpp(output->dev->format), | |
619 | nlanes, phy_cfg); | |
620 | ||
621 | ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode, mode_valid_check); | |
622 | if (ret) | |
623 | return ret; | |
624 | ||
625 | ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &output->phy_opts); | |
4dad3e7f MR |
626 | if (ret) |
627 | return ret; | |
628 | ||
629 | dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD; | |
630 | if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
631 | dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD; | |
e1923395 BB |
632 | |
633 | /* | |
634 | * Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO | |
635 | * is empty before we start a receiving a new line on the DPI | |
636 | * interface. | |
637 | */ | |
fced5a36 | 638 | if ((u64)phy_cfg->hs_clk_rate * |
4dad3e7f | 639 | mode_to_dpi_hfp(mode, mode_valid_check) * nlanes < |
e1923395 BB |
640 | (u64)dsi_hss_hsa_hse_hbp * |
641 | (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000) | |
642 | return -EINVAL; | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
a25b988f LP |
647 | static int cdns_dsi_bridge_attach(struct drm_bridge *bridge, |
648 | enum drm_bridge_attach_flags flags) | |
e1923395 BB |
649 | { |
650 | struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); | |
651 | struct cdns_dsi *dsi = input_to_dsi(input); | |
652 | struct cdns_dsi_output *output = &dsi->output; | |
653 | ||
654 | if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { | |
655 | dev_err(dsi->base.dev, | |
656 | "cdns-dsi driver is only compatible with DRM devices supporting atomic updates"); | |
657 | return -ENOTSUPP; | |
658 | } | |
659 | ||
a25b988f LP |
660 | return drm_bridge_attach(bridge->encoder, output->bridge, bridge, |
661 | flags); | |
e1923395 BB |
662 | } |
663 | ||
664 | static enum drm_mode_status | |
665 | cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge, | |
12c683e1 | 666 | const struct drm_display_info *info, |
e1923395 BB |
667 | const struct drm_display_mode *mode) |
668 | { | |
669 | struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); | |
670 | struct cdns_dsi *dsi = input_to_dsi(input); | |
671 | struct cdns_dsi_output *output = &dsi->output; | |
e1923395 | 672 | struct cdns_dsi_cfg dsi_cfg; |
4dad3e7f | 673 | int bpp, ret; |
e1923395 BB |
674 | |
675 | /* | |
676 | * VFP_DSI should be less than VFP_DPI and VFP_DSI should be at | |
677 | * least 1. | |
678 | */ | |
679 | if (mode->vtotal - mode->vsync_end < 2) | |
680 | return MODE_V_ILLEGAL; | |
681 | ||
682 | /* VSA_DSI = VSA_DPI and must be at least 2. */ | |
683 | if (mode->vsync_end - mode->vsync_start < 2) | |
684 | return MODE_V_ILLEGAL; | |
685 | ||
686 | /* HACT must be 32-bits aligned. */ | |
687 | bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); | |
688 | if ((mode->hdisplay * bpp) % 32) | |
689 | return MODE_H_ILLEGAL; | |
690 | ||
fced5a36 | 691 | ret = cdns_dsi_check_conf(dsi, mode, &dsi_cfg, true); |
e1923395 | 692 | if (ret) |
4dad3e7f | 693 | return MODE_BAD; |
e1923395 BB |
694 | |
695 | return MODE_OK; | |
696 | } | |
697 | ||
698 | static void cdns_dsi_bridge_disable(struct drm_bridge *bridge) | |
699 | { | |
700 | struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); | |
701 | struct cdns_dsi *dsi = input_to_dsi(input); | |
702 | u32 val; | |
703 | ||
704 | val = readl(dsi->regs + MCTL_MAIN_DATA_CTL); | |
705 | val &= ~(IF_VID_SELECT_MASK | IF_VID_MODE | VID_EN | HOST_EOT_GEN | | |
706 | DISP_EOT_GEN); | |
707 | writel(val, dsi->regs + MCTL_MAIN_DATA_CTL); | |
708 | ||
709 | val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id); | |
710 | writel(val, dsi->regs + MCTL_MAIN_EN); | |
711 | pm_runtime_put(dsi->base.dev); | |
712 | } | |
713 | ||
fced5a36 | 714 | static void cdns_dsi_hs_init(struct cdns_dsi *dsi) |
e1923395 | 715 | { |
fced5a36 | 716 | struct cdns_dsi_output *output = &dsi->output; |
e1923395 BB |
717 | u32 status; |
718 | ||
719 | /* | |
720 | * Power all internal DPHY blocks down and maintain their reset line | |
721 | * asserted before changing the DPHY config. | |
722 | */ | |
723 | writel(DPHY_CMN_PSO | DPHY_PLL_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | | |
724 | DPHY_CMN_PDN | DPHY_PLL_PDN, | |
725 | dsi->regs + MCTL_DPHY_CFG0); | |
726 | ||
fced5a36 MR |
727 | phy_init(dsi->dphy); |
728 | phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY); | |
729 | phy_configure(dsi->dphy, &output->phy_opts); | |
730 | phy_power_on(dsi->dphy); | |
e1923395 BB |
731 | |
732 | /* Activate the PLL and wait until it's locked. */ | |
733 | writel(PLL_LOCKED, dsi->regs + MCTL_MAIN_STS_CLR); | |
734 | writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN, | |
735 | dsi->regs + MCTL_DPHY_CFG0); | |
736 | WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status, | |
737 | status & PLL_LOCKED, 100, 100)); | |
738 | /* De-assert data and clock reset lines. */ | |
739 | writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN | | |
fced5a36 | 740 | DPHY_D_RSTB(output->dev->lanes) | DPHY_C_RSTB, |
e1923395 BB |
741 | dsi->regs + MCTL_DPHY_CFG0); |
742 | } | |
743 | ||
744 | static void cdns_dsi_init_link(struct cdns_dsi *dsi) | |
745 | { | |
746 | struct cdns_dsi_output *output = &dsi->output; | |
747 | unsigned long sysclk_period, ulpout; | |
748 | u32 val; | |
749 | int i; | |
750 | ||
751 | if (dsi->link_initialized) | |
752 | return; | |
753 | ||
754 | val = 0; | |
755 | for (i = 1; i < output->dev->lanes; i++) | |
756 | val |= DATA_LANE_EN(i); | |
757 | ||
758 | if (!(output->dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) | |
759 | val |= CLK_CONTINUOUS; | |
760 | ||
761 | writel(val, dsi->regs + MCTL_MAIN_PHY_CTL); | |
762 | ||
763 | /* ULPOUT should be set to 1ms and is expressed in sysclk cycles. */ | |
764 | sysclk_period = NSEC_PER_SEC / clk_get_rate(dsi->dsi_sys_clk); | |
765 | ulpout = DIV_ROUND_UP(NSEC_PER_MSEC, sysclk_period); | |
766 | writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout), | |
767 | dsi->regs + MCTL_ULPOUT_TIME); | |
768 | ||
769 | writel(LINK_EN, dsi->regs + MCTL_MAIN_DATA_CTL); | |
770 | ||
771 | val = CLK_LANE_EN | PLL_START; | |
772 | for (i = 0; i < output->dev->lanes; i++) | |
773 | val |= DATA_LANE_START(i); | |
774 | ||
775 | writel(val, dsi->regs + MCTL_MAIN_EN); | |
776 | ||
777 | dsi->link_initialized = true; | |
778 | } | |
779 | ||
780 | static void cdns_dsi_bridge_enable(struct drm_bridge *bridge) | |
781 | { | |
782 | struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); | |
783 | struct cdns_dsi *dsi = input_to_dsi(input); | |
784 | struct cdns_dsi_output *output = &dsi->output; | |
785 | struct drm_display_mode *mode; | |
fced5a36 | 786 | struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy; |
e1923395 BB |
787 | unsigned long tx_byte_period; |
788 | struct cdns_dsi_cfg dsi_cfg; | |
789 | u32 tmp, reg_wakeup, div; | |
303e2a3c | 790 | int nlanes; |
e1923395 BB |
791 | |
792 | if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0)) | |
793 | return; | |
794 | ||
795 | mode = &bridge->encoder->crtc->state->adjusted_mode; | |
e1923395 BB |
796 | nlanes = output->dev->lanes; |
797 | ||
fced5a36 | 798 | WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false)); |
e1923395 | 799 | |
fced5a36 | 800 | cdns_dsi_hs_init(dsi); |
e1923395 BB |
801 | cdns_dsi_init_link(dsi); |
802 | ||
803 | writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa), | |
804 | dsi->regs + VID_HSIZE1); | |
805 | writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact), | |
806 | dsi->regs + VID_HSIZE2); | |
807 | ||
808 | writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end - 1) | | |
809 | VFP_LEN(mode->crtc_vsync_start - mode->crtc_vdisplay) | | |
810 | VSA_LEN(mode->crtc_vsync_end - mode->crtc_vsync_start + 1), | |
811 | dsi->regs + VID_VSIZE1); | |
812 | writel(mode->crtc_vdisplay, dsi->regs + VID_VSIZE2); | |
813 | ||
814 | tmp = dsi_cfg.htotal - | |
815 | (dsi_cfg.hsa + DSI_BLANKING_FRAME_OVERHEAD + | |
816 | DSI_HSA_FRAME_OVERHEAD); | |
817 | writel(BLK_LINE_PULSE_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE2); | |
818 | if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
819 | writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD), | |
820 | dsi->regs + VID_VCA_SETTING2); | |
821 | ||
822 | tmp = dsi_cfg.htotal - | |
823 | (DSI_HSS_VSS_VSE_FRAME_OVERHEAD + DSI_BLANKING_FRAME_OVERHEAD); | |
824 | writel(BLK_LINE_EVENT_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE1); | |
825 | if (!(output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) | |
826 | writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD), | |
827 | dsi->regs + VID_VCA_SETTING2); | |
828 | ||
829 | tmp = DIV_ROUND_UP(dsi_cfg.htotal, nlanes) - | |
830 | DIV_ROUND_UP(dsi_cfg.hsa, nlanes); | |
831 | ||
0f3b68b6 | 832 | if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)) |
e1923395 BB |
833 | tmp -= DIV_ROUND_UP(DSI_EOT_PKT_SIZE, nlanes); |
834 | ||
835 | tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8, | |
fced5a36 MR |
836 | phy_cfg->hs_clk_rate); |
837 | reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period; | |
e1923395 BB |
838 | writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp), |
839 | dsi->regs + VID_DPHY_TIME); | |
840 | ||
841 | /* | |
842 | * HSTX and LPRX timeouts are both expressed in TX byte clk cycles and | |
843 | * both should be set to at least the time it takes to transmit a | |
844 | * frame. | |
845 | */ | |
846 | tmp = NSEC_PER_SEC / drm_mode_vrefresh(mode); | |
847 | tmp /= tx_byte_period; | |
848 | ||
849 | for (div = 0; div <= CLK_DIV_MAX; div++) { | |
850 | if (tmp <= HSTX_TIMEOUT_MAX) | |
851 | break; | |
852 | ||
853 | tmp >>= 1; | |
854 | } | |
855 | ||
856 | if (tmp > HSTX_TIMEOUT_MAX) | |
857 | tmp = HSTX_TIMEOUT_MAX; | |
858 | ||
859 | writel(CLK_DIV(div) | HSTX_TIMEOUT(tmp), | |
860 | dsi->regs + MCTL_DPHY_TIMEOUT1); | |
861 | ||
862 | writel(LPRX_TIMEOUT(tmp), dsi->regs + MCTL_DPHY_TIMEOUT2); | |
863 | ||
864 | if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
865 | switch (output->dev->format) { | |
866 | case MIPI_DSI_FMT_RGB888: | |
867 | tmp = VID_PIXEL_MODE_RGB888 | | |
868 | VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_24); | |
869 | break; | |
870 | ||
871 | case MIPI_DSI_FMT_RGB666: | |
872 | tmp = VID_PIXEL_MODE_RGB666 | | |
873 | VID_DATATYPE(MIPI_DSI_PIXEL_STREAM_3BYTE_18); | |
874 | break; | |
875 | ||
876 | case MIPI_DSI_FMT_RGB666_PACKED: | |
877 | tmp = VID_PIXEL_MODE_RGB666_PACKED | | |
878 | VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_18); | |
879 | break; | |
880 | ||
881 | case MIPI_DSI_FMT_RGB565: | |
882 | tmp = VID_PIXEL_MODE_RGB565 | | |
883 | VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_16); | |
884 | break; | |
885 | ||
886 | default: | |
887 | dev_err(dsi->base.dev, "Unsupported DSI format\n"); | |
888 | return; | |
889 | } | |
890 | ||
891 | if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
892 | tmp |= SYNC_PULSE_ACTIVE | SYNC_PULSE_HORIZONTAL; | |
893 | ||
894 | tmp |= REG_BLKLINE_MODE(REG_BLK_MODE_BLANKING_PKT) | | |
895 | REG_BLKEOL_MODE(REG_BLK_MODE_BLANKING_PKT) | | |
896 | RECOVERY_MODE(RECOVERY_MODE_NEXT_HSYNC) | | |
897 | VID_IGNORE_MISS_VSYNC; | |
898 | ||
899 | writel(tmp, dsi->regs + VID_MAIN_CTL); | |
900 | } | |
901 | ||
902 | tmp = readl(dsi->regs + MCTL_MAIN_DATA_CTL); | |
903 | tmp &= ~(IF_VID_SELECT_MASK | HOST_EOT_GEN | IF_VID_MODE); | |
904 | ||
0f3b68b6 | 905 | if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)) |
e1923395 BB |
906 | tmp |= HOST_EOT_GEN; |
907 | ||
908 | if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO) | |
909 | tmp |= IF_VID_MODE | IF_VID_SELECT(input->id) | VID_EN; | |
910 | ||
911 | writel(tmp, dsi->regs + MCTL_MAIN_DATA_CTL); | |
912 | ||
913 | tmp = readl(dsi->regs + MCTL_MAIN_EN) | IF_EN(input->id); | |
914 | writel(tmp, dsi->regs + MCTL_MAIN_EN); | |
915 | } | |
916 | ||
917 | static const struct drm_bridge_funcs cdns_dsi_bridge_funcs = { | |
918 | .attach = cdns_dsi_bridge_attach, | |
919 | .mode_valid = cdns_dsi_bridge_mode_valid, | |
920 | .disable = cdns_dsi_bridge_disable, | |
921 | .enable = cdns_dsi_bridge_enable, | |
922 | }; | |
923 | ||
924 | static int cdns_dsi_attach(struct mipi_dsi_host *host, | |
925 | struct mipi_dsi_device *dev) | |
926 | { | |
927 | struct cdns_dsi *dsi = to_cdns_dsi(host); | |
928 | struct cdns_dsi_output *output = &dsi->output; | |
929 | struct cdns_dsi_input *input = &dsi->input; | |
930 | struct drm_bridge *bridge; | |
931 | struct drm_panel *panel; | |
932 | struct device_node *np; | |
933 | int ret; | |
934 | ||
935 | /* | |
936 | * We currently do not support connecting several DSI devices to the | |
937 | * same host. In order to support that we'd need the DRM bridge | |
938 | * framework to allow dynamic reconfiguration of the bridge chain. | |
939 | */ | |
940 | if (output->dev) | |
941 | return -EBUSY; | |
942 | ||
943 | /* We do not support burst mode yet. */ | |
944 | if (dev->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
945 | return -ENOTSUPP; | |
946 | ||
947 | /* | |
948 | * The host <-> device link might be described using an OF-graph | |
949 | * representation, in this case we extract the device of_node from | |
950 | * this representation, otherwise we use dsidev->dev.of_node which | |
951 | * should have been filled by the core. | |
952 | */ | |
953 | np = of_graph_get_remote_node(dsi->base.dev->of_node, DSI_OUTPUT_PORT, | |
954 | dev->channel); | |
955 | if (!np) | |
956 | np = of_node_get(dev->dev.of_node); | |
957 | ||
958 | panel = of_drm_find_panel(np); | |
5fa8e4a2 | 959 | if (!IS_ERR(panel)) { |
89958b7c LP |
960 | bridge = drm_panel_bridge_add_typed(panel, |
961 | DRM_MODE_CONNECTOR_DSI); | |
e1923395 BB |
962 | } else { |
963 | bridge = of_drm_find_bridge(dev->dev.of_node); | |
964 | if (!bridge) | |
965 | bridge = ERR_PTR(-EINVAL); | |
966 | } | |
967 | ||
968 | of_node_put(np); | |
969 | ||
970 | if (IS_ERR(bridge)) { | |
971 | ret = PTR_ERR(bridge); | |
972 | dev_err(host->dev, "failed to add DSI device %s (err = %d)", | |
973 | dev->name, ret); | |
974 | return ret; | |
975 | } | |
976 | ||
977 | output->dev = dev; | |
978 | output->bridge = bridge; | |
979 | output->panel = panel; | |
980 | ||
981 | /* | |
982 | * The DSI output has been properly configured, we can now safely | |
983 | * register the input to the bridge framework so that it can take place | |
984 | * in a display pipeline. | |
985 | */ | |
986 | drm_bridge_add(&input->bridge); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static int cdns_dsi_detach(struct mipi_dsi_host *host, | |
992 | struct mipi_dsi_device *dev) | |
993 | { | |
994 | struct cdns_dsi *dsi = to_cdns_dsi(host); | |
995 | struct cdns_dsi_output *output = &dsi->output; | |
996 | struct cdns_dsi_input *input = &dsi->input; | |
997 | ||
998 | drm_bridge_remove(&input->bridge); | |
999 | if (output->panel) | |
1000 | drm_panel_bridge_remove(output->bridge); | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static irqreturn_t cdns_dsi_interrupt(int irq, void *data) | |
1006 | { | |
1007 | struct cdns_dsi *dsi = data; | |
1008 | irqreturn_t ret = IRQ_NONE; | |
1009 | u32 flag, ctl; | |
1010 | ||
1011 | flag = readl(dsi->regs + DIRECT_CMD_STS_FLAG); | |
1012 | if (flag) { | |
1013 | ctl = readl(dsi->regs + DIRECT_CMD_STS_CTL); | |
1014 | ctl &= ~flag; | |
1015 | writel(ctl, dsi->regs + DIRECT_CMD_STS_CTL); | |
1016 | complete(&dsi->direct_cmd_comp); | |
1017 | ret = IRQ_HANDLED; | |
1018 | } | |
1019 | ||
1020 | return ret; | |
1021 | } | |
1022 | ||
1023 | static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host, | |
1024 | const struct mipi_dsi_msg *msg) | |
1025 | { | |
1026 | struct cdns_dsi *dsi = to_cdns_dsi(host); | |
1027 | u32 cmd, sts, val, wait = WRITE_COMPLETED, ctl = 0; | |
1028 | struct mipi_dsi_packet packet; | |
1029 | int ret, i, tx_len, rx_len; | |
1030 | ||
33f90f27 | 1031 | ret = pm_runtime_resume_and_get(host->dev); |
e1923395 BB |
1032 | if (ret < 0) |
1033 | return ret; | |
1034 | ||
1035 | cdns_dsi_init_link(dsi); | |
1036 | ||
1037 | ret = mipi_dsi_create_packet(&packet, msg); | |
1038 | if (ret) | |
1039 | goto out; | |
1040 | ||
1041 | tx_len = msg->tx_buf ? msg->tx_len : 0; | |
1042 | rx_len = msg->rx_buf ? msg->rx_len : 0; | |
1043 | ||
1044 | /* For read operations, the maximum TX len is 2. */ | |
1045 | if (rx_len && tx_len > 2) { | |
1046 | ret = -ENOTSUPP; | |
1047 | goto out; | |
1048 | } | |
1049 | ||
1050 | /* TX len is limited by the CMD FIFO depth. */ | |
1051 | if (tx_len > dsi->direct_cmd_fifo_depth) { | |
1052 | ret = -ENOTSUPP; | |
1053 | goto out; | |
1054 | } | |
1055 | ||
1056 | /* RX len is limited by the RX FIFO depth. */ | |
1057 | if (rx_len > dsi->rx_fifo_depth) { | |
1058 | ret = -ENOTSUPP; | |
1059 | goto out; | |
1060 | } | |
1061 | ||
1062 | cmd = CMD_SIZE(tx_len) | CMD_VCHAN_ID(msg->channel) | | |
1063 | CMD_DATATYPE(msg->type); | |
1064 | ||
1065 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) | |
1066 | cmd |= CMD_LP_EN; | |
1067 | ||
1068 | if (mipi_dsi_packet_format_is_long(msg->type)) | |
1069 | cmd |= CMD_LONG; | |
1070 | ||
1071 | if (rx_len) { | |
1072 | cmd |= READ_CMD; | |
1073 | wait = READ_COMPLETED_WITH_ERR | READ_COMPLETED; | |
1074 | ctl = READ_EN | BTA_EN; | |
1075 | } else if (msg->flags & MIPI_DSI_MSG_REQ_ACK) { | |
1076 | cmd |= BTA_REQ; | |
1077 | wait = ACK_WITH_ERR_RCVD | ACK_RCVD; | |
1078 | ctl = BTA_EN; | |
1079 | } | |
1080 | ||
1081 | writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) | ctl, | |
1082 | dsi->regs + MCTL_MAIN_DATA_CTL); | |
1083 | ||
1084 | writel(cmd, dsi->regs + DIRECT_CMD_MAIN_SETTINGS); | |
1085 | ||
1086 | for (i = 0; i < tx_len; i += 4) { | |
1087 | const u8 *buf = msg->tx_buf; | |
1088 | int j; | |
1089 | ||
1090 | val = 0; | |
1091 | for (j = 0; j < 4 && j + i < tx_len; j++) | |
1092 | val |= (u32)buf[i + j] << (8 * j); | |
1093 | ||
1094 | writel(val, dsi->regs + DIRECT_CMD_WRDATA); | |
1095 | } | |
1096 | ||
1097 | /* Clear status flags before sending the command. */ | |
1098 | writel(wait, dsi->regs + DIRECT_CMD_STS_CLR); | |
1099 | writel(wait, dsi->regs + DIRECT_CMD_STS_CTL); | |
1100 | reinit_completion(&dsi->direct_cmd_comp); | |
1101 | writel(0, dsi->regs + DIRECT_CMD_SEND); | |
1102 | ||
1103 | wait_for_completion_timeout(&dsi->direct_cmd_comp, | |
1104 | msecs_to_jiffies(1000)); | |
1105 | ||
1106 | sts = readl(dsi->regs + DIRECT_CMD_STS); | |
1107 | writel(wait, dsi->regs + DIRECT_CMD_STS_CLR); | |
1108 | writel(0, dsi->regs + DIRECT_CMD_STS_CTL); | |
1109 | ||
1110 | writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) & ~ctl, | |
1111 | dsi->regs + MCTL_MAIN_DATA_CTL); | |
1112 | ||
1113 | /* We did not receive the events we were waiting for. */ | |
1114 | if (!(sts & wait)) { | |
1115 | ret = -ETIMEDOUT; | |
1116 | goto out; | |
1117 | } | |
1118 | ||
1119 | /* 'READ' or 'WRITE with ACK' failed. */ | |
1120 | if (sts & (READ_COMPLETED_WITH_ERR | ACK_WITH_ERR_RCVD)) { | |
1121 | ret = -EIO; | |
1122 | goto out; | |
1123 | } | |
1124 | ||
1125 | for (i = 0; i < rx_len; i += 4) { | |
1126 | u8 *buf = msg->rx_buf; | |
1127 | int j; | |
1128 | ||
1129 | val = readl(dsi->regs + DIRECT_CMD_RDDATA); | |
1130 | for (j = 0; j < 4 && j + i < rx_len; j++) | |
1131 | buf[i + j] = val >> (8 * j); | |
1132 | } | |
1133 | ||
1134 | out: | |
1135 | pm_runtime_put(host->dev); | |
1136 | return ret; | |
1137 | } | |
1138 | ||
1139 | static const struct mipi_dsi_host_ops cdns_dsi_ops = { | |
1140 | .attach = cdns_dsi_attach, | |
1141 | .detach = cdns_dsi_detach, | |
1142 | .transfer = cdns_dsi_transfer, | |
1143 | }; | |
1144 | ||
eea740a9 | 1145 | static int __maybe_unused cdns_dsi_resume(struct device *dev) |
e1923395 BB |
1146 | { |
1147 | struct cdns_dsi *dsi = dev_get_drvdata(dev); | |
1148 | ||
1149 | reset_control_deassert(dsi->dsi_p_rst); | |
1150 | clk_prepare_enable(dsi->dsi_p_clk); | |
1151 | clk_prepare_enable(dsi->dsi_sys_clk); | |
e1923395 BB |
1152 | |
1153 | return 0; | |
1154 | } | |
1155 | ||
eea740a9 | 1156 | static int __maybe_unused cdns_dsi_suspend(struct device *dev) |
e1923395 BB |
1157 | { |
1158 | struct cdns_dsi *dsi = dev_get_drvdata(dev); | |
1159 | ||
e1923395 BB |
1160 | clk_disable_unprepare(dsi->dsi_sys_clk); |
1161 | clk_disable_unprepare(dsi->dsi_p_clk); | |
1162 | reset_control_assert(dsi->dsi_p_rst); | |
1163 | dsi->link_initialized = false; | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | static UNIVERSAL_DEV_PM_OPS(cdns_dsi_pm_ops, cdns_dsi_suspend, cdns_dsi_resume, | |
1168 | NULL); | |
1169 | ||
e1923395 BB |
1170 | static int cdns_dsi_drm_probe(struct platform_device *pdev) |
1171 | { | |
1172 | struct cdns_dsi *dsi; | |
1173 | struct cdns_dsi_input *input; | |
1174 | struct resource *res; | |
1175 | int ret, irq; | |
1176 | u32 val; | |
1177 | ||
1178 | dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); | |
1179 | if (!dsi) | |
1180 | return -ENOMEM; | |
1181 | ||
1182 | platform_set_drvdata(pdev, dsi); | |
1183 | ||
1184 | input = &dsi->input; | |
1185 | ||
1186 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1187 | dsi->regs = devm_ioremap_resource(&pdev->dev, res); | |
1188 | if (IS_ERR(dsi->regs)) | |
1189 | return PTR_ERR(dsi->regs); | |
1190 | ||
1191 | dsi->dsi_p_clk = devm_clk_get(&pdev->dev, "dsi_p_clk"); | |
1192 | if (IS_ERR(dsi->dsi_p_clk)) | |
1193 | return PTR_ERR(dsi->dsi_p_clk); | |
1194 | ||
1195 | dsi->dsi_p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, | |
1196 | "dsi_p_rst"); | |
1197 | if (IS_ERR(dsi->dsi_p_rst)) | |
1198 | return PTR_ERR(dsi->dsi_p_rst); | |
1199 | ||
1200 | dsi->dsi_sys_clk = devm_clk_get(&pdev->dev, "dsi_sys_clk"); | |
1201 | if (IS_ERR(dsi->dsi_sys_clk)) | |
1202 | return PTR_ERR(dsi->dsi_sys_clk); | |
1203 | ||
1204 | irq = platform_get_irq(pdev, 0); | |
1205 | if (irq < 0) | |
1206 | return irq; | |
1207 | ||
fced5a36 | 1208 | dsi->dphy = devm_phy_get(&pdev->dev, "dphy"); |
e1923395 BB |
1209 | if (IS_ERR(dsi->dphy)) |
1210 | return PTR_ERR(dsi->dphy); | |
1211 | ||
1212 | ret = clk_prepare_enable(dsi->dsi_p_clk); | |
1213 | if (ret) | |
fced5a36 | 1214 | return ret; |
e1923395 BB |
1215 | |
1216 | val = readl(dsi->regs + ID_REG); | |
1217 | if (REV_VENDOR_ID(val) != 0xcad) { | |
1218 | dev_err(&pdev->dev, "invalid vendor id\n"); | |
1219 | ret = -EINVAL; | |
1220 | goto err_disable_pclk; | |
1221 | } | |
1222 | ||
1223 | val = readl(dsi->regs + IP_CONF); | |
1224 | dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2); | |
1225 | dsi->rx_fifo_depth = RX_FIFO_DEPTH(val); | |
1226 | init_completion(&dsi->direct_cmd_comp); | |
1227 | ||
1228 | writel(0, dsi->regs + MCTL_MAIN_DATA_CTL); | |
1229 | writel(0, dsi->regs + MCTL_MAIN_EN); | |
1230 | writel(0, dsi->regs + MCTL_MAIN_PHY_CTL); | |
1231 | ||
1232 | /* | |
1233 | * We only support the DPI input, so force input->id to | |
1234 | * CDNS_DPI_INPUT. | |
1235 | */ | |
1236 | input->id = CDNS_DPI_INPUT; | |
1237 | input->bridge.funcs = &cdns_dsi_bridge_funcs; | |
1238 | input->bridge.of_node = pdev->dev.of_node; | |
1239 | ||
1240 | /* Mask all interrupts before registering the IRQ handler. */ | |
1241 | writel(0, dsi->regs + MCTL_MAIN_STS_CTL); | |
1242 | writel(0, dsi->regs + MCTL_DPHY_ERR_CTL1); | |
1243 | writel(0, dsi->regs + CMD_MODE_STS_CTL); | |
1244 | writel(0, dsi->regs + DIRECT_CMD_STS_CTL); | |
1245 | writel(0, dsi->regs + DIRECT_CMD_RD_STS_CTL); | |
1246 | writel(0, dsi->regs + VID_MODE_STS_CTL); | |
1247 | writel(0, dsi->regs + TVG_STS_CTL); | |
1248 | writel(0, dsi->regs + DPI_IRQ_EN); | |
1249 | ret = devm_request_irq(&pdev->dev, irq, cdns_dsi_interrupt, 0, | |
1250 | dev_name(&pdev->dev), dsi); | |
1251 | if (ret) | |
1252 | goto err_disable_pclk; | |
1253 | ||
1254 | pm_runtime_enable(&pdev->dev); | |
1255 | dsi->base.dev = &pdev->dev; | |
1256 | dsi->base.ops = &cdns_dsi_ops; | |
1257 | ||
1258 | ret = mipi_dsi_host_register(&dsi->base); | |
1259 | if (ret) | |
1260 | goto err_disable_runtime_pm; | |
1261 | ||
1262 | clk_disable_unprepare(dsi->dsi_p_clk); | |
1263 | ||
1264 | return 0; | |
1265 | ||
1266 | err_disable_runtime_pm: | |
1267 | pm_runtime_disable(&pdev->dev); | |
1268 | ||
1269 | err_disable_pclk: | |
1270 | clk_disable_unprepare(dsi->dsi_p_clk); | |
1271 | ||
e1923395 BB |
1272 | return ret; |
1273 | } | |
1274 | ||
1275 | static int cdns_dsi_drm_remove(struct platform_device *pdev) | |
1276 | { | |
1277 | struct cdns_dsi *dsi = platform_get_drvdata(pdev); | |
1278 | ||
1279 | mipi_dsi_host_unregister(&dsi->base); | |
1280 | pm_runtime_disable(&pdev->dev); | |
e1923395 BB |
1281 | |
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static const struct of_device_id cdns_dsi_of_match[] = { | |
1286 | { .compatible = "cdns,dsi" }, | |
1287 | { }, | |
1288 | }; | |
1289 | ||
1290 | static struct platform_driver cdns_dsi_platform_driver = { | |
1291 | .probe = cdns_dsi_drm_probe, | |
1292 | .remove = cdns_dsi_drm_remove, | |
1293 | .driver = { | |
1294 | .name = "cdns-dsi", | |
1295 | .of_match_table = cdns_dsi_of_match, | |
1296 | .pm = &cdns_dsi_pm_ops, | |
1297 | }, | |
1298 | }; | |
1299 | module_platform_driver(cdns_dsi_platform_driver); | |
1300 | ||
1301 | MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>"); | |
1302 | MODULE_DESCRIPTION("Cadence DSI driver"); | |
1303 | MODULE_LICENSE("GPL"); | |
1304 | MODULE_ALIAS("platform:cdns-dsi"); | |
1305 |