[linux-2.6-block.git] / drivers / gpu / drm / atmel-hlcdc / atmel_hlcdc_dc.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2014 Traphandler
 * Copyright (C) 2014 Free Electrons
 * Copyright (C) 2014 Atmel
 *
 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 */

#ifndef DRM_ATMEL_HLCDC_H
#define DRM_ATMEL_HLCDC_H

#include <linux/clk.h>
#include <linux/dmapool.h>
#include <linux/irqdomain.h>
#include <linux/mfd/atmel-hlcdc.h>
#include <linux/pwm.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_panel.h>
#include <drm/drm_plane_helper.h>
#include <drm/drmP.h>

#define ATMEL_HLCDC_LAYER_CHER			0x0
#define ATMEL_HLCDC_LAYER_CHDR			0x4
#define ATMEL_HLCDC_LAYER_CHSR			0x8
#define ATMEL_HLCDC_LAYER_EN			BIT(0)
#define ATMEL_HLCDC_LAYER_UPDATE		BIT(1)
#define ATMEL_HLCDC_LAYER_A2Q			BIT(2)
#define ATMEL_HLCDC_LAYER_RST			BIT(8)

#define ATMEL_HLCDC_LAYER_IER			0xc
#define ATMEL_HLCDC_LAYER_IDR			0x10
#define ATMEL_HLCDC_LAYER_IMR			0x14
#define ATMEL_HLCDC_LAYER_ISR			0x18
#define ATMEL_HLCDC_LAYER_DFETCH		BIT(0)
#define ATMEL_HLCDC_LAYER_LFETCH		BIT(1)
#define ATMEL_HLCDC_LAYER_DMA_IRQ(p)		BIT(2 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_DSCR_IRQ(p)		BIT(3 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_ADD_IRQ(p)		BIT(4 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_DONE_IRQ(p)		BIT(5 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_OVR_IRQ(p)		BIT(6 + (8 * (p)))

#define ATMEL_HLCDC_LAYER_PLANE_HEAD(p)		(((p) * 0x10) + 0x1c)
#define ATMEL_HLCDC_LAYER_PLANE_ADDR(p)		(((p) * 0x10) + 0x20)
#define ATMEL_HLCDC_LAYER_PLANE_CTRL(p)		(((p) * 0x10) + 0x24)
#define ATMEL_HLCDC_LAYER_PLANE_NEXT(p)		(((p) * 0x10) + 0x28)

#define ATMEL_HLCDC_LAYER_DMA_CFG		0
#define ATMEL_HLCDC_LAYER_DMA_SIF		BIT(0)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK		GENMASK(5, 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE	(0 << 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4	(1 << 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8	(2 << 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16	(3 << 4)
#define ATMEL_HLCDC_LAYER_DMA_DLBO		BIT(8)
#define ATMEL_HLCDC_LAYER_DMA_ROTDIS		BIT(12)
#define ATMEL_HLCDC_LAYER_DMA_LOCKDIS		BIT(13)

#define ATMEL_HLCDC_LAYER_FORMAT_CFG		1
#define ATMEL_HLCDC_LAYER_RGB			(0 << 0)
#define ATMEL_HLCDC_LAYER_CLUT			(1 << 0)
#define ATMEL_HLCDC_LAYER_YUV			(2 << 0)
#define ATMEL_HLCDC_RGB_MODE(m)			\
	(ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4))
#define ATMEL_HLCDC_CLUT_MODE(m)		\
	(ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8))
#define ATMEL_HLCDC_YUV_MODE(m)			\
	(ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12))
#define ATMEL_HLCDC_YUV422ROT			BIT(16)
#define ATMEL_HLCDC_YUV422SWP			BIT(17)
#define ATMEL_HLCDC_DSCALEOPT			BIT(20)

#define ATMEL_HLCDC_C1_MODE			ATMEL_HLCDC_CLUT_MODE(0)
#define ATMEL_HLCDC_C2_MODE			ATMEL_HLCDC_CLUT_MODE(1)
#define ATMEL_HLCDC_C4_MODE			ATMEL_HLCDC_CLUT_MODE(2)
#define ATMEL_HLCDC_C8_MODE			ATMEL_HLCDC_CLUT_MODE(3)

#define ATMEL_HLCDC_XRGB4444_MODE		ATMEL_HLCDC_RGB_MODE(0)
#define ATMEL_HLCDC_ARGB4444_MODE		ATMEL_HLCDC_RGB_MODE(1)
#define ATMEL_HLCDC_RGBA4444_MODE		ATMEL_HLCDC_RGB_MODE(2)
#define ATMEL_HLCDC_RGB565_MODE			ATMEL_HLCDC_RGB_MODE(3)
#define ATMEL_HLCDC_ARGB1555_MODE		ATMEL_HLCDC_RGB_MODE(4)
#define ATMEL_HLCDC_XRGB8888_MODE		ATMEL_HLCDC_RGB_MODE(9)
#define ATMEL_HLCDC_RGB888_MODE			ATMEL_HLCDC_RGB_MODE(10)
#define ATMEL_HLCDC_ARGB8888_MODE		ATMEL_HLCDC_RGB_MODE(12)
#define ATMEL_HLCDC_RGBA8888_MODE		ATMEL_HLCDC_RGB_MODE(13)

#define ATMEL_HLCDC_AYUV_MODE			ATMEL_HLCDC_YUV_MODE(0)
#define ATMEL_HLCDC_YUYV_MODE			ATMEL_HLCDC_YUV_MODE(1)
#define ATMEL_HLCDC_UYVY_MODE			ATMEL_HLCDC_YUV_MODE(2)
#define ATMEL_HLCDC_YVYU_MODE			ATMEL_HLCDC_YUV_MODE(3)
#define ATMEL_HLCDC_VYUY_MODE			ATMEL_HLCDC_YUV_MODE(4)
#define ATMEL_HLCDC_NV61_MODE			ATMEL_HLCDC_YUV_MODE(5)
#define ATMEL_HLCDC_YUV422_MODE			ATMEL_HLCDC_YUV_MODE(6)
#define ATMEL_HLCDC_NV21_MODE			ATMEL_HLCDC_YUV_MODE(7)
#define ATMEL_HLCDC_YUV420_MODE			ATMEL_HLCDC_YUV_MODE(8)

#define ATMEL_HLCDC_LAYER_POS(x, y)		((x) | ((y) << 16))
#define ATMEL_HLCDC_LAYER_SIZE(w, h)		(((w) - 1) | (((h) - 1) << 16))

#define ATMEL_HLCDC_LAYER_CRKEY			BIT(0)
#define ATMEL_HLCDC_LAYER_INV			BIT(1)
#define ATMEL_HLCDC_LAYER_ITER2BL		BIT(2)
#define ATMEL_HLCDC_LAYER_ITER			BIT(3)
#define ATMEL_HLCDC_LAYER_REVALPHA		BIT(4)
#define ATMEL_HLCDC_LAYER_GAEN			BIT(5)
#define ATMEL_HLCDC_LAYER_LAEN			BIT(6)
#define ATMEL_HLCDC_LAYER_OVR			BIT(7)
#define ATMEL_HLCDC_LAYER_DMA			BIT(8)
#define ATMEL_HLCDC_LAYER_REP			BIT(9)
#define ATMEL_HLCDC_LAYER_DSTKEY		BIT(10)
#define ATMEL_HLCDC_LAYER_DISCEN		BIT(11)
#define ATMEL_HLCDC_LAYER_GA_SHIFT		16
#define ATMEL_HLCDC_LAYER_GA_MASK		\
	GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
#define ATMEL_HLCDC_LAYER_GA(x)			\
	((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)

#define ATMEL_HLCDC_LAYER_DISC_POS(x, y)	((x) | ((y) << 16))
#define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h)	(((w) - 1) | (((h) - 1) << 16))

#define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y)	((x) | ((y) << 16))
#define ATMEL_HLCDC_LAYER_SCALER_ENABLE		BIT(31)

#define ATMEL_HLCDC_LAYER_MAX_PLANES		3

#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED	BIT(0)
#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED	BIT(1)
#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE	BIT(2)
#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN	BIT(3)

#define ATMEL_HLCDC_CLUT_SIZE			256

#define ATMEL_HLCDC_MAX_LAYERS			6

/**
 * Atmel HLCDC Layer registers layout structure
 *
 * Each HLCDC layer has its own register organization and a given register
 * can be placed differently on 2 different layers depending on its
 * capabilities.
 * This structure stores common registers layout for a given layer and is
 * used by HLCDC layer code to choose the appropriate register to write to
 * or to read from.
 *
 * For all fields, a value of zero means "unsupported".
 *
 * See Atmel's datasheet for a detailled description of these registers.
 *
 * @xstride: xstride registers
 * @pstride: pstride registers
 * @pos: position register
 * @size: displayed size register
 * @memsize: memory size register
 * @default_color: default color register
 * @chroma_key: chroma key register
 * @chroma_key_mask: chroma key mask register
 * @general_config: general layer config register
 * @sacler_config: scaler factors register
 * @phicoeffs: X/Y PHI coefficient registers
 * @disc_pos: discard area position register
 * @disc_size: discard area size register
 * @csc: color space conversion register
 */
struct atmel_hlcdc_layer_cfg_layout {
	int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
	int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
	int pos;
	int size;
	int memsize;
	int default_color;
	int chroma_key;
	int chroma_key_mask;
	int general_config;
	int scaler_config;
	struct {
		int x;
		int y;
	} phicoeffs;
	int disc_pos;
	int disc_size;
	int csc;
};

/**
 * Atmel HLCDC DMA descriptor structure
 *
 * This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
 *
 * The structure fields must remain in this specific order, because they're
 * used by the HLCDC DMA engine, which expect them in this order.
 * HLCDC DMA descriptors must be aligned on 64 bits.
 *
 * @addr: buffer DMA address
 * @ctrl: DMA transfer options
 * @next: next DMA descriptor to fetch
 * @self: descriptor DMA address
 */
struct atmel_hlcdc_dma_channel_dscr {
	dma_addr_t addr;
	u32 ctrl;
	dma_addr_t next;
	dma_addr_t self;
} __aligned(sizeof(u64));

/**
 * Atmel HLCDC layer types
 */
enum atmel_hlcdc_layer_type {
	ATMEL_HLCDC_NO_LAYER,
	ATMEL_HLCDC_BASE_LAYER,
	ATMEL_HLCDC_OVERLAY_LAYER,
	ATMEL_HLCDC_CURSOR_LAYER,
	ATMEL_HLCDC_PP_LAYER,
};

/**
 * Atmel HLCDC Supported formats structure
 *
 * This structure list all the formats supported by a given layer.
 *
 * @nformats: number of supported formats
 * @formats: supported formats
 */
struct atmel_hlcdc_formats {
	int nformats;
	u32 *formats;
};

/**
 * Atmel HLCDC Layer description structure
 *
 * This structure describes the capabilities provided by a given layer.
 *
 * @name: layer name
 * @type: layer type
 * @id: layer id
 * @regs_offset: offset of the layer registers from the HLCDC registers base
 * @cfgs_offset: CFGX registers offset from the layer registers base
 * @formats: supported formats
 * @layout: config registers layout
 * @max_width: maximum width supported by this layer (0 means unlimited)
 * @max_height: maximum height supported by this layer (0 means unlimited)
 */
struct atmel_hlcdc_layer_desc {
	const char *name;
	enum atmel_hlcdc_layer_type type;
	int id;
	int regs_offset;
	int cfgs_offset;
	int clut_offset;
	struct atmel_hlcdc_formats *formats;
	struct atmel_hlcdc_layer_cfg_layout layout;
	int max_width;
	int max_height;
};

/**
 * Atmel HLCDC Layer.
 *
 * A layer can be a DRM plane of a post processing layer used to render
 * HLCDC composition into memory.
 *
 * @desc: layer description
 * @regmap: pointer to the HLCDC regmap
 */
struct atmel_hlcdc_layer {
	const struct atmel_hlcdc_layer_desc *desc;
	struct regmap *regmap;
};

/**
 * Atmel HLCDC Plane.
 *
 * @base: base DRM plane structure
 * @layer: HLCDC layer structure
 * @properties: pointer to the property definitions structure
 */
struct atmel_hlcdc_plane {
	struct drm_plane base;
	struct atmel_hlcdc_layer layer;
};

static inline struct atmel_hlcdc_plane *
drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
{
	return container_of(p, struct atmel_hlcdc_plane, base);
}

static inline struct atmel_hlcdc_plane *
atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)
{
	return container_of(layer, struct atmel_hlcdc_plane, layer);
}

/**
 * Atmel HLCDC Display Controller description structure.
 *
 * This structure describes the HLCDC IP capabilities and depends on the
 * HLCDC IP version (or Atmel SoC family).
 *
 * @min_width: minimum width supported by the Display Controller
 * @min_height: minimum height supported by the Display Controller
 * @max_width: maximum width supported by the Display Controller
 * @max_height: maximum height supported by the Display Controller
 * @max_spw: maximum vertical/horizontal pulse width
 * @max_vpw: maximum vertical back/front porch width
 * @max_hpw: maximum horizontal back/front porch width
 * @conflicting_output_formats: true if RGBXXX output formats conflict with
 *				each other.
 * @layers: a layer description table describing available layers
 * @nlayers: layer description table size
 */
struct atmel_hlcdc_dc_desc {
	int min_width;
	int min_height;
	int max_width;
	int max_height;
	int max_spw;
	int max_vpw;
	int max_hpw;
	bool conflicting_output_formats;
	const struct atmel_hlcdc_layer_desc *layers;
	int nlayers;
};

/**
 * Atmel HLCDC Display Controller.
 *
 * @desc: HLCDC Display Controller description
 * @dscrpool: DMA coherent pool used to allocate DMA descriptors
 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
 * @fbdev: framebuffer device attached to the Display Controller
 * @crtc: CRTC provided by the display controller
 * @planes: instantiated planes
 * @layers: active HLCDC layers
 * @wq: display controller workqueue
 * @suspend: used to store the HLCDC state when entering suspend
 * @commit: used for async commit handling
 */
struct atmel_hlcdc_dc {
	const struct atmel_hlcdc_dc_desc *desc;
	struct dma_pool *dscrpool;
	struct atmel_hlcdc *hlcdc;
	struct drm_crtc *crtc;
	struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
	struct workqueue_struct *wq;
	struct {
		u32 imr;
		struct drm_atomic_state *state;
	} suspend;
	struct {
		wait_queue_head_t wait;
		bool pending;
	} commit;
};

extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;

static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,
					       unsigned int reg, u32 val)
{
	regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);
}

static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,
					     unsigned int reg)
{
	u32 val;

	regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);

	return val;
}

static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,
					       unsigned int cfgid, u32 val)
{
	atmel_hlcdc_layer_write_reg(layer,
				    layer->desc->cfgs_offset +
				    (cfgid * sizeof(u32)), val);
}

static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,
					     unsigned int cfgid)
{
	return atmel_hlcdc_layer_read_reg(layer,
					  layer->desc->cfgs_offset +
					  (cfgid * sizeof(u32)));
}

static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer,
						unsigned int c, u32 val)
{
	regmap_write(layer->regmap,
		     layer->desc->clut_offset + c * sizeof(u32),
		     val);
}

static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
				const struct atmel_hlcdc_layer_desc *desc,
				struct regmap *regmap)
{
	layer->desc = desc;
	layer->regmap = regmap;
}

enum drm_mode_status
atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
			  const struct drm_display_mode *mode);

int atmel_hlcdc_create_planes(struct drm_device *dev);
void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);

int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);

void atmel_hlcdc_crtc_irq(struct drm_crtc *c);

int atmel_hlcdc_crtc_create(struct drm_device *dev);

int atmel_hlcdc_create_outputs(struct drm_device *dev);
int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder);

#endif /* DRM_ATMEL_HLCDC_H */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
1a396789 BB	2	/*
	3	* Copyright (C) 2014 Traphandler
	4	* Copyright (C) 2014 Free Electrons
	5	* Copyright (C) 2014 Atmel
	6	*
	7	* Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
	8	* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
1a396789 BB	9	*/
	10
	11	#ifndef DRM_ATMEL_HLCDC_H
	12	#define DRM_ATMEL_HLCDC_H
	13
	14	#include <linux/clk.h>
9a45d33c	15	#include <linux/dmapool.h>
1a396789	16	#include <linux/irqdomain.h>
9a45d33c	17	#include <linux/mfd/atmel-hlcdc.h>
1a396789 BB	18	#include <linux/pwm.h>
1a396789 BB	19
2389fc13 BB	20	#include <drm/drm_atomic.h>
2389fc13 BB	21	#include <drm/drm_atomic_helper.h>
1a396789	22	#include <drm/drm_crtc.h>
fcd70cd3	23	#include <drm/drm_probe_helper.h>
ce4eb35b	24	#include <drm/drm_fb_helper.h>
1a396789 BB	25	#include <drm/drm_fb_cma_helper.h>
1a396789 BB	26	#include <drm/drm_gem_cma_helper.h>
2a6f7139	27	#include <drm/drm_gem_framebuffer_helper.h>
1a396789	28	#include <drm/drm_panel.h>
2389fc13	29	#include <drm/drm_plane_helper.h>
1a396789 BB	30	#include <drm/drmP.h>
1a396789 BB	31
9a45d33c BB	32	#define ATMEL_HLCDC_LAYER_CHER 0x0
	33	#define ATMEL_HLCDC_LAYER_CHDR 0x4
	34	#define ATMEL_HLCDC_LAYER_CHSR 0x8
	35	#define ATMEL_HLCDC_LAYER_EN BIT(0)
	36	#define ATMEL_HLCDC_LAYER_UPDATE BIT(1)
	37	#define ATMEL_HLCDC_LAYER_A2Q BIT(2)
	38	#define ATMEL_HLCDC_LAYER_RST BIT(8)
1a396789	39
9a45d33c BB	40	#define ATMEL_HLCDC_LAYER_IER 0xc
	41	#define ATMEL_HLCDC_LAYER_IDR 0x10
	42	#define ATMEL_HLCDC_LAYER_IMR 0x14
	43	#define ATMEL_HLCDC_LAYER_ISR 0x18
	44	#define ATMEL_HLCDC_LAYER_DFETCH BIT(0)
	45	#define ATMEL_HLCDC_LAYER_LFETCH BIT(1)
	46	#define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p)))
	47	#define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p)))
	48	#define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p)))
	49	#define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p)))
	50	#define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p)))
	51
	52	#define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) (((p) * 0x10) + 0x1c)
	53	#define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x10) + 0x20)
	54	#define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) (((p) * 0x10) + 0x24)
	55	#define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) (((p) * 0x10) + 0x28)
	56
	57	#define ATMEL_HLCDC_LAYER_DMA_CFG 0
	58	#define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0)
	59	#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4)
	60	#define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4)
	61	#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4)
	62	#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4)
	63	#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4)
	64	#define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8)
	65	#define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12)
	66	#define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13)
	67
	68	#define ATMEL_HLCDC_LAYER_FORMAT_CFG 1
	69	#define ATMEL_HLCDC_LAYER_RGB (0 << 0)
	70	#define ATMEL_HLCDC_LAYER_CLUT (1 << 0)
	71	#define ATMEL_HLCDC_LAYER_YUV (2 << 0)
	72	#define ATMEL_HLCDC_RGB_MODE(m) \
	73	(ATMEL_HLCDC_LAYER_RGB \| (((m) & 0xf) << 4))
	74	#define ATMEL_HLCDC_CLUT_MODE(m) \
	75	(ATMEL_HLCDC_LAYER_CLUT \| (((m) & 0x3) << 8))
	76	#define ATMEL_HLCDC_YUV_MODE(m) \
	77	(ATMEL_HLCDC_LAYER_YUV \| (((m) & 0xf) << 12))
	78	#define ATMEL_HLCDC_YUV422ROT BIT(16)
	79	#define ATMEL_HLCDC_YUV422SWP BIT(17)
	80	#define ATMEL_HLCDC_DSCALEOPT BIT(20)
	81
364a7bf5 PR	82	#define ATMEL_HLCDC_C1_MODE ATMEL_HLCDC_CLUT_MODE(0)
	83	#define ATMEL_HLCDC_C2_MODE ATMEL_HLCDC_CLUT_MODE(1)
	84	#define ATMEL_HLCDC_C4_MODE ATMEL_HLCDC_CLUT_MODE(2)
	85	#define ATMEL_HLCDC_C8_MODE ATMEL_HLCDC_CLUT_MODE(3)
	86
9a45d33c BB	87	#define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0)
	88	#define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1)
	89	#define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2)
	90	#define ATMEL_HLCDC_RGB565_MODE ATMEL_HLCDC_RGB_MODE(3)
	91	#define ATMEL_HLCDC_ARGB1555_MODE ATMEL_HLCDC_RGB_MODE(4)
	92	#define ATMEL_HLCDC_XRGB8888_MODE ATMEL_HLCDC_RGB_MODE(9)
	93	#define ATMEL_HLCDC_RGB888_MODE ATMEL_HLCDC_RGB_MODE(10)
	94	#define ATMEL_HLCDC_ARGB8888_MODE ATMEL_HLCDC_RGB_MODE(12)
	95	#define ATMEL_HLCDC_RGBA8888_MODE ATMEL_HLCDC_RGB_MODE(13)
	96
	97	#define ATMEL_HLCDC_AYUV_MODE ATMEL_HLCDC_YUV_MODE(0)
	98	#define ATMEL_HLCDC_YUYV_MODE ATMEL_HLCDC_YUV_MODE(1)
	99	#define ATMEL_HLCDC_UYVY_MODE ATMEL_HLCDC_YUV_MODE(2)
	100	#define ATMEL_HLCDC_YVYU_MODE ATMEL_HLCDC_YUV_MODE(3)
	101	#define ATMEL_HLCDC_VYUY_MODE ATMEL_HLCDC_YUV_MODE(4)
	102	#define ATMEL_HLCDC_NV61_MODE ATMEL_HLCDC_YUV_MODE(5)
	103	#define ATMEL_HLCDC_YUV422_MODE ATMEL_HLCDC_YUV_MODE(6)
	104	#define ATMEL_HLCDC_NV21_MODE ATMEL_HLCDC_YUV_MODE(7)
	105	#define ATMEL_HLCDC_YUV420_MODE ATMEL_HLCDC_YUV_MODE(8)
	106
	107	#define ATMEL_HLCDC_LAYER_POS(x, y) ((x) \| ((y) << 16))
	108	#define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) \| (((h) - 1) << 16))
	109
	110	#define ATMEL_HLCDC_LAYER_CRKEY BIT(0)
	111	#define ATMEL_HLCDC_LAYER_INV BIT(1)
	112	#define ATMEL_HLCDC_LAYER_ITER2BL BIT(2)
	113	#define ATMEL_HLCDC_LAYER_ITER BIT(3)
	114	#define ATMEL_HLCDC_LAYER_REVALPHA BIT(4)
	115	#define ATMEL_HLCDC_LAYER_GAEN BIT(5)
	116	#define ATMEL_HLCDC_LAYER_LAEN BIT(6)
	117	#define ATMEL_HLCDC_LAYER_OVR BIT(7)
	118	#define ATMEL_HLCDC_LAYER_DMA BIT(8)
	119	#define ATMEL_HLCDC_LAYER_REP BIT(9)
	120	#define ATMEL_HLCDC_LAYER_DSTKEY BIT(10)
	121	#define ATMEL_HLCDC_LAYER_DISCEN BIT(11)
	122	#define ATMEL_HLCDC_LAYER_GA_SHIFT 16
	123	#define ATMEL_HLCDC_LAYER_GA_MASK \
	124	GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
	125	#define ATMEL_HLCDC_LAYER_GA(x) \
	126	((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
	127
	128	#define ATMEL_HLCDC_LAYER_DISC_POS(x, y) ((x) \| ((y) << 16))
	129	#define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) \| (((h) - 1) << 16))
	130
	131	#define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) ((x) \| ((y) << 16))
	132	#define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31)
	133
	134	#define ATMEL_HLCDC_LAYER_MAX_PLANES 3
	135
	136	#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0)
	137	#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1)
	138	#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2)
	139	#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3)
	140
364a7bf5 PR	141	#define ATMEL_HLCDC_CLUT_SIZE 256
364a7bf5 PR	142
9a45d33c	143	#define ATMEL_HLCDC_MAX_LAYERS 6
1a396789 BB	144
1a396789 BB	145	/**
9a45d33c	146	* Atmel HLCDC Layer registers layout structure
1a396789	147	*
9a45d33c BB	148	* Each HLCDC layer has its own register organization and a given register
	149	* can be placed differently on 2 different layers depending on its
	150	* capabilities.
	151	* This structure stores common registers layout for a given layer and is
	152	* used by HLCDC layer code to choose the appropriate register to write to
	153	* or to read from.
1a396789	154	*
9a45d33c BB	155	* For all fields, a value of zero means "unsupported".
	156	*
	157	* See Atmel's datasheet for a detailled description of these registers.
	158	*
	159	* @xstride: xstride registers
	160	* @pstride: pstride registers
	161	* @pos: position register
	162	* @size: displayed size register
	163	* @memsize: memory size register
	164	* @default_color: default color register
	165	* @chroma_key: chroma key register
	166	* @chroma_key_mask: chroma key mask register
	167	* @general_config: general layer config register
	168	* @sacler_config: scaler factors register
	169	* @phicoeffs: X/Y PHI coefficient registers
	170	* @disc_pos: discard area position register
	171	* @disc_size: discard area size register
	172	* @csc: color space conversion register
1a396789	173	*/
9a45d33c BB	174	struct atmel_hlcdc_layer_cfg_layout {
	175	int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
	176	int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
	177	int pos;
	178	int size;
	179	int memsize;
	180	int default_color;
	181	int chroma_key;
	182	int chroma_key_mask;
	183	int general_config;
	184	int scaler_config;
	185	struct {
	186	int x;
	187	int y;
	188	} phicoeffs;
	189	int disc_pos;
	190	int disc_size;
	191	int csc;
	192	};
	193
	194	/**
	195	* Atmel HLCDC DMA descriptor structure
	196	*
	197	* This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
	198	*
	199	* The structure fields must remain in this specific order, because they're
	200	* used by the HLCDC DMA engine, which expect them in this order.
	201	* HLCDC DMA descriptors must be aligned on 64 bits.
	202	*
	203	* @addr: buffer DMA address
	204	* @ctrl: DMA transfer options
	205	* @next: next DMA descriptor to fetch
	206	* @self: descriptor DMA address
	207	*/
	208	struct atmel_hlcdc_dma_channel_dscr {
	209	dma_addr_t addr;
	210	u32 ctrl;
	211	dma_addr_t next;
	212	dma_addr_t self;
	213	} __aligned(sizeof(u64));
	214
	215	/**
	216	* Atmel HLCDC layer types
	217	*/
	218	enum atmel_hlcdc_layer_type {
	219	ATMEL_HLCDC_NO_LAYER,
	220	ATMEL_HLCDC_BASE_LAYER,
	221	ATMEL_HLCDC_OVERLAY_LAYER,
	222	ATMEL_HLCDC_CURSOR_LAYER,
	223	ATMEL_HLCDC_PP_LAYER,
	224	};
	225
	226	/**
	227	* Atmel HLCDC Supported formats structure
	228	*
	229	* This structure list all the formats supported by a given layer.
	230	*
	231	* @nformats: number of supported formats
	232	* @formats: supported formats
	233	*/
	234	struct atmel_hlcdc_formats {
	235	int nformats;
	236	u32 *formats;
	237	};
238
239	/**
240	* Atmel HLCDC Layer description structure
241	*
242	* This structure describes the capabilities provided by a given layer.
243	*
244	* @name: layer name
245	* @type: layer type
246	* @id: layer id
247	* @regs_offset: offset of the layer registers from the HLCDC registers base
248	* @cfgs_offset: CFGX registers offset from the layer registers base
249	* @formats: supported formats
250	* @layout: config registers layout
251	* @max_width: maximum width supported by this layer (0 means unlimited)
252	* @max_height: maximum height supported by this layer (0 means unlimited)
253	*/
254	struct atmel_hlcdc_layer_desc {
255	const char *name;
256	enum atmel_hlcdc_layer_type type;
257	int id;
258	int regs_offset;
259	int cfgs_offset;
364a7bf5	260	int clut_offset;
9a45d33c BB	261	struct atmel_hlcdc_formats *formats;
9a45d33c BB	262	struct atmel_hlcdc_layer_cfg_layout layout;
1a396789 BB	263	int max_width;
1a396789 BB	264	int max_height;
1a396789 BB	265	};
	266
	267	/**
9a45d33c	268	* Atmel HLCDC Layer.
1a396789	269	*
9a45d33c BB	270	* A layer can be a DRM plane of a post processing layer used to render
9a45d33c BB	271	* HLCDC composition into memory.
1a396789	272	*
9a45d33c BB	273	* @desc: layer description
9a45d33c BB	274	* @regmap: pointer to the HLCDC regmap
1a396789	275	*/
9a45d33c BB	276	struct atmel_hlcdc_layer {
	277	const struct atmel_hlcdc_layer_desc *desc;
	278	struct regmap *regmap;
1a396789 BB	279	};
	280
	281	/**
	282	* Atmel HLCDC Plane.
	283	*
	284	* @base: base DRM plane structure
	285	* @layer: HLCDC layer structure
	286	* @properties: pointer to the property definitions structure
1a396789 BB	287	*/
	288	struct atmel_hlcdc_plane {
	289	struct drm_plane base;
	290	struct atmel_hlcdc_layer layer;
1a396789 BB	291	};
	292
	293	static inline struct atmel_hlcdc_plane *
	294	drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
	295	{
	296	return container_of(p, struct atmel_hlcdc_plane, base);
	297	}
	298
	299	static inline struct atmel_hlcdc_plane *
9a45d33c	300	atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)
1a396789	301	{
9a45d33c	302	return container_of(layer, struct atmel_hlcdc_plane, layer);
1a396789 BB	303	}
1a396789 BB	304
1a396789	305	/**
9a45d33c	306	* Atmel HLCDC Display Controller description structure.
1a396789	307	*
9a45d33c BB	308	* This structure describes the HLCDC IP capabilities and depends on the
9a45d33c BB	309	* HLCDC IP version (or Atmel SoC family).
1a396789	310	*
9a45d33c BB	311	* @min_width: minimum width supported by the Display Controller
	312	* @min_height: minimum height supported by the Display Controller
	313	* @max_width: maximum width supported by the Display Controller
	314	* @max_height: maximum height supported by the Display Controller
	315	* @max_spw: maximum vertical/horizontal pulse width
	316	* @max_vpw: maximum vertical back/front porch width
	317	* @max_hpw: maximum horizontal back/front porch width
	318	* @conflicting_output_formats: true if RGBXXX output formats conflict with
	319	* each other.
	320	* @layers: a layer description table describing available layers
	321	* @nlayers: layer description table size
1a396789	322	*/
9a45d33c BB	323	struct atmel_hlcdc_dc_desc {
	324	int min_width;
	325	int min_height;
	326	int max_width;
	327	int max_height;
	328	int max_spw;
	329	int max_vpw;
	330	int max_hpw;
	331	bool conflicting_output_formats;
	332	const struct atmel_hlcdc_layer_desc *layers;
	333	int nlayers;
	334	};
	335
1a396789 BB	336	/**
	337	* Atmel HLCDC Display Controller.
	338	*
	339	* @desc: HLCDC Display Controller description
9a45d33c	340	* @dscrpool: DMA coherent pool used to allocate DMA descriptors
1a396789 BB	341	* @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
	342	* @fbdev: framebuffer device attached to the Display Controller
	343	* @crtc: CRTC provided by the display controller
	344	* @planes: instantiated planes
9a45d33c	345	* @layers: active HLCDC layers
1a396789	346	* @wq: display controller workqueue
99ed4d7e	347	* @suspend: used to store the HLCDC state when entering suspend
9b190610	348	* @commit: used for async commit handling
1a396789 BB	349	*/
	350	struct atmel_hlcdc_dc {
	351	const struct atmel_hlcdc_dc_desc *desc;
9a45d33c	352	struct dma_pool *dscrpool;
1a396789	353	struct atmel_hlcdc *hlcdc;
1a396789	354	struct drm_crtc *crtc;
1a396789 BB	355	struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
1a396789 BB	356	struct workqueue_struct *wq;
99ed4d7e BB	357	struct {
	358	u32 imr;
	359	struct drm_atomic_state *state;
	360	} suspend;
9b190610 BB	361	struct {
	362	wait_queue_head_t wait;
	363	bool pending;
	364	} commit;
1a396789 BB	365	};
	366
	367	extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
	368	extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;
	369
9a45d33c BB	370	static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,
	371	unsigned int reg, u32 val)
	372	{
	373	regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);
	374	}
	375
	376	static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,
	377	unsigned int reg)
	378	{
	379	u32 val;
	380
	381	regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);
	382
	383	return val;
	384	}
	385
	386	static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,
	387	unsigned int cfgid, u32 val)
	388	{
	389	atmel_hlcdc_layer_write_reg(layer,
	390	layer->desc->cfgs_offset +
	391	(cfgid * sizeof(u32)), val);
	392	}
	393
	394	static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,
	395	unsigned int cfgid)
	396	{
	397	return atmel_hlcdc_layer_read_reg(layer,
	398	layer->desc->cfgs_offset +
	399	(cfgid * sizeof(u32)));
	400	}
	401
364a7bf5 PR	402	static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer,
	403	unsigned int c, u32 val)
	404	{
	405	regmap_write(layer->regmap,
	406	layer->desc->clut_offset + c * sizeof(u32),
	407	val);
	408	}
	409
9a45d33c BB	410	static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
	411	const struct atmel_hlcdc_layer_desc *desc,
	412	struct regmap *regmap)
	413	{
	414	layer->desc = desc;
	415	layer->regmap = regmap;
	416	}
	417
a57bf53e JA	418	enum drm_mode_status
	419	atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
	420	const struct drm_display_mode *mode);
1a396789	421
9a45d33c BB	422	int atmel_hlcdc_create_planes(struct drm_device *dev);
9a45d33c BB	423	void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);
1a396789	424
5957017d	425	int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
ebab87ab	426	int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);
5957017d	427
1a396789 BB	428	void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
1a396789 BB	429
1a396789 BB	430	int atmel_hlcdc_crtc_create(struct drm_device *dev);
	431
	432	int atmel_hlcdc_create_outputs(struct drm_device *dev);
b6e075c3	433	int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder);
1a396789 BB	434
1a396789 BB	435	#endif /* DRM_ATMEL_HLCDC_H */