[linux-2.6-block.git] / drivers / gpu / drm / atmel-hlcdc / atmel_hlcdc_crtc.c

/*
 * Copyright (C) 2014 Traphandler
 * Copyright (C) 2014 Free Electrons
 *
 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/pinctrl/consumer.h>

#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drmP.h>

#include <video/videomode.h>

#include "atmel_hlcdc_dc.h"

/**
 * Atmel HLCDC CRTC structure
 *
 * @base: base DRM CRTC structure
 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
 * @event: pointer to the current page flip event
 * @id: CRTC id (returned by drm_crtc_index)
 * @enabled: CRTC state
 */
struct atmel_hlcdc_crtc {
	struct drm_crtc base;
	struct atmel_hlcdc_dc *dc;
	struct drm_pending_vblank_event *event;
	int id;
	bool enabled;
};

static inline struct atmel_hlcdc_crtc *
drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
{
	return container_of(crtc, struct atmel_hlcdc_crtc, base);
}

static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
{
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	struct regmap *regmap = crtc->dc->hlcdc->regmap;
	struct drm_display_mode *adj = &c->state->adjusted_mode;
	unsigned long mode_rate;
	struct videomode vm;
	unsigned long prate;
	unsigned int cfg;
	int div;

	vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
	vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
	vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
	vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay;
	vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end;
	vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start;

	regmap_write(regmap, ATMEL_HLCDC_CFG(1),
		     (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16));

	regmap_write(regmap, ATMEL_HLCDC_CFG(2),
		     (vm.vfront_porch - 1) | (vm.vback_porch << 16));

	regmap_write(regmap, ATMEL_HLCDC_CFG(3),
		     (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16));

	regmap_write(regmap, ATMEL_HLCDC_CFG(4),
		     (adj->crtc_hdisplay - 1) |
		     ((adj->crtc_vdisplay - 1) << 16));

	cfg = 0;

	prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
	mode_rate = adj->crtc_clock * 1000;
	if ((prate / 2) < mode_rate) {
		prate *= 2;
		cfg |= ATMEL_HLCDC_CLKSEL;
	}

	div = DIV_ROUND_UP(prate, mode_rate);
	if (div < 2)
		div = 2;

	cfg |= ATMEL_HLCDC_CLKDIV(div);

	regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0),
			   ATMEL_HLCDC_CLKSEL | ATMEL_HLCDC_CLKDIV_MASK |
			   ATMEL_HLCDC_CLKPOL, cfg);

	cfg = 0;

	if (adj->flags & DRM_MODE_FLAG_NVSYNC)
		cfg |= ATMEL_HLCDC_VSPOL;

	if (adj->flags & DRM_MODE_FLAG_NHSYNC)
		cfg |= ATMEL_HLCDC_HSPOL;

	regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
			   ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |
			   ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |
			   ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |
			   ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
			   ATMEL_HLCDC_GUARDTIME_MASK,
			   cfg);
}

static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc,
					const struct drm_display_mode *mode,
					struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void atmel_hlcdc_crtc_disable(struct drm_crtc *c)
{
	struct drm_device *dev = c->dev;
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	struct regmap *regmap = crtc->dc->hlcdc->regmap;
	unsigned int status;

	if (!crtc->enabled)
		return;

	drm_crtc_vblank_off(c);

	pm_runtime_get_sync(dev->dev);

	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	       (status & ATMEL_HLCDC_DISP))
		cpu_relax();

	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	       (status & ATMEL_HLCDC_SYNC))
		cpu_relax();

	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	       (status & ATMEL_HLCDC_PIXEL_CLK))
		cpu_relax();

	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
	pinctrl_pm_select_sleep_state(dev->dev);

	pm_runtime_allow(dev->dev);

	pm_runtime_put_sync(dev->dev);

	crtc->enabled = false;
}

static void atmel_hlcdc_crtc_enable(struct drm_crtc *c)
{
	struct drm_device *dev = c->dev;
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	struct regmap *regmap = crtc->dc->hlcdc->regmap;
	unsigned int status;

	if (crtc->enabled)
		return;

	pm_runtime_get_sync(dev->dev);

	pm_runtime_forbid(dev->dev);

	pinctrl_pm_select_default_state(dev->dev);
	clk_prepare_enable(crtc->dc->hlcdc->sys_clk);

	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	       !(status & ATMEL_HLCDC_PIXEL_CLK))
		cpu_relax();


	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	       !(status & ATMEL_HLCDC_SYNC))
		cpu_relax();

	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	       !(status & ATMEL_HLCDC_DISP))
		cpu_relax();

	pm_runtime_put_sync(dev->dev);

	drm_crtc_vblank_on(c);

	crtc->enabled = true;
}

void atmel_hlcdc_crtc_suspend(struct drm_crtc *c)
{
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);

	if (crtc->enabled) {
		atmel_hlcdc_crtc_disable(c);
		/* save enable state for resume */
		crtc->enabled = true;
	}
}

void atmel_hlcdc_crtc_resume(struct drm_crtc *c)
{
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);

	if (crtc->enabled) {
		crtc->enabled = false;
		atmel_hlcdc_crtc_enable(c);
	}
}

static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,
					 struct drm_crtc_state *s)
{
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);

	if (atmel_hlcdc_dc_mode_valid(crtc->dc, &s->adjusted_mode) != MODE_OK)
		return -EINVAL;

	return atmel_hlcdc_plane_prepare_disc_area(s);
}

static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c)
{
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);

	if (c->state->event) {
		c->state->event->pipe = drm_crtc_index(c);

		WARN_ON(drm_crtc_vblank_get(c) != 0);

		crtc->event = c->state->event;
		c->state->event = NULL;
	}
}

static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc)
{
	/* TODO: write common plane control register if available */
}

static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
	.mode_fixup = atmel_hlcdc_crtc_mode_fixup,
	.mode_set = drm_helper_crtc_mode_set,
	.mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
	.mode_set_base = drm_helper_crtc_mode_set_base,
	.disable = atmel_hlcdc_crtc_disable,
	.enable = atmel_hlcdc_crtc_enable,
	.atomic_check = atmel_hlcdc_crtc_atomic_check,
	.atomic_begin = atmel_hlcdc_crtc_atomic_begin,
	.atomic_flush = atmel_hlcdc_crtc_atomic_flush,
};

static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c)
{
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);

	drm_crtc_cleanup(c);
	kfree(crtc);
}

void atmel_hlcdc_crtc_cancel_page_flip(struct drm_crtc *c,
				       struct drm_file *file)
{
	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	struct drm_pending_vblank_event *event;
	struct drm_device *dev = c->dev;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	event = crtc->event;
	if (event && event->base.file_priv == file) {
		event->base.destroy(&event->base);
		drm_vblank_put(dev, crtc->id);
		crtc->event = NULL;
	}
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	if (crtc->event) {
		drm_send_vblank_event(dev, crtc->id, crtc->event);
		drm_vblank_put(dev, crtc->id);
		crtc->event = NULL;
	}
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
{
	drm_handle_vblank(c->dev, 0);
	atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
}

static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
	.page_flip = drm_atomic_helper_page_flip,
	.set_config = drm_atomic_helper_set_config,
	.destroy = atmel_hlcdc_crtc_destroy,
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state =  drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};

int atmel_hlcdc_crtc_create(struct drm_device *dev)
{
	struct atmel_hlcdc_dc *dc = dev->dev_private;
	struct atmel_hlcdc_planes *planes = dc->planes;
	struct atmel_hlcdc_crtc *crtc;
	int ret;
	int i;

	crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
	if (!crtc)
		return -ENOMEM;

	crtc->dc = dc;

	ret = drm_crtc_init_with_planes(dev, &crtc->base,
				&planes->primary->base,
				planes->cursor ? &planes->cursor->base : NULL,
				&atmel_hlcdc_crtc_funcs);
	if (ret < 0)
		goto fail;

	crtc->id = drm_crtc_index(&crtc->base);

	if (planes->cursor)
		planes->cursor->base.possible_crtcs = 1 << crtc->id;

	for (i = 0; i < planes->noverlays; i++)
		planes->overlays[i]->base.possible_crtcs = 1 << crtc->id;

	drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
	drm_crtc_vblank_reset(&crtc->base);

	dc->crtc = &crtc->base;

	return 0;

fail:
	atmel_hlcdc_crtc_destroy(&crtc->base);
	return ret;
}
Commit	Line	Data
1a396789 BB	1	/*
	2	* Copyright (C) 2014 Traphandler
	3	* Copyright (C) 2014 Free Electrons
	4	*
	5	* Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
	6	* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License version 2 as published by
	10	* the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/clk.h>
	22	#include <linux/pm.h>
	23	#include <linux/pm_runtime.h>
16e6004e	24	#include <linux/pinctrl/consumer.h>
1a396789 BB	25
	26	#include <drm/drm_crtc.h>
	27	#include <drm/drm_crtc_helper.h>
	28	#include <drm/drmP.h>
	29
	30	#include <video/videomode.h>
	31
	32	#include "atmel_hlcdc_dc.h"
	33
	34	/**
	35	* Atmel HLCDC CRTC structure
	36	*
	37	* @base: base DRM CRTC structure
	38	* @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
	39	* @event: pointer to the current page flip event
	40	* @id: CRTC id (returned by drm_crtc_index)
2389fc13	41	* @enabled: CRTC state
1a396789 BB	42	*/
	43	struct atmel_hlcdc_crtc {
	44	struct drm_crtc base;
	45	struct atmel_hlcdc_dc *dc;
	46	struct drm_pending_vblank_event *event;
	47	int id;
2389fc13	48	bool enabled;
1a396789 BB	49	};
	50
	51	static inline struct atmel_hlcdc_crtc *
	52	drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
	53	{
	54	return container_of(crtc, struct atmel_hlcdc_crtc, base);
	55	}
	56
2389fc13	57	static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
1a396789	58	{
1a396789 BB	59	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
1a396789 BB	60	struct regmap *regmap = crtc->dc->hlcdc->regmap;
2389fc13	61	struct drm_display_mode *adj = &c->state->adjusted_mode;
1a396789 BB	62	unsigned long mode_rate;
	63	struct videomode vm;
	64	unsigned long prate;
	65	unsigned int cfg;
	66	int div;
	67
1a396789 BB	68	vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
	69	vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
	70	vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
	71	vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay;
	72	vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end;
	73	vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start;
	74
	75	regmap_write(regmap, ATMEL_HLCDC_CFG(1),
	76	(vm.hsync_len - 1) \| ((vm.vsync_len - 1) << 16));
	77
	78	regmap_write(regmap, ATMEL_HLCDC_CFG(2),
	79	(vm.vfront_porch - 1) \| (vm.vback_porch << 16));
	80
	81	regmap_write(regmap, ATMEL_HLCDC_CFG(3),
	82	(vm.hfront_porch - 1) \| ((vm.hback_porch - 1) << 16));
	83
	84	regmap_write(regmap, ATMEL_HLCDC_CFG(4),
	85	(adj->crtc_hdisplay - 1) \|
	86	((adj->crtc_vdisplay - 1) << 16));
	87
0bb59cb0	88	cfg = 0;
1a396789 BB	89
1a396789 BB	90	prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
2389fc13	91	mode_rate = adj->crtc_clock * 1000;
1a396789 BB	92	if ((prate / 2) < mode_rate) {
	93	prate *= 2;
	94	cfg \|= ATMEL_HLCDC_CLKSEL;
	95	}
	96
	97	div = DIV_ROUND_UP(prate, mode_rate);
	98	if (div < 2)
	99	div = 2;
	100
	101	cfg \|= ATMEL_HLCDC_CLKDIV(div);
	102
	103	regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0),
	104	ATMEL_HLCDC_CLKSEL \| ATMEL_HLCDC_CLKDIV_MASK \|
	105	ATMEL_HLCDC_CLKPOL, cfg);
	106
	107	cfg = 0;
	108
2389fc13	109	if (adj->flags & DRM_MODE_FLAG_NVSYNC)
1a396789 BB	110	cfg \|= ATMEL_HLCDC_VSPOL;
1a396789 BB	111
2389fc13	112	if (adj->flags & DRM_MODE_FLAG_NHSYNC)
1a396789 BB	113	cfg \|= ATMEL_HLCDC_HSPOL;
	114
	115	regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
	116	ATMEL_HLCDC_HSPOL \| ATMEL_HLCDC_VSPOL \|
	117	ATMEL_HLCDC_VSPDLYS \| ATMEL_HLCDC_VSPDLYE \|
	118	ATMEL_HLCDC_DISPPOL \| ATMEL_HLCDC_DISPDLY \|
	119	ATMEL_HLCDC_VSPSU \| ATMEL_HLCDC_VSPHO \|
	120	ATMEL_HLCDC_GUARDTIME_MASK,
	121	cfg);
1a396789 BB	122	}
1a396789 BB	123
2389fc13 BB	124	static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc,
	125	const struct drm_display_mode *mode,
	126	struct drm_display_mode *adjusted_mode)
1a396789	127	{
2389fc13	128	return true;
1a396789 BB	129	}
1a396789 BB	130
2389fc13	131	static void atmel_hlcdc_crtc_disable(struct drm_crtc *c)
1a396789	132	{
2389fc13 BB	133	struct drm_device *dev = c->dev;
	134	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	135	struct regmap *regmap = crtc->dc->hlcdc->regmap;
	136	unsigned int status;
	137
	138	if (!crtc->enabled)
	139	return;
	140
	141	drm_crtc_vblank_off(c);
	142
	143	pm_runtime_get_sync(dev->dev);
	144
	145	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
	146	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	147	(status & ATMEL_HLCDC_DISP))
	148	cpu_relax();
	149
	150	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
	151	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	152	(status & ATMEL_HLCDC_SYNC))
	153	cpu_relax();
	154
	155	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
	156	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	157	(status & ATMEL_HLCDC_PIXEL_CLK))
	158	cpu_relax();
	159
	160	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
16e6004e	161	pinctrl_pm_select_sleep_state(dev->dev);
2389fc13 BB	162
	163	pm_runtime_allow(dev->dev);
	164
	165	pm_runtime_put_sync(dev->dev);
	166
	167	crtc->enabled = false;
1a396789 BB	168	}
1a396789 BB	169
2389fc13	170	static void atmel_hlcdc_crtc_enable(struct drm_crtc *c)
1a396789	171	{
2389fc13 BB	172	struct drm_device *dev = c->dev;
	173	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	174	struct regmap *regmap = crtc->dc->hlcdc->regmap;
	175	unsigned int status;
	176
	177	if (crtc->enabled)
	178	return;
	179
	180	pm_runtime_get_sync(dev->dev);
	181
	182	pm_runtime_forbid(dev->dev);
	183
16e6004e	184	pinctrl_pm_select_default_state(dev->dev);
2389fc13 BB	185	clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
	186
	187	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
	188	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	189	!(status & ATMEL_HLCDC_PIXEL_CLK))
	190	cpu_relax();
	191
	192
	193	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
	194	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	195	!(status & ATMEL_HLCDC_SYNC))
	196	cpu_relax();
	197
	198	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
	199	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
	200	!(status & ATMEL_HLCDC_DISP))
	201	cpu_relax();
	202
	203	pm_runtime_put_sync(dev->dev);
	204
	205	drm_crtc_vblank_on(c);
	206
	207	crtc->enabled = true;
1a396789 BB	208	}
1a396789 BB	209
f026eb6e SR	210	void atmel_hlcdc_crtc_suspend(struct drm_crtc *c)
	211	{
	212	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	213
	214	if (crtc->enabled) {
	215	atmel_hlcdc_crtc_disable(c);
	216	/* save enable state for resume */
	217	crtc->enabled = true;
	218	}
	219	}
	220
	221	void atmel_hlcdc_crtc_resume(struct drm_crtc *c)
	222	{
	223	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	224
	225	if (crtc->enabled) {
	226	crtc->enabled = false;
	227	atmel_hlcdc_crtc_enable(c);
	228	}
	229	}
	230
2389fc13 BB	231	static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,
2389fc13 BB	232	struct drm_crtc_state *s)
1a396789	233	{
2389fc13 BB	234	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	235
	236	if (atmel_hlcdc_dc_mode_valid(crtc->dc, &s->adjusted_mode) != MODE_OK)
	237	return -EINVAL;
	238
5957017d	239	return atmel_hlcdc_plane_prepare_disc_area(s);
1a396789 BB	240	}
1a396789 BB	241
2389fc13	242	static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c)
1a396789	243	{
2389fc13	244	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
1a396789	245
2389fc13 BB	246	if (c->state->event) {
2389fc13 BB	247	c->state->event->pipe = drm_crtc_index(c);
1a396789	248
2389fc13	249	WARN_ON(drm_crtc_vblank_get(c) != 0);
1a396789	250
2389fc13 BB	251	crtc->event = c->state->event;
2389fc13 BB	252	c->state->event = NULL;
1a396789 BB	253	}
	254	}
	255
2389fc13 BB	256	static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc)
	257	{
	258	/* TODO: write common plane control register if available */
	259	}
	260
1a396789 BB	261	static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
1a396789 BB	262	.mode_fixup = atmel_hlcdc_crtc_mode_fixup,
2389fc13 BB	263	.mode_set = drm_helper_crtc_mode_set,
	264	.mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
	265	.mode_set_base = drm_helper_crtc_mode_set_base,
1a396789	266	.disable = atmel_hlcdc_crtc_disable,
2389fc13 BB	267	.enable = atmel_hlcdc_crtc_enable,
	268	.atomic_check = atmel_hlcdc_crtc_atomic_check,
	269	.atomic_begin = atmel_hlcdc_crtc_atomic_begin,
	270	.atomic_flush = atmel_hlcdc_crtc_atomic_flush,
1a396789 BB	271	};
	272
	273	static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c)
	274	{
	275	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	276
	277	drm_crtc_cleanup(c);
	278	kfree(crtc);
	279	}
	280
	281	void atmel_hlcdc_crtc_cancel_page_flip(struct drm_crtc *c,
	282	struct drm_file *file)
	283	{
	284	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
	285	struct drm_pending_vblank_event *event;
	286	struct drm_device *dev = c->dev;
	287	unsigned long flags;
	288
	289	spin_lock_irqsave(&dev->event_lock, flags);
	290	event = crtc->event;
	291	if (event && event->base.file_priv == file) {
	292	event->base.destroy(&event->base);
	293	drm_vblank_put(dev, crtc->id);
	294	crtc->event = NULL;
	295	}
	296	spin_unlock_irqrestore(&dev->event_lock, flags);
	297	}
	298
	299	static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc)
	300	{
	301	struct drm_device *dev = crtc->base.dev;
	302	unsigned long flags;
	303
	304	spin_lock_irqsave(&dev->event_lock, flags);
	305	if (crtc->event) {
	306	drm_send_vblank_event(dev, crtc->id, crtc->event);
	307	drm_vblank_put(dev, crtc->id);
	308	crtc->event = NULL;
	309	}
	310	spin_unlock_irqrestore(&dev->event_lock, flags);
	311	}
	312
	313	void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
	314	{
	315	drm_handle_vblank(c->dev, 0);
	316	atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
	317	}
	318
1a396789	319	static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
2389fc13 BB	320	.page_flip = drm_atomic_helper_page_flip,
2389fc13 BB	321	.set_config = drm_atomic_helper_set_config,
1a396789	322	.destroy = atmel_hlcdc_crtc_destroy,
2389fc13 BB	323	.reset = drm_atomic_helper_crtc_reset,
	324	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	325	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1a396789 BB	326	};
	327
	328	int atmel_hlcdc_crtc_create(struct drm_device *dev)
	329	{
	330	struct atmel_hlcdc_dc *dc = dev->dev_private;
	331	struct atmel_hlcdc_planes *planes = dc->planes;
	332	struct atmel_hlcdc_crtc *crtc;
	333	int ret;
	334	int i;
	335
	336	crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
	337	if (!crtc)
	338	return -ENOMEM;
	339
1a396789 BB	340	crtc->dc = dc;
	341
	342	ret = drm_crtc_init_with_planes(dev, &crtc->base,
	343	&planes->primary->base,
	344	planes->cursor ? &planes->cursor->base : NULL,
	345	&atmel_hlcdc_crtc_funcs);
	346	if (ret < 0)
	347	goto fail;
	348
	349	crtc->id = drm_crtc_index(&crtc->base);
	350
	351	if (planes->cursor)
	352	planes->cursor->base.possible_crtcs = 1 << crtc->id;
	353
	354	for (i = 0; i < planes->noverlays; i++)
	355	planes->overlays[i]->base.possible_crtcs = 1 << crtc->id;
	356
	357	drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
8c4b4b0d	358	drm_crtc_vblank_reset(&crtc->base);
1a396789 BB	359
	360	dc->crtc = &crtc->base;
	361
	362	return 0;
	363
	364	fail:
	365	atmel_hlcdc_crtc_destroy(&crtc->base);
	366	return ret;
	367	}
	368