Commit | Line | Data |
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1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file ati_pcigart.c |
1da177e4 LT |
3 | * ATI PCI GART support |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com | |
10 | * | |
11 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
12 | * All Rights Reserved. | |
13 | * | |
14 | * Permission is hereby granted, free of charge, to any person obtaining a | |
15 | * copy of this software and associated documentation files (the "Software"), | |
16 | * to deal in the Software without restriction, including without limitation | |
17 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
18 | * and/or sell copies of the Software, and to permit persons to whom the | |
19 | * Software is furnished to do so, subject to the following conditions: | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the next | |
22 | * paragraph) shall be included in all copies or substantial portions of the | |
23 | * Software. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
26 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
27 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
28 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
29 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
30 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
31 | * DEALINGS IN THE SOFTWARE. | |
32 | */ | |
33 | ||
2d1a8a48 | 34 | #include <linux/export.h> |
1da177e4 | 35 | |
fd7e0d71 | 36 | #include <drm/ati_pcigart.h> |
0500c04e | 37 | #include <drm/drm_device.h> |
0500c04e SR |
38 | #include <drm/drm_pci.h> |
39 | #include <drm/drm_print.h> | |
fd7e0d71 | 40 | |
1da177e4 LT |
41 | # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ |
42 | ||
b05c2385 DA |
43 | static int drm_ati_alloc_pcigart_table(struct drm_device *dev, |
44 | struct drm_ati_pcigart_info *gart_info) | |
1da177e4 | 45 | { |
b05c2385 | 46 | gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size, |
e6be8d9d | 47 | PAGE_SIZE); |
b05c2385 DA |
48 | if (gart_info->table_handle == NULL) |
49 | return -ENOMEM; | |
1da177e4 | 50 | |
b05c2385 | 51 | return 0; |
1da177e4 LT |
52 | } |
53 | ||
b05c2385 DA |
54 | static void drm_ati_free_pcigart_table(struct drm_device *dev, |
55 | struct drm_ati_pcigart_info *gart_info) | |
1da177e4 | 56 | { |
b05c2385 DA |
57 | drm_pci_free(dev, gart_info->table_handle); |
58 | gart_info->table_handle = NULL; | |
1da177e4 LT |
59 | } |
60 | ||
55910517 | 61 | int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 62 | { |
55910517 | 63 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
64 | unsigned long pages; |
65 | int i; | |
b05c2385 | 66 | int max_pages; |
1da177e4 LT |
67 | |
68 | /* we need to support large memory configurations */ | |
b5e89ed5 DA |
69 | if (!entry) { |
70 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
71 | return 0; |
72 | } | |
73 | ||
ea98a92f | 74 | if (gart_info->bus_addr) { |
1da177e4 | 75 | |
f2b04cd2 DA |
76 | max_pages = (gart_info->table_size / sizeof(u32)); |
77 | pages = (entry->pages <= max_pages) | |
78 | ? entry->pages : max_pages; | |
1da177e4 | 79 | |
b5e89ed5 DA |
80 | for (i = 0; i < pages; i++) { |
81 | if (!entry->busaddr[i]) | |
82 | break; | |
7ec700fc | 83 | pci_unmap_page(dev->pdev, entry->busaddr[i], |
296c6ae0 | 84 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
1da177e4 | 85 | } |
b5e89ed5 DA |
86 | |
87 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) | |
88 | gart_info->bus_addr = 0; | |
1da177e4 LT |
89 | } |
90 | ||
b05c2385 DA |
91 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN && |
92 | gart_info->table_handle) { | |
93 | drm_ati_free_pcigart_table(dev, gart_info); | |
1da177e4 LT |
94 | } |
95 | ||
96 | return 1; | |
97 | } | |
98 | EXPORT_SYMBOL(drm_ati_pcigart_cleanup); | |
99 | ||
55910517 | 100 | int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 101 | { |
5a7aad9a | 102 | struct drm_local_map *map = &gart_info->mapping; |
55910517 | 103 | struct drm_sg_mem *entry = dev->sg; |
f26c473c | 104 | void *address = NULL; |
1da177e4 | 105 | unsigned long pages; |
6abf6601 | 106 | u32 *pci_gart = NULL, page_base, gart_idx; |
b05c2385 | 107 | dma_addr_t bus_address = 0; |
c27889ca | 108 | int i, j, ret = -ENOMEM; |
d30333bb | 109 | int max_ati_pages, max_real_pages; |
1da177e4 | 110 | |
b5e89ed5 DA |
111 | if (!entry) { |
112 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
113 | goto done; |
114 | } | |
115 | ||
b5e89ed5 | 116 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
ea98a92f | 117 | DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); |
b5e89ed5 | 118 | |
e6be8d9d ZW |
119 | if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) { |
120 | DRM_ERROR("fail to set dma mask to 0x%Lx\n", | |
d7748bac | 121 | (unsigned long long)gart_info->table_mask); |
c27889ca | 122 | ret = -EFAULT; |
e6be8d9d ZW |
123 | goto done; |
124 | } | |
125 | ||
b05c2385 DA |
126 | ret = drm_ati_alloc_pcigart_table(dev, gart_info); |
127 | if (ret) { | |
b5e89ed5 | 128 | DRM_ERROR("cannot allocate PCI GART page!\n"); |
ea98a92f DA |
129 | goto done; |
130 | } | |
b5e89ed5 | 131 | |
6abf6601 | 132 | pci_gart = gart_info->table_handle->vaddr; |
b05c2385 DA |
133 | address = gart_info->table_handle->vaddr; |
134 | bus_address = gart_info->table_handle->busaddr; | |
b5e89ed5 | 135 | } else { |
ea98a92f DA |
136 | address = gart_info->addr; |
137 | bus_address = gart_info->bus_addr; | |
f67e74ca AM |
138 | DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n", |
139 | (unsigned long long)bus_address, | |
140 | (unsigned long)address); | |
1da177e4 LT |
141 | } |
142 | ||
1da177e4 | 143 | |
d30333bb DM |
144 | max_ati_pages = (gart_info->table_size / sizeof(u32)); |
145 | max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); | |
146 | pages = (entry->pages <= max_real_pages) | |
147 | ? entry->pages : max_real_pages; | |
1da177e4 | 148 | |
5a7aad9a | 149 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
d30333bb | 150 | memset(pci_gart, 0, max_ati_pages * sizeof(u32)); |
5a7aad9a | 151 | } else { |
6abf6601 | 152 | memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32)); |
5a7aad9a | 153 | } |
1da177e4 | 154 | |
5a7aad9a | 155 | gart_idx = 0; |
b5e89ed5 | 156 | for (i = 0; i < pages; i++) { |
1da177e4 | 157 | /* we need to support large memory configurations */ |
7ec700fc | 158 | entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i], |
296c6ae0 | 159 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
a30f6fb7 | 160 | if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) { |
b5e89ed5 | 161 | DRM_ERROR("unable to map PCIGART pages!\n"); |
ea98a92f | 162 | drm_ati_pcigart_cleanup(dev, gart_info); |
f26c473c | 163 | address = NULL; |
1da177e4 | 164 | bus_address = 0; |
c27889ca | 165 | ret = -ENOMEM; |
1da177e4 LT |
166 | goto done; |
167 | } | |
168 | page_base = (u32) entry->busaddr[i]; | |
169 | ||
170 | for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { | |
03fda35d | 171 | u32 offset; |
5a7aad9a DM |
172 | u32 val; |
173 | ||
f2b04cd2 DA |
174 | switch(gart_info->gart_reg_if) { |
175 | case DRM_ATI_GART_IGP: | |
5a7aad9a | 176 | val = page_base | 0xc; |
f2b04cd2 DA |
177 | break; |
178 | case DRM_ATI_GART_PCIE: | |
5a7aad9a | 179 | val = (page_base >> 8) | 0xc; |
f2b04cd2 DA |
180 | break; |
181 | default: | |
182 | case DRM_ATI_GART_PCI: | |
5a7aad9a | 183 | val = page_base; |
f2b04cd2 DA |
184 | break; |
185 | } | |
5a7aad9a | 186 | if (gart_info->gart_table_location == |
03fda35d | 187 | DRM_ATI_GART_MAIN) { |
5a7aad9a | 188 | pci_gart[gart_idx] = cpu_to_le32(val); |
03fda35d SR |
189 | } else { |
190 | offset = gart_idx * sizeof(u32); | |
191 | writel(val, (void __iomem *)map->handle + offset); | |
192 | } | |
5a7aad9a | 193 | gart_idx++; |
1da177e4 LT |
194 | page_base += ATI_PCIGART_PAGE_SIZE; |
195 | } | |
196 | } | |
c27889ca | 197 | ret = 0; |
1da177e4 LT |
198 | |
199 | #if defined(__i386__) || defined(__x86_64__) | |
200 | wbinvd(); | |
201 | #else | |
202 | mb(); | |
203 | #endif | |
204 | ||
b5e89ed5 | 205 | done: |
ea98a92f | 206 | gart_info->addr = address; |
b5e89ed5 | 207 | gart_info->bus_addr = bus_address; |
1da177e4 LT |
208 | return ret; |
209 | } | |
210 | EXPORT_SYMBOL(drm_ati_pcigart_init); |