[linux-2.6-block.git] / drivers / gpu / drm / ast / ast_main.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors: Dave Airlie <airlied@redhat.com>
 */

#include <linux/of.h>
#include <linux/pci.h>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_gem.h>
#include <drm/drm_managed.h>

#include "ast_drv.h"

static void ast_detect_widescreen(struct ast_device *ast)
{
	u8 jreg;

	/* Check if we support wide screen */
	switch (AST_GEN(ast)) {
	case 1:
		ast->support_wide_screen = false;
		break;
	default:
		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
		if (!(jreg & 0x80))
			ast->support_wide_screen = true;
		else if (jreg & 0x01)
			ast->support_wide_screen = true;
		else {
			ast->support_wide_screen = false;
			if (ast->chip == AST1300)
				ast->support_wide_screen = true;
			if (ast->chip == AST1400)
				ast->support_wide_screen = true;
			if (ast->chip == AST2510)
				ast->support_wide_screen = true;
			if (IS_AST_GEN7(ast))
				ast->support_wide_screen = true;
		}
		break;
	}
}

static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
{
	struct drm_device *dev = &ast->base;
	u8 jreg;

	/* Check 3rd Tx option (digital output afaik) */
	ast->tx_chip_types |= AST_TX_NONE_BIT;

	/*
	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
	 *
	 * Don't make that assumption if we the chip wasn't enabled and
	 * is at power-on reset, otherwise we'll incorrectly "detect" a
	 * SIL164 when there is none.
	 */
	if (!need_post) {
		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
		if (jreg & 0x80)
			ast->tx_chip_types = AST_TX_SIL164_BIT;
	}

	if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
		/*
		 * On AST GEN4+, look the configuration set by the SoC in
		 * the SOC scratch register #1 bits 11:8 (interestingly marked
		 * as "reserved" in the spec)
		 */
		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
		switch (jreg) {
		case 0x04:
			ast->tx_chip_types = AST_TX_SIL164_BIT;
			break;
		case 0x08:
			ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
			if (ast->dp501_fw_addr) {
				/* backup firmware */
				if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
					drmm_kfree(dev, ast->dp501_fw_addr);
					ast->dp501_fw_addr = NULL;
				}
			}
			fallthrough;
		case 0x0c:
			ast->tx_chip_types = AST_TX_DP501_BIT;
		}
	} else if (IS_AST_GEN7(ast)) {
		if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) ==
		    ASTDP_DPMCU_TX) {
			int ret = ast_dp_launch(ast);

			if (!ret)
				ast->tx_chip_types = AST_TX_ASTDP_BIT;
		}
	}

	/* Print stuff for diagnostic purposes */
	if (ast->tx_chip_types & AST_TX_NONE_BIT)
		drm_info(dev, "Using analog VGA\n");
	if (ast->tx_chip_types & AST_TX_SIL164_BIT)
		drm_info(dev, "Using Sil164 TMDS transmitter\n");
	if (ast->tx_chip_types & AST_TX_DP501_BIT)
		drm_info(dev, "Using DP501 DisplayPort transmitter\n");
	if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
		drm_info(dev, "Using ASPEED DisplayPort transmitter\n");
}

static int ast_get_dram_info(struct drm_device *dev)
{
	struct device_node *np = dev->dev->of_node;
	struct ast_device *ast = to_ast_device(dev);
	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
	uint32_t denum, num, div, ref_pll, dsel;

	switch (ast->config_mode) {
	case ast_use_dt:
		/*
		 * If some properties are missing, use reasonable
		 * defaults for GEN5
		 */
		if (of_property_read_u32(np, "aspeed,mcr-configuration",
					 &mcr_cfg))
			mcr_cfg = 0x00000577;
		if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
					 &mcr_scu_mpll))
			mcr_scu_mpll = 0x000050C0;
		if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
					 &mcr_scu_strap))
			mcr_scu_strap = 0;
		break;
	case ast_use_p2a:
		ast_write32(ast, 0xf004, 0x1e6e0000);
		ast_write32(ast, 0xf000, 0x1);
		mcr_cfg = ast_read32(ast, 0x10004);
		mcr_scu_mpll = ast_read32(ast, 0x10120);
		mcr_scu_strap = ast_read32(ast, 0x10170);
		break;
	case ast_use_defaults:
	default:
		ast->dram_bus_width = 16;
		ast->dram_type = AST_DRAM_1Gx16;
		if (IS_AST_GEN6(ast))
			ast->mclk = 800;
		else
			ast->mclk = 396;
		return 0;
	}

	if (mcr_cfg & 0x40)
		ast->dram_bus_width = 16;
	else
		ast->dram_bus_width = 32;

	if (IS_AST_GEN6(ast)) {
		switch (mcr_cfg & 0x03) {
		case 0:
			ast->dram_type = AST_DRAM_1Gx16;
			break;
		default:
		case 1:
			ast->dram_type = AST_DRAM_2Gx16;
			break;
		case 2:
			ast->dram_type = AST_DRAM_4Gx16;
			break;
		case 3:
			ast->dram_type = AST_DRAM_8Gx16;
			break;
		}
	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast)) {
		switch (mcr_cfg & 0x03) {
		case 0:
			ast->dram_type = AST_DRAM_512Mx16;
			break;
		default:
		case 1:
			ast->dram_type = AST_DRAM_1Gx16;
			break;
		case 2:
			ast->dram_type = AST_DRAM_2Gx16;
			break;
		case 3:
			ast->dram_type = AST_DRAM_4Gx16;
			break;
		}
	} else {
		switch (mcr_cfg & 0x0c) {
		case 0:
		case 4:
			ast->dram_type = AST_DRAM_512Mx16;
			break;
		case 8:
			if (mcr_cfg & 0x40)
				ast->dram_type = AST_DRAM_1Gx16;
			else
				ast->dram_type = AST_DRAM_512Mx32;
			break;
		case 0xc:
			ast->dram_type = AST_DRAM_1Gx32;
			break;
		}
	}

	if (mcr_scu_strap & 0x2000)
		ref_pll = 14318;
	else
		ref_pll = 12000;

	denum = mcr_scu_mpll & 0x1f;
	num = (mcr_scu_mpll & 0x3fe0) >> 5;
	dsel = (mcr_scu_mpll & 0xc000) >> 14;
	switch (dsel) {
	case 3:
		div = 0x4;
		break;
	case 2:
	case 1:
		div = 0x2;
		break;
	default:
		div = 0x1;
		break;
	}
	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
	return 0;
}

struct drm_device *ast_device_create(struct pci_dev *pdev,
				     const struct drm_driver *drv,
				     enum ast_chip chip,
				     enum ast_config_mode config_mode,
				     void __iomem *regs,
				     void __iomem *ioregs,
				     bool need_post)
{
	struct drm_device *dev;
	struct ast_device *ast;
	int ret;

	ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
	if (IS_ERR(ast))
		return ERR_CAST(ast);
	dev = &ast->base;

	ast->chip = chip;
	ast->config_mode = config_mode;
	ast->regs = regs;
	ast->ioregs = ioregs;

	ast_detect_widescreen(ast);
	ast_detect_tx_chip(ast, need_post);

	ret = ast_get_dram_info(dev);
	if (ret)
		return ERR_PTR(ret);

	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
		 ast->mclk, ast->dram_type, ast->dram_bus_width);

	if (need_post)
		ast_post_gpu(dev);

	ret = ast_mm_init(ast);
	if (ret)
		return ERR_PTR(ret);

	/* map reserved buffer */
	ast->dp501_fw_buf = NULL;
	if (ast->vram_size < pci_resource_len(pdev, 0)) {
		ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
		if (!ast->dp501_fw_buf)
			drm_info(dev, "failed to map reserved buffer!\n");
	}

	ret = ast_mode_config_init(ast);
	if (ret)
		return ERR_PTR(ret);

	return dev;
}
Commit	Line	Data
312fec14 DA	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the
	6	* "Software"), to deal in the Software without restriction, including
	7	* without limitation the rights to use, copy, modify, merge, publish,
	8	* distribute, sub license, and/or sell copies of the Software, and to
	9	* permit persons to whom the Software is furnished to do so, subject to
	10	* the following conditions:
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	16	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	17	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	18	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* The above copyright notice and this permission notice (including the
	21	* next paragraph) shall be included in all copies or substantial portions
	22	* of the Software.
	23	*
	24	*/
	25	/*
	26	* Authors: Dave Airlie <airlied@redhat.com>
	27	*/
fbbbd160	28
8463b66b	29	#include <linux/of.h>
fbbbd160	30	#include <linux/pci.h>
312fec14	31
4961eb60	32	#include <drm/drm_atomic_helper.h>
fbe01716	33	#include <drm/drm_drv.h>
fbbbd160	34	#include <drm/drm_gem.h>
4bc85b82	35	#include <drm/drm_managed.h>
fbbbd160 SR	36
fbbbd160 SR	37	#include "ast_drv.h"
312fec14	38
546b959e TZ	39	static void ast_detect_widescreen(struct ast_device *ast)
	40	{
	41	u8 jreg;
	42
d1b98557	43	/* Check if we support wide screen */
ecf64579 TZ	44	switch (AST_GEN(ast)) {
ecf64579 TZ	45	case 1:
f1f62f2c DA	46	ast->support_wide_screen = false;
	47	break;
	48	default:
c79479fa	49	jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
f1f62f2c DA	50	if (!(jreg & 0x80))
	51	ast->support_wide_screen = true;
	52	else if (jreg & 0x01)
	53	ast->support_wide_screen = true;
	54	else {
	55	ast->support_wide_screen = false;
6bd576da	56	if (ast->chip == AST1300)
71f677a9	57	ast->support_wide_screen = true;
86d86d1b	58	if (ast->chip == AST1400)
71f677a9	59	ast->support_wide_screen = true;
52c29330	60	if (ast->chip == AST2510)
9f93c8b3	61	ast->support_wide_screen = true;
ecf64579	62	if (IS_AST_GEN7(ast))
59a39fcc	63	ast->support_wide_screen = true;
f1f62f2c DA	64	}
	65	break;
	66	}
546b959e TZ	67	}
	68
	69	static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
	70	{
	71	struct drm_device *dev = &ast->base;
	72	u8 jreg;
f1f62f2c	73
d1b98557	74	/* Check 3rd Tx option (digital output afaik) */
7f35680a	75	ast->tx_chip_types \|= AST_TX_NONE_BIT;
d1b98557 BH	76
	77	/*
	78	* VGACRA3 Enhanced Color Mode Register, check if DVO is already
	79	* enabled, in that case, assume we have a SIL164 TMDS transmitter
42fb1427 BH	80	*
	81	* Don't make that assumption if we the chip wasn't enabled and
	82	* is at power-on reset, otherwise we'll incorrectly "detect" a
	83	* SIL164 when there is none.
d1b98557	84	*/
3bfe25b5	85	if (!need_post) {
c79479fa	86	jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
42fb1427	87	if (jreg & 0x80)
7f35680a	88	ast->tx_chip_types = AST_TX_SIL164_BIT;
42fb1427	89	}
d1b98557	90
ecf64579	91	if (IS_AST_GEN4(ast) \|\| IS_AST_GEN5(ast) \|\| IS_AST_GEN6(ast)) {
d1b98557	92	/*
ecf64579	93	* On AST GEN4+, look the configuration set by the SoC in
d1b98557	94	* the SOC scratch register #1 bits 11:8 (interestingly marked
42fb1427	95	* as "reserved" in the spec)
d1b98557	96	*/
c79479fa	97	jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
83c6620b DA	98	switch (jreg) {
83c6620b DA	99	case 0x04:
7f35680a	100	ast->tx_chip_types = AST_TX_SIL164_BIT;
83c6620b DA	101	break;
83c6620b DA	102	case 0x08:
4bc85b82	103	ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
83c6620b DA	104	if (ast->dp501_fw_addr) {
	105	/* backup firmware */
	106	if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
4bc85b82	107	drmm_kfree(dev, ast->dp501_fw_addr);
83c6620b DA	108	ast->dp501_fw_addr = NULL;
	109	}
	110	}
df561f66	111	fallthrough;
83c6620b	112	case 0x0c:
7f35680a	113	ast->tx_chip_types = AST_TX_DP501_BIT;
83c6620b	114	}
ecf64579	115	} else if (IS_AST_GEN7(ast)) {
c79479fa	116	if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) ==
bed61c8f	117	ASTDP_DPMCU_TX) {
c91d75a3 TZ	118	int ret = ast_dp_launch(ast);
	119
	120	if (!ret)
	121	ast->tx_chip_types = AST_TX_ASTDP_BIT;
bed61c8f JH	122	}
bed61c8f JH	123	}
83c6620b	124
d1b98557	125	/* Print stuff for diagnostic purposes */
7f35680a TZ	126	if (ast->tx_chip_types & AST_TX_NONE_BIT)
	127	drm_info(dev, "Using analog VGA\n");
	128	if (ast->tx_chip_types & AST_TX_SIL164_BIT)
1a19b4cb	129	drm_info(dev, "Using Sil164 TMDS transmitter\n");
7f35680a	130	if (ast->tx_chip_types & AST_TX_DP501_BIT)
1a19b4cb	131	drm_info(dev, "Using DP501 DisplayPort transmitter\n");
bed61c8f JH	132	if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
bed61c8f JH	133	drm_info(dev, "Using ASPEED DisplayPort transmitter\n");
312fec14 DA	134	}
	135
	136	static int ast_get_dram_info(struct drm_device *dev)
	137	{
46fb883c	138	struct device_node *np = dev->dev->of_node;
5abaa683	139	struct ast_device *ast = to_ast_device(dev);
71f677a9 RC	140	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
71f677a9 RC	141	uint32_t denum, num, div, ref_pll, dsel;
312fec14	142
71f677a9 RC	143	switch (ast->config_mode) {
	144	case ast_use_dt:
	145	/*
	146	* If some properties are missing, use reasonable
ecf64579	147	* defaults for GEN5
71f677a9 RC	148	*/
	149	if (of_property_read_u32(np, "aspeed,mcr-configuration",
	150	&mcr_cfg))
	151	mcr_cfg = 0x00000577;
	152	if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
	153	&mcr_scu_mpll))
	154	mcr_scu_mpll = 0x000050C0;
	155	if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
	156	&mcr_scu_strap))
	157	mcr_scu_strap = 0;
	158	break;
	159	case ast_use_p2a:
	160	ast_write32(ast, 0xf004, 0x1e6e0000);
	161	ast_write32(ast, 0xf000, 0x1);
	162	mcr_cfg = ast_read32(ast, 0x10004);
	163	mcr_scu_mpll = ast_read32(ast, 0x10120);
	164	mcr_scu_strap = ast_read32(ast, 0x10170);
	165	break;
	166	case ast_use_defaults:
	167	default:
6c971c09 C	168	ast->dram_bus_width = 16;
6c971c09 C	169	ast->dram_type = AST_DRAM_1Gx16;
ecf64579	170	if (IS_AST_GEN6(ast))
9f93c8b3 C	171	ast->mclk = 800;
	172	else
	173	ast->mclk = 396;
71f677a9	174	return 0;
6c971c09	175	}
312fec14	176
71f677a9 RC	177	if (mcr_cfg & 0x40)
	178	ast->dram_bus_width = 16;
	179	else
	180	ast->dram_bus_width = 32;
312fec14	181
ecf64579	182	if (IS_AST_GEN6(ast)) {
9f93c8b3 C	183	switch (mcr_cfg & 0x03) {
	184	case 0:
	185	ast->dram_type = AST_DRAM_1Gx16;
	186	break;
	187	default:
	188	case 1:
	189	ast->dram_type = AST_DRAM_2Gx16;
	190	break;
	191	case 2:
	192	ast->dram_type = AST_DRAM_4Gx16;
	193	break;
	194	case 3:
	195	ast->dram_type = AST_DRAM_8Gx16;
	196	break;
	197	}
ecf64579	198	} else if (IS_AST_GEN4(ast) \|\| IS_AST_GEN5(ast)) {
71f677a9 RC	199	switch (mcr_cfg & 0x03) {
	200	case 0:
	201	ast->dram_type = AST_DRAM_512Mx16;
312fec14	202	break;
71f677a9	203	default:
6c971c09	204	case 1:
71f677a9	205	ast->dram_type = AST_DRAM_1Gx16;
312fec14	206	break;
71f677a9 RC	207	case 2:
	208	ast->dram_type = AST_DRAM_2Gx16;
	209	break;
	210	case 3:
	211	ast->dram_type = AST_DRAM_4Gx16;
	212	break;
	213	}
	214	} else {
	215	switch (mcr_cfg & 0x0c) {
	216	case 0:
	217	case 4:
	218	ast->dram_type = AST_DRAM_512Mx16;
	219	break;
	220	case 8:
	221	if (mcr_cfg & 0x40)
	222	ast->dram_type = AST_DRAM_1Gx16;
	223	else
	224	ast->dram_type = AST_DRAM_512Mx32;
	225	break;
	226	case 0xc:
	227	ast->dram_type = AST_DRAM_1Gx32;
312fec14 DA	228	break;
	229	}
	230	}
71f677a9 RC	231
	232	if (mcr_scu_strap & 0x2000)
	233	ref_pll = 14318;
	234	else
	235	ref_pll = 12000;
	236
	237	denum = mcr_scu_mpll & 0x1f;
	238	num = (mcr_scu_mpll & 0x3fe0) >> 5;
	239	dsel = (mcr_scu_mpll & 0xc000) >> 14;
	240	switch (dsel) {
	241	case 3:
	242	div = 0x4;
	243	break;
	244	case 2:
	245	case 1:
	246	div = 0x2;
	247	break;
	248	default:
	249	div = 0x1;
	250	break;
	251	}
6475a7cc	252	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
312fec14 DA	253	return 0;
	254	}
	255
83dc1029 TZ	256	struct drm_device ast_device_create(struct pci_dev pdev,
	257	const struct drm_driver *drv,
	258	enum ast_chip chip,
	259	enum ast_config_mode config_mode,
	260	void __iomem *regs,
	261	void __iomem *ioregs,
	262	bool need_post)
312fec14	263	{
fbe01716	264	struct drm_device *dev;
37b42cf9	265	struct ast_device *ast;
83dc1029	266	int ret;
312fec14	267
37b42cf9	268	ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
e0f5a738	269	if (IS_ERR(ast))
83dc1029	270	return ERR_CAST(ast);
e0f5a738	271	dev = &ast->base;
fbe01716	272
51412f86 TZ	273	ast->chip = chip;
51412f86 TZ	274	ast->config_mode = config_mode;
83dc1029 TZ	275	ast->regs = regs;
83dc1029 TZ	276	ast->ioregs = ioregs;
51412f86	277
546b959e TZ	278	ast_detect_widescreen(ast);
546b959e TZ	279	ast_detect_tx_chip(ast, need_post);
312fec14	280
05f13f5b TZ	281	ret = ast_get_dram_info(dev);
05f13f5b TZ	282	if (ret)
e0f5a738 TZ	283	return ERR_PTR(ret);
e0f5a738 TZ	284
0149e780 TZ	285	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
0149e780 TZ	286	ast->mclk, ast->dram_type, ast->dram_bus_width);
312fec14	287
244d0128 TZ	288	if (need_post)
	289	ast_post_gpu(dev);
	290
312fec14 DA	291	ret = ast_mm_init(ast);
312fec14 DA	292	if (ret)
e0f5a738	293	return ERR_PTR(ret);
312fec14	294
ba4e0339 KC	295	/* map reserved buffer */
ba4e0339 KC	296	ast->dp501_fw_buf = NULL;
f2fa5a99 TZ	297	if (ast->vram_size < pci_resource_len(pdev, 0)) {
f2fa5a99 TZ	298	ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
ba4e0339 KC	299	if (!ast->dp501_fw_buf)
	300	drm_info(dev, "failed to map reserved buffer!\n");
	301	}
	302
e6949ff3	303	ret = ast_mode_config_init(ast);
312fec14	304	if (ret)
e0f5a738	305	return ERR_PTR(ret);
312fec14	306
83dc1029	307	return dev;
312fec14	308	}