[linux-2.6-block.git] / drivers / gpu / drm / ast / ast_main.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors: Dave Airlie <airlied@redhat.com>
 */

#include <linux/pci.h>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_gem.h>
#include <drm/drm_managed.h>

#include "ast_drv.h"

static bool ast_is_vga_enabled(struct drm_device *dev)
{
	struct ast_device *ast = to_ast_device(dev);
	u8 ch;

	ch = ast_io_read8(ast, AST_IO_VGAER);

	return !!(ch & 0x01);
}

static void ast_enable_vga(struct drm_device *dev)
{
	struct ast_device *ast = to_ast_device(dev);

	ast_io_write8(ast, AST_IO_VGAER, 0x01);
	ast_io_write8(ast, AST_IO_VGAMR_W, 0x01);
}

/*
 * Run this function as part of the HW device cleanup; not
 * when the DRM device gets released.
 */
static void ast_enable_mmio_release(void *data)
{
	struct ast_device *ast = data;

	/* enable standard VGA decode */
	ast_set_index_reg(ast, AST_IO_VGACRI, 0xa1, 0x04);
}

static int ast_enable_mmio(struct ast_device *ast)
{
	struct drm_device *dev = &ast->base;

	ast_set_index_reg(ast, AST_IO_VGACRI, 0xa1, 0x06);

	return devm_add_action_or_reset(dev->dev, ast_enable_mmio_release, ast);
}

static void ast_open_key(struct ast_device *ast)
{
	ast_set_index_reg(ast, AST_IO_VGACRI, 0x80, 0xA8);
}

static int ast_device_config_init(struct ast_device *ast)
{
	struct drm_device *dev = &ast->base;
	struct pci_dev *pdev = to_pci_dev(dev->dev);
	struct device_node *np = dev->dev->of_node;
	uint32_t scu_rev = 0xffffffff;
	u32 data;
	u8 jregd0, jregd1;

	/*
	 * Find configuration mode and read SCU revision
	 */

	ast->config_mode = ast_use_defaults;

	/* Check if we have device-tree properties */
	if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) {
		/* We do, disable P2A access */
		ast->config_mode = ast_use_dt;
		scu_rev = data;
	} else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge
		/*
		 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
		 * is disabled. We force using P2A if VGA only mode bit
		 * is set D[7]
		 */
		jregd0 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
		jregd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
		if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {

			/*
			 * We have a P2A bridge and it is enabled.
			 */

			/* Patch AST2500/AST2510 */
			if ((pdev->revision & 0xf0) == 0x40) {
				if (!(jregd0 & AST_VRAM_INIT_STATUS_MASK))
					ast_patch_ahb_2500(ast);
			}

			/* Double check that it's actually working */
			data = ast_read32(ast, 0xf004);
			if ((data != 0xffffffff) && (data != 0x00)) {
				ast->config_mode = ast_use_p2a;

				/* Read SCU7c (silicon revision register) */
				ast_write32(ast, 0xf004, 0x1e6e0000);
				ast_write32(ast, 0xf000, 0x1);
				scu_rev = ast_read32(ast, 0x1207c);
			}
		}
	}

	switch (ast->config_mode) {
	case ast_use_defaults:
		drm_info(dev, "Using default configuration\n");
		break;
	case ast_use_dt:
		drm_info(dev, "Using device-tree for configuration\n");
		break;
	case ast_use_p2a:
		drm_info(dev, "Using P2A bridge for configuration\n");
		break;
	}

	/*
	 * Identify chipset
	 */

	if (pdev->revision >= 0x50) {
		ast->chip = AST2600;
		drm_info(dev, "AST 2600 detected\n");
	} else if (pdev->revision >= 0x40) {
		switch (scu_rev & 0x300) {
		case 0x0100:
			ast->chip = AST2510;
			drm_info(dev, "AST 2510 detected\n");
			break;
		default:
			ast->chip = AST2500;
			drm_info(dev, "AST 2500 detected\n");
		}
	} else if (pdev->revision >= 0x30) {
		switch (scu_rev & 0x300) {
		case 0x0100:
			ast->chip = AST1400;
			drm_info(dev, "AST 1400 detected\n");
			break;
		default:
			ast->chip = AST2400;
			drm_info(dev, "AST 2400 detected\n");
		}
	} else if (pdev->revision >= 0x20) {
		switch (scu_rev & 0x300) {
		case 0x0000:
			ast->chip = AST1300;
			drm_info(dev, "AST 1300 detected\n");
			break;
		default:
			ast->chip = AST2300;
			drm_info(dev, "AST 2300 detected\n");
			break;
		}
	} else if (pdev->revision >= 0x10) {
		switch (scu_rev & 0x0300) {
		case 0x0200:
			ast->chip = AST1100;
			drm_info(dev, "AST 1100 detected\n");
			break;
		case 0x0100:
			ast->chip = AST2200;
			drm_info(dev, "AST 2200 detected\n");
			break;
		case 0x0000:
			ast->chip = AST2150;
			drm_info(dev, "AST 2150 detected\n");
			break;
		default:
			ast->chip = AST2100;
			drm_info(dev, "AST 2100 detected\n");
			break;
		}
	} else {
		ast->chip = AST2000;
		drm_info(dev, "AST 2000 detected\n");
	}

	return 0;
}

static void ast_detect_widescreen(struct ast_device *ast)
{
	u8 jreg;

	/* Check if we support wide screen */
	switch (AST_GEN(ast)) {
	case 1:
		ast->support_wide_screen = false;
		break;
	default:
		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
		if (!(jreg & 0x80))
			ast->support_wide_screen = true;
		else if (jreg & 0x01)
			ast->support_wide_screen = true;
		else {
			ast->support_wide_screen = false;
			if (ast->chip == AST1300)
				ast->support_wide_screen = true;
			if (ast->chip == AST1400)
				ast->support_wide_screen = true;
			if (ast->chip == AST2510)
				ast->support_wide_screen = true;
			if (IS_AST_GEN7(ast))
				ast->support_wide_screen = true;
		}
		break;
	}
}

static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
{
	struct drm_device *dev = &ast->base;
	u8 jreg;

	/* Check 3rd Tx option (digital output afaik) */
	ast->tx_chip_types |= AST_TX_NONE_BIT;

	/*
	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
	 *
	 * Don't make that assumption if we the chip wasn't enabled and
	 * is at power-on reset, otherwise we'll incorrectly "detect" a
	 * SIL164 when there is none.
	 */
	if (!need_post) {
		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
		if (jreg & 0x80)
			ast->tx_chip_types = AST_TX_SIL164_BIT;
	}

	if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
		/*
		 * On AST GEN4+, look the configuration set by the SoC in
		 * the SOC scratch register #1 bits 11:8 (interestingly marked
		 * as "reserved" in the spec)
		 */
		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
		switch (jreg) {
		case 0x04:
			ast->tx_chip_types = AST_TX_SIL164_BIT;
			break;
		case 0x08:
			ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
			if (ast->dp501_fw_addr) {
				/* backup firmware */
				if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
					drmm_kfree(dev, ast->dp501_fw_addr);
					ast->dp501_fw_addr = NULL;
				}
			}
			fallthrough;
		case 0x0c:
			ast->tx_chip_types = AST_TX_DP501_BIT;
		}
	} else if (IS_AST_GEN7(ast)) {
		if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) ==
		    ASTDP_DPMCU_TX) {
			ast->tx_chip_types = AST_TX_ASTDP_BIT;
			ast_dp_launch(&ast->base);
		}
	}

	/* Print stuff for diagnostic purposes */
	if (ast->tx_chip_types & AST_TX_NONE_BIT)
		drm_info(dev, "Using analog VGA\n");
	if (ast->tx_chip_types & AST_TX_SIL164_BIT)
		drm_info(dev, "Using Sil164 TMDS transmitter\n");
	if (ast->tx_chip_types & AST_TX_DP501_BIT)
		drm_info(dev, "Using DP501 DisplayPort transmitter\n");
	if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
		drm_info(dev, "Using ASPEED DisplayPort transmitter\n");
}

static int ast_get_dram_info(struct drm_device *dev)
{
	struct device_node *np = dev->dev->of_node;
	struct ast_device *ast = to_ast_device(dev);
	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
	uint32_t denum, num, div, ref_pll, dsel;

	switch (ast->config_mode) {
	case ast_use_dt:
		/*
		 * If some properties are missing, use reasonable
		 * defaults for GEN5
		 */
		if (of_property_read_u32(np, "aspeed,mcr-configuration",
					 &mcr_cfg))
			mcr_cfg = 0x00000577;
		if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
					 &mcr_scu_mpll))
			mcr_scu_mpll = 0x000050C0;
		if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
					 &mcr_scu_strap))
			mcr_scu_strap = 0;
		break;
	case ast_use_p2a:
		ast_write32(ast, 0xf004, 0x1e6e0000);
		ast_write32(ast, 0xf000, 0x1);
		mcr_cfg = ast_read32(ast, 0x10004);
		mcr_scu_mpll = ast_read32(ast, 0x10120);
		mcr_scu_strap = ast_read32(ast, 0x10170);
		break;
	case ast_use_defaults:
	default:
		ast->dram_bus_width = 16;
		ast->dram_type = AST_DRAM_1Gx16;
		if (IS_AST_GEN6(ast))
			ast->mclk = 800;
		else
			ast->mclk = 396;
		return 0;
	}

	if (mcr_cfg & 0x40)
		ast->dram_bus_width = 16;
	else
		ast->dram_bus_width = 32;

	if (IS_AST_GEN6(ast)) {
		switch (mcr_cfg & 0x03) {
		case 0:
			ast->dram_type = AST_DRAM_1Gx16;
			break;
		default:
		case 1:
			ast->dram_type = AST_DRAM_2Gx16;
			break;
		case 2:
			ast->dram_type = AST_DRAM_4Gx16;
			break;
		case 3:
			ast->dram_type = AST_DRAM_8Gx16;
			break;
		}
	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast)) {
		switch (mcr_cfg & 0x03) {
		case 0:
			ast->dram_type = AST_DRAM_512Mx16;
			break;
		default:
		case 1:
			ast->dram_type = AST_DRAM_1Gx16;
			break;
		case 2:
			ast->dram_type = AST_DRAM_2Gx16;
			break;
		case 3:
			ast->dram_type = AST_DRAM_4Gx16;
			break;
		}
	} else {
		switch (mcr_cfg & 0x0c) {
		case 0:
		case 4:
			ast->dram_type = AST_DRAM_512Mx16;
			break;
		case 8:
			if (mcr_cfg & 0x40)
				ast->dram_type = AST_DRAM_1Gx16;
			else
				ast->dram_type = AST_DRAM_512Mx32;
			break;
		case 0xc:
			ast->dram_type = AST_DRAM_1Gx32;
			break;
		}
	}

	if (mcr_scu_strap & 0x2000)
		ref_pll = 14318;
	else
		ref_pll = 12000;

	denum = mcr_scu_mpll & 0x1f;
	num = (mcr_scu_mpll & 0x3fe0) >> 5;
	dsel = (mcr_scu_mpll & 0xc000) >> 14;
	switch (dsel) {
	case 3:
		div = 0x4;
		break;
	case 2:
	case 1:
		div = 0x2;
		break;
	default:
		div = 0x1;
		break;
	}
	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
	return 0;
}

struct ast_device *ast_device_create(const struct drm_driver *drv,
				     struct pci_dev *pdev,
				     unsigned long flags)
{
	struct drm_device *dev;
	struct ast_device *ast;
	bool need_post = false;
	int ret = 0;

	ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
	if (IS_ERR(ast))
		return ast;
	dev = &ast->base;

	pci_set_drvdata(pdev, dev);

	ast->regs = pcim_iomap(pdev, 1, 0);
	if (!ast->regs)
		return ERR_PTR(-EIO);

	if (pdev->revision >= 0x40) {
		/*
		 * On AST2500 and later models, MMIO is enabled by
		 * default. Adopt it to be compatible with ARM.
		 */
		resource_size_t len = pci_resource_len(pdev, 1);

		if (len < AST_IO_MM_OFFSET)
			return ERR_PTR(-EIO);
		if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
			return ERR_PTR(-EIO);
		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
	} else if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) {
		/*
		 * Map I/O registers if we have a PCI BAR for I/O.
		 */
		resource_size_t len = pci_resource_len(pdev, 2);

		if (len < AST_IO_MM_LENGTH)
			return -EIO;
		ast->ioregs = pcim_iomap(pdev, 2, 0);
		if (!ast->ioregs)
			return ERR_PTR(-EIO);
	} else {
		/*
		 * Anything else is best effort.
		 */
		resource_size_t len = pci_resource_len(pdev, 1);

		if (len < AST_IO_MM_OFFSET)
			return ERR_PTR(-EIO);
		if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
			return ERR_PTR(-EIO);
		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;

		drm_info(dev, "Platform has no I/O space, using MMIO\n");
	}

	if (!ast_is_vga_enabled(dev)) {
		drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
		need_post = true;
	}

	/*
	 * If VGA isn't enabled, we need to enable now or subsequent
	 * access to the scratch registers will fail.
	 */
	if (need_post)
		ast_enable_vga(dev);

	/* Enable extended register access */
	ast_open_key(ast);
	ret = ast_enable_mmio(ast);
	if (ret)
		return ERR_PTR(ret);

	ret = ast_device_config_init(ast);
	if (ret)
		return ERR_PTR(ret);

	ast_detect_widescreen(ast);
	ast_detect_tx_chip(ast, need_post);

	ret = ast_get_dram_info(dev);
	if (ret)
		return ERR_PTR(ret);

	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
		 ast->mclk, ast->dram_type, ast->dram_bus_width);

	if (need_post)
		ast_post_gpu(dev);

	ret = ast_mm_init(ast);
	if (ret)
		return ERR_PTR(ret);

	/* map reserved buffer */
	ast->dp501_fw_buf = NULL;
	if (ast->vram_size < pci_resource_len(pdev, 0)) {
		ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
		if (!ast->dp501_fw_buf)
			drm_info(dev, "failed to map reserved buffer!\n");
	}

	ret = ast_mode_config_init(ast);
	if (ret)
		return ERR_PTR(ret);

	return ast;
}
Commit	Line	Data
312fec14 DA	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the
	6	* "Software"), to deal in the Software without restriction, including
	7	* without limitation the rights to use, copy, modify, merge, publish,
	8	* distribute, sub license, and/or sell copies of the Software, and to
	9	* permit persons to whom the Software is furnished to do so, subject to
	10	* the following conditions:
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	16	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	17	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	18	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* The above copyright notice and this permission notice (including the
	21	* next paragraph) shall be included in all copies or substantial portions
	22	* of the Software.
	23	*
	24	*/
	25	/*
	26	* Authors: Dave Airlie <airlied@redhat.com>
	27	*/
fbbbd160 SR	28
fbbbd160 SR	29	#include <linux/pci.h>
312fec14	30
4961eb60	31	#include <drm/drm_atomic_helper.h>
fbe01716	32	#include <drm/drm_drv.h>
fbbbd160	33	#include <drm/drm_gem.h>
4bc85b82	34	#include <drm/drm_managed.h>
fbbbd160 SR	35
fbbbd160 SR	36	#include "ast_drv.h"
312fec14	37
5b71707d TZ	38	static bool ast_is_vga_enabled(struct drm_device *dev)
	39	{
	40	struct ast_device *ast = to_ast_device(dev);
	41	u8 ch;
	42
ba51b3ed	43	ch = ast_io_read8(ast, AST_IO_VGAER);
5b71707d TZ	44
	45	return !!(ch & 0x01);
	46	}
	47
	48	static void ast_enable_vga(struct drm_device *dev)
	49	{
	50	struct ast_device *ast = to_ast_device(dev);
	51
ba51b3ed	52	ast_io_write8(ast, AST_IO_VGAER, 0x01);
b3945edd	53	ast_io_write8(ast, AST_IO_VGAMR_W, 0x01);
5b71707d TZ	54	}
5b71707d TZ	55
a74ec2bc TZ	56	/*
	57	* Run this function as part of the HW device cleanup; not
	58	* when the DRM device gets released.
	59	*/
	60	static void ast_enable_mmio_release(void *data)
5b71707d	61	{
a74ec2bc TZ	62	struct ast_device *ast = data;
	63
	64	/* enable standard VGA decode */
c79479fa	65	ast_set_index_reg(ast, AST_IO_VGACRI, 0xa1, 0x04);
a74ec2bc TZ	66	}
	67
	68	static int ast_enable_mmio(struct ast_device *ast)
	69	{
	70	struct drm_device *dev = &ast->base;
5b71707d	71
c79479fa	72	ast_set_index_reg(ast, AST_IO_VGACRI, 0xa1, 0x06);
a74ec2bc TZ	73
a74ec2bc TZ	74	return devm_add_action_or_reset(dev->dev, ast_enable_mmio_release, ast);
5b71707d TZ	75	}
	76
	77	static void ast_open_key(struct ast_device *ast)
	78	{
c79479fa	79	ast_set_index_reg(ast, AST_IO_VGACRI, 0x80, 0xA8);
5b71707d TZ	80	}
5b71707d TZ	81
95badecb	82	static int ast_device_config_init(struct ast_device *ast)
71f677a9	83	{
95badecb	84	struct drm_device *dev = &ast->base;
46fb883c	85	struct pci_dev *pdev = to_pci_dev(dev->dev);
95badecb TZ	86	struct device_node *np = dev->dev->of_node;
	87	uint32_t scu_rev = 0xffffffff;
	88	u32 data;
	89	u8 jregd0, jregd1;
	90
	91	/*
	92	* Find configuration mode and read SCU revision
	93	*/
71f677a9	94
71f677a9	95	ast->config_mode = ast_use_defaults;
71f677a9 RC	96
71f677a9 RC	97	/* Check if we have device-tree properties */
95badecb	98	if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) {
71f677a9 RC	99	/* We do, disable P2A access */
71f677a9 RC	100	ast->config_mode = ast_use_dt;
95badecb TZ	101	scu_rev = data;
	102	} else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge
	103	/*
	104	* The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
	105	* is disabled. We force using P2A if VGA only mode bit
	106	* is set D[7]
	107	*/
c79479fa TZ	108	jregd0 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
c79479fa TZ	109	jregd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
95badecb TZ	110	if (!(jregd0 & 0x80) \|\| !(jregd1 & 0x10)) {
	111
	112	/*
	113	* We have a P2A bridge and it is enabled.
	114	*/
	115
	116	/* Patch AST2500/AST2510 */
	117	if ((pdev->revision & 0xf0) == 0x40) {
	118	if (!(jregd0 & AST_VRAM_INIT_STATUS_MASK))
	119	ast_patch_ahb_2500(ast);
	120	}
71f677a9	121
95badecb TZ	122	/* Double check that it's actually working */
	123	data = ast_read32(ast, 0xf004);
	124	if ((data != 0xffffffff) && (data != 0x00)) {
	125	ast->config_mode = ast_use_p2a;
71f677a9	126
95badecb TZ	127	/* Read SCU7c (silicon revision register) */
	128	ast_write32(ast, 0xf004, 0x1e6e0000);
	129	ast_write32(ast, 0xf000, 0x1);
	130	scu_rev = ast_read32(ast, 0x1207c);
	131	}
71f677a9 RC	132	}
	133	}
	134
95badecb TZ	135	switch (ast->config_mode) {
	136	case ast_use_defaults:
	137	drm_info(dev, "Using default configuration\n");
	138	break;
	139	case ast_use_dt:
	140	drm_info(dev, "Using device-tree for configuration\n");
	141	break;
	142	case ast_use_p2a:
	143	drm_info(dev, "Using P2A bridge for configuration\n");
	144	break;
	145	}
312fec14	146
95badecb TZ	147	/*
	148	* Identify chipset
	149	*/
71f677a9	150
46fb883c	151	if (pdev->revision >= 0x50) {
f9bd00e0 KC	152	ast->chip = AST2600;
f9bd00e0 KC	153	drm_info(dev, "AST 2600 detected\n");
46fb883c	154	} else if (pdev->revision >= 0x40) {
52c29330 TZ	155	switch (scu_rev & 0x300) {
	156	case 0x0100:
	157	ast->chip = AST2510;
	158	drm_info(dev, "AST 2510 detected\n");
	159	break;
	160	default:
	161	ast->chip = AST2500;
	162	drm_info(dev, "AST 2500 detected\n");
	163	}
46fb883c	164	} else if (pdev->revision >= 0x30) {
86d86d1b TZ	165	switch (scu_rev & 0x300) {
	166	case 0x0100:
	167	ast->chip = AST1400;
	168	drm_info(dev, "AST 1400 detected\n");
	169	break;
	170	default:
	171	ast->chip = AST2400;
	172	drm_info(dev, "AST 2400 detected\n");
	173	}
46fb883c	174	} else if (pdev->revision >= 0x20) {
6bd576da TZ	175	switch (scu_rev & 0x300) {
	176	case 0x0000:
	177	ast->chip = AST1300;
	178	drm_info(dev, "AST 1300 detected\n");
	179	break;
	180	default:
	181	ast->chip = AST2300;
	182	drm_info(dev, "AST 2300 detected\n");
	183	break;
	184	}
46fb883c	185	} else if (pdev->revision >= 0x10) {
05f13f5b TZ	186	switch (scu_rev & 0x0300) {
	187	case 0x0200:
	188	ast->chip = AST1100;
1a19b4cb	189	drm_info(dev, "AST 1100 detected\n");
05f13f5b TZ	190	break;
	191	case 0x0100:
	192	ast->chip = AST2200;
1a19b4cb	193	drm_info(dev, "AST 2200 detected\n");
05f13f5b TZ	194	break;
	195	case 0x0000:
	196	ast->chip = AST2150;
1a19b4cb	197	drm_info(dev, "AST 2150 detected\n");
05f13f5b TZ	198	break;
	199	default:
	200	ast->chip = AST2100;
1a19b4cb	201	drm_info(dev, "AST 2100 detected\n");
05f13f5b	202	break;
312fec14	203	}
05f13f5b TZ	204	} else {
05f13f5b TZ	205	ast->chip = AST2000;
1a19b4cb	206	drm_info(dev, "AST 2000 detected\n");
312fec14	207	}
f1f62f2c	208
546b959e TZ	209	return 0;
	210	}
	211
	212	static void ast_detect_widescreen(struct ast_device *ast)
	213	{
	214	u8 jreg;
	215
d1b98557	216	/* Check if we support wide screen */
ecf64579 TZ	217	switch (AST_GEN(ast)) {
ecf64579 TZ	218	case 1:
f1f62f2c DA	219	ast->support_wide_screen = false;
	220	break;
	221	default:
c79479fa	222	jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
f1f62f2c DA	223	if (!(jreg & 0x80))
	224	ast->support_wide_screen = true;
	225	else if (jreg & 0x01)
	226	ast->support_wide_screen = true;
	227	else {
	228	ast->support_wide_screen = false;
6bd576da	229	if (ast->chip == AST1300)
71f677a9	230	ast->support_wide_screen = true;
86d86d1b	231	if (ast->chip == AST1400)
71f677a9	232	ast->support_wide_screen = true;
52c29330	233	if (ast->chip == AST2510)
9f93c8b3	234	ast->support_wide_screen = true;
ecf64579	235	if (IS_AST_GEN7(ast))
59a39fcc	236	ast->support_wide_screen = true;
f1f62f2c DA	237	}
	238	break;
	239	}
546b959e TZ	240	}
	241
	242	static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
	243	{
	244	struct drm_device *dev = &ast->base;
	245	u8 jreg;
f1f62f2c	246
d1b98557	247	/* Check 3rd Tx option (digital output afaik) */
7f35680a	248	ast->tx_chip_types \|= AST_TX_NONE_BIT;
d1b98557 BH	249
	250	/*
	251	* VGACRA3 Enhanced Color Mode Register, check if DVO is already
	252	* enabled, in that case, assume we have a SIL164 TMDS transmitter
42fb1427 BH	253	*
	254	* Don't make that assumption if we the chip wasn't enabled and
	255	* is at power-on reset, otherwise we'll incorrectly "detect" a
	256	* SIL164 when there is none.
d1b98557	257	*/
3bfe25b5	258	if (!need_post) {
c79479fa	259	jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
42fb1427	260	if (jreg & 0x80)
7f35680a	261	ast->tx_chip_types = AST_TX_SIL164_BIT;
42fb1427	262	}
d1b98557	263
ecf64579	264	if (IS_AST_GEN4(ast) \|\| IS_AST_GEN5(ast) \|\| IS_AST_GEN6(ast)) {
d1b98557	265	/*
ecf64579	266	* On AST GEN4+, look the configuration set by the SoC in
d1b98557	267	* the SOC scratch register #1 bits 11:8 (interestingly marked
42fb1427	268	* as "reserved" in the spec)
d1b98557	269	*/
c79479fa	270	jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
83c6620b DA	271	switch (jreg) {
83c6620b DA	272	case 0x04:
7f35680a	273	ast->tx_chip_types = AST_TX_SIL164_BIT;
83c6620b DA	274	break;
83c6620b DA	275	case 0x08:
4bc85b82	276	ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
83c6620b DA	277	if (ast->dp501_fw_addr) {
	278	/* backup firmware */
	279	if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
4bc85b82	280	drmm_kfree(dev, ast->dp501_fw_addr);
83c6620b DA	281	ast->dp501_fw_addr = NULL;
	282	}
	283	}
df561f66	284	fallthrough;
83c6620b	285	case 0x0c:
7f35680a	286	ast->tx_chip_types = AST_TX_DP501_BIT;
83c6620b	287	}
ecf64579	288	} else if (IS_AST_GEN7(ast)) {
c79479fa	289	if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) ==
bed61c8f JH	290	ASTDP_DPMCU_TX) {
	291	ast->tx_chip_types = AST_TX_ASTDP_BIT;
	292	ast_dp_launch(&ast->base);
	293	}
	294	}
83c6620b	295
d1b98557	296	/* Print stuff for diagnostic purposes */
7f35680a TZ	297	if (ast->tx_chip_types & AST_TX_NONE_BIT)
	298	drm_info(dev, "Using analog VGA\n");
	299	if (ast->tx_chip_types & AST_TX_SIL164_BIT)
1a19b4cb	300	drm_info(dev, "Using Sil164 TMDS transmitter\n");
7f35680a	301	if (ast->tx_chip_types & AST_TX_DP501_BIT)
1a19b4cb	302	drm_info(dev, "Using DP501 DisplayPort transmitter\n");
bed61c8f JH	303	if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
bed61c8f JH	304	drm_info(dev, "Using ASPEED DisplayPort transmitter\n");
312fec14 DA	305	}
	306
	307	static int ast_get_dram_info(struct drm_device *dev)
	308	{
46fb883c	309	struct device_node *np = dev->dev->of_node;
5abaa683	310	struct ast_device *ast = to_ast_device(dev);
71f677a9 RC	311	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
71f677a9 RC	312	uint32_t denum, num, div, ref_pll, dsel;
312fec14	313
71f677a9 RC	314	switch (ast->config_mode) {
	315	case ast_use_dt:
	316	/*
	317	* If some properties are missing, use reasonable
ecf64579	318	* defaults for GEN5
71f677a9 RC	319	*/
	320	if (of_property_read_u32(np, "aspeed,mcr-configuration",
	321	&mcr_cfg))
	322	mcr_cfg = 0x00000577;
	323	if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
	324	&mcr_scu_mpll))
	325	mcr_scu_mpll = 0x000050C0;
	326	if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
	327	&mcr_scu_strap))
	328	mcr_scu_strap = 0;
	329	break;
	330	case ast_use_p2a:
	331	ast_write32(ast, 0xf004, 0x1e6e0000);
	332	ast_write32(ast, 0xf000, 0x1);
	333	mcr_cfg = ast_read32(ast, 0x10004);
	334	mcr_scu_mpll = ast_read32(ast, 0x10120);
	335	mcr_scu_strap = ast_read32(ast, 0x10170);
	336	break;
	337	case ast_use_defaults:
	338	default:
6c971c09 C	339	ast->dram_bus_width = 16;
6c971c09 C	340	ast->dram_type = AST_DRAM_1Gx16;
ecf64579	341	if (IS_AST_GEN6(ast))
9f93c8b3 C	342	ast->mclk = 800;
	343	else
	344	ast->mclk = 396;
71f677a9	345	return 0;
6c971c09	346	}
312fec14	347
71f677a9 RC	348	if (mcr_cfg & 0x40)
	349	ast->dram_bus_width = 16;
	350	else
	351	ast->dram_bus_width = 32;
312fec14	352
ecf64579	353	if (IS_AST_GEN6(ast)) {
9f93c8b3 C	354	switch (mcr_cfg & 0x03) {
	355	case 0:
	356	ast->dram_type = AST_DRAM_1Gx16;
	357	break;
	358	default:
	359	case 1:
	360	ast->dram_type = AST_DRAM_2Gx16;
	361	break;
	362	case 2:
	363	ast->dram_type = AST_DRAM_4Gx16;
	364	break;
	365	case 3:
	366	ast->dram_type = AST_DRAM_8Gx16;
	367	break;
	368	}
ecf64579	369	} else if (IS_AST_GEN4(ast) \|\| IS_AST_GEN5(ast)) {
71f677a9 RC	370	switch (mcr_cfg & 0x03) {
	371	case 0:
	372	ast->dram_type = AST_DRAM_512Mx16;
312fec14	373	break;
71f677a9	374	default:
6c971c09	375	case 1:
71f677a9	376	ast->dram_type = AST_DRAM_1Gx16;
312fec14	377	break;
71f677a9 RC	378	case 2:
	379	ast->dram_type = AST_DRAM_2Gx16;
	380	break;
	381	case 3:
	382	ast->dram_type = AST_DRAM_4Gx16;
	383	break;
	384	}
	385	} else {
	386	switch (mcr_cfg & 0x0c) {
	387	case 0:
	388	case 4:
	389	ast->dram_type = AST_DRAM_512Mx16;
	390	break;
	391	case 8:
	392	if (mcr_cfg & 0x40)
	393	ast->dram_type = AST_DRAM_1Gx16;
	394	else
	395	ast->dram_type = AST_DRAM_512Mx32;
	396	break;
	397	case 0xc:
	398	ast->dram_type = AST_DRAM_1Gx32;
312fec14 DA	399	break;
	400	}
	401	}
71f677a9 RC	402
	403	if (mcr_scu_strap & 0x2000)
	404	ref_pll = 14318;
	405	else
	406	ref_pll = 12000;
	407
	408	denum = mcr_scu_mpll & 0x1f;
	409	num = (mcr_scu_mpll & 0x3fe0) >> 5;
	410	dsel = (mcr_scu_mpll & 0xc000) >> 14;
	411	switch (dsel) {
	412	case 3:
	413	div = 0x4;
	414	break;
	415	case 2:
	416	case 1:
	417	div = 0x2;
	418	break;
	419	default:
	420	div = 0x1;
	421	break;
	422	}
6475a7cc	423	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
312fec14 DA	424	return 0;
	425	}
	426
37b42cf9 TZ	427	struct ast_device ast_device_create(const struct drm_driver drv,
	428	struct pci_dev *pdev,
	429	unsigned long flags)
312fec14	430	{
fbe01716	431	struct drm_device *dev;
37b42cf9	432	struct ast_device *ast;
3bfe25b5	433	bool need_post = false;
312fec14 DA	434	int ret = 0;
312fec14 DA	435
37b42cf9	436	ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
e0f5a738 TZ	437	if (IS_ERR(ast))
	438	return ast;
	439	dev = &ast->base;
fbe01716	440
fbe01716 TZ	441	pci_set_drvdata(pdev, dev);
fbe01716 TZ	442
9ea172a9	443	ast->regs = pcim_iomap(pdev, 1, 0);
e0f5a738 TZ	444	if (!ast->regs)
e0f5a738 TZ	445	return ERR_PTR(-EIO);
0dd68309	446
4327a613	447	if (pdev->revision >= 0x40) {
0ccaa3dd TZ	448	/*
	449	* On AST2500 and later models, MMIO is enabled by
	450	* default. Adopt it to be compatible with ARM.
	451	*/
	452	resource_size_t len = pci_resource_len(pdev, 1);
	453
	454	if (len < AST_IO_MM_OFFSET)
	455	return ERR_PTR(-EIO);
	456	if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
	457	return ERR_PTR(-EIO);
4327a613	458	ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
0ccaa3dd TZ	459	} else if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) {
	460	/*
	461	* Map I/O registers if we have a PCI BAR for I/O.
	462	*/
	463	resource_size_t len = pci_resource_len(pdev, 2);
0dd68309	464
0ccaa3dd TZ	465	if (len < AST_IO_MM_LENGTH)
0ccaa3dd TZ	466	return -EIO;
9ea172a9	467	ast->ioregs = pcim_iomap(pdev, 2, 0);
e0f5a738 TZ	468	if (!ast->ioregs)
e0f5a738 TZ	469	return ERR_PTR(-EIO);
0ccaa3dd TZ	470	} else {
	471	/*
	472	* Anything else is best effort.
	473	*/
	474	resource_size_t len = pci_resource_len(pdev, 1);
	475
	476	if (len < AST_IO_MM_OFFSET)
	477	return ERR_PTR(-EIO);
	478	if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
	479	return ERR_PTR(-EIO);
	480	ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
	481
	482	drm_info(dev, "Platform has no I/O space, using MMIO\n");
312fec14 DA	483	}
312fec14 DA	484
3bfe25b5 TZ	485	if (!ast_is_vga_enabled(dev)) {
	486	drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
	487	need_post = true;
	488	}
	489
	490	/*
	491	* If VGA isn't enabled, we need to enable now or subsequent
	492	* access to the scratch registers will fail.
	493	*/
	494	if (need_post)
	495	ast_enable_vga(dev);
	496
	497	/* Enable extended register access */
	498	ast_open_key(ast);
a74ec2bc TZ	499	ret = ast_enable_mmio(ast);
	500	if (ret)
	501	return ERR_PTR(ret);
3bfe25b5	502
95badecb TZ	503	ret = ast_device_config_init(ast);
	504	if (ret)
	505	return ERR_PTR(ret);
3bfe25b5	506
546b959e TZ	507	ast_detect_widescreen(ast);
546b959e TZ	508	ast_detect_tx_chip(ast, need_post);
312fec14	509
05f13f5b TZ	510	ret = ast_get_dram_info(dev);
05f13f5b TZ	511	if (ret)
e0f5a738 TZ	512	return ERR_PTR(ret);
e0f5a738 TZ	513
0149e780 TZ	514	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
0149e780 TZ	515	ast->mclk, ast->dram_type, ast->dram_bus_width);
312fec14	516
244d0128 TZ	517	if (need_post)
	518	ast_post_gpu(dev);
	519
312fec14 DA	520	ret = ast_mm_init(ast);
312fec14 DA	521	if (ret)
e0f5a738	522	return ERR_PTR(ret);
312fec14	523
ba4e0339 KC	524	/* map reserved buffer */
ba4e0339 KC	525	ast->dp501_fw_buf = NULL;
f2fa5a99 TZ	526	if (ast->vram_size < pci_resource_len(pdev, 0)) {
f2fa5a99 TZ	527	ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
ba4e0339 KC	528	if (!ast->dp501_fw_buf)
	529	drm_info(dev, "failed to map reserved buffer!\n");
	530	}
	531
e6949ff3	532	ret = ast_mode_config_init(ast);
312fec14	533	if (ret)
e0f5a738	534	return ERR_PTR(ret);
312fec14	535
cff0adca	536	return ast;
312fec14	537	}