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drm/ast: Add cursor plane
[linux-2.6-block.git] / drivers / gpu / drm / ast / ast_main.c
CommitLineData
312fec14
DA		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
fbbbd160
SR		 28
29#include <linux/pci.h>
312fec14 30
760285e7 31#include <drm/drm_crtc_helper.h>
5ed7191d 32#include <drm/drm_fb_helper.h>
fbbbd160 33#include <drm/drm_gem.h>
5ed7191d 34#include <drm/drm_gem_framebuffer_helper.h>
fbbbd160 35#include <drm/drm_gem_vram_helper.h>
fbbbd160
SR		 36
37#include "ast_drv.h"
312fec14 38
312fec14
DA		 39void ast_set_index_reg_mask(struct ast_private *ast,
40 uint32_t base, uint8_t index,
41 uint8_t mask, uint8_t val)
42{
43 u8 tmp;
44 ast_io_write8(ast, base, index);
45 tmp = (ast_io_read8(ast, base + 1) & mask) | val;
46 ast_set_index_reg(ast, base, index, tmp);
47}
48
49uint8_t ast_get_index_reg(struct ast_private *ast,
50 uint32_t base, uint8_t index)
51{
52 uint8_t ret;
53 ast_io_write8(ast, base, index);
54 ret = ast_io_read8(ast, base + 1);
55 return ret;
56}
57
58uint8_t ast_get_index_reg_mask(struct ast_private *ast,
59 uint32_t base, uint8_t index, uint8_t mask)
60{
61 uint8_t ret;
62 ast_io_write8(ast, base, index);
63 ret = ast_io_read8(ast, base + 1) & mask;
64 return ret;
65}
66
71f677a9
RC		 67static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
68{
69 struct device_node *np = dev->pdev->dev.of_node;
70 struct ast_private *ast = dev->dev_private;
71 uint32_t data, jregd0, jregd1;
72
73 /* Defaults */
74 ast->config_mode = ast_use_defaults;
75 *scu_rev = 0xffffffff;
76
77 /* Check if we have device-tree properties */
78 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
79 scu_rev)) {
80 /* We do, disable P2A access */
81 ast->config_mode = ast_use_dt;
82 DRM_INFO("Using device-tree for configuration\n");
83 return;
84 }
85
86 /* Not all families have a P2A bridge */
87 if (dev->pdev->device != PCI_CHIP_AST2000)
88 return;
89
90 /*
91 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
92 * is disabled. We force using P2A if VGA only mode bit
93 * is set D[7]
94 */
95 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
96 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
97 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
98 /* Double check it's actually working */
99 data = ast_read32(ast, 0xf004);
100 if (data != 0xFFFFFFFF) {
101 /* P2A works, grab silicon revision */
102 ast->config_mode = ast_use_p2a;
103
104 DRM_INFO("Using P2A bridge for configuration\n");
105
106 /* Read SCU7c (silicon revision register) */
107 ast_write32(ast, 0xf004, 0x1e6e0000);
108 ast_write32(ast, 0xf000, 0x1);
109 *scu_rev = ast_read32(ast, 0x1207c);
110 return;
111 }
112 }
113
114 /* We have a P2A bridge but it's disabled */
115 DRM_INFO("P2A bridge disabled, using default configuration\n");
116}
312fec14 117
d1b98557 118static int ast_detect_chip(struct drm_device *dev, bool *need_post)
312fec14
DA		 119{
120 struct ast_private *ast = dev->dev_private;
71f677a9
RC		 121 uint32_t jreg, scu_rev;
122
123 /*
124 * If VGA isn't enabled, we need to enable now or subsequent
125 * access to the scratch registers will fail. We also inform
126 * our caller that it needs to POST the chip
127 * (Assumption: VGA not enabled -> need to POST)
128 */
129 if (!ast_is_vga_enabled(dev)) {
130 ast_enable_vga(dev);
131 DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
132 *need_post = true;
133 } else
134 *need_post = false;
135
136
137 /* Enable extended register access */
8f372e25 138 ast_open_key(ast);
05b43971 139 ast_enable_mmio(dev);
312fec14 140
71f677a9
RC		 141 /* Find out whether P2A works or whether to use device-tree */
142 ast_detect_config_mode(dev, &scu_rev);
143
144 /* Identify chipset */
312fec14
DA		 145 if (dev->pdev->device == PCI_CHIP_AST1180) {
146 ast->chip = AST1100;
147 DRM_INFO("AST 1180 detected\n");
148 } else {
9f93c8b3
C		 149 if (dev->pdev->revision >= 0x40) {
150 ast->chip = AST2500;
151 DRM_INFO("AST 2500 detected\n");
152 } else if (dev->pdev->revision >= 0x30) {
1453bf4c
DA		 153 ast->chip = AST2400;
154 DRM_INFO("AST 2400 detected\n");
155 } else if (dev->pdev->revision >= 0x20) {
312fec14
DA		 156 ast->chip = AST2300;
157 DRM_INFO("AST 2300 detected\n");
158 } else if (dev->pdev->revision >= 0x10) {
71f677a9 159 switch (scu_rev & 0x0300) {
312fec14
DA		 160 case 0x0200:
161 ast->chip = AST1100;
162 DRM_INFO("AST 1100 detected\n");
163 break;
164 case 0x0100:
165 ast->chip = AST2200;
166 DRM_INFO("AST 2200 detected\n");
167 break;
168 case 0x0000:
169 ast->chip = AST2150;
170 DRM_INFO("AST 2150 detected\n");
171 break;
172 default:
173 ast->chip = AST2100;
174 DRM_INFO("AST 2100 detected\n");
175 break;
176 }
177 ast->vga2_clone = false;
178 } else {
83502a5d 179 ast->chip = AST2000;
312fec14
DA		 180 DRM_INFO("AST 2000 detected\n");
181 }
182 }
f1f62f2c 183
d1b98557 184 /* Check if we support wide screen */
f1f62f2c
DA		 185 switch (ast->chip) {
186 case AST1180:
187 ast->support_wide_screen = true;
188 break;
189 case AST2000:
190 ast->support_wide_screen = false;
191 break;
192 default:
193 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
194 if (!(jreg & 0x80))
195 ast->support_wide_screen = true;
196 else if (jreg & 0x01)
197 ast->support_wide_screen = true;
198 else {
199 ast->support_wide_screen = false;
71f677a9
RC		 200 if (ast->chip == AST2300 &&
201 (scu_rev & 0x300) == 0x0) /* ast1300 */
202 ast->support_wide_screen = true;
203 if (ast->chip == AST2400 &&
204 (scu_rev & 0x300) == 0x100) /* ast1400 */
205 ast->support_wide_screen = true;
9f93c8b3
C		 206 if (ast->chip == AST2500 &&
207 scu_rev == 0x100) /* ast2510 */
208 ast->support_wide_screen = true;
f1f62f2c
DA		 209 }
210 break;
211 }
212
d1b98557 213 /* Check 3rd Tx option (digital output afaik) */
83c6620b 214 ast->tx_chip_type = AST_TX_NONE;
d1b98557
BH		 215
216 /*
217 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
218 * enabled, in that case, assume we have a SIL164 TMDS transmitter
42fb1427
BH		 219 *
220 * Don't make that assumption if we the chip wasn't enabled and
221 * is at power-on reset, otherwise we'll incorrectly "detect" a
222 * SIL164 when there is none.
d1b98557 223 */
42fb1427
BH		 224 if (!*need_post) {
225 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
226 if (jreg & 0x80)
227 ast->tx_chip_type = AST_TX_SIL164;
228 }
d1b98557 229
83c6620b 230 if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
d1b98557
BH		 231 /*
232 * On AST2300 and 2400, look the configuration set by the SoC in
233 * the SOC scratch register #1 bits 11:8 (interestingly marked
42fb1427 234 * as "reserved" in the spec)
d1b98557 235 */
83c6620b
DA		 236 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
237 switch (jreg) {
238 case 0x04:
239 ast->tx_chip_type = AST_TX_SIL164;
240 break;
241 case 0x08:
242 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
243 if (ast->dp501_fw_addr) {
244 /* backup firmware */
245 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
246 kfree(ast->dp501_fw_addr);
247 ast->dp501_fw_addr = NULL;
248 }
249 }
250 /* fallthrough */
251 case 0x0c:
252 ast->tx_chip_type = AST_TX_DP501;
253 }
254 }
255
d1b98557
BH		 256 /* Print stuff for diagnostic purposes */
257 switch(ast->tx_chip_type) {
258 case AST_TX_SIL164:
259 DRM_INFO("Using Sil164 TMDS transmitter\n");
260 break;
261 case AST_TX_DP501:
262 DRM_INFO("Using DP501 DisplayPort transmitter\n");
263 break;
264 default:
265 DRM_INFO("Analog VGA only\n");
266 }
312fec14
DA		 267 return 0;
268}
269
270static int ast_get_dram_info(struct drm_device *dev)
271{
71f677a9 272 struct device_node *np = dev->pdev->dev.of_node;
312fec14 273 struct ast_private *ast = dev->dev_private;
71f677a9
RC		 274 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
275 uint32_t denum, num, div, ref_pll, dsel;
312fec14 276
71f677a9
RC		 277 switch (ast->config_mode) {
278 case ast_use_dt:
279 /*
280 * If some properties are missing, use reasonable
281 * defaults for AST2400
282 */
283 if (of_property_read_u32(np, "aspeed,mcr-configuration",
284 &mcr_cfg))
285 mcr_cfg = 0x00000577;
286 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
287 &mcr_scu_mpll))
288 mcr_scu_mpll = 0x000050C0;
289 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
290 &mcr_scu_strap))
291 mcr_scu_strap = 0;
292 break;
293 case ast_use_p2a:
294 ast_write32(ast, 0xf004, 0x1e6e0000);
295 ast_write32(ast, 0xf000, 0x1);
296 mcr_cfg = ast_read32(ast, 0x10004);
297 mcr_scu_mpll = ast_read32(ast, 0x10120);
298 mcr_scu_strap = ast_read32(ast, 0x10170);
299 break;
300 case ast_use_defaults:
301 default:
6c971c09
C		 302 ast->dram_bus_width = 16;
303 ast->dram_type = AST_DRAM_1Gx16;
9f93c8b3
C		 304 if (ast->chip == AST2500)
305 ast->mclk = 800;
306 else
307 ast->mclk = 396;
71f677a9 308 return 0;
6c971c09 309 }
312fec14 310
71f677a9
RC		 311 if (mcr_cfg & 0x40)
312 ast->dram_bus_width = 16;
313 else
314 ast->dram_bus_width = 32;
312fec14 315
9f93c8b3
C		 316 if (ast->chip == AST2500) {
317 switch (mcr_cfg & 0x03) {
318 case 0:
319 ast->dram_type = AST_DRAM_1Gx16;
320 break;
321 default:
322 case 1:
323 ast->dram_type = AST_DRAM_2Gx16;
324 break;
325 case 2:
326 ast->dram_type = AST_DRAM_4Gx16;
327 break;
328 case 3:
329 ast->dram_type = AST_DRAM_8Gx16;
330 break;
331 }
332 } else if (ast->chip == AST2300 || ast->chip == AST2400) {
71f677a9
RC		 333 switch (mcr_cfg & 0x03) {
334 case 0:
335 ast->dram_type = AST_DRAM_512Mx16;
312fec14 336 break;
71f677a9 337 default:
6c971c09 338 case 1:
71f677a9 339 ast->dram_type = AST_DRAM_1Gx16;
312fec14 340 break;
71f677a9
RC		 341 case 2:
342 ast->dram_type = AST_DRAM_2Gx16;
343 break;
344 case 3:
345 ast->dram_type = AST_DRAM_4Gx16;
346 break;
347 }
348 } else {
349 switch (mcr_cfg & 0x0c) {
350 case 0:
351 case 4:
352 ast->dram_type = AST_DRAM_512Mx16;
353 break;
354 case 8:
355 if (mcr_cfg & 0x40)
356 ast->dram_type = AST_DRAM_1Gx16;
357 else
358 ast->dram_type = AST_DRAM_512Mx32;
359 break;
360 case 0xc:
361 ast->dram_type = AST_DRAM_1Gx32;
312fec14
DA		 362 break;
363 }
364 }
71f677a9
RC		 365
366 if (mcr_scu_strap & 0x2000)
367 ref_pll = 14318;
368 else
369 ref_pll = 12000;
370
371 denum = mcr_scu_mpll & 0x1f;
372 num = (mcr_scu_mpll & 0x3fe0) >> 5;
373 dsel = (mcr_scu_mpll & 0xc000) >> 14;
374 switch (dsel) {
375 case 3:
376 div = 0x4;
377 break;
378 case 2:
379 case 1:
380 div = 0x2;
381 break;
382 default:
383 div = 0x1;
384 break;
385 }
6475a7cc 386 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
312fec14
DA		 387 return 0;
388}
389
9253f830
TZ		 390enum drm_mode_status ast_mode_config_mode_valid(struct drm_device *dev,
391 const struct drm_display_mode *mode)
392{
393 static const unsigned long max_bpp = 4; /* DRM_FORMAT_XRGBA8888 */
394
395 struct ast_private *ast = dev->dev_private;
396 unsigned long fbsize, fbpages, max_fbpages;
397
398 /* To support double buffering, a framebuffer may not
399 * consume more than half of the available VRAM.
400 */
401 max_fbpages = (ast->vram_size / 2) >> PAGE_SHIFT;
402
403 fbsize = mode->hdisplay * mode->vdisplay * max_bpp;
404 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE);
405
406 if (fbpages > max_fbpages)
407 return MODE_MEM;
408
409 return MODE_OK;
410}
411
312fec14 412static const struct drm_mode_config_funcs ast_mode_funcs = {
9253f830
TZ		 413 .fb_create = drm_gem_fb_create,
414 .mode_valid = ast_mode_config_mode_valid,
312fec14
DA		 415};
416
417static u32 ast_get_vram_info(struct drm_device *dev)
418{
419 struct ast_private *ast = dev->dev_private;
420 u8 jreg;
83c6620b 421 u32 vram_size;
312fec14
DA		 422 ast_open_key(ast);
423
83c6620b 424 vram_size = AST_VIDMEM_DEFAULT_SIZE;
312fec14
DA		 425 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
426 switch (jreg & 3) {
83c6620b
DA		 427 case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
428 case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
429 case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
430 case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
312fec14 431 }
83c6620b
DA		 432
433 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
434 switch (jreg & 0x03) {
435 case 1:
436 vram_size -= 0x100000;
437 break;
438 case 2:
439 vram_size -= 0x200000;
440 break;
441 case 3:
442 vram_size -= 0x400000;
443 break;
444 }
445
446 return vram_size;
312fec14
DA		 447}
448
449int ast_driver_load(struct drm_device *dev, unsigned long flags)
450{
451 struct ast_private *ast;
d1b98557 452 bool need_post;
312fec14
DA		 453 int ret = 0;
454
455 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
456 if (!ast)
457 return -ENOMEM;
458
459 dev->dev_private = ast;
460 ast->dev = dev;
461
462 ast->regs = pci_iomap(dev->pdev, 1, 0);
463 if (!ast->regs) {
464 ret = -EIO;
465 goto out_free;
466 }
0dd68309
BH		 467
468 /*
469 * If we don't have IO space at all, use MMIO now and
470 * assume the chip has MMIO enabled by default (rev 0x20
471 * and higher).
472 */
473 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
474 DRM_INFO("platform has no IO space, trying MMIO\n");
475 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
476 }
477
478 /* "map" IO regs if the above hasn't done so already */
312fec14 479 if (!ast->ioregs) {
0dd68309
BH		 480 ast->ioregs = pci_iomap(dev->pdev, 2, 0);
481 if (!ast->ioregs) {
482 ret = -EIO;
483 goto out_free;
484 }
312fec14
DA		 485 }
486
d1b98557 487 ast_detect_chip(dev, &need_post);
312fec14 488
bad09da6
C		 489 if (need_post)
490 ast_post_gpu(dev);
491
312fec14 492 if (ast->chip != AST1180) {
298360af
RC		 493 ret = ast_get_dram_info(dev);
494 if (ret)
495 goto out_free;
312fec14 496 ast->vram_size = ast_get_vram_info(dev);
6475a7cc
BH		 497 DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
498 ast->mclk, ast->dram_type,
499 ast->dram_bus_width, ast->vram_size);
312fec14
DA		 500 }
501
502 ret = ast_mm_init(ast);
503 if (ret)
504 goto out_free;
505
506 drm_mode_config_init(dev);
507
508 dev->mode_config.funcs = (void *)&ast_mode_funcs;
509 dev->mode_config.min_width = 0;
510 dev->mode_config.min_height = 0;
511 dev->mode_config.preferred_depth = 24;
512 dev->mode_config.prefer_shadow = 1;
28fb4cb7 513 dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0);
312fec14
DA		 514
515 if (ast->chip == AST2100 ||
516 ast->chip == AST2200 ||
517 ast->chip == AST2300 ||
1453bf4c 518 ast->chip == AST2400 ||
9f93c8b3 519 ast->chip == AST2500 ||
312fec14
DA		 520 ast->chip == AST1180) {
521 dev->mode_config.max_width = 1920;
522 dev->mode_config.max_height = 2048;
523 } else {
524 dev->mode_config.max_width = 1600;
525 dev->mode_config.max_height = 1200;
526 }
527
528 ret = ast_mode_init(dev);
529 if (ret)
530 goto out_free;
531
8a99de3d 532 ret = drm_fbdev_generic_setup(dev, 32);
312fec14
DA		 533 if (ret)
534 goto out_free;
535
536 return 0;
537out_free:
538 kfree(ast);
539 dev->dev_private = NULL;
540 return ret;
541}
542
11b3c20b 543void ast_driver_unload(struct drm_device *dev)
312fec14
DA		 544{
545 struct ast_private *ast = dev->dev_private;
546
05b43971
C		 547 /* enable standard VGA decode */
548 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
549
12f8030e 550 ast_release_firmware(dev);
83c6620b 551 kfree(ast->dp501_fw_addr);
312fec14 552 ast_mode_fini(dev);
312fec14
DA		 553 drm_mode_config_cleanup(dev);
554
555 ast_mm_fini(ast);
dc25ab06
SB		 556 if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET)
557 pci_iounmap(dev->pdev, ast->ioregs);
312fec14
DA		 558 pci_iounmap(dev->pdev, ast->regs);
559 kfree(ast);
312fec14 560}
Linux 6.x block layer and io_uring tree(s)