[linux-2.6-block.git] / drivers / gpu / drm / ast / ast_drv.h

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors: Dave Airlie <airlied@redhat.com>
 */
#ifndef __AST_DRV_H__
#define __AST_DRV_H__

#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/io.h>
#include <linux/types.h>

#include <drm/drm_connector.h>
#include <drm/drm_crtc.h>
#include <drm/drm_encoder.h>
#include <drm/drm_mode.h>
#include <drm/drm_framebuffer.h>

#define DRIVER_AUTHOR		"Dave Airlie"

#define DRIVER_NAME		"ast"
#define DRIVER_DESC		"AST"
#define DRIVER_DATE		"20120228"

#define DRIVER_MAJOR		0
#define DRIVER_MINOR		1
#define DRIVER_PATCHLEVEL	0

#define PCI_CHIP_AST2000 0x2000
#define PCI_CHIP_AST2100 0x2010

#define __AST_CHIP(__gen, __index)	((__gen) << 16 | (__index))

enum ast_chip {
	/* 1st gen */
	AST1000 = __AST_CHIP(1, 0), // unused
	AST2000 = __AST_CHIP(1, 1),
	/* 2nd gen */
	AST1100 = __AST_CHIP(2, 0),
	AST2100 = __AST_CHIP(2, 1),
	AST2050 = __AST_CHIP(2, 2), // unused
	/* 3rd gen */
	AST2200 = __AST_CHIP(3, 0),
	AST2150 = __AST_CHIP(3, 1),
	/* 4th gen */
	AST2300 = __AST_CHIP(4, 0),
	AST1300 = __AST_CHIP(4, 1),
	AST1050 = __AST_CHIP(4, 2), // unused
	/* 5th gen */
	AST2400 = __AST_CHIP(5, 0),
	AST1400 = __AST_CHIP(5, 1),
	AST1250 = __AST_CHIP(5, 2), // unused
	/* 6th gen */
	AST2500 = __AST_CHIP(6, 0),
	AST2510 = __AST_CHIP(6, 1), // unused
	AST2520 = __AST_CHIP(6, 2), // unused
	/* 7th gen */
	AST2600 = __AST_CHIP(7, 0),
	AST2620 = __AST_CHIP(7, 1), // unused
};

#define __AST_CHIP_GEN(__chip)	(((unsigned long)(__chip)) >> 16)

enum ast_tx_chip {
	AST_TX_NONE,
	AST_TX_SIL164,
	AST_TX_DP501,
	AST_TX_ASTDP,
};

#define AST_TX_NONE_BIT		BIT(AST_TX_NONE)
#define AST_TX_SIL164_BIT	BIT(AST_TX_SIL164)
#define AST_TX_DP501_BIT	BIT(AST_TX_DP501)
#define AST_TX_ASTDP_BIT	BIT(AST_TX_ASTDP)

#define AST_DRAM_512Mx16 0
#define AST_DRAM_1Gx16   1
#define AST_DRAM_512Mx32 2
#define AST_DRAM_1Gx32   3
#define AST_DRAM_2Gx16   6
#define AST_DRAM_4Gx16   7
#define AST_DRAM_8Gx16   8

/*
 * Hardware cursor
 */

#define AST_MAX_HWC_WIDTH	64
#define AST_MAX_HWC_HEIGHT	64

#define AST_HWC_SIZE		(AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
#define AST_HWC_SIGNATURE_SIZE	32

/* define for signature structure */
#define AST_HWC_SIGNATURE_CHECKSUM	0x00
#define AST_HWC_SIGNATURE_SizeX		0x04
#define AST_HWC_SIGNATURE_SizeY		0x08
#define AST_HWC_SIGNATURE_X		0x0C
#define AST_HWC_SIGNATURE_Y		0x10
#define AST_HWC_SIGNATURE_HOTSPOTX	0x14
#define AST_HWC_SIGNATURE_HOTSPOTY	0x18

/*
 * Planes
 */

struct ast_plane {
	struct drm_plane base;

	void __iomem *vaddr;
	u64 offset;
	unsigned long size;
};

static inline struct ast_plane *to_ast_plane(struct drm_plane *plane)
{
	return container_of(plane, struct ast_plane, base);
}

/*
 * Connector with i2c channel
 */

struct ast_i2c_chan {
	struct i2c_adapter adapter;
	struct drm_device *dev;
	struct i2c_algo_bit_data bit;
};

struct ast_vga_connector {
	struct drm_connector base;
	struct ast_i2c_chan *i2c;
};

static inline struct ast_vga_connector *
to_ast_vga_connector(struct drm_connector *connector)
{
	return container_of(connector, struct ast_vga_connector, base);
}

struct ast_sil164_connector {
	struct drm_connector base;
	struct ast_i2c_chan *i2c;
};

static inline struct ast_sil164_connector *
to_ast_sil164_connector(struct drm_connector *connector)
{
	return container_of(connector, struct ast_sil164_connector, base);
}

/*
 * Device
 */

struct ast_device {
	struct drm_device base;

	struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */
	void __iomem *regs;
	void __iomem *ioregs;
	void __iomem *dp501_fw_buf;

	enum ast_chip chip;
	uint32_t dram_bus_width;
	uint32_t dram_type;
	uint32_t mclk;

	void __iomem	*vram;
	unsigned long	vram_base;
	unsigned long	vram_size;
	unsigned long	vram_fb_available;

	struct ast_plane primary_plane;
	struct ast_plane cursor_plane;
	struct drm_crtc crtc;
	struct {
		struct {
			struct drm_encoder encoder;
			struct ast_vga_connector vga_connector;
		} vga;
		struct {
			struct drm_encoder encoder;
			struct ast_sil164_connector sil164_connector;
		} sil164;
		struct {
			struct drm_encoder encoder;
			struct drm_connector connector;
		} dp501;
		struct {
			struct drm_encoder encoder;
			struct drm_connector connector;
		} astdp;
	} output;

	bool support_wide_screen;
	enum {
		ast_use_p2a,
		ast_use_dt,
		ast_use_defaults
	} config_mode;

	unsigned long tx_chip_types;		/* bitfield of enum ast_chip_type */
	u8 *dp501_fw_addr;
	const struct firmware *dp501_fw;	/* dp501 fw */
};

static inline struct ast_device *to_ast_device(struct drm_device *dev)
{
	return container_of(dev, struct ast_device, base);
}

struct ast_device *ast_device_create(const struct drm_driver *drv,
				     struct pci_dev *pdev,
				     unsigned long flags);

static inline unsigned long __ast_gen(struct ast_device *ast)
{
	return __AST_CHIP_GEN(ast->chip);
}
#define AST_GEN(__ast)	__ast_gen(__ast)

static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen)
{
	return __ast_gen(ast) == gen;
}
#define IS_AST_GEN1(__ast)	__ast_gen_is_eq(__ast, 1)
#define IS_AST_GEN2(__ast)	__ast_gen_is_eq(__ast, 2)
#define IS_AST_GEN3(__ast)	__ast_gen_is_eq(__ast, 3)
#define IS_AST_GEN4(__ast)	__ast_gen_is_eq(__ast, 4)
#define IS_AST_GEN5(__ast)	__ast_gen_is_eq(__ast, 5)
#define IS_AST_GEN6(__ast)	__ast_gen_is_eq(__ast, 6)
#define IS_AST_GEN7(__ast)	__ast_gen_is_eq(__ast, 7)

#define AST_IO_AR_PORT_WRITE		(0x40)
#define AST_IO_MISC_PORT_WRITE		(0x42)
#define AST_IO_VGA_ENABLE_PORT		(0x43)
#define AST_IO_SEQ_PORT			(0x44)
#define AST_IO_DAC_INDEX_READ		(0x47)
#define AST_IO_DAC_INDEX_WRITE		(0x48)
#define AST_IO_DAC_DATA		        (0x49)
#define AST_IO_GR_PORT			(0x4E)
#define AST_IO_CRTC_PORT		(0x54)
#define AST_IO_INPUT_STATUS1_READ	(0x5A)
#define AST_IO_MISC_PORT_READ		(0x4C)

#define AST_IO_MM_OFFSET		(0x380)

#define AST_IO_VGAIR1_VREFRESH		BIT(3)

#define AST_IO_VGACRCB_HWC_ENABLED     BIT(1)
#define AST_IO_VGACRCB_HWC_16BPP       BIT(0) /* set: ARGB4444, cleared: 2bpp palette */

static inline u32 ast_read32(struct ast_device *ast, u32 reg)
{
	return ioread32(ast->regs + reg);
}

static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
{
	iowrite32(val, ast->regs + reg);
}

static inline u8 ast_io_read8(struct ast_device *ast, u32 reg)
{
	return ioread8(ast->ioregs + reg);
}

static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
{
	iowrite8(val, ast->ioregs + reg);
}

static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index)
{
	ast_io_write8(ast, base, index);
	++base;
	return ast_io_read8(ast, base);
}

static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
					u8 preserve_mask)
{
	u8 val = ast_get_index_reg(ast, base, index);

	return val & preserve_mask;
}

static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
{
	ast_io_write8(ast, base, index);
	++base;
	ast_io_write8(ast, base, val);
}

static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
					  u8 preserve_mask, u8 val)
{
	u8 tmp = ast_get_index_reg_mask(ast, base, index, preserve_mask);

	tmp |= val;
	ast_set_index_reg(ast, base, index, tmp);
}

#define AST_VIDMEM_SIZE_8M    0x00800000
#define AST_VIDMEM_SIZE_16M   0x01000000
#define AST_VIDMEM_SIZE_32M   0x02000000
#define AST_VIDMEM_SIZE_64M   0x04000000
#define AST_VIDMEM_SIZE_128M  0x08000000

#define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M

struct ast_vbios_stdtable {
	u8 misc;
	u8 seq[4];
	u8 crtc[25];
	u8 ar[20];
	u8 gr[9];
};

struct ast_vbios_enhtable {
	u32 ht;
	u32 hde;
	u32 hfp;
	u32 hsync;
	u32 vt;
	u32 vde;
	u32 vfp;
	u32 vsync;
	u32 dclk_index;
	u32 flags;
	u32 refresh_rate;
	u32 refresh_rate_index;
	u32 mode_id;
};

struct ast_vbios_dclk_info {
	u8 param1;
	u8 param2;
	u8 param3;
};

struct ast_vbios_mode_info {
	const struct ast_vbios_stdtable *std_table;
	const struct ast_vbios_enhtable *enh_table;
};

struct ast_crtc_state {
	struct drm_crtc_state base;

	/* Last known format of primary plane */
	const struct drm_format_info *format;

	struct ast_vbios_mode_info vbios_mode_info;
};

#define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)

int ast_mode_config_init(struct ast_device *ast);

#define AST_MM_ALIGN_SHIFT 4
#define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)

#define AST_DP501_FW_VERSION_MASK	GENMASK(7, 4)
#define AST_DP501_FW_VERSION_1		BIT(4)
#define AST_DP501_PNP_CONNECTED		BIT(1)

#define AST_DP501_DEFAULT_DCLK	65

#define AST_DP501_GBL_VERSION	0xf000
#define AST_DP501_PNPMONITOR	0xf010
#define AST_DP501_LINKRATE	0xf014
#define AST_DP501_EDID_DATA	0xf020

/*
 * Display Transmitter Type:
 */
#define TX_TYPE_MASK				GENMASK(3, 1)
#define NO_TX						(0 << 1)
#define ITE66121_VBIOS_TX			(1 << 1)
#define SI164_VBIOS_TX				(2 << 1)
#define CH7003_VBIOS_TX			(3 << 1)
#define DP501_VBIOS_TX				(4 << 1)
#define ANX9807_VBIOS_TX			(5 << 1)
#define TX_FW_EMBEDDED_FW_TX		(6 << 1)
#define ASTDP_DPMCU_TX				(7 << 1)

#define AST_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
//#define AST_VRAM_INIT_BY_BMC		BIT(7)
//#define AST_VRAM_INIT_READY		BIT(6)

/* Define for Soc scratched reg used on ASTDP */
#define AST_DP_PHY_SLEEP			BIT(4)
#define AST_DP_VIDEO_ENABLE		BIT(0)

#define AST_DP_POWER_ON			true
#define AST_DP_POWER_OFF			false

/*
 * CRD1[b5]: DP MCU FW is executing
 * CRDC[b0]: DP link success
 * CRDF[b0]: DP HPD
 * CRE5[b0]: Host reading EDID process is done
 */
#define ASTDP_MCU_FW_EXECUTING			BIT(5)
#define ASTDP_LINK_SUCCESS				BIT(0)
#define ASTDP_HPD						BIT(0)
#define ASTDP_HOST_EDID_READ_DONE		BIT(0)
#define ASTDP_HOST_EDID_READ_DONE_MASK	GENMASK(0, 0)

/*
 * CRB8[b1]: Enable VSYNC off
 * CRB8[b0]: Enable HSYNC off
 */
#define AST_DPMS_VSYNC_OFF				BIT(1)
#define AST_DPMS_HSYNC_OFF				BIT(0)

/*
 * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
 * Precondition:	A. ~AST_DP_PHY_SLEEP  &&
 *			B. DP_HPD &&
 *			C. DP_LINK_SUCCESS
 */
#define ASTDP_MIRROR_VIDEO_ENABLE		BIT(4)

#define ASTDP_EDID_READ_POINTER_MASK	GENMASK(7, 0)
#define ASTDP_EDID_VALID_FLAG_MASK		GENMASK(0, 0)
#define ASTDP_EDID_READ_DATA_MASK		GENMASK(7, 0)

/*
 * ASTDP setmode registers:
 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
 * CRE1[7:0]: MISC1 (default: 0x00)
 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
 */
#define ASTDP_MISC0_24bpp			BIT(5)
#define ASTDP_MISC1				0
#define ASTDP_AND_CLEAR_MASK		0x00

/*
 * ASTDP resoultion table:
 * EX:	ASTDP_A_B_C:
 *		A: Resolution
 *		B: Refresh Rate
 *		C: Misc information, such as CVT, Reduce Blanked
 */
#define ASTDP_640x480_60		0x00
#define ASTDP_640x480_72		0x01
#define ASTDP_640x480_75		0x02
#define ASTDP_640x480_85		0x03
#define ASTDP_800x600_56		0x04
#define ASTDP_800x600_60		0x05
#define ASTDP_800x600_72		0x06
#define ASTDP_800x600_75		0x07
#define ASTDP_800x600_85		0x08
#define ASTDP_1024x768_60		0x09
#define ASTDP_1024x768_70		0x0A
#define ASTDP_1024x768_75		0x0B
#define ASTDP_1024x768_85		0x0C
#define ASTDP_1280x1024_60		0x0D
#define ASTDP_1280x1024_75		0x0E
#define ASTDP_1280x1024_85		0x0F
#define ASTDP_1600x1200_60		0x10
#define ASTDP_320x240_60		0x11
#define ASTDP_400x300_60		0x12
#define ASTDP_512x384_60		0x13
#define ASTDP_1920x1200_60		0x14
#define ASTDP_1920x1080_60		0x15
#define ASTDP_1280x800_60		0x16
#define ASTDP_1280x800_60_RB	0x17
#define ASTDP_1440x900_60		0x18
#define ASTDP_1440x900_60_RB	0x19
#define ASTDP_1680x1050_60		0x1A
#define ASTDP_1680x1050_60_RB	0x1B
#define ASTDP_1600x900_60		0x1C
#define ASTDP_1600x900_60_RB	0x1D
#define ASTDP_1366x768_60		0x1E
#define ASTDP_1152x864_75		0x1F

int ast_mm_init(struct ast_device *ast);

/* ast post */
void ast_post_gpu(struct drm_device *dev);
u32 ast_mindwm(struct ast_device *ast, u32 r);
void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
void ast_patch_ahb_2500(struct ast_device *ast);
/* ast dp501 */
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
u8 ast_get_dp501_max_clk(struct drm_device *dev);
void ast_init_3rdtx(struct drm_device *dev);

/* ast_i2c.c */
struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);

/* aspeed DP */
int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata);
void ast_dp_launch(struct drm_device *dev);
void ast_dp_power_on_off(struct drm_device *dev, bool no);
void ast_dp_set_on_off(struct drm_device *dev, bool no);
void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode);

#endif
Commit	Line	Data
312fec14 DA	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the
	6	* "Software"), to deal in the Software without restriction, including
	7	* without limitation the rights to use, copy, modify, merge, publish,
	8	* distribute, sub license, and/or sell copies of the Software, and to
	9	* permit persons to whom the Software is furnished to do so, subject to
	10	* the following conditions:
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	16	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	17	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	18	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* The above copyright notice and this permission notice (including the
	21	* next paragraph) shall be included in all copies or substantial portions
	22	* of the Software.
	23	*
	24	*/
	25	/*
	26	* Authors: Dave Airlie <airlied@redhat.com>
	27	*/
	28	#ifndef __AST_DRV_H__
	29	#define __AST_DRV_H__
	30
312fec14 DA	31	#include <linux/i2c.h>
312fec14 DA	32	#include <linux/i2c-algo-bit.h>
49a3f51d TZ	33	#include <linux/io.h>
49a3f51d TZ	34	#include <linux/types.h>
312fec14	35
fbbbd160 SR	36	#include <drm/drm_connector.h>
	37	#include <drm/drm_crtc.h>
	38	#include <drm/drm_encoder.h>
	39	#include <drm/drm_mode.h>
	40	#include <drm/drm_framebuffer.h>
fbbbd160	41
312fec14 DA	42	#define DRIVER_AUTHOR "Dave Airlie"
	43
	44	#define DRIVER_NAME "ast"
	45	#define DRIVER_DESC "AST"
	46	#define DRIVER_DATE "20120228"
	47
	48	#define DRIVER_MAJOR 0
	49	#define DRIVER_MINOR 1
	50	#define DRIVER_PATCHLEVEL 0
	51
	52	#define PCI_CHIP_AST2000 0x2000
	53	#define PCI_CHIP_AST2100 0x2010
312fec14	54
ecf64579 TZ	55	#define __AST_CHIP(__gen, __index) ((__gen) << 16 \| (__index))
ecf64579 TZ	56
312fec14	57	enum ast_chip {
ecf64579 TZ	58	/* 1st gen */
	59	AST1000 = __AST_CHIP(1, 0), // unused
	60	AST2000 = __AST_CHIP(1, 1),
	61	/* 2nd gen */
	62	AST1100 = __AST_CHIP(2, 0),
	63	AST2100 = __AST_CHIP(2, 1),
	64	AST2050 = __AST_CHIP(2, 2), // unused
	65	/* 3rd gen */
	66	AST2200 = __AST_CHIP(3, 0),
	67	AST2150 = __AST_CHIP(3, 1),
	68	/* 4th gen */
	69	AST2300 = __AST_CHIP(4, 0),
6bd576da	70	AST1300 = __AST_CHIP(4, 1),
ecf64579 TZ	71	AST1050 = __AST_CHIP(4, 2), // unused
	72	/* 5th gen */
	73	AST2400 = __AST_CHIP(5, 0),
86d86d1b	74	AST1400 = __AST_CHIP(5, 1),
ecf64579 TZ	75	AST1250 = __AST_CHIP(5, 2), // unused
	76	/* 6th gen */
	77	AST2500 = __AST_CHIP(6, 0),
	78	AST2510 = __AST_CHIP(6, 1), // unused
	79	AST2520 = __AST_CHIP(6, 2), // unused
	80	/* 7th gen */
	81	AST2600 = __AST_CHIP(7, 0),
	82	AST2620 = __AST_CHIP(7, 1), // unused
312fec14 DA	83	};
312fec14 DA	84
ecf64579 TZ	85	#define __AST_CHIP_GEN(__chip) (((unsigned long)(__chip)) >> 16)
ecf64579 TZ	86
83c6620b DA	87	enum ast_tx_chip {
	88	AST_TX_NONE,
	89	AST_TX_SIL164,
83c6620b	90	AST_TX_DP501,
594e9c04	91	AST_TX_ASTDP,
83c6620b DA	92	};
83c6620b DA	93
7f35680a TZ	94	#define AST_TX_NONE_BIT BIT(AST_TX_NONE)
	95	#define AST_TX_SIL164_BIT BIT(AST_TX_SIL164)
	96	#define AST_TX_DP501_BIT BIT(AST_TX_DP501)
	97	#define AST_TX_ASTDP_BIT BIT(AST_TX_ASTDP)
	98
312fec14 DA	99	#define AST_DRAM_512Mx16 0
	100	#define AST_DRAM_1Gx16 1
	101	#define AST_DRAM_512Mx32 2
	102	#define AST_DRAM_1Gx32 3
	103	#define AST_DRAM_2Gx16 6
	104	#define AST_DRAM_4Gx16 7
9f93c8b3	105	#define AST_DRAM_8Gx16 8
312fec14	106
a0ba992d	107	/*
537a1db9	108	* Hardware cursor
a0ba992d	109	*/
0090ef3e TZ	110
	111	#define AST_MAX_HWC_WIDTH 64
	112	#define AST_MAX_HWC_HEIGHT 64
	113
	114	#define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
	115	#define AST_HWC_SIGNATURE_SIZE 32
	116
0090ef3e TZ	117	/* define for signature structure */
	118	#define AST_HWC_SIGNATURE_CHECKSUM 0x00
	119	#define AST_HWC_SIGNATURE_SizeX 0x04
	120	#define AST_HWC_SIGNATURE_SizeY 0x08
	121	#define AST_HWC_SIGNATURE_X 0x0C
	122	#define AST_HWC_SIGNATURE_Y 0x10
	123	#define AST_HWC_SIGNATURE_HOTSPOTX 0x14
	124	#define AST_HWC_SIGNATURE_HOTSPOTY 0x18
	125
537a1db9 TZ	126	/*
	127	* Planes
	128	*/
	129
	130	struct ast_plane {
a0ba992d	131	struct drm_plane base;
afee7e95	132
f2fa5a99 TZ	133	void __iomem *vaddr;
	134	u64 offset;
	135	unsigned long size;
a0ba992d TZ	136	};
a0ba992d TZ	137
537a1db9	138	static inline struct ast_plane to_ast_plane(struct drm_plane plane)
a0ba992d	139	{
537a1db9	140	return container_of(plane, struct ast_plane, base);
a0ba992d TZ	141	}
	142
	143	/*
	144	* Connector with i2c channel
	145	*/
	146
6a470dc2 TZ	147	struct ast_i2c_chan {
	148	struct i2c_adapter adapter;
	149	struct drm_device *dev;
	150	struct i2c_algo_bit_data bit;
	151	};
	152
b20384d9	153	struct ast_vga_connector {
6a470dc2 TZ	154	struct drm_connector base;
	155	struct ast_i2c_chan *i2c;
	156	};
	157
b20384d9 TZ	158	static inline struct ast_vga_connector *
b20384d9 TZ	159	to_ast_vga_connector(struct drm_connector *connector)
6a470dc2	160	{
b20384d9	161	return container_of(connector, struct ast_vga_connector, base);
6a470dc2	162	}
0090ef3e	163
5e78d59a TZ	164	struct ast_sil164_connector {
	165	struct drm_connector base;
	166	struct ast_i2c_chan *i2c;
	167	};
	168
	169	static inline struct ast_sil164_connector *
	170	to_ast_sil164_connector(struct drm_connector *connector)
	171	{
	172	return container_of(connector, struct ast_sil164_connector, base);
6a470dc2	173	}
0090ef3e	174
a0ba992d TZ	175	/*
	176	* Device
	177	*/
	178
37b42cf9	179	struct ast_device {
e0f5a738	180	struct drm_device base;
312fec14	181
f870231f	182	struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */
312fec14 DA	183	void __iomem *regs;
312fec14 DA	184	void __iomem *ioregs;
ba4e0339	185	void __iomem *dp501_fw_buf;
312fec14 DA	186
312fec14 DA	187	enum ast_chip chip;
312fec14 DA	188	uint32_t dram_bus_width;
	189	uint32_t dram_type;
	190	uint32_t mclk;
312fec14	191
f2fa5a99 TZ	192	void __iomem *vram;
	193	unsigned long vram_base;
	194	unsigned long vram_size;
	195	unsigned long vram_fb_available;
	196
	197	struct ast_plane primary_plane;
537a1db9	198	struct ast_plane cursor_plane;
6a470dc2	199	struct drm_crtc crtc;
7f35680a	200	struct {
a59b0264 TZ	201	struct {
	202	struct drm_encoder encoder;
	203	struct ast_vga_connector vga_connector;
	204	} vga;
5e78d59a TZ	205	struct {
	206	struct drm_encoder encoder;
	207	struct ast_sil164_connector sil164_connector;
	208	} sil164;
3ab26edd TZ	209	struct {
	210	struct drm_encoder encoder;
	211	struct drm_connector connector;
	212	} dp501;
594e9c04 KC	213	struct {
	214	struct drm_encoder encoder;
	215	struct drm_connector connector;
	216	} astdp;
a59b0264	217	} output;
a6ff807b	218
f1f62f2c	219	bool support_wide_screen;
71f677a9 RC	220	enum {
	221	ast_use_p2a,
	222	ast_use_dt,
	223	ast_use_defaults
	224	} config_mode;
83c6620b	225
7f35680a	226	unsigned long tx_chip_types; /* bitfield of enum ast_chip_type */
83c6620b DA	227	u8 *dp501_fw_addr;
83c6620b DA	228	const struct firmware dp501_fw; / dp501 fw */
312fec14 DA	229	};
312fec14 DA	230
5abaa683	231	static inline struct ast_device to_ast_device(struct drm_device dev)
fa7dbd76	232	{
37b42cf9	233	return container_of(dev, struct ast_device, base);
fa7dbd76 TZ	234	}
fa7dbd76 TZ	235
37b42cf9 TZ	236	struct ast_device ast_device_create(const struct drm_driver drv,
	237	struct pci_dev *pdev,
	238	unsigned long flags);
312fec14	239
ecf64579 TZ	240	static inline unsigned long __ast_gen(struct ast_device *ast)
	241	{
	242	return __AST_CHIP_GEN(ast->chip);
	243	}
	244	#define AST_GEN(__ast) __ast_gen(__ast)
	245
	246	static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen)
	247	{
	248	return __ast_gen(ast) == gen;
	249	}
	250	#define IS_AST_GEN1(__ast) __ast_gen_is_eq(__ast, 1)
	251	#define IS_AST_GEN2(__ast) __ast_gen_is_eq(__ast, 2)
	252	#define IS_AST_GEN3(__ast) __ast_gen_is_eq(__ast, 3)
	253	#define IS_AST_GEN4(__ast) __ast_gen_is_eq(__ast, 4)
	254	#define IS_AST_GEN5(__ast) __ast_gen_is_eq(__ast, 5)
	255	#define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6)
	256	#define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7)
	257
312fec14 DA	258	#define AST_IO_AR_PORT_WRITE (0x40)
312fec14 DA	259	#define AST_IO_MISC_PORT_WRITE (0x42)
0dd68309	260	#define AST_IO_VGA_ENABLE_PORT (0x43)
312fec14	261	#define AST_IO_SEQ_PORT (0x44)
0dd68309	262	#define AST_IO_DAC_INDEX_READ (0x47)
312fec14 DA	263	#define AST_IO_DAC_INDEX_WRITE (0x48)
	264	#define AST_IO_DAC_DATA (0x49)
	265	#define AST_IO_GR_PORT (0x4E)
	266	#define AST_IO_CRTC_PORT (0x54)
	267	#define AST_IO_INPUT_STATUS1_READ (0x5A)
	268	#define AST_IO_MISC_PORT_READ (0x4C)
	269
0dd68309 BH	270	#define AST_IO_MM_OFFSET (0x380)
0dd68309 BH	271
39edb287 TZ	272	#define AST_IO_VGAIR1_VREFRESH BIT(3)
39edb287 TZ	273
4a11bd1e TZ	274	#define AST_IO_VGACRCB_HWC_ENABLED BIT(1)
	275	#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
	276
37b42cf9	277	static inline u32 ast_read32(struct ast_device *ast, u32 reg)
faf67f64 TZ	278	{
faf67f64 TZ	279	return ioread32(ast->regs + reg);
312fec14 DA	280	}
312fec14 DA	281
37b42cf9	282	static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
faf67f64 TZ	283	{
faf67f64 TZ	284	iowrite32(val, ast->regs + reg);
312fec14 DA	285	}
312fec14 DA	286
37b42cf9	287	static inline u8 ast_io_read8(struct ast_device *ast, u32 reg)
faf67f64 TZ	288	{
	289	return ioread8(ast->ioregs + reg);
	290	}
312fec14	291
37b42cf9	292	static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
faf67f64 TZ	293	{
	294	iowrite8(val, ast->ioregs + reg);
	295	}
312fec14	296
1da14d57 TZ	297	static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index)
	298	{
	299	ast_io_write8(ast, base, index);
	300	++base;
	301	return ast_io_read8(ast, base);
	302	}
	303
	304	static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
	305	u8 preserve_mask)
	306	{
	307	u8 val = ast_get_index_reg(ast, base, index);
	308
	309	return val & preserve_mask;
	310	}
	311
	312	static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
312fec14	313	{
a3841086 TZ	314	ast_io_write8(ast, base, index);
	315	++base;
	316	ast_io_write8(ast, base, val);
312fec14 DA	317	}
312fec14 DA	318
1da14d57 TZ	319	static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
	320	u8 preserve_mask, u8 val)
	321	{
	322	u8 tmp = ast_get_index_reg_mask(ast, base, index, preserve_mask);
	323
	324	tmp \|= val;
	325	ast_set_index_reg(ast, base, index, tmp);
	326	}
312fec14	327
312fec14 DA	328	#define AST_VIDMEM_SIZE_8M 0x00800000
	329	#define AST_VIDMEM_SIZE_16M 0x01000000
	330	#define AST_VIDMEM_SIZE_32M 0x02000000
	331	#define AST_VIDMEM_SIZE_64M 0x04000000
	332	#define AST_VIDMEM_SIZE_128M 0x08000000
	333
	334	#define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
	335
312fec14 DA	336	struct ast_vbios_stdtable {
	337	u8 misc;
	338	u8 seq[4];
	339	u8 crtc[25];
	340	u8 ar[20];
	341	u8 gr[9];
	342	};
	343
	344	struct ast_vbios_enhtable {
	345	u32 ht;
	346	u32 hde;
	347	u32 hfp;
	348	u32 hsync;
	349	u32 vt;
	350	u32 vde;
	351	u32 vfp;
	352	u32 vsync;
	353	u32 dclk_index;
	354	u32 flags;
	355	u32 refresh_rate;
	356	u32 refresh_rate_index;
	357	u32 mode_id;
	358	};
	359
	360	struct ast_vbios_dclk_info {
	361	u8 param1;
	362	u8 param2;
	363	u8 param3;
	364	};
	365
	366	struct ast_vbios_mode_info {
22acdbb1 BH	367	const struct ast_vbios_stdtable *std_table;
22acdbb1 BH	368	const struct ast_vbios_enhtable *enh_table;
312fec14 DA	369	};
312fec14 DA	370
83be6a3c TZ	371	struct ast_crtc_state {
83be6a3c TZ	372	struct drm_crtc_state base;
e7d70cd4	373
3339fdf5 TZ	374	/* Last known format of primary plane */
	375	const struct drm_format_info *format;
	376
e7d70cd4	377	struct ast_vbios_mode_info vbios_mode_info;
83be6a3c TZ	378	};
	379
	380	#define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
	381
37b42cf9	382	int ast_mode_config_init(struct ast_device *ast);
312fec14	383
312fec14 DA	384	#define AST_MM_ALIGN_SHIFT 4
	385	#define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
	386
ba4e0339 KC	387	#define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
	388	#define AST_DP501_FW_VERSION_1 BIT(4)
	389	#define AST_DP501_PNP_CONNECTED BIT(1)
	390
	391	#define AST_DP501_DEFAULT_DCLK 65
	392
	393	#define AST_DP501_GBL_VERSION 0xf000
	394	#define AST_DP501_PNPMONITOR 0xf010
	395	#define AST_DP501_LINKRATE 0xf014
	396	#define AST_DP501_EDID_DATA 0xf020
	397
594e9c04 KC	398	/*
	399	* Display Transmitter Type:
	400	*/
	401	#define TX_TYPE_MASK GENMASK(3, 1)
	402	#define NO_TX (0 << 1)
	403	#define ITE66121_VBIOS_TX (1 << 1)
	404	#define SI164_VBIOS_TX (2 << 1)
	405	#define CH7003_VBIOS_TX (3 << 1)
	406	#define DP501_VBIOS_TX (4 << 1)
	407	#define ANX9807_VBIOS_TX (5 << 1)
	408	#define TX_FW_EMBEDDED_FW_TX (6 << 1)
	409	#define ASTDP_DPMCU_TX (7 << 1)
	410
f34bf652 KC	411	#define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6)
	412	//#define AST_VRAM_INIT_BY_BMC BIT(7)
	413	//#define AST_VRAM_INIT_READY BIT(6)
	414
594e9c04 KC	415	/* Define for Soc scratched reg used on ASTDP */
	416	#define AST_DP_PHY_SLEEP BIT(4)
	417	#define AST_DP_VIDEO_ENABLE BIT(0)
	418
	419	#define AST_DP_POWER_ON true
	420	#define AST_DP_POWER_OFF false
	421
	422	/*
	423	* CRD1[b5]: DP MCU FW is executing
	424	* CRDC[b0]: DP link success
	425	* CRDF[b0]: DP HPD
	426	* CRE5[b0]: Host reading EDID process is done
	427	*/
	428	#define ASTDP_MCU_FW_EXECUTING BIT(5)
	429	#define ASTDP_LINK_SUCCESS BIT(0)
	430	#define ASTDP_HPD BIT(0)
	431	#define ASTDP_HOST_EDID_READ_DONE BIT(0)
	432	#define ASTDP_HOST_EDID_READ_DONE_MASK GENMASK(0, 0)
	433
	434	/*
	435	* CRB8[b1]: Enable VSYNC off
	436	* CRB8[b0]: Enable HSYNC off
	437	*/
	438	#define AST_DPMS_VSYNC_OFF BIT(1)
	439	#define AST_DPMS_HSYNC_OFF BIT(0)
	440
	441	/*
	442	* CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
	443	* Precondition: A. ~AST_DP_PHY_SLEEP &&
	444	* B. DP_HPD &&
	445	* C. DP_LINK_SUCCESS
	446	*/
	447	#define ASTDP_MIRROR_VIDEO_ENABLE BIT(4)
	448
	449	#define ASTDP_EDID_READ_POINTER_MASK GENMASK(7, 0)
	450	#define ASTDP_EDID_VALID_FLAG_MASK GENMASK(0, 0)
	451	#define ASTDP_EDID_READ_DATA_MASK GENMASK(7, 0)
	452
	453	/*
	454	* ASTDP setmode registers:
	455	* CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
	456	* CRE1[7:0]: MISC1 (default: 0x00)
	457	* CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
	458	*/
	459	#define ASTDP_MISC0_24bpp BIT(5)
	460	#define ASTDP_MISC1 0
232b95ba	461	#define ASTDP_AND_CLEAR_MASK 0x00
594e9c04 KC	462
	463	/*
	464	* ASTDP resoultion table:
	465	* EX: ASTDP_A_B_C:
	466	* A: Resolution
	467	* B: Refresh Rate
	468	* C: Misc information, such as CVT, Reduce Blanked
	469	*/
	470	#define ASTDP_640x480_60 0x00
	471	#define ASTDP_640x480_72 0x01
	472	#define ASTDP_640x480_75 0x02
	473	#define ASTDP_640x480_85 0x03
	474	#define ASTDP_800x600_56 0x04
	475	#define ASTDP_800x600_60 0x05
	476	#define ASTDP_800x600_72 0x06
	477	#define ASTDP_800x600_75 0x07
	478	#define ASTDP_800x600_85 0x08
	479	#define ASTDP_1024x768_60 0x09
	480	#define ASTDP_1024x768_70 0x0A
	481	#define ASTDP_1024x768_75 0x0B
	482	#define ASTDP_1024x768_85 0x0C
	483	#define ASTDP_1280x1024_60 0x0D
	484	#define ASTDP_1280x1024_75 0x0E
	485	#define ASTDP_1280x1024_85 0x0F
	486	#define ASTDP_1600x1200_60 0x10
	487	#define ASTDP_320x240_60 0x11
	488	#define ASTDP_400x300_60 0x12
	489	#define ASTDP_512x384_60 0x13
	490	#define ASTDP_1920x1200_60 0x14
	491	#define ASTDP_1920x1080_60 0x15
	492	#define ASTDP_1280x800_60 0x16
	493	#define ASTDP_1280x800_60_RB 0x17
	494	#define ASTDP_1440x900_60 0x18
	495	#define ASTDP_1440x900_60_RB 0x19
	496	#define ASTDP_1680x1050_60 0x1A
	497	#define ASTDP_1680x1050_60_RB 0x1B
	498	#define ASTDP_1600x900_60 0x1C
	499	#define ASTDP_1600x900_60_RB 0x1D
	500	#define ASTDP_1366x768_60 0x1E
	501	#define ASTDP_1152x864_75 0x1F
	502
37b42cf9	503	int ast_mm_init(struct ast_device *ast);
312fec14	504
312fec14 DA	505	/* ast post */
312fec14 DA	506	void ast_post_gpu(struct drm_device *dev);
37b42cf9 TZ	507	u32 ast_mindwm(struct ast_device *ast, u32 r);
	508	void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
	509	void ast_patch_ahb_2500(struct ast_device *ast);
83c6620b	510	/* ast dp501 */
83c6620b	511	void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
83c6620b DA	512	bool ast_backup_fw(struct drm_device dev, u8 addr, u32 size);
	513	bool ast_dp501_read_edid(struct drm_device dev, u8 ediddata);
	514	u8 ast_get_dp501_max_clk(struct drm_device *dev);
	515	void ast_init_3rdtx(struct drm_device *dev);
2ccebf56	516
d0a0b6cd TZ	517	/* ast_i2c.c */
	518	struct ast_i2c_chan ast_i2c_create(struct drm_device dev);
	519
594e9c04 KC	520	/* aspeed DP */
594e9c04 KC	521	int ast_astdp_read_edid(struct drm_device dev, u8 ediddata);
bed61c8f	522	void ast_dp_launch(struct drm_device *dev);
594e9c04 KC	523	void ast_dp_power_on_off(struct drm_device *dev, bool no);
	524	void ast_dp_set_on_off(struct drm_device *dev, bool no);
	525	void ast_dp_set_mode(struct drm_crtc crtc, struct ast_vbios_mode_info vbios_mode);
	526
312fec14	527	#endif