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96f60e37 RK |
1 | /* |
2 | * Copyright (C) 2012 Russell King | |
3 | * Rewritten from the dovefb driver, and Armada510 manuals. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | #ifndef ARMADA_HW_H | |
10 | #define ARMADA_HW_H | |
11 | ||
12 | /* | |
13 | * Note: the following registers are written from IRQ context: | |
14 | * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL | |
15 | * LCD_SPU_DMA_START_ADDR_[YUV][01], LCD_SPU_DMA_PITCH_YC, | |
16 | * LCD_SPU_DMA_PITCH_UV, LCD_SPU_DMA_OVSA_HPXL_VLN, | |
17 | * LCD_SPU_DMA_HPXL_VLN, LCD_SPU_DZM_HPXL_VLN, LCD_SPU_DMA_CTRL0 | |
18 | */ | |
19 | enum { | |
20 | LCD_SPU_ADV_REG = 0x0084, /* Armada 510 */ | |
21 | LCD_SPU_DMA_START_ADDR_Y0 = 0x00c0, | |
22 | LCD_SPU_DMA_START_ADDR_U0 = 0x00c4, | |
23 | LCD_SPU_DMA_START_ADDR_V0 = 0x00c8, | |
24 | LCD_CFG_DMA_START_ADDR_0 = 0x00cc, | |
25 | LCD_SPU_DMA_START_ADDR_Y1 = 0x00d0, | |
26 | LCD_SPU_DMA_START_ADDR_U1 = 0x00d4, | |
27 | LCD_SPU_DMA_START_ADDR_V1 = 0x00d8, | |
28 | LCD_CFG_DMA_START_ADDR_1 = 0x00dc, | |
29 | LCD_SPU_DMA_PITCH_YC = 0x00e0, | |
30 | LCD_SPU_DMA_PITCH_UV = 0x00e4, | |
31 | LCD_SPU_DMA_OVSA_HPXL_VLN = 0x00e8, | |
32 | LCD_SPU_DMA_HPXL_VLN = 0x00ec, | |
33 | LCD_SPU_DZM_HPXL_VLN = 0x00f0, | |
34 | LCD_CFG_GRA_START_ADDR0 = 0x00f4, | |
35 | LCD_CFG_GRA_START_ADDR1 = 0x00f8, | |
36 | LCD_CFG_GRA_PITCH = 0x00fc, | |
37 | LCD_SPU_GRA_OVSA_HPXL_VLN = 0x0100, | |
38 | LCD_SPU_GRA_HPXL_VLN = 0x0104, | |
39 | LCD_SPU_GZM_HPXL_VLN = 0x0108, | |
40 | LCD_SPU_HWC_OVSA_HPXL_VLN = 0x010c, | |
41 | LCD_SPU_HWC_HPXL_VLN = 0x0110, | |
42 | LCD_SPUT_V_H_TOTAL = 0x0114, | |
43 | LCD_SPU_V_H_ACTIVE = 0x0118, | |
44 | LCD_SPU_H_PORCH = 0x011c, | |
45 | LCD_SPU_V_PORCH = 0x0120, | |
46 | LCD_SPU_BLANKCOLOR = 0x0124, | |
47 | LCD_SPU_ALPHA_COLOR1 = 0x0128, | |
48 | LCD_SPU_ALPHA_COLOR2 = 0x012c, | |
49 | LCD_SPU_COLORKEY_Y = 0x0130, | |
50 | LCD_SPU_COLORKEY_U = 0x0134, | |
51 | LCD_SPU_COLORKEY_V = 0x0138, | |
52 | LCD_CFG_RDREG4F = 0x013c, /* Armada 510 */ | |
53 | LCD_SPU_SPI_RXDATA = 0x0140, | |
54 | LCD_SPU_ISA_RXDATA = 0x0144, | |
55 | LCD_SPU_HWC_RDDAT = 0x0158, | |
56 | LCD_SPU_GAMMA_RDDAT = 0x015c, | |
57 | LCD_SPU_PALETTE_RDDAT = 0x0160, | |
58 | LCD_SPU_IOPAD_IN = 0x0178, | |
59 | LCD_CFG_RDREG5F = 0x017c, | |
60 | LCD_SPU_SPI_CTRL = 0x0180, | |
61 | LCD_SPU_SPI_TXDATA = 0x0184, | |
62 | LCD_SPU_SMPN_CTRL = 0x0188, | |
63 | LCD_SPU_DMA_CTRL0 = 0x0190, | |
64 | LCD_SPU_DMA_CTRL1 = 0x0194, | |
65 | LCD_SPU_SRAM_CTRL = 0x0198, | |
66 | LCD_SPU_SRAM_WRDAT = 0x019c, | |
67 | LCD_SPU_SRAM_PARA0 = 0x01a0, /* Armada 510 */ | |
68 | LCD_SPU_SRAM_PARA1 = 0x01a4, | |
69 | LCD_CFG_SCLK_DIV = 0x01a8, | |
70 | LCD_SPU_CONTRAST = 0x01ac, | |
71 | LCD_SPU_SATURATION = 0x01b0, | |
72 | LCD_SPU_CBSH_HUE = 0x01b4, | |
73 | LCD_SPU_DUMB_CTRL = 0x01b8, | |
74 | LCD_SPU_IOPAD_CONTROL = 0x01bc, | |
75 | LCD_SPU_IRQ_ENA = 0x01c0, | |
76 | LCD_SPU_IRQ_ISR = 0x01c4, | |
77 | }; | |
78 | ||
79 | /* For LCD_SPU_ADV_REG */ | |
80 | enum { | |
81 | ADV_VSYNC_L_OFF = 0xfff << 20, | |
82 | ADV_GRACOLORKEY = 1 << 19, | |
83 | ADV_VIDCOLORKEY = 1 << 18, | |
84 | ADV_HWC32BLEND = 1 << 15, | |
85 | ADV_HWC32ARGB = 1 << 14, | |
86 | ADV_HWC32ENABLE = 1 << 13, | |
87 | ADV_VSYNCOFFEN = 1 << 12, | |
88 | ADV_VSYNC_H_OFF = 0xfff << 0, | |
89 | }; | |
90 | ||
91 | enum { | |
92 | CFG_565 = 0, | |
93 | CFG_1555 = 1, | |
94 | CFG_888PACK = 2, | |
95 | CFG_X888 = 3, | |
96 | CFG_8888 = 4, | |
97 | CFG_422PACK = 5, | |
98 | CFG_422 = 6, | |
99 | CFG_420 = 7, | |
100 | CFG_PSEUDO4 = 9, | |
101 | CFG_PSEUDO8 = 10, | |
102 | CFG_SWAPRB = 1 << 4, | |
103 | CFG_SWAPUV = 1 << 3, | |
104 | CFG_SWAPYU = 1 << 2, | |
105 | CFG_YUV2RGB = 1 << 1, | |
106 | }; | |
107 | ||
108 | /* For LCD_SPU_DMA_CTRL0 */ | |
109 | enum { | |
110 | CFG_NOBLENDING = 1 << 31, | |
111 | CFG_GAMMA_ENA = 1 << 30, | |
112 | CFG_CBSH_ENA = 1 << 29, | |
113 | CFG_PALETTE_ENA = 1 << 28, | |
114 | CFG_ARBFAST_ENA = 1 << 27, | |
115 | CFG_HWC_1BITMOD = 1 << 26, | |
116 | CFG_HWC_1BITENA = 1 << 25, | |
117 | CFG_HWC_ENA = 1 << 24, | |
118 | CFG_DMAFORMAT = 0xf << 20, | |
119 | #define CFG_DMA_FMT(x) ((x) << 20) | |
120 | CFG_GRAFORMAT = 0xf << 16, | |
121 | #define CFG_GRA_FMT(x) ((x) << 16) | |
122 | #define CFG_GRA_MOD(x) ((x) << 8) | |
123 | CFG_GRA_FTOGGLE = 1 << 15, | |
124 | CFG_GRA_HSMOOTH = 1 << 14, | |
125 | CFG_GRA_TSTMODE = 1 << 13, | |
126 | CFG_GRA_ENA = 1 << 8, | |
127 | #define CFG_DMA_MOD(x) ((x) << 0) | |
128 | CFG_DMA_FTOGGLE = 1 << 7, | |
129 | CFG_DMA_HSMOOTH = 1 << 6, | |
130 | CFG_DMA_TSTMODE = 1 << 5, | |
131 | CFG_DMA_ENA = 1 << 0, | |
132 | }; | |
133 | ||
134 | enum { | |
135 | CKMODE_DISABLE = 0, | |
136 | CKMODE_Y = 1, | |
137 | CKMODE_U = 2, | |
138 | CKMODE_RGB = 3, | |
139 | CKMODE_V = 4, | |
140 | CKMODE_R = 5, | |
141 | CKMODE_G = 6, | |
142 | CKMODE_B = 7, | |
143 | }; | |
144 | ||
145 | /* For LCD_SPU_DMA_CTRL1 */ | |
146 | enum { | |
147 | CFG_FRAME_TRIG = 1 << 31, | |
148 | CFG_VSYNC_INV = 1 << 27, | |
149 | CFG_CKMODE_MASK = 0x7 << 24, | |
150 | #define CFG_CKMODE(x) ((x) << 24) | |
151 | CFG_CARRY = 1 << 23, | |
152 | CFG_GATED_CLK = 1 << 21, | |
153 | CFG_PWRDN_ENA = 1 << 20, | |
154 | CFG_DSCALE_MASK = 0x3 << 18, | |
155 | CFG_DSCALE_NONE = 0x0 << 18, | |
156 | CFG_DSCALE_HALF = 0x1 << 18, | |
157 | CFG_DSCALE_QUAR = 0x2 << 18, | |
158 | CFG_ALPHAM_MASK = 0x3 << 16, | |
159 | CFG_ALPHAM_VIDEO = 0x0 << 16, | |
160 | CFG_ALPHAM_GRA = 0x1 << 16, | |
161 | CFG_ALPHAM_CFG = 0x2 << 16, | |
162 | CFG_ALPHA_MASK = 0xff << 8, | |
163 | CFG_PIXCMD_MASK = 0xff, | |
164 | }; | |
165 | ||
166 | /* For LCD_SPU_SRAM_CTRL */ | |
167 | enum { | |
168 | SRAM_READ = 0 << 14, | |
169 | SRAM_WRITE = 2 << 14, | |
170 | SRAM_INIT = 3 << 14, | |
662af0d8 RK |
171 | SRAM_HWC32_RAM1 = 0xc << 8, |
172 | SRAM_HWC32_RAM2 = 0xd << 8, | |
173 | SRAM_HWC32_RAMR = SRAM_HWC32_RAM1, | |
174 | SRAM_HWC32_RAMG = SRAM_HWC32_RAM2, | |
96f60e37 RK |
175 | SRAM_HWC32_RAMB = 0xe << 8, |
176 | SRAM_HWC32_TRAN = 0xf << 8, | |
177 | SRAM_HWC = 0xf << 8, | |
178 | }; | |
179 | ||
180 | /* For LCD_SPU_SRAM_PARA1 */ | |
181 | enum { | |
182 | CFG_CSB_256x32 = 1 << 15, /* cursor */ | |
183 | CFG_CSB_256x24 = 1 << 14, /* palette */ | |
184 | CFG_CSB_256x8 = 1 << 13, /* gamma */ | |
185 | CFG_PDWN1920x32 = 1 << 8, /* Armada 510: power down vscale ram */ | |
186 | CFG_PDWN256x32 = 1 << 7, /* power down cursor */ | |
187 | CFG_PDWN256x24 = 1 << 6, /* power down palette */ | |
188 | CFG_PDWN256x8 = 1 << 5, /* power down gamma */ | |
189 | CFG_PDWNHWC = 1 << 4, /* Armada 510: power down all hwc ram */ | |
190 | CFG_PDWN32x32 = 1 << 3, /* power down slave->smart ram */ | |
191 | CFG_PDWN16x66 = 1 << 2, /* power down UV fifo */ | |
192 | CFG_PDWN32x66 = 1 << 1, /* power down Y fifo */ | |
193 | CFG_PDWN64x66 = 1 << 0, /* power down graphic fifo */ | |
194 | }; | |
195 | ||
196 | /* For LCD_CFG_SCLK_DIV */ | |
197 | enum { | |
198 | /* Armada 510 */ | |
199 | SCLK_510_AXI = 0x0 << 30, | |
200 | SCLK_510_EXTCLK0 = 0x1 << 30, | |
201 | SCLK_510_PLL = 0x2 << 30, | |
202 | SCLK_510_EXTCLK1 = 0x3 << 30, | |
203 | SCLK_510_DIV_CHANGE = 1 << 29, | |
204 | SCLK_510_FRAC_DIV_MASK = 0xfff << 16, | |
205 | SCLK_510_INT_DIV_MASK = 0xffff << 0, | |
206 | ||
207 | /* Armada 16x */ | |
208 | SCLK_16X_AHB = 0x0 << 28, | |
209 | SCLK_16X_PCLK = 0x1 << 28, | |
210 | SCLK_16X_AXI = 0x4 << 28, | |
211 | SCLK_16X_PLL = 0x8 << 28, | |
212 | SCLK_16X_FRAC_DIV_MASK = 0xfff << 16, | |
213 | SCLK_16X_INT_DIV_MASK = 0xffff << 0, | |
214 | }; | |
215 | ||
216 | /* For LCD_SPU_DUMB_CTRL */ | |
217 | enum { | |
218 | DUMB16_RGB565_0 = 0x0 << 28, | |
219 | DUMB16_RGB565_1 = 0x1 << 28, | |
220 | DUMB18_RGB666_0 = 0x2 << 28, | |
221 | DUMB18_RGB666_1 = 0x3 << 28, | |
222 | DUMB12_RGB444_0 = 0x4 << 28, | |
223 | DUMB12_RGB444_1 = 0x5 << 28, | |
224 | DUMB24_RGB888_0 = 0x6 << 28, | |
225 | DUMB_BLANK = 0x7 << 28, | |
226 | DUMB_MASK = 0xf << 28, | |
227 | CFG_BIAS_OUT = 1 << 8, | |
228 | CFG_REV_RGB = 1 << 7, | |
229 | CFG_INV_CBLANK = 1 << 6, | |
230 | CFG_INV_CSYNC = 1 << 5, /* Normally active high */ | |
231 | CFG_INV_HENA = 1 << 4, | |
232 | CFG_INV_VSYNC = 1 << 3, /* Normally active high */ | |
233 | CFG_INV_HSYNC = 1 << 2, /* Normally active high */ | |
234 | CFG_INV_PCLK = 1 << 1, | |
235 | CFG_DUMB_ENA = 1 << 0, | |
236 | }; | |
237 | ||
238 | /* For LCD_SPU_IOPAD_CONTROL */ | |
239 | enum { | |
240 | CFG_VSCALE_LN_EN = 3 << 18, | |
241 | CFG_GRA_VM_ENA = 1 << 15, | |
242 | CFG_DMA_VM_ENA = 1 << 13, | |
243 | CFG_CMD_VM_ENA = 1 << 11, | |
244 | CFG_CSC_MASK = 3 << 8, | |
245 | CFG_CSC_YUV_CCIR709 = 1 << 9, | |
246 | CFG_CSC_YUV_CCIR601 = 0 << 9, | |
247 | CFG_CSC_RGB_STUDIO = 1 << 8, | |
248 | CFG_CSC_RGB_COMPUTER = 0 << 8, | |
249 | CFG_IOPAD_MASK = 0xf << 0, | |
250 | CFG_IOPAD_DUMB24 = 0x0 << 0, | |
251 | CFG_IOPAD_DUMB18SPI = 0x1 << 0, | |
252 | CFG_IOPAD_DUMB18GPIO = 0x2 << 0, | |
253 | CFG_IOPAD_DUMB16SPI = 0x3 << 0, | |
254 | CFG_IOPAD_DUMB16GPIO = 0x4 << 0, | |
255 | CFG_IOPAD_DUMB12GPIO = 0x5 << 0, | |
256 | CFG_IOPAD_SMART18 = 0x6 << 0, | |
257 | CFG_IOPAD_SMART16 = 0x7 << 0, | |
258 | CFG_IOPAD_SMART8 = 0x8 << 0, | |
259 | }; | |
260 | ||
261 | #define IOPAD_DUMB24 0x0 | |
262 | ||
263 | /* For LCD_SPU_IRQ_ENA */ | |
264 | enum { | |
265 | DMA_FRAME_IRQ0_ENA = 1 << 31, | |
266 | DMA_FRAME_IRQ1_ENA = 1 << 30, | |
267 | DMA_FRAME_IRQ_ENA = DMA_FRAME_IRQ0_ENA | DMA_FRAME_IRQ1_ENA, | |
268 | DMA_FF_UNDERFLOW_ENA = 1 << 29, | |
269 | GRA_FRAME_IRQ0_ENA = 1 << 27, | |
270 | GRA_FRAME_IRQ1_ENA = 1 << 26, | |
271 | GRA_FRAME_IRQ_ENA = GRA_FRAME_IRQ0_ENA | GRA_FRAME_IRQ1_ENA, | |
272 | GRA_FF_UNDERFLOW_ENA = 1 << 25, | |
273 | VSYNC_IRQ_ENA = 1 << 23, | |
274 | DUMB_FRAMEDONE_ENA = 1 << 22, | |
275 | TWC_FRAMEDONE_ENA = 1 << 21, | |
276 | HWC_FRAMEDONE_ENA = 1 << 20, | |
277 | SLV_IRQ_ENA = 1 << 19, | |
278 | SPI_IRQ_ENA = 1 << 18, | |
279 | PWRDN_IRQ_ENA = 1 << 17, | |
280 | ERR_IRQ_ENA = 1 << 16, | |
281 | CLEAN_SPU_IRQ_ISR = 0xffff, | |
282 | }; | |
283 | ||
284 | /* For LCD_SPU_IRQ_ISR */ | |
285 | enum { | |
286 | DMA_FRAME_IRQ0 = 1 << 31, | |
287 | DMA_FRAME_IRQ1 = 1 << 30, | |
288 | DMA_FRAME_IRQ = DMA_FRAME_IRQ0 | DMA_FRAME_IRQ1, | |
289 | DMA_FF_UNDERFLOW = 1 << 29, | |
290 | GRA_FRAME_IRQ0 = 1 << 27, | |
291 | GRA_FRAME_IRQ1 = 1 << 26, | |
292 | GRA_FRAME_IRQ = GRA_FRAME_IRQ0 | GRA_FRAME_IRQ1, | |
293 | GRA_FF_UNDERFLOW = 1 << 25, | |
294 | VSYNC_IRQ = 1 << 23, | |
295 | DUMB_FRAMEDONE = 1 << 22, | |
296 | TWC_FRAMEDONE = 1 << 21, | |
297 | HWC_FRAMEDONE = 1 << 20, | |
298 | SLV_IRQ = 1 << 19, | |
299 | SPI_IRQ = 1 << 18, | |
300 | PWRDN_IRQ = 1 << 17, | |
301 | ERR_IRQ = 1 << 16, | |
302 | DMA_FRAME_IRQ0_LEVEL = 1 << 15, | |
303 | DMA_FRAME_IRQ1_LEVEL = 1 << 14, | |
304 | DMA_FRAME_CNT_ISR = 3 << 12, | |
305 | GRA_FRAME_IRQ0_LEVEL = 1 << 11, | |
306 | GRA_FRAME_IRQ1_LEVEL = 1 << 10, | |
307 | GRA_FRAME_CNT_ISR = 3 << 8, | |
308 | VSYNC_IRQ_LEVEL = 1 << 7, | |
309 | DUMB_FRAMEDONE_LEVEL = 1 << 6, | |
310 | TWC_FRAMEDONE_LEVEL = 1 << 5, | |
311 | HWC_FRAMEDONE_LEVEL = 1 << 4, | |
312 | SLV_FF_EMPTY = 1 << 3, | |
313 | DMA_FF_ALLEMPTY = 1 << 2, | |
314 | GRA_FF_ALLEMPTY = 1 << 1, | |
315 | PWRDN_IRQ_LEVEL = 1 << 0, | |
316 | }; | |
317 | ||
318 | #endif |