[linux-2.6-block.git] / drivers / gpu / drm / armada / armada_crtc.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012 Russell King
 */
#ifndef ARMADA_CRTC_H
#define ARMADA_CRTC_H

#include <drm/drm_crtc.h>

struct armada_gem_object;

struct armada_regs {
	uint32_t offset;
	uint32_t mask;
	uint32_t val;
};

#define armada_reg_queue_mod(_r, _i, _v, _m, _o)	\
	do {					\
		struct armada_regs *__reg = _r;	\
		__reg[_i].offset = _o;		\
		__reg[_i].mask = ~(_m);		\
		__reg[_i].val = _v;		\
		_i++;				\
	} while (0)

#define armada_reg_queue_set(_r, _i, _v, _o)	\
	armada_reg_queue_mod(_r, _i, _v, ~0, _o)

#define armada_reg_queue_end(_r, _i)		\
	armada_reg_queue_mod(_r, _i, 0, 0, ~0)

struct armada_crtc;
struct armada_variant;

struct armada_crtc {
	struct drm_crtc		crtc;
	const struct armada_variant *variant;
	void			*variant_data;
	unsigned		num;
	void __iomem		*base;
	struct clk		*clk;
	struct {
		uint32_t	spu_v_h_total;
		uint32_t	spu_v_porch;
		uint32_t	spu_adv_reg;
	} v[2];
	bool			interlaced;
	bool			cursor_update;

	struct armada_gem_object	*cursor_obj;
	int			cursor_x;
	int			cursor_y;
	uint32_t		cursor_hw_pos;
	uint32_t		cursor_hw_sz;
	uint32_t		cursor_w;
	uint32_t		cursor_h;

	uint32_t		cfg_dumb_ctrl;
	uint32_t		spu_iopad_ctrl;

	spinlock_t		irq_lock;
	uint32_t		irq_ena;

	bool			update_pending;
	struct drm_pending_vblank_event *event;
	struct armada_regs	atomic_regs[32];
	struct armada_regs	*regs;
	unsigned int		regs_idx;
};
#define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc)

void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *);

struct armada_clocking_params {
	unsigned long permillage_min;
	unsigned long permillage_max;
	u32 settable;
	u32 div_max;
};

struct armada_clk_result {
	unsigned long desired_clk_hz;
	struct clk *clk;
	u32 div;
};

int armada_crtc_select_clock(struct armada_crtc *dcrtc,
			     struct armada_clk_result *res,
			     const struct armada_clocking_params *params,
			     struct clk *clks[], size_t num_clks,
			     unsigned long desired_khz);

extern struct platform_driver armada_lcd_platform_driver;

#endif
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
96f60e37 RK	2	/*
96f60e37 RK	3	* Copyright (C) 2012 Russell King
96f60e37 RK	4	*/
	5	#ifndef ARMADA_CRTC_H
	6	#define ARMADA_CRTC_H
	7
fcd70cd3 DV	8	#include <drm/drm_crtc.h>
fcd70cd3 DV	9
96f60e37 RK	10	struct armada_gem_object;
	11
	12	struct armada_regs {
	13	uint32_t offset;
	14	uint32_t mask;
	15	uint32_t val;
	16	};
	17
	18	#define armada_reg_queue_mod(_r, _i, _v, _m, _o) \
	19	do { \
	20	struct armada_regs *__reg = _r; \
	21	__reg[_i].offset = _o; \
	22	__reg[_i].mask = ~(_m); \
	23	__reg[_i].val = _v; \
	24	_i++; \
	25	} while (0)
	26
	27	#define armada_reg_queue_set(_r, _i, _v, _o) \
	28	armada_reg_queue_mod(_r, _i, _v, ~0, _o)
	29
	30	#define armada_reg_queue_end(_r, _i) \
	31	armada_reg_queue_mod(_r, _i, 0, 0, ~0)
	32
4b5dda82	33	struct armada_crtc;
42e62ba7	34	struct armada_variant;
96f60e37 RK	35
	36	struct armada_crtc {
	37	struct drm_crtc crtc;
42e62ba7	38	const struct armada_variant *variant;
1ba246f2	39	void *variant_data;
96f60e37 RK	40	unsigned num;
	41	void __iomem *base;
	42	struct clk *clk;
	43	struct {
	44	uint32_t spu_v_h_total;
	45	uint32_t spu_v_porch;
	46	uint32_t spu_adv_reg;
	47	} v[2];
	48	bool interlaced;
662af0d8	49	bool cursor_update;
96f60e37	50
662af0d8 RK	51	struct armada_gem_object *cursor_obj;
	52	int cursor_x;
	53	int cursor_y;
	54	uint32_t cursor_hw_pos;
	55	uint32_t cursor_hw_sz;
	56	uint32_t cursor_w;
	57	uint32_t cursor_h;
	58
96f60e37	59	uint32_t cfg_dumb_ctrl;
96f60e37 RK	60	uint32_t spu_iopad_ctrl;
96f60e37 RK	61
96f60e37 RK	62	spinlock_t irq_lock;
96f60e37 RK	63	uint32_t irq_ena;
c36045e1	64
3cb13ac9	65	bool update_pending;
dbb4ca8a	66	struct drm_pending_vblank_event *event;
c36045e1 RK	67	struct armada_regs atomic_regs[32];
	68	struct armada_regs *regs;
	69	unsigned int regs_idx;
96f60e37 RK	70	};
	71	#define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc)
	72
96f60e37 RK	73	void armada_drm_crtc_update_regs(struct armada_crtc , struct armada_regs );
96f60e37 RK	74
1ba246f2 RK	75	struct armada_clocking_params {
	76	unsigned long permillage_min;
	77	unsigned long permillage_max;
	78	u32 settable;
	79	u32 div_max;
	80	};
	81
	82	struct armada_clk_result {
	83	unsigned long desired_clk_hz;
	84	struct clk *clk;
	85	u32 div;
	86	};
	87
	88	int armada_crtc_select_clock(struct armada_crtc *dcrtc,
	89	struct armada_clk_result *res,
	90	const struct armada_clocking_params *params,
	91	struct clk *clks[], size_t num_clks,
	92	unsigned long desired_khz);
	93
d8c96083 RK	94	extern struct platform_driver armada_lcd_platform_driver;
d8c96083 RK	95
96f60e37	96	#endif