Commit | Line | Data |
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e559355a | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ad49f860 LD |
2 | /* |
3 | * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. | |
4 | * Author: Liviu Dudau <Liviu.Dudau@arm.com> | |
5 | * | |
ad49f860 LD |
6 | * ARM Mali DP plane manipulation routines. |
7 | */ | |
8 | ||
1f23a56a | 9 | #include <linux/iommu.h> |
535d1b94 | 10 | #include <linux/platform_device.h> |
1f23a56a | 11 | |
b9c3315c | 12 | #include <drm/drm_atomic.h> |
ad49f860 | 13 | #include <drm/drm_atomic_helper.h> |
535d1b94 | 14 | #include <drm/drm_drv.h> |
ad49f860 | 15 | #include <drm/drm_fb_cma_helper.h> |
535d1b94 | 16 | #include <drm/drm_fourcc.h> |
ad49f860 | 17 | #include <drm/drm_gem_cma_helper.h> |
1f23a56a | 18 | #include <drm/drm_gem_framebuffer_helper.h> |
ad49f860 | 19 | #include <drm/drm_plane_helper.h> |
88d4d90f | 20 | #include <drm/drm_print.h> |
ad49f860 LD |
21 | |
22 | #include "malidp_hw.h" | |
23 | #include "malidp_drv.h" | |
24 | ||
25 | /* Layer specific register offsets */ | |
26 | #define MALIDP_LAYER_FORMAT 0x000 | |
ad7fda2e | 27 | #define LAYER_FORMAT_MASK 0x3f |
ad49f860 LD |
28 | #define MALIDP_LAYER_CONTROL 0x004 |
29 | #define LAYER_ENABLE (1 << 0) | |
28ce675b MA |
30 | #define LAYER_FLOWCFG_MASK 7 |
31 | #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1) | |
32 | #define LAYER_FLOWCFG_SCALE_SE 3 | |
ad49f860 LD |
33 | #define LAYER_ROT_OFFSET 8 |
34 | #define LAYER_H_FLIP (1 << 10) | |
35 | #define LAYER_V_FLIP (1 << 11) | |
36 | #define LAYER_ROT_MASK (0xf << 8) | |
c57eb710 BS |
37 | #define LAYER_COMP_MASK (0x3 << 12) |
38 | #define LAYER_COMP_PIXEL (0x3 << 12) | |
39 | #define LAYER_COMP_PLANE (0x2 << 12) | |
187f7f21 | 40 | #define LAYER_PMUL_ENABLE (0x1 << 14) |
f0437819 AH |
41 | #define LAYER_ALPHA_OFFSET (16) |
42 | #define LAYER_ALPHA_MASK (0xff) | |
43 | #define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) | |
c57eb710 | 44 | #define MALIDP_LAYER_COMPOSE 0x008 |
ad49f860 LD |
45 | #define MALIDP_LAYER_SIZE 0x00c |
46 | #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) | |
47 | #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16) | |
48 | #define MALIDP_LAYER_COMP_SIZE 0x010 | |
49 | #define MALIDP_LAYER_OFFSET 0x014 | |
d1479f61 MA |
50 | #define MALIDP550_LS_ENABLE 0x01c |
51 | #define MALIDP550_LS_R1_IN_SIZE 0x020 | |
ad49f860 | 52 | |
5e290226 AKH |
53 | #define MODIFIERS_COUNT_MAX 15 |
54 | ||
c57eb710 BS |
55 | /* |
56 | * This 4-entry look-up-table is used to determine the full 8-bit alpha value | |
57 | * for formats with 1- or 2-bit alpha channels. | |
58 | * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0% | |
59 | * opacity for 2-bit formats. | |
60 | */ | |
61 | #define MALIDP_ALPHA_LUT 0xffaa5500 | |
62 | ||
1f23a56a JF |
63 | /* page sizes the MMU prefetcher can support */ |
64 | #define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K) | |
65 | #define MALIDP_MMU_PREFETCH_FULL_PGSIZES (SZ_1M | SZ_2M) | |
66 | ||
67 | /* readahead for partial-frame prefetch */ | |
68 | #define MALIDP_MMU_PREFETCH_READAHEAD 8 | |
69 | ||
ad49f860 LD |
70 | static void malidp_de_plane_destroy(struct drm_plane *plane) |
71 | { | |
72 | struct malidp_plane *mp = to_malidp_plane(plane); | |
73 | ||
ad49f860 | 74 | drm_plane_cleanup(plane); |
084ffbd7 | 75 | kfree(mp); |
ad49f860 LD |
76 | } |
77 | ||
fe10cd67 MA |
78 | /* |
79 | * Replicate what the default ->reset hook does: free the state pointer and | |
80 | * allocate a new empty object. We just need enough space to store | |
81 | * a malidp_plane_state instead of a drm_plane_state. | |
82 | */ | |
83 | static void malidp_plane_reset(struct drm_plane *plane) | |
84 | { | |
85 | struct malidp_plane_state *state = to_malidp_plane_state(plane->state); | |
86 | ||
87 | if (state) | |
88 | __drm_atomic_helper_plane_destroy_state(&state->base); | |
89 | kfree(state); | |
90 | plane->state = NULL; | |
91 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
ffcf4626 AG |
92 | if (state) |
93 | __drm_atomic_helper_plane_reset(plane, &state->base); | |
fe10cd67 MA |
94 | } |
95 | ||
ed8b0c0f BX |
96 | static struct |
97 | drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) | |
ad49f860 LD |
98 | { |
99 | struct malidp_plane_state *state, *m_state; | |
100 | ||
101 | if (!plane->state) | |
102 | return NULL; | |
103 | ||
104 | state = kmalloc(sizeof(*state), GFP_KERNEL); | |
94d8b9b7 SV |
105 | if (!state) |
106 | return NULL; | |
107 | ||
108 | m_state = to_malidp_plane_state(plane->state); | |
109 | __drm_atomic_helper_plane_duplicate_state(plane, &state->base); | |
110 | state->rotmem_size = m_state->rotmem_size; | |
111 | state->format = m_state->format; | |
112 | state->n_planes = m_state->n_planes; | |
ad49f860 | 113 | |
1f23a56a JF |
114 | state->mmu_prefetch_mode = m_state->mmu_prefetch_mode; |
115 | state->mmu_prefetch_pgsize = m_state->mmu_prefetch_pgsize; | |
116 | ||
ad49f860 LD |
117 | return &state->base; |
118 | } | |
119 | ||
ed8b0c0f BX |
120 | static void malidp_destroy_plane_state(struct drm_plane *plane, |
121 | struct drm_plane_state *state) | |
ad49f860 LD |
122 | { |
123 | struct malidp_plane_state *m_state = to_malidp_plane_state(state); | |
124 | ||
125 | __drm_atomic_helper_plane_destroy_state(state); | |
126 | kfree(m_state); | |
127 | } | |
128 | ||
1f23a56a JF |
129 | static const char * const prefetch_mode_names[] = { |
130 | [MALIDP_PREFETCH_MODE_NONE] = "MMU_PREFETCH_NONE", | |
131 | [MALIDP_PREFETCH_MODE_PARTIAL] = "MMU_PREFETCH_PARTIAL", | |
132 | [MALIDP_PREFETCH_MODE_FULL] = "MMU_PREFETCH_FULL", | |
133 | }; | |
134 | ||
88d4d90f MA |
135 | static void malidp_plane_atomic_print_state(struct drm_printer *p, |
136 | const struct drm_plane_state *state) | |
137 | { | |
138 | struct malidp_plane_state *ms = to_malidp_plane_state(state); | |
88d4d90f MA |
139 | |
140 | drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size); | |
141 | drm_printf(p, "\tformat_id=%u\n", ms->format); | |
142 | drm_printf(p, "\tn_planes=%u\n", ms->n_planes); | |
1f23a56a JF |
143 | drm_printf(p, "\tmmu_prefetch_mode=%s\n", |
144 | prefetch_mode_names[ms->mmu_prefetch_mode]); | |
145 | drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize); | |
88d4d90f MA |
146 | } |
147 | ||
5e290226 AKH |
148 | bool malidp_format_mod_supported(struct drm_device *drm, |
149 | u32 format, u64 modifier) | |
150 | { | |
151 | const struct drm_format_info *info; | |
152 | const u64 *modifiers; | |
153 | struct malidp_drm *malidp = drm->dev_private; | |
154 | const struct malidp_hw_regmap *map = &malidp->dev->hw->map; | |
155 | ||
156 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
157 | return false; | |
158 | ||
159 | /* Some pixel formats are supported without any modifier */ | |
160 | if (modifier == DRM_FORMAT_MOD_LINEAR) { | |
161 | /* | |
162 | * However these pixel formats need to be supported with | |
163 | * modifiers only | |
164 | */ | |
165 | return !malidp_hw_format_is_afbc_only(format); | |
166 | } | |
167 | ||
168 | if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_ARM) { | |
169 | DRM_ERROR("Unknown modifier (not Arm)\n"); | |
170 | return false; | |
171 | } | |
172 | ||
173 | if (modifier & | |
174 | ~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) { | |
175 | DRM_DEBUG_KMS("Unsupported modifiers\n"); | |
176 | return false; | |
177 | } | |
178 | ||
179 | modifiers = malidp_format_modifiers; | |
180 | ||
181 | /* SPLIT buffers must use SPARSE layout */ | |
182 | if (WARN_ON_ONCE((modifier & AFBC_SPLIT) && !(modifier & AFBC_SPARSE))) | |
183 | return false; | |
184 | ||
185 | /* CBR only applies to YUV formats, where YTR should be always 0 */ | |
186 | if (WARN_ON_ONCE((modifier & AFBC_CBR) && (modifier & AFBC_YTR))) | |
187 | return false; | |
188 | ||
189 | while (*modifiers != DRM_FORMAT_MOD_INVALID) { | |
190 | if (*modifiers == modifier) | |
191 | break; | |
192 | ||
193 | modifiers++; | |
194 | } | |
195 | ||
196 | /* return false, if the modifier was not found */ | |
197 | if (*modifiers == DRM_FORMAT_MOD_INVALID) { | |
198 | DRM_DEBUG_KMS("Unsupported modifier\n"); | |
199 | return false; | |
200 | } | |
201 | ||
202 | info = drm_format_info(format); | |
203 | ||
204 | if (info->num_planes != 1) { | |
205 | DRM_DEBUG_KMS("AFBC buffers expect one plane\n"); | |
206 | return false; | |
207 | } | |
208 | ||
209 | if (malidp_hw_format_is_linear_only(format) == true) { | |
210 | DRM_DEBUG_KMS("Given format (0x%x) is supported is linear mode only\n", | |
211 | format); | |
212 | return false; | |
213 | } | |
214 | ||
215 | /* | |
216 | * RGB formats need to provide YTR modifier and YUV formats should not | |
217 | * provide YTR modifier. | |
218 | */ | |
219 | if (!(info->is_yuv) != !!(modifier & AFBC_FORMAT_MOD_YTR)) { | |
220 | DRM_DEBUG_KMS("AFBC_FORMAT_MOD_YTR is %s for %s formats\n", | |
221 | info->is_yuv ? "disallowed" : "mandatory", | |
222 | info->is_yuv ? "YUV" : "RGB"); | |
223 | return false; | |
224 | } | |
225 | ||
226 | if (modifier & AFBC_SPLIT) { | |
227 | if (!info->is_yuv) { | |
b0f986b4 | 228 | if (info->cpp[0] <= 2) { |
5e290226 AKH |
229 | DRM_DEBUG_KMS("RGB formats <= 16bpp are not supported with SPLIT\n"); |
230 | return false; | |
231 | } | |
232 | } | |
233 | ||
f3e9632c | 234 | if ((info->hsub != 1) || (info->vsub != 1)) { |
5e290226 AKH |
235 | if (!(format == DRM_FORMAT_YUV420_10BIT && |
236 | (map->features & MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT))) { | |
237 | DRM_DEBUG_KMS("Formats which are sub-sampled should never be split\n"); | |
238 | return false; | |
239 | } | |
240 | } | |
241 | } | |
242 | ||
243 | if (modifier & AFBC_CBR) { | |
f3e9632c | 244 | if ((info->hsub == 1) || (info->vsub == 1)) { |
5e290226 AKH |
245 | DRM_DEBUG_KMS("Formats which are not sub-sampled should not have CBR set\n"); |
246 | return false; | |
247 | } | |
248 | } | |
249 | ||
250 | return true; | |
251 | } | |
252 | ||
253 | static bool malidp_format_mod_supported_per_plane(struct drm_plane *plane, | |
254 | u32 format, u64 modifier) | |
255 | { | |
256 | return malidp_format_mod_supported(plane->dev, format, modifier); | |
257 | } | |
258 | ||
ad49f860 LD |
259 | static const struct drm_plane_funcs malidp_de_plane_funcs = { |
260 | .update_plane = drm_atomic_helper_update_plane, | |
261 | .disable_plane = drm_atomic_helper_disable_plane, | |
262 | .destroy = malidp_de_plane_destroy, | |
fe10cd67 | 263 | .reset = malidp_plane_reset, |
ad49f860 LD |
264 | .atomic_duplicate_state = malidp_duplicate_plane_state, |
265 | .atomic_destroy_state = malidp_destroy_plane_state, | |
88d4d90f | 266 | .atomic_print_state = malidp_plane_atomic_print_state, |
5e290226 | 267 | .format_mod_supported = malidp_format_mod_supported_per_plane, |
ad49f860 LD |
268 | }; |
269 | ||
28ce675b MA |
270 | static int malidp_se_check_scaling(struct malidp_plane *mp, |
271 | struct drm_plane_state *state) | |
272 | { | |
273 | struct drm_crtc_state *crtc_state = | |
274 | drm_atomic_get_existing_crtc_state(state->state, state->crtc); | |
275 | struct malidp_crtc_state *mc; | |
28ce675b MA |
276 | u32 src_w, src_h; |
277 | int ret; | |
278 | ||
279 | if (!crtc_state) | |
280 | return -EINVAL; | |
281 | ||
f2f2c85c DC |
282 | mc = to_malidp_crtc_state(crtc_state); |
283 | ||
81af63a4 | 284 | ret = drm_atomic_helper_check_plane_state(state, crtc_state, |
a01cb8ba | 285 | 0, INT_MAX, true, true); |
28ce675b MA |
286 | if (ret) |
287 | return ret; | |
288 | ||
e0521c05 LD |
289 | if (state->rotation & MALIDP_ROTATED_MASK) { |
290 | src_w = state->src_h >> 16; | |
291 | src_h = state->src_w >> 16; | |
292 | } else { | |
293 | src_w = state->src_w >> 16; | |
294 | src_h = state->src_h >> 16; | |
295 | } | |
296 | ||
28ce675b MA |
297 | if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { |
298 | /* Scaling not necessary for this plane. */ | |
299 | mc->scaled_planes_mask &= ~(mp->layer->id); | |
300 | return 0; | |
301 | } | |
302 | ||
303 | if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) | |
304 | return -EINVAL; | |
305 | ||
28ce675b MA |
306 | mc->scaled_planes_mask |= mp->layer->id; |
307 | /* Defer scaling requirements calculation to the crtc check. */ | |
308 | return 0; | |
309 | } | |
310 | ||
1f23a56a JF |
311 | static u32 malidp_get_pgsize_bitmap(struct malidp_plane *mp) |
312 | { | |
313 | u32 pgsize_bitmap = 0; | |
314 | ||
315 | if (iommu_present(&platform_bus_type)) { | |
316 | struct iommu_domain *mmu_dom = | |
317 | iommu_get_domain_for_dev(mp->base.dev->dev); | |
318 | ||
319 | if (mmu_dom) | |
320 | pgsize_bitmap = mmu_dom->pgsize_bitmap; | |
321 | } | |
322 | ||
323 | return pgsize_bitmap; | |
324 | } | |
325 | ||
326 | /* | |
327 | * Check if the framebuffer is entirely made up of pages at least pgsize in | |
328 | * size. Only a heuristic: assumes that each scatterlist entry has been aligned | |
329 | * to the largest page size smaller than its length and that the MMU maps to | |
330 | * the largest page size possible. | |
331 | */ | |
332 | static bool malidp_check_pages_threshold(struct malidp_plane_state *ms, | |
333 | u32 pgsize) | |
334 | { | |
335 | int i; | |
336 | ||
337 | for (i = 0; i < ms->n_planes; i++) { | |
338 | struct drm_gem_object *obj; | |
339 | struct drm_gem_cma_object *cma_obj; | |
340 | struct sg_table *sgt; | |
341 | struct scatterlist *sgl; | |
342 | ||
343 | obj = drm_gem_fb_get_obj(ms->base.fb, i); | |
344 | cma_obj = to_drm_gem_cma_obj(obj); | |
345 | ||
346 | if (cma_obj->sgt) | |
347 | sgt = cma_obj->sgt; | |
348 | else | |
d3d1bbe7 | 349 | sgt = obj->funcs->get_sg_table(obj); |
1f23a56a JF |
350 | |
351 | if (!sgt) | |
352 | return false; | |
353 | ||
354 | sgl = sgt->sgl; | |
355 | ||
356 | while (sgl) { | |
357 | if (sgl->length < pgsize) { | |
358 | if (!cma_obj->sgt) | |
359 | kfree(sgt); | |
360 | return false; | |
361 | } | |
362 | ||
363 | sgl = sg_next(sgl); | |
364 | } | |
365 | if (!cma_obj->sgt) | |
366 | kfree(sgt); | |
367 | } | |
368 | ||
369 | return true; | |
370 | } | |
371 | ||
372 | /* | |
373 | * Check if it is possible to enable partial-frame MMU prefetch given the | |
374 | * current format, AFBC state and rotation. | |
375 | */ | |
376 | static bool malidp_partial_prefetch_supported(u32 format, u64 modifier, | |
377 | unsigned int rotation) | |
378 | { | |
379 | bool afbc, sparse; | |
380 | ||
381 | /* rotation and horizontal flip not supported for partial prefetch */ | |
382 | if (rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | | |
383 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X)) | |
384 | return false; | |
385 | ||
386 | afbc = modifier & DRM_FORMAT_MOD_ARM_AFBC(0); | |
387 | sparse = modifier & AFBC_FORMAT_MOD_SPARSE; | |
388 | ||
389 | switch (format) { | |
390 | case DRM_FORMAT_ARGB2101010: | |
391 | case DRM_FORMAT_RGBA1010102: | |
392 | case DRM_FORMAT_BGRA1010102: | |
393 | case DRM_FORMAT_ARGB8888: | |
394 | case DRM_FORMAT_RGBA8888: | |
395 | case DRM_FORMAT_BGRA8888: | |
396 | case DRM_FORMAT_XRGB8888: | |
397 | case DRM_FORMAT_XBGR8888: | |
398 | case DRM_FORMAT_RGBX8888: | |
399 | case DRM_FORMAT_BGRX8888: | |
400 | case DRM_FORMAT_RGB888: | |
401 | case DRM_FORMAT_RGBA5551: | |
402 | case DRM_FORMAT_RGB565: | |
403 | /* always supported */ | |
404 | return true; | |
405 | ||
406 | case DRM_FORMAT_ABGR2101010: | |
407 | case DRM_FORMAT_ABGR8888: | |
408 | case DRM_FORMAT_ABGR1555: | |
409 | case DRM_FORMAT_BGR565: | |
410 | /* supported, but if AFBC then must be sparse mode */ | |
411 | return (!afbc) || (afbc && sparse); | |
412 | ||
413 | case DRM_FORMAT_BGR888: | |
414 | /* supported, but not for AFBC */ | |
415 | return !afbc; | |
416 | ||
417 | case DRM_FORMAT_YUYV: | |
418 | case DRM_FORMAT_UYVY: | |
419 | case DRM_FORMAT_NV12: | |
420 | case DRM_FORMAT_YUV420: | |
421 | /* not supported */ | |
422 | return false; | |
423 | ||
424 | default: | |
425 | return false; | |
426 | } | |
427 | } | |
428 | ||
429 | /* | |
430 | * Select the preferred MMU prefetch mode. Full-frame prefetch is preferred as | |
431 | * long as the framebuffer is all large pages. Otherwise partial-frame prefetch | |
432 | * is selected as long as it is supported for the current format. The selected | |
433 | * page size for prefetch is returned in pgsize_bitmap. | |
434 | */ | |
435 | static enum mmu_prefetch_mode malidp_mmu_prefetch_select_mode | |
436 | (struct malidp_plane_state *ms, u32 *pgsize_bitmap) | |
437 | { | |
438 | u32 pgsizes; | |
439 | ||
440 | /* get the full-frame prefetch page size(s) supported by the MMU */ | |
441 | pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_FULL_PGSIZES; | |
442 | ||
443 | while (pgsizes) { | |
444 | u32 largest_pgsize = 1 << __fls(pgsizes); | |
445 | ||
446 | if (malidp_check_pages_threshold(ms, largest_pgsize)) { | |
447 | *pgsize_bitmap = largest_pgsize; | |
448 | return MALIDP_PREFETCH_MODE_FULL; | |
449 | } | |
450 | ||
451 | pgsizes -= largest_pgsize; | |
452 | } | |
453 | ||
454 | /* get the partial-frame prefetch page size(s) supported by the MMU */ | |
455 | pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES; | |
456 | ||
457 | if (malidp_partial_prefetch_supported(ms->base.fb->format->format, | |
458 | ms->base.fb->modifier, | |
459 | ms->base.rotation)) { | |
460 | /* partial prefetch using the smallest page size */ | |
461 | *pgsize_bitmap = 1 << __ffs(pgsizes); | |
462 | return MALIDP_PREFETCH_MODE_PARTIAL; | |
463 | } | |
464 | *pgsize_bitmap = 0; | |
465 | return MALIDP_PREFETCH_MODE_NONE; | |
466 | } | |
467 | ||
468 | static u32 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode, | |
469 | u8 readahead, u8 n_planes, u32 pgsize) | |
470 | { | |
471 | u32 mmu_ctrl = 0; | |
472 | ||
473 | if (mode != MALIDP_PREFETCH_MODE_NONE) { | |
474 | mmu_ctrl |= MALIDP_MMU_CTRL_EN; | |
475 | ||
476 | if (mode == MALIDP_PREFETCH_MODE_PARTIAL) { | |
477 | mmu_ctrl |= MALIDP_MMU_CTRL_MODE; | |
478 | mmu_ctrl |= MALIDP_MMU_CTRL_PP_NUM_REQ(readahead); | |
479 | } | |
480 | ||
481 | if (pgsize == SZ_64K || pgsize == SZ_2M) { | |
482 | int i; | |
483 | ||
484 | for (i = 0; i < n_planes; i++) | |
485 | mmu_ctrl |= MALIDP_MMU_CTRL_PX_PS(i); | |
486 | } | |
487 | } | |
488 | ||
489 | return mmu_ctrl; | |
490 | } | |
491 | ||
492 | static void malidp_de_prefetch_settings(struct malidp_plane *mp, | |
493 | struct malidp_plane_state *ms) | |
494 | { | |
495 | if (!mp->layer->mmu_ctrl_offset) | |
496 | return; | |
497 | ||
498 | /* get the page sizes supported by the MMU */ | |
499 | ms->mmu_prefetch_pgsize = malidp_get_pgsize_bitmap(mp); | |
500 | ms->mmu_prefetch_mode = | |
501 | malidp_mmu_prefetch_select_mode(ms, &ms->mmu_prefetch_pgsize); | |
502 | } | |
503 | ||
ad49f860 LD |
504 | static int malidp_de_plane_check(struct drm_plane *plane, |
505 | struct drm_plane_state *state) | |
506 | { | |
507 | struct malidp_plane *mp = to_malidp_plane(plane); | |
508 | struct malidp_plane_state *ms = to_malidp_plane_state(state); | |
fcad73b9 | 509 | bool rotated = state->rotation & MALIDP_ROTATED_MASK; |
a46a096a | 510 | struct drm_framebuffer *fb; |
187f7f21 | 511 | u16 pixel_alpha = state->pixel_blend_mode; |
b9c3315c | 512 | int i, ret; |
55bc277d | 513 | unsigned int block_w, block_h; |
ad49f860 | 514 | |
e529878e | 515 | if (!state->crtc || WARN_ON(!state->fb)) |
ad49f860 LD |
516 | return 0; |
517 | ||
a46a096a BS |
518 | fb = state->fb; |
519 | ||
a6993b21 | 520 | ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, |
5e290226 AKH |
521 | mp->layer->id, fb->format->format, |
522 | !!fb->modifier); | |
70c94a3c | 523 | if (ms->format == MALIDP_INVALID_FORMAT_ID) |
ad49f860 LD |
524 | return -EINVAL; |
525 | ||
bcb0b461 | 526 | ms->n_planes = fb->format->num_planes; |
70c94a3c | 527 | for (i = 0; i < ms->n_planes; i++) { |
fcad73b9 | 528 | u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); |
55bc277d | 529 | |
0f6c18de AKH |
530 | if (((fb->pitches[i] * drm_format_info_block_height(fb->format, i)) |
531 | & (alignment - 1)) && !(fb->modifier)) { | |
a46a096a BS |
532 | DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", |
533 | fb->pitches[i], i); | |
534 | return -EINVAL; | |
535 | } | |
536 | } | |
537 | ||
55bc277d AG |
538 | block_w = drm_format_info_block_width(fb->format, 0); |
539 | block_h = drm_format_info_block_height(fb->format, 0); | |
540 | if (fb->width % block_w || fb->height % block_h) { | |
541 | DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes"); | |
542 | return -EINVAL; | |
543 | } | |
544 | if ((state->src_x >> 16) % block_w || (state->src_y >> 16) % block_h) { | |
545 | DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes"); | |
546 | return -EINVAL; | |
547 | } | |
548 | ||
ad49f860 LD |
549 | if ((state->crtc_w > mp->hwdev->max_line_size) || |
550 | (state->crtc_h > mp->hwdev->max_line_size) || | |
551 | (state->crtc_w < mp->hwdev->min_line_size) || | |
b2a2ddb0 | 552 | (state->crtc_h < mp->hwdev->min_line_size)) |
ad49f860 LD |
553 | return -EINVAL; |
554 | ||
83d642ee MA |
555 | /* |
556 | * DP550/650 video layers can accept 3 plane formats only if | |
557 | * fb->pitches[1] == fb->pitches[2] since they don't have a | |
558 | * third plane stride register. | |
559 | */ | |
560 | if (ms->n_planes == 3 && | |
a6993b21 | 561 | !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && |
83d642ee MA |
562 | (state->fb->pitches[1] != state->fb->pitches[2])) |
563 | return -EINVAL; | |
564 | ||
28ce675b MA |
565 | ret = malidp_se_check_scaling(mp, state); |
566 | if (ret) | |
567 | return ret; | |
568 | ||
66da13a5 LD |
569 | /* validate the rotation constraints for each layer */ |
570 | if (state->rotation != DRM_MODE_ROTATE_0) { | |
571 | if (mp->layer->rot == ROTATE_NONE) | |
572 | return -EINVAL; | |
573 | if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier)) | |
574 | return -EINVAL; | |
575 | /* | |
576 | * packed RGB888 / BGR888 can't be rotated or flipped | |
577 | * unless they are stored in a compressed way | |
578 | */ | |
579 | if ((fb->format->format == DRM_FORMAT_RGB888 || | |
580 | fb->format->format == DRM_FORMAT_BGR888) && !(fb->modifier)) | |
581 | return -EINVAL; | |
582 | } | |
ad49f860 | 583 | |
5e290226 AKH |
584 | /* SMART layer does not support AFBC */ |
585 | if (mp->layer->id == DE_SMART && fb->modifier) { | |
586 | DRM_ERROR("AFBC framebuffer not supported in SMART layer"); | |
587 | return -EINVAL; | |
588 | } | |
589 | ||
ad49f860 LD |
590 | ms->rotmem_size = 0; |
591 | if (state->rotation & MALIDP_ROTATED_MASK) { | |
592 | int val; | |
593 | ||
c6cf387e AKH |
594 | val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, |
595 | state->crtc_h, | |
b8207562 AKH |
596 | fb->format->format, |
597 | !!(fb->modifier)); | |
ad49f860 LD |
598 | if (val < 0) |
599 | return val; | |
600 | ||
601 | ms->rotmem_size = val; | |
602 | } | |
603 | ||
187f7f21 LL |
604 | /* HW can't support plane + pixel blending */ |
605 | if ((state->alpha != DRM_BLEND_ALPHA_OPAQUE) && | |
606 | (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) && | |
607 | fb->format->has_alpha) | |
608 | return -EINVAL; | |
609 | ||
1f23a56a JF |
610 | malidp_de_prefetch_settings(mp, ms); |
611 | ||
ad49f860 LD |
612 | return 0; |
613 | } | |
614 | ||
83d642ee MA |
615 | static void malidp_de_set_plane_pitches(struct malidp_plane *mp, |
616 | int num_planes, unsigned int pitches[3]) | |
617 | { | |
618 | int i; | |
619 | int num_strides = num_planes; | |
620 | ||
621 | if (!mp->layer->stride_offset) | |
622 | return; | |
623 | ||
624 | if (num_planes == 3) | |
a6993b21 | 625 | num_strides = (mp->hwdev->hw->features & |
83d642ee MA |
626 | MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; |
627 | ||
55bc277d AG |
628 | /* |
629 | * The drm convention for pitch is that it needs to cover width * cpp, | |
630 | * but our hardware wants the pitch/stride to cover all rows included | |
631 | * in a tile. | |
632 | */ | |
633 | for (i = 0; i < num_strides; ++i) { | |
634 | unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i); | |
635 | ||
636 | malidp_hw_write(mp->hwdev, pitches[i] * block_h, | |
83d642ee MA |
637 | mp->layer->base + |
638 | mp->layer->stride_offset + i * 4); | |
55bc277d | 639 | } |
83d642ee MA |
640 | } |
641 | ||
6e810eb5 MA |
642 | static const s16 |
643 | malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = { | |
644 | [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { | |
645 | 1192, 0, 1634, | |
646 | 1192, -401, -832, | |
647 | 1192, 2066, 0, | |
648 | 64, 512, 512 | |
649 | }, | |
650 | [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { | |
651 | 1024, 0, 1436, | |
652 | 1024, -352, -731, | |
653 | 1024, 1815, 0, | |
654 | 0, 512, 512 | |
655 | }, | |
656 | [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { | |
657 | 1192, 0, 1836, | |
658 | 1192, -218, -546, | |
659 | 1192, 2163, 0, | |
660 | 64, 512, 512 | |
661 | }, | |
662 | [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { | |
663 | 1024, 0, 1613, | |
664 | 1024, -192, -479, | |
665 | 1024, 1900, 0, | |
666 | 0, 512, 512 | |
667 | }, | |
668 | [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = { | |
669 | 1024, 0, 1476, | |
670 | 1024, -165, -572, | |
671 | 1024, 1884, 0, | |
672 | 0, 512, 512 | |
673 | }, | |
674 | [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = { | |
675 | 1024, 0, 1510, | |
676 | 1024, -168, -585, | |
677 | 1024, 1927, 0, | |
678 | 0, 512, 512 | |
679 | } | |
680 | }; | |
681 | ||
682 | static void malidp_de_set_color_encoding(struct malidp_plane *plane, | |
683 | enum drm_color_encoding enc, | |
684 | enum drm_color_range range) | |
685 | { | |
686 | unsigned int i; | |
687 | ||
688 | for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) { | |
689 | /* coefficients are signed, two's complement values */ | |
690 | malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], | |
691 | plane->layer->base + plane->layer->yuv2rgb_offset + | |
692 | i * 4); | |
693 | } | |
694 | } | |
695 | ||
1f23a56a JF |
696 | static void malidp_de_set_mmu_control(struct malidp_plane *mp, |
697 | struct malidp_plane_state *ms) | |
698 | { | |
699 | u32 mmu_ctrl; | |
700 | ||
701 | /* check hardware supports MMU prefetch */ | |
702 | if (!mp->layer->mmu_ctrl_offset) | |
703 | return; | |
704 | ||
705 | mmu_ctrl = malidp_calc_mmu_control_value(ms->mmu_prefetch_mode, | |
706 | MALIDP_MMU_PREFETCH_READAHEAD, | |
707 | ms->n_planes, | |
708 | ms->mmu_prefetch_pgsize); | |
709 | ||
710 | malidp_hw_write(mp->hwdev, mmu_ctrl, | |
711 | mp->layer->base + mp->layer->mmu_ctrl_offset); | |
712 | } | |
713 | ||
54b4260a AKH |
714 | static void malidp_set_plane_base_addr(struct drm_framebuffer *fb, |
715 | struct malidp_plane *mp, | |
716 | int plane_index) | |
717 | { | |
718 | dma_addr_t paddr; | |
719 | u16 ptr; | |
720 | struct drm_plane *plane = &mp->base; | |
721 | bool afbc = fb->modifier ? true : false; | |
722 | ||
723 | ptr = mp->layer->ptr + (plane_index << 4); | |
724 | ||
725 | /* | |
726 | * drm_fb_cma_get_gem_addr() alters the physical base address of the | |
727 | * framebuffer as per the plane's src_x, src_y co-ordinates (ie to | |
728 | * take care of source cropping). | |
729 | * For AFBC, this is not needed as the cropping is handled by _AD_CROP_H | |
730 | * and _AD_CROP_V registers. | |
731 | */ | |
732 | if (!afbc) { | |
733 | paddr = drm_fb_cma_get_gem_addr(fb, plane->state, | |
734 | plane_index); | |
735 | } else { | |
736 | struct drm_gem_cma_object *obj; | |
737 | ||
738 | obj = drm_fb_cma_get_gem_obj(fb, plane_index); | |
739 | ||
740 | if (WARN_ON(!obj)) | |
741 | return; | |
742 | paddr = obj->paddr; | |
743 | } | |
744 | ||
745 | malidp_hw_write(mp->hwdev, lower_32_bits(paddr), ptr); | |
746 | malidp_hw_write(mp->hwdev, upper_32_bits(paddr), ptr + 4); | |
747 | } | |
748 | ||
749 | static void malidp_de_set_plane_afbc(struct drm_plane *plane) | |
750 | { | |
751 | struct malidp_plane *mp; | |
752 | u32 src_w, src_h, val = 0, src_x, src_y; | |
753 | struct drm_framebuffer *fb = plane->state->fb; | |
754 | ||
755 | mp = to_malidp_plane(plane); | |
756 | ||
757 | /* no afbc_decoder_offset means AFBC is not supported on this plane */ | |
758 | if (!mp->layer->afbc_decoder_offset) | |
759 | return; | |
760 | ||
761 | if (!fb->modifier) { | |
762 | malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset); | |
763 | return; | |
764 | } | |
765 | ||
766 | /* convert src values from Q16 fixed point to integer */ | |
767 | src_w = plane->state->src_w >> 16; | |
768 | src_h = plane->state->src_h >> 16; | |
769 | src_x = plane->state->src_x >> 16; | |
770 | src_y = plane->state->src_y >> 16; | |
771 | ||
772 | val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) | | |
773 | src_x; | |
774 | malidp_hw_write(mp->hwdev, val, | |
775 | mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_H); | |
776 | ||
777 | val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) | | |
778 | src_y; | |
779 | malidp_hw_write(mp->hwdev, val, | |
780 | mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_V); | |
781 | ||
782 | val = MALIDP_AD_EN; | |
783 | if (fb->modifier & AFBC_FORMAT_MOD_SPLIT) | |
784 | val |= MALIDP_AD_BS; | |
785 | if (fb->modifier & AFBC_FORMAT_MOD_YTR) | |
786 | val |= MALIDP_AD_YTR; | |
787 | ||
788 | malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset); | |
789 | } | |
790 | ||
ad49f860 LD |
791 | static void malidp_de_plane_update(struct drm_plane *plane, |
792 | struct drm_plane_state *old_state) | |
793 | { | |
ad49f860 | 794 | struct malidp_plane *mp; |
70c94a3c | 795 | struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); |
187f7f21 LL |
796 | struct drm_plane_state *state = plane->state; |
797 | u16 pixel_alpha = state->pixel_blend_mode; | |
798 | u8 plane_alpha = state->alpha >> 8; | |
70c94a3c BS |
799 | u32 src_w, src_h, dest_w, dest_h, val; |
800 | int i; | |
54b4260a | 801 | struct drm_framebuffer *fb = plane->state->fb; |
ad49f860 LD |
802 | |
803 | mp = to_malidp_plane(plane); | |
ad49f860 | 804 | |
54b4260a AKH |
805 | /* |
806 | * For AFBC framebuffer, use the framebuffer width and height for | |
807 | * configuring layer input size register. | |
808 | */ | |
809 | if (fb->modifier) { | |
810 | src_w = fb->width; | |
811 | src_h = fb->height; | |
812 | } else { | |
813 | /* convert src values from Q16 fixed point to integer */ | |
814 | src_w = state->src_w >> 16; | |
815 | src_h = state->src_h >> 16; | |
816 | } | |
817 | ||
187f7f21 LL |
818 | dest_w = state->crtc_w; |
819 | dest_h = state->crtc_h; | |
ad49f860 | 820 | |
ad7fda2e AKH |
821 | val = malidp_hw_read(mp->hwdev, mp->layer->base); |
822 | val = (val & ~LAYER_FORMAT_MASK) | ms->format; | |
823 | malidp_hw_write(mp->hwdev, val, mp->layer->base); | |
ad49f860 | 824 | |
54b4260a AKH |
825 | for (i = 0; i < ms->n_planes; i++) |
826 | malidp_set_plane_base_addr(fb, mp, i); | |
1f23a56a JF |
827 | |
828 | malidp_de_set_mmu_control(mp, ms); | |
829 | ||
83d642ee | 830 | malidp_de_set_plane_pitches(mp, ms->n_planes, |
187f7f21 | 831 | state->fb->pitches); |
ad49f860 | 832 | |
6e810eb5 MA |
833 | if ((plane->state->color_encoding != old_state->color_encoding) || |
834 | (plane->state->color_range != old_state->color_range)) | |
835 | malidp_de_set_color_encoding(mp, plane->state->color_encoding, | |
836 | plane->state->color_range); | |
837 | ||
ad49f860 LD |
838 | malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), |
839 | mp->layer->base + MALIDP_LAYER_SIZE); | |
840 | ||
841 | malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), | |
842 | mp->layer->base + MALIDP_LAYER_COMP_SIZE); | |
843 | ||
187f7f21 LL |
844 | malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) | |
845 | LAYER_V_VAL(state->crtc_y), | |
ad49f860 LD |
846 | mp->layer->base + MALIDP_LAYER_OFFSET); |
847 | ||
791d54fa AG |
848 | if (mp->layer->id == DE_SMART) { |
849 | /* | |
850 | * Enable the first rectangle in the SMART layer to be | |
851 | * able to use it as a drm plane. | |
852 | */ | |
853 | malidp_hw_write(mp->hwdev, 1, | |
854 | mp->layer->base + MALIDP550_LS_ENABLE); | |
d1479f61 MA |
855 | malidp_hw_write(mp->hwdev, |
856 | LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), | |
857 | mp->layer->base + MALIDP550_LS_R1_IN_SIZE); | |
791d54fa | 858 | } |
d1479f61 | 859 | |
54b4260a AKH |
860 | malidp_de_set_plane_afbc(plane); |
861 | ||
c57eb710 BS |
862 | /* first clear the rotation bits */ |
863 | val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); | |
864 | val &= ~LAYER_ROT_MASK; | |
ad49f860 LD |
865 | |
866 | /* setup the rotation and axis flip bits */ | |
187f7f21 | 867 | if (state->rotation & DRM_MODE_ROTATE_MASK) |
c2c446ad | 868 | val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) << |
c7ffa59c | 869 | LAYER_ROT_OFFSET; |
187f7f21 | 870 | if (state->rotation & DRM_MODE_REFLECT_X) |
ad49f860 | 871 | val |= LAYER_H_FLIP; |
187f7f21 | 872 | if (state->rotation & DRM_MODE_REFLECT_Y) |
7916efe5 | 873 | val |= LAYER_V_FLIP; |
ad49f860 | 874 | |
187f7f21 | 875 | val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff)); |
f0437819 | 876 | |
187f7f21 | 877 | if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) { |
f0437819 | 878 | val |= LAYER_COMP_PLANE; |
187f7f21 LL |
879 | } else if (state->fb->format->has_alpha) { |
880 | /* We only care about blend mode if the format has alpha */ | |
881 | switch (pixel_alpha) { | |
882 | case DRM_MODE_BLEND_PREMULTI: | |
883 | val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE; | |
884 | break; | |
885 | case DRM_MODE_BLEND_COVERAGE: | |
886 | val |= LAYER_COMP_PIXEL; | |
887 | break; | |
888 | } | |
f0437819 | 889 | } |
187f7f21 | 890 | val |= LAYER_ALPHA(plane_alpha); |
c57eb710 | 891 | |
28ce675b | 892 | val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); |
187f7f21 | 893 | if (state->crtc) { |
28ce675b | 894 | struct malidp_crtc_state *m = |
187f7f21 | 895 | to_malidp_crtc_state(state->crtc->state); |
28ce675b MA |
896 | |
897 | if (m->scaler_config.scale_enable && | |
898 | m->scaler_config.plane_src_id == mp->layer->id) | |
899 | val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE); | |
900 | } | |
901 | ||
ad49f860 LD |
902 | /* set the 'enable layer' bit */ |
903 | val |= LAYER_ENABLE; | |
904 | ||
c57eb710 BS |
905 | malidp_hw_write(mp->hwdev, val, |
906 | mp->layer->base + MALIDP_LAYER_CONTROL); | |
ad49f860 LD |
907 | } |
908 | ||
909 | static void malidp_de_plane_disable(struct drm_plane *plane, | |
910 | struct drm_plane_state *state) | |
911 | { | |
912 | struct malidp_plane *mp = to_malidp_plane(plane); | |
913 | ||
28ce675b MA |
914 | malidp_hw_clearbits(mp->hwdev, |
915 | LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK), | |
ad49f860 LD |
916 | mp->layer->base + MALIDP_LAYER_CONTROL); |
917 | } | |
918 | ||
919 | static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = { | |
920 | .atomic_check = malidp_de_plane_check, | |
921 | .atomic_update = malidp_de_plane_update, | |
922 | .atomic_disable = malidp_de_plane_disable, | |
923 | }; | |
924 | ||
925 | int malidp_de_planes_init(struct drm_device *drm) | |
926 | { | |
927 | struct malidp_drm *malidp = drm->dev_private; | |
a6993b21 | 928 | const struct malidp_hw_regmap *map = &malidp->dev->hw->map; |
ad49f860 LD |
929 | struct malidp_plane *plane = NULL; |
930 | enum drm_plane_type plane_type; | |
5f368dde | 931 | unsigned long crtcs = BIT(drm->mode_config.num_crtc); |
c2c446ad RF |
932 | unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | |
933 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; | |
187f7f21 LL |
934 | unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | |
935 | BIT(DRM_MODE_BLEND_PREMULTI) | | |
936 | BIT(DRM_MODE_BLEND_COVERAGE); | |
ad49f860 | 937 | u32 *formats; |
25570b5e AKH |
938 | int ret, i = 0, j = 0, n; |
939 | u64 supported_modifiers[MODIFIERS_COUNT_MAX]; | |
940 | const u64 *modifiers; | |
941 | ||
942 | modifiers = malidp_format_modifiers; | |
943 | ||
944 | if (!(map->features & MALIDP_DEVICE_AFBC_SUPPORT_SPLIT)) { | |
945 | /* | |
946 | * Since our hardware does not support SPLIT, so build the list | |
947 | * of supported modifiers excluding SPLIT ones. | |
948 | */ | |
949 | while (*modifiers != DRM_FORMAT_MOD_INVALID) { | |
950 | if (!(*modifiers & AFBC_SPLIT)) | |
951 | supported_modifiers[j++] = *modifiers; | |
952 | ||
953 | modifiers++; | |
954 | } | |
955 | supported_modifiers[j++] = DRM_FORMAT_MOD_INVALID; | |
956 | modifiers = supported_modifiers; | |
957 | } | |
ad49f860 | 958 | |
6211b486 | 959 | formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL); |
ad49f860 LD |
960 | if (!formats) { |
961 | ret = -ENOMEM; | |
962 | goto cleanup; | |
963 | } | |
964 | ||
965 | for (i = 0; i < map->n_layers; i++) { | |
966 | u8 id = map->layers[i].id; | |
967 | ||
968 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
969 | if (!plane) { | |
970 | ret = -ENOMEM; | |
971 | goto cleanup; | |
972 | } | |
973 | ||
974 | /* build the list of DRM supported formats based on the map */ | |
6211b486 BS |
975 | for (n = 0, j = 0; j < map->n_pixel_formats; j++) { |
976 | if ((map->pixel_formats[j].layer & id) == id) | |
977 | formats[n++] = map->pixel_formats[j].format; | |
ad49f860 LD |
978 | } |
979 | ||
980 | plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : | |
981 | DRM_PLANE_TYPE_OVERLAY; | |
25570b5e AKH |
982 | |
983 | /* | |
984 | * All the layers except smart layer supports AFBC modifiers. | |
985 | */ | |
ad49f860 | 986 | ret = drm_universal_plane_init(drm, &plane->base, crtcs, |
25570b5e AKH |
987 | &malidp_de_plane_funcs, formats, n, |
988 | (id == DE_SMART) ? NULL : modifiers, plane_type, | |
989 | NULL); | |
990 | ||
ad49f860 LD |
991 | if (ret < 0) |
992 | goto cleanup; | |
993 | ||
ad49f860 LD |
994 | drm_plane_helper_add(&plane->base, |
995 | &malidp_de_plane_helper_funcs); | |
996 | plane->hwdev = malidp->dev; | |
997 | plane->layer = &map->layers[i]; | |
15807780 | 998 | |
187f7f21 LL |
999 | drm_plane_create_alpha_property(&plane->base); |
1000 | drm_plane_create_blend_mode_property(&plane->base, blend_caps); | |
1001 | ||
d1479f61 | 1002 | if (id == DE_SMART) { |
d1479f61 | 1003 | /* Skip the features which the SMART layer doesn't have. */ |
15807780 | 1004 | continue; |
d1479f61 | 1005 | } |
15807780 | 1006 | |
c2c446ad | 1007 | drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); |
c57eb710 BS |
1008 | malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT, |
1009 | plane->layer->base + MALIDP_LAYER_COMPOSE); | |
6e810eb5 MA |
1010 | |
1011 | /* Attach the YUV->RGB property only to video layers */ | |
1012 | if (id & (DE_VIDEO1 | DE_VIDEO2)) { | |
1013 | /* default encoding for YUV->RGB is BT601 NARROW */ | |
1014 | enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; | |
1015 | enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; | |
1016 | ||
1017 | ret = drm_plane_create_color_properties(&plane->base, | |
1018 | BIT(DRM_COLOR_YCBCR_BT601) | \ | |
1019 | BIT(DRM_COLOR_YCBCR_BT709) | \ | |
1020 | BIT(DRM_COLOR_YCBCR_BT2020), | |
1021 | BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ | |
1022 | BIT(DRM_COLOR_YCBCR_FULL_RANGE), | |
1023 | enc, range); | |
1024 | if (!ret) | |
1025 | /* program the HW registers */ | |
1026 | malidp_de_set_color_encoding(plane, enc, range); | |
1027 | else | |
1028 | DRM_WARN("Failed to create video layer %d color properties\n", id); | |
1029 | } | |
ad49f860 LD |
1030 | } |
1031 | ||
1032 | kfree(formats); | |
1033 | ||
1034 | return 0; | |
1035 | ||
1036 | cleanup: | |
ad49f860 LD |
1037 | kfree(formats); |
1038 | ||
1039 | return ret; | |
1040 | } |