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8e22d792 LD |
1 | /* |
2 | * Copyright (C) 2013-2015 ARM Limited | |
3 | * Author: Liviu Dudau <Liviu.Dudau@arm.com> | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file COPYING in the main directory of this archive | |
7 | * for more details. | |
8 | * | |
9 | * ARM HDLCD Driver | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/component.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/of_graph.h> | |
18 | #include <linux/of_reserved_mem.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | ||
21 | #include <drm/drmP.h> | |
22 | #include <drm/drm_atomic_helper.h> | |
23 | #include <drm/drm_crtc.h> | |
24 | #include <drm/drm_crtc_helper.h> | |
25 | #include <drm/drm_fb_helper.h> | |
26 | #include <drm/drm_fb_cma_helper.h> | |
27 | #include <drm/drm_gem_cma_helper.h> | |
28 | #include <drm/drm_of.h> | |
29 | ||
30 | #include "hdlcd_drv.h" | |
31 | #include "hdlcd_regs.h" | |
32 | ||
33 | static int hdlcd_load(struct drm_device *drm, unsigned long flags) | |
34 | { | |
35 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
36 | struct platform_device *pdev = to_platform_device(drm->dev); | |
37 | struct resource *res; | |
38 | u32 version; | |
39 | int ret; | |
40 | ||
41 | hdlcd->clk = devm_clk_get(drm->dev, "pxlclk"); | |
42 | if (IS_ERR(hdlcd->clk)) | |
43 | return PTR_ERR(hdlcd->clk); | |
44 | ||
45 | #ifdef CONFIG_DEBUG_FS | |
46 | atomic_set(&hdlcd->buffer_underrun_count, 0); | |
47 | atomic_set(&hdlcd->bus_error_count, 0); | |
48 | atomic_set(&hdlcd->vsync_count, 0); | |
49 | atomic_set(&hdlcd->dma_end_count, 0); | |
50 | #endif | |
51 | ||
52 | INIT_LIST_HEAD(&hdlcd->event_list); | |
53 | ||
54 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
55 | hdlcd->mmio = devm_ioremap_resource(drm->dev, res); | |
56 | if (IS_ERR(hdlcd->mmio)) { | |
57 | DRM_ERROR("failed to map control registers area\n"); | |
69c2565a | 58 | ret = PTR_ERR(hdlcd->mmio); |
8e22d792 | 59 | hdlcd->mmio = NULL; |
69c2565a | 60 | return ret; |
8e22d792 LD |
61 | } |
62 | ||
63 | version = hdlcd_read(hdlcd, HDLCD_REG_VERSION); | |
64 | if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) { | |
65 | DRM_ERROR("unknown product id: 0x%x\n", version); | |
61a6dcd7 | 66 | return -EINVAL; |
8e22d792 LD |
67 | } |
68 | DRM_INFO("found ARM HDLCD version r%dp%d\n", | |
69 | (version & HDLCD_VERSION_MAJOR_MASK) >> 8, | |
70 | version & HDLCD_VERSION_MINOR_MASK); | |
71 | ||
72 | /* Get the optional framebuffer memory resource */ | |
73 | ret = of_reserved_mem_device_init(drm->dev); | |
74 | if (ret && ret != -ENODEV) | |
61a6dcd7 | 75 | return ret; |
8e22d792 LD |
76 | |
77 | ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); | |
78 | if (ret) | |
79 | goto setup_fail; | |
80 | ||
81 | ret = hdlcd_setup_crtc(drm); | |
82 | if (ret < 0) { | |
83 | DRM_ERROR("failed to create crtc\n"); | |
84 | goto setup_fail; | |
85 | } | |
86 | ||
87 | pm_runtime_enable(drm->dev); | |
88 | ||
89 | pm_runtime_get_sync(drm->dev); | |
90 | ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); | |
91 | pm_runtime_put_sync(drm->dev); | |
92 | if (ret < 0) { | |
93 | DRM_ERROR("failed to install IRQ handler\n"); | |
94 | goto irq_fail; | |
95 | } | |
96 | ||
97 | return 0; | |
98 | ||
99 | irq_fail: | |
100 | drm_crtc_cleanup(&hdlcd->crtc); | |
101 | setup_fail: | |
102 | of_reserved_mem_device_release(drm->dev); | |
8e22d792 LD |
103 | |
104 | return ret; | |
105 | } | |
106 | ||
107 | static void hdlcd_fb_output_poll_changed(struct drm_device *drm) | |
108 | { | |
109 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
110 | ||
111 | if (hdlcd->fbdev) | |
112 | drm_fbdev_cma_hotplug_event(hdlcd->fbdev); | |
113 | } | |
114 | ||
115 | static int hdlcd_atomic_commit(struct drm_device *dev, | |
116 | struct drm_atomic_state *state, bool async) | |
117 | { | |
118 | return drm_atomic_helper_commit(dev, state, false); | |
119 | } | |
120 | ||
121 | static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = { | |
122 | .fb_create = drm_fb_cma_create, | |
123 | .output_poll_changed = hdlcd_fb_output_poll_changed, | |
124 | .atomic_check = drm_atomic_helper_check, | |
125 | .atomic_commit = hdlcd_atomic_commit, | |
126 | }; | |
127 | ||
128 | static void hdlcd_setup_mode_config(struct drm_device *drm) | |
129 | { | |
130 | drm_mode_config_init(drm); | |
131 | drm->mode_config.min_width = 0; | |
132 | drm->mode_config.min_height = 0; | |
133 | drm->mode_config.max_width = HDLCD_MAX_XRES; | |
134 | drm->mode_config.max_height = HDLCD_MAX_YRES; | |
135 | drm->mode_config.funcs = &hdlcd_mode_config_funcs; | |
136 | } | |
137 | ||
138 | static void hdlcd_lastclose(struct drm_device *drm) | |
139 | { | |
140 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
141 | ||
142 | drm_fbdev_cma_restore_mode(hdlcd->fbdev); | |
143 | } | |
144 | ||
145 | static irqreturn_t hdlcd_irq(int irq, void *arg) | |
146 | { | |
147 | struct drm_device *drm = arg; | |
148 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
149 | unsigned long irq_status; | |
150 | ||
151 | irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS); | |
152 | ||
153 | #ifdef CONFIG_DEBUG_FS | |
154 | if (irq_status & HDLCD_INTERRUPT_UNDERRUN) | |
155 | atomic_inc(&hdlcd->buffer_underrun_count); | |
156 | ||
157 | if (irq_status & HDLCD_INTERRUPT_DMA_END) | |
158 | atomic_inc(&hdlcd->dma_end_count); | |
159 | ||
160 | if (irq_status & HDLCD_INTERRUPT_BUS_ERROR) | |
161 | atomic_inc(&hdlcd->bus_error_count); | |
162 | ||
163 | if (irq_status & HDLCD_INTERRUPT_VSYNC) | |
164 | atomic_inc(&hdlcd->vsync_count); | |
165 | ||
166 | #endif | |
167 | if (irq_status & HDLCD_INTERRUPT_VSYNC) { | |
168 | bool events_sent = false; | |
169 | unsigned long flags; | |
170 | struct drm_pending_vblank_event *e, *t; | |
171 | ||
172 | drm_crtc_handle_vblank(&hdlcd->crtc); | |
173 | ||
174 | spin_lock_irqsave(&drm->event_lock, flags); | |
175 | list_for_each_entry_safe(e, t, &hdlcd->event_list, base.link) { | |
176 | list_del(&e->base.link); | |
177 | drm_crtc_send_vblank_event(&hdlcd->crtc, e); | |
178 | events_sent = true; | |
179 | } | |
180 | if (events_sent) | |
181 | drm_crtc_vblank_put(&hdlcd->crtc); | |
182 | spin_unlock_irqrestore(&drm->event_lock, flags); | |
183 | } | |
184 | ||
185 | /* acknowledge interrupt(s) */ | |
186 | hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status); | |
187 | ||
188 | return IRQ_HANDLED; | |
189 | } | |
190 | ||
191 | static void hdlcd_irq_preinstall(struct drm_device *drm) | |
192 | { | |
193 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
194 | /* Ensure interrupts are disabled */ | |
195 | hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0); | |
196 | hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0); | |
197 | } | |
198 | ||
199 | static int hdlcd_irq_postinstall(struct drm_device *drm) | |
200 | { | |
201 | #ifdef CONFIG_DEBUG_FS | |
202 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
203 | unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); | |
204 | ||
205 | /* enable debug interrupts */ | |
206 | irq_mask |= HDLCD_DEBUG_INT_MASK; | |
207 | ||
208 | hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); | |
209 | #endif | |
210 | return 0; | |
211 | } | |
212 | ||
213 | static void hdlcd_irq_uninstall(struct drm_device *drm) | |
214 | { | |
215 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
216 | /* disable all the interrupts that we might have enabled */ | |
217 | unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); | |
218 | ||
219 | #ifdef CONFIG_DEBUG_FS | |
220 | /* disable debug interrupts */ | |
221 | irq_mask &= ~HDLCD_DEBUG_INT_MASK; | |
222 | #endif | |
223 | ||
224 | /* disable vsync interrupts */ | |
225 | irq_mask &= ~HDLCD_INTERRUPT_VSYNC; | |
226 | ||
227 | hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); | |
228 | } | |
229 | ||
230 | static int hdlcd_enable_vblank(struct drm_device *drm, unsigned int crtc) | |
231 | { | |
232 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
233 | unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); | |
234 | ||
235 | hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
240 | static void hdlcd_disable_vblank(struct drm_device *drm, unsigned int crtc) | |
241 | { | |
242 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
243 | unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); | |
244 | ||
245 | hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); | |
246 | } | |
247 | ||
248 | #ifdef CONFIG_DEBUG_FS | |
249 | static int hdlcd_show_underrun_count(struct seq_file *m, void *arg) | |
250 | { | |
251 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
252 | struct drm_device *drm = node->minor->dev; | |
253 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
254 | ||
255 | seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count)); | |
256 | seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count)); | |
257 | seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count)); | |
258 | seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count)); | |
259 | return 0; | |
260 | } | |
261 | ||
262 | static int hdlcd_show_pxlclock(struct seq_file *m, void *arg) | |
263 | { | |
264 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
265 | struct drm_device *drm = node->minor->dev; | |
266 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
267 | unsigned long clkrate = clk_get_rate(hdlcd->clk); | |
268 | unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000; | |
269 | ||
270 | seq_printf(m, "hw : %lu\n", clkrate); | |
271 | seq_printf(m, "mode: %lu\n", mode_clock); | |
272 | return 0; | |
273 | } | |
274 | ||
275 | static struct drm_info_list hdlcd_debugfs_list[] = { | |
276 | { "interrupt_count", hdlcd_show_underrun_count, 0 }, | |
277 | { "clocks", hdlcd_show_pxlclock, 0 }, | |
278 | }; | |
279 | ||
280 | static int hdlcd_debugfs_init(struct drm_minor *minor) | |
281 | { | |
282 | return drm_debugfs_create_files(hdlcd_debugfs_list, | |
283 | ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor); | |
284 | } | |
285 | ||
286 | static void hdlcd_debugfs_cleanup(struct drm_minor *minor) | |
287 | { | |
288 | drm_debugfs_remove_files(hdlcd_debugfs_list, | |
289 | ARRAY_SIZE(hdlcd_debugfs_list), minor); | |
290 | } | |
291 | #endif | |
292 | ||
293 | static const struct file_operations fops = { | |
294 | .owner = THIS_MODULE, | |
295 | .open = drm_open, | |
296 | .release = drm_release, | |
297 | .unlocked_ioctl = drm_ioctl, | |
298 | #ifdef CONFIG_COMPAT | |
299 | .compat_ioctl = drm_compat_ioctl, | |
300 | #endif | |
301 | .poll = drm_poll, | |
302 | .read = drm_read, | |
303 | .llseek = noop_llseek, | |
304 | .mmap = drm_gem_cma_mmap, | |
305 | }; | |
306 | ||
307 | static struct drm_driver hdlcd_driver = { | |
308 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | | |
309 | DRIVER_MODESET | DRIVER_PRIME | | |
310 | DRIVER_ATOMIC, | |
311 | .lastclose = hdlcd_lastclose, | |
312 | .irq_handler = hdlcd_irq, | |
313 | .irq_preinstall = hdlcd_irq_preinstall, | |
314 | .irq_postinstall = hdlcd_irq_postinstall, | |
315 | .irq_uninstall = hdlcd_irq_uninstall, | |
316 | .get_vblank_counter = drm_vblank_no_hw_counter, | |
317 | .enable_vblank = hdlcd_enable_vblank, | |
318 | .disable_vblank = hdlcd_disable_vblank, | |
319 | .gem_free_object = drm_gem_cma_free_object, | |
320 | .gem_vm_ops = &drm_gem_cma_vm_ops, | |
321 | .dumb_create = drm_gem_cma_dumb_create, | |
322 | .dumb_map_offset = drm_gem_cma_dumb_map_offset, | |
323 | .dumb_destroy = drm_gem_dumb_destroy, | |
324 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
325 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
326 | .gem_prime_export = drm_gem_prime_export, | |
327 | .gem_prime_import = drm_gem_prime_import, | |
328 | .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, | |
329 | .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, | |
330 | .gem_prime_vmap = drm_gem_cma_prime_vmap, | |
331 | .gem_prime_vunmap = drm_gem_cma_prime_vunmap, | |
332 | .gem_prime_mmap = drm_gem_cma_prime_mmap, | |
333 | #ifdef CONFIG_DEBUG_FS | |
334 | .debugfs_init = hdlcd_debugfs_init, | |
335 | .debugfs_cleanup = hdlcd_debugfs_cleanup, | |
336 | #endif | |
337 | .fops = &fops, | |
338 | .name = "hdlcd", | |
339 | .desc = "ARM HDLCD Controller DRM", | |
340 | .date = "20151021", | |
341 | .major = 1, | |
342 | .minor = 0, | |
343 | }; | |
344 | ||
345 | static int hdlcd_drm_bind(struct device *dev) | |
346 | { | |
347 | struct drm_device *drm; | |
348 | struct hdlcd_drm_private *hdlcd; | |
349 | int ret; | |
350 | ||
351 | hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL); | |
352 | if (!hdlcd) | |
353 | return -ENOMEM; | |
354 | ||
355 | drm = drm_dev_alloc(&hdlcd_driver, dev); | |
356 | if (!drm) | |
357 | return -ENOMEM; | |
358 | ||
359 | drm->dev_private = hdlcd; | |
360 | hdlcd_setup_mode_config(drm); | |
361 | ret = hdlcd_load(drm, 0); | |
362 | if (ret) | |
363 | goto err_free; | |
364 | ||
365 | ret = drm_dev_register(drm, 0); | |
366 | if (ret) | |
367 | goto err_unload; | |
368 | ||
369 | dev_set_drvdata(dev, drm); | |
370 | ||
371 | ret = component_bind_all(dev, drm); | |
372 | if (ret) { | |
373 | DRM_ERROR("Failed to bind all components\n"); | |
374 | goto err_unregister; | |
375 | } | |
376 | ||
377 | ret = drm_vblank_init(drm, drm->mode_config.num_crtc); | |
378 | if (ret < 0) { | |
379 | DRM_ERROR("failed to initialise vblank\n"); | |
380 | goto err_vblank; | |
381 | } | |
382 | drm->vblank_disable_allowed = true; | |
383 | ||
384 | drm_mode_config_reset(drm); | |
385 | drm_kms_helper_poll_init(drm); | |
386 | ||
387 | hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc, | |
388 | drm->mode_config.num_connector); | |
389 | ||
390 | if (IS_ERR(hdlcd->fbdev)) { | |
391 | ret = PTR_ERR(hdlcd->fbdev); | |
392 | hdlcd->fbdev = NULL; | |
393 | goto err_fbdev; | |
394 | } | |
395 | ||
396 | return 0; | |
397 | ||
398 | err_fbdev: | |
399 | drm_kms_helper_poll_fini(drm); | |
400 | drm_mode_config_cleanup(drm); | |
401 | drm_vblank_cleanup(drm); | |
402 | err_vblank: | |
403 | component_unbind_all(dev, drm); | |
404 | err_unregister: | |
405 | drm_dev_unregister(drm); | |
406 | err_unload: | |
407 | pm_runtime_get_sync(drm->dev); | |
408 | drm_irq_uninstall(drm); | |
409 | pm_runtime_put_sync(drm->dev); | |
410 | pm_runtime_disable(drm->dev); | |
411 | of_reserved_mem_device_release(drm->dev); | |
8e22d792 LD |
412 | err_free: |
413 | drm_dev_unref(drm); | |
414 | ||
415 | return ret; | |
416 | } | |
417 | ||
418 | static void hdlcd_drm_unbind(struct device *dev) | |
419 | { | |
420 | struct drm_device *drm = dev_get_drvdata(dev); | |
421 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
422 | ||
423 | if (hdlcd->fbdev) { | |
424 | drm_fbdev_cma_fini(hdlcd->fbdev); | |
425 | hdlcd->fbdev = NULL; | |
426 | } | |
427 | drm_kms_helper_poll_fini(drm); | |
428 | component_unbind_all(dev, drm); | |
429 | drm_vblank_cleanup(drm); | |
430 | pm_runtime_get_sync(drm->dev); | |
431 | drm_irq_uninstall(drm); | |
432 | pm_runtime_put_sync(drm->dev); | |
433 | pm_runtime_disable(drm->dev); | |
434 | of_reserved_mem_device_release(drm->dev); | |
8e22d792 LD |
435 | drm_mode_config_cleanup(drm); |
436 | drm_dev_unregister(drm); | |
437 | drm_dev_unref(drm); | |
438 | drm->dev_private = NULL; | |
439 | dev_set_drvdata(dev, NULL); | |
440 | } | |
441 | ||
442 | static const struct component_master_ops hdlcd_master_ops = { | |
443 | .bind = hdlcd_drm_bind, | |
444 | .unbind = hdlcd_drm_unbind, | |
445 | }; | |
446 | ||
447 | static int compare_dev(struct device *dev, void *data) | |
448 | { | |
449 | return dev->of_node == data; | |
450 | } | |
451 | ||
452 | static int hdlcd_probe(struct platform_device *pdev) | |
453 | { | |
454 | struct device_node *port, *ep; | |
455 | struct component_match *match = NULL; | |
456 | ||
457 | if (!pdev->dev.of_node) | |
458 | return -ENODEV; | |
459 | ||
460 | /* there is only one output port inside each device, find it */ | |
461 | ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL); | |
462 | if (!ep) | |
463 | return -ENODEV; | |
464 | ||
465 | if (!of_device_is_available(ep)) { | |
466 | of_node_put(ep); | |
467 | return -ENODEV; | |
468 | } | |
469 | ||
470 | /* add the remote encoder port as component */ | |
471 | port = of_graph_get_remote_port_parent(ep); | |
472 | of_node_put(ep); | |
473 | if (!port || !of_device_is_available(port)) { | |
474 | of_node_put(port); | |
475 | return -EAGAIN; | |
476 | } | |
477 | ||
478 | component_match_add(&pdev->dev, &match, compare_dev, port); | |
479 | ||
480 | return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops, | |
481 | match); | |
482 | } | |
483 | ||
484 | static int hdlcd_remove(struct platform_device *pdev) | |
485 | { | |
486 | component_master_del(&pdev->dev, &hdlcd_master_ops); | |
487 | return 0; | |
488 | } | |
489 | ||
490 | static const struct of_device_id hdlcd_of_match[] = { | |
491 | { .compatible = "arm,hdlcd" }, | |
492 | {}, | |
493 | }; | |
494 | MODULE_DEVICE_TABLE(of, hdlcd_of_match); | |
495 | ||
496 | static int __maybe_unused hdlcd_pm_suspend(struct device *dev) | |
497 | { | |
498 | struct drm_device *drm = dev_get_drvdata(dev); | |
499 | struct drm_crtc *crtc; | |
500 | ||
501 | if (pm_runtime_suspended(dev)) | |
502 | return 0; | |
503 | ||
504 | drm_modeset_lock_all(drm); | |
505 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) | |
506 | hdlcd_crtc_suspend(crtc); | |
507 | drm_modeset_unlock_all(drm); | |
508 | return 0; | |
509 | } | |
510 | ||
511 | static int __maybe_unused hdlcd_pm_resume(struct device *dev) | |
512 | { | |
513 | struct drm_device *drm = dev_get_drvdata(dev); | |
514 | struct drm_crtc *crtc; | |
515 | ||
516 | if (!pm_runtime_suspended(dev)) | |
517 | return 0; | |
518 | ||
519 | drm_modeset_lock_all(drm); | |
520 | list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) | |
521 | hdlcd_crtc_resume(crtc); | |
522 | drm_modeset_unlock_all(drm); | |
523 | return 0; | |
524 | } | |
525 | ||
526 | static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume); | |
527 | ||
528 | static struct platform_driver hdlcd_platform_driver = { | |
529 | .probe = hdlcd_probe, | |
530 | .remove = hdlcd_remove, | |
531 | .driver = { | |
532 | .name = "hdlcd", | |
533 | .pm = &hdlcd_pm_ops, | |
534 | .of_match_table = hdlcd_of_match, | |
535 | }, | |
536 | }; | |
537 | ||
538 | module_platform_driver(hdlcd_platform_driver); | |
539 | ||
540 | MODULE_AUTHOR("Liviu Dudau"); | |
541 | MODULE_DESCRIPTION("ARM HDLCD DRM driver"); | |
542 | MODULE_LICENSE("GPL v2"); |