[linux-block.git] / drivers / gpu / drm / arm / hdlcd_crtc.c

/*
 * Copyright (C) 2013-2015 ARM Limited
 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 *
 *  Implementation of a CRTC class for the HDLCD driver.
 */

#include <linux/clk.h>
#include <linux/of_graph.h>
#include <linux/platform_data/simplefb.h>

#include <video/videomode.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_fb_dma_helper.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>

#include "hdlcd_drv.h"
#include "hdlcd_regs.h"

/*
 * The HDLCD controller is a dumb RGB streamer that gets connected to
 * a single HDMI transmitter or in the case of the ARM Models it gets
 * emulated by the software that does the actual rendering.
 *
 */

static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);

	/* stop the controller on cleanup */
	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
	drm_crtc_cleanup(crtc);
}

static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);

	return 0;
}

static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
}

static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
	.destroy = hdlcd_crtc_cleanup,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	.enable_vblank = hdlcd_crtc_enable_vblank,
	.disable_vblank = hdlcd_crtc_disable_vblank,
};

static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;

/*
 * Setup the HDLCD registers for decoding the pixels out of the framebuffer
 */
static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
{
	unsigned int btpp;
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	const struct drm_framebuffer *fb = crtc->primary->state->fb;
	uint32_t pixel_format;
	struct simplefb_format *format = NULL;
	int i;

	pixel_format = fb->format->format;

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
		if (supported_formats[i].fourcc == pixel_format)
			format = &supported_formats[i];
	}

	if (WARN_ON(!format))
		return 0;

	/* HDLCD uses 'bytes per pixel', zero means 1 byte */
	btpp = (format->bits_per_pixel + 7) / 8;
	hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);

	/*
	 * The format of the HDLCD_REG_<color>_SELECT register is:
	 *   - bits[23:16] - default value for that color component
	 *   - bits[11:8]  - number of bits to extract for each color component
	 *   - bits[4:0]   - index of the lowest bit to extract
	 *
	 * The default color value is used when bits[11:8] are zero, when the
	 * pixel is outside the visible frame area or when there is a
	 * buffer underrun.
	 */
	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
#ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
		    0x00ff0000 |	/* show underruns in red */
#endif
		    ((format->red.length & 0xf) << 8));
	hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
		    ((format->green.length & 0xf) << 8));
	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
		    ((format->blue.length & 0xf) << 8));

	return 0;
}

static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	struct videomode vm;
	unsigned int polarities, err;

	vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
	vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
	vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
	vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
	vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
	vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;

	polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;

	if (m->flags & DRM_MODE_FLAG_PHSYNC)
		polarities |= HDLCD_POLARITY_HSYNC;
	if (m->flags & DRM_MODE_FLAG_PVSYNC)
		polarities |= HDLCD_POLARITY_VSYNC;

	/* Allow max number of outstanding requests and largest burst size */
	hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
		    HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);

	hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
	hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
	hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);

	err = hdlcd_set_pxl_fmt(crtc);
	if (err)
		return;

	clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
}

static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
				     struct drm_atomic_state *state)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);

	clk_prepare_enable(hdlcd->clk);
	hdlcd_crtc_mode_set_nofb(crtc);
	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
	drm_crtc_vblank_on(crtc);
}

static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,
				      struct drm_atomic_state *state)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);

	drm_crtc_vblank_off(crtc);
	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
	clk_disable_unprepare(hdlcd->clk);
}

static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,
		const struct drm_display_mode *mode)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	long rate, clk_rate = mode->clock * 1000;

	rate = clk_round_rate(hdlcd->clk, clk_rate);
	/* 0.1% seems a close enough tolerance for the TDA19988 on Juno */
	if (abs(rate - clk_rate) * 1000 > clk_rate) {
		/* clock required by mode not supported by hardware */
		return MODE_NOCLOCK;
	}

	return MODE_OK;
}

static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
				    struct drm_atomic_state *state)
{
	struct drm_pending_vblank_event *event = crtc->state->event;

	if (event) {
		crtc->state->event = NULL;

		spin_lock_irq(&crtc->dev->event_lock);
		if (drm_crtc_vblank_get(crtc) == 0)
			drm_crtc_arm_vblank_event(crtc, event);
		else
			drm_crtc_send_vblank_event(crtc, event);
		spin_unlock_irq(&crtc->dev->event_lock);
	}
}

static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
	.mode_valid	= hdlcd_crtc_mode_valid,
	.atomic_begin	= hdlcd_crtc_atomic_begin,
	.atomic_enable	= hdlcd_crtc_atomic_enable,
	.atomic_disable	= hdlcd_crtc_atomic_disable,
};

static int hdlcd_plane_atomic_check(struct drm_plane *plane,
				    struct drm_atomic_state *state)
{
	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
										 plane);
	int i;
	struct drm_crtc *crtc;
	struct drm_crtc_state *crtc_state;
	u32 src_h = new_plane_state->src_h >> 16;

	/* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
	if (src_h >= HDLCD_MAX_YRES) {
		DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
		return -EINVAL;
	}

	for_each_new_crtc_in_state(state, crtc, crtc_state,
				   i) {
		/* we cannot disable the plane while the CRTC is active */
		if (!new_plane_state->fb && crtc_state->active)
			return -EINVAL;
		return drm_atomic_helper_check_plane_state(new_plane_state,
							   crtc_state,
							   DRM_PLANE_NO_SCALING,
							   DRM_PLANE_NO_SCALING,
							   false, true);
	}

	return 0;
}

static void hdlcd_plane_atomic_update(struct drm_plane *plane,
				      struct drm_atomic_state *state)
{
	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
										 plane);
	struct drm_framebuffer *fb = new_plane_state->fb;
	struct hdlcd_drm_private *hdlcd;
	u32 dest_h;
	dma_addr_t scanout_start;

	if (!fb)
		return;

	dest_h = drm_rect_height(&new_plane_state->dst);
	scanout_start = drm_fb_dma_get_gem_addr(fb, new_plane_state, 0);

	hdlcd = drm_to_hdlcd_priv(plane->dev);
	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
	hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
}

static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
	.atomic_check = hdlcd_plane_atomic_check,
	.atomic_update = hdlcd_plane_atomic_update,
};

static const struct drm_plane_funcs hdlcd_plane_funcs = {
	.update_plane		= drm_atomic_helper_update_plane,
	.disable_plane		= drm_atomic_helper_disable_plane,
	.reset			= drm_atomic_helper_plane_reset,
	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
};

static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
	struct drm_plane *plane = NULL;
	u32 formats[ARRAY_SIZE(supported_formats)], i;

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
		formats[i] = supported_formats[i].fourcc;

	plane = drmm_universal_plane_alloc(drm, struct drm_plane, dev, 0xff,
					   &hdlcd_plane_funcs,
					   formats, ARRAY_SIZE(formats),
					   NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
	if (IS_ERR(plane))
		return plane;

	drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
	hdlcd->plane = plane;

	return plane;
}

int hdlcd_setup_crtc(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
	struct drm_plane *primary;
	int ret;

	primary = hdlcd_plane_init(drm);
	if (IS_ERR(primary))
		return PTR_ERR(primary);

	ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
					&hdlcd_crtc_funcs, NULL);
	if (ret)
		return ret;

	drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
	return 0;
}
Commit	Line	Data
8e22d792 LD	1	/*
	2	* Copyright (C) 2013-2015 ARM Limited
	3	* Author: Liviu Dudau <Liviu.Dudau@arm.com>
	4	*
	5	* This file is subject to the terms and conditions of the GNU General Public
	6	* License. See the file COPYING in the main directory of this archive
	7	* for more details.
	8	*
	9	* Implementation of a CRTC class for the HDLCD driver.
	10	*/
	11
535d1b94 SR	12	#include <linux/clk.h>
	13	#include <linux/of_graph.h>
	14	#include <linux/platform_data/simplefb.h>
	15
	16	#include <video/videomode.h>
	17
1de3cd4f	18	#include <drm/drm_atomic.h>
8e22d792 LD	19	#include <drm/drm_atomic_helper.h>
8e22d792 LD	20	#include <drm/drm_crtc.h>
6bcfe8ea	21	#include <drm/drm_fb_dma_helper.h>
720cf96d	22	#include <drm/drm_framebuffer.h>
4a83c26a	23	#include <drm/drm_gem_dma_helper.h>
8e22d792	24	#include <drm/drm_of.h>
fcd70cd3	25	#include <drm/drm_probe_helper.h>
535d1b94	26	#include <drm/drm_vblank.h>
8e22d792 LD	27
	28	#include "hdlcd_drv.h"
	29	#include "hdlcd_regs.h"
	30
	31	/*
	32	* The HDLCD controller is a dumb RGB streamer that gets connected to
	33	* a single HDMI transmitter or in the case of the ARM Models it gets
	34	* emulated by the software that does the actual rendering.
	35	*
	36	*/
	37
a95acec1 LD	38	static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
	39	{
	40	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	41
	42	/* stop the controller on cleanup */
	43	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
	44	drm_crtc_cleanup(crtc);
	45	}
	46
1fe25980 SG	47	static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
	48	{
	49	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	50	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	51
	52	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask \| HDLCD_INTERRUPT_VSYNC);
	53
	54	return 0;
	55	}
	56
	57	static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
	58	{
	59	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	60	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	61
	62	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
	63	}
	64
8e22d792	65	static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
a95acec1	66	.destroy = hdlcd_crtc_cleanup,
8e22d792 LD	67	.set_config = drm_atomic_helper_set_config,
	68	.page_flip = drm_atomic_helper_page_flip,
	69	.reset = drm_atomic_helper_crtc_reset,
	70	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	71	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1fe25980 SG	72	.enable_vblank = hdlcd_crtc_enable_vblank,
1fe25980 SG	73	.disable_vblank = hdlcd_crtc_disable_vblank,
8e22d792 LD	74	};
	75
	76	static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;
	77
	78	/*
	79	* Setup the HDLCD registers for decoding the pixels out of the framebuffer
	80	*/
	81	static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
	82	{
	83	unsigned int btpp;
	84	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
59477fa9	85	const struct drm_framebuffer *fb = crtc->primary->state->fb;
8e22d792 LD	86	uint32_t pixel_format;
	87	struct simplefb_format *format = NULL;
	88	int i;
	89
438b74a5	90	pixel_format = fb->format->format;
8e22d792 LD	91
	92	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
	93	if (supported_formats[i].fourcc == pixel_format)
	94	format = &supported_formats[i];
	95	}
	96
	97	if (WARN_ON(!format))
	98	return 0;
	99
	100	/* HDLCD uses 'bytes per pixel', zero means 1 byte */
	101	btpp = (format->bits_per_pixel + 7) / 8;
	102	hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
	103
	104	/*
	105	* The format of the HDLCD_REG_<color>_SELECT register is:
	106	* - bits[23:16] - default value for that color component
	107	* - bits[11:8] - number of bits to extract for each color component
	108	* - bits[4:0] - index of the lowest bit to extract
	109	*
	110	* The default color value is used when bits[11:8] are zero, when the
	111	* pixel is outside the visible frame area or when there is a
	112	* buffer underrun.
	113	*/
	114	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset \|
	115	#ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
	116	0x00ff0000 \| /* show underruns in red */
	117	#endif
	118	((format->red.length & 0xf) << 8));
	119	hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset \|
	120	((format->green.length & 0xf) << 8));
	121	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset \|
	122	((format->blue.length & 0xf) << 8));
	123
	124	return 0;
	125	}
	126
	127	static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
	128	{
	129	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	130	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	131	struct videomode vm;
96ebb1f3	132	unsigned int polarities, err;
8e22d792 LD	133
	134	vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
	135	vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
	136	vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
	137	vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
	138	vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
	139	vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
	140
	141	polarities = HDLCD_POLARITY_DATAEN \| HDLCD_POLARITY_DATA;
	142
	143	if (m->flags & DRM_MODE_FLAG_PHSYNC)
	144	polarities \|= HDLCD_POLARITY_HSYNC;
	145	if (m->flags & DRM_MODE_FLAG_PVSYNC)
	146	polarities \|= HDLCD_POLARITY_VSYNC;
	147
8e22d792 LD	148	/* Allow max number of outstanding requests and largest burst size */
	149	hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
	150	HDLCD_BUS_MAX_OUTSTAND \| HDLCD_BUS_BURST_16);
	151
8e22d792 LD	152	hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
	153	hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
	154	hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
	155	hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
96ebb1f3	156	hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
8e22d792 LD	157	hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
	158	hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
	159	hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
8e22d792 LD	160	hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
	161
	162	err = hdlcd_set_pxl_fmt(crtc);
	163	if (err)
	164	return;
	165
	166	clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
	167	}
	168
0b20a0f8	169	static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
351f950d	170	struct drm_atomic_state *state)
8e22d792 LD	171	{
	172	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	173
	174	clk_prepare_enable(hdlcd->clk);
96ebb1f3	175	hdlcd_crtc_mode_set_nofb(crtc);
8e22d792	176	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
7a79279e	177	drm_crtc_vblank_on(crtc);
8e22d792 LD	178	}
8e22d792 LD	179
64581714	180	static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,
351f950d	181	struct drm_atomic_state *state)
8e22d792 LD	182	{
	183	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	184
7a79279e	185	drm_crtc_vblank_off(crtc);
8e22d792	186	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
a95acec1	187	clk_disable_unprepare(hdlcd->clk);
8e22d792 LD	188	}
8e22d792 LD	189
b96151ed RM	190	static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,
b96151ed RM	191	const struct drm_display_mode *mode)
8e22d792 LD	192	{
8e22d792 LD	193	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
8e22d792 LD	194	long rate, clk_rate = mode->clock * 1000;
	195
	196	rate = clk_round_rate(hdlcd->clk, clk_rate);
1c810739 RM	197	/* 0.1% seems a close enough tolerance for the TDA19988 on Juno */
1c810739 RM	198	if (abs(rate - clk_rate) * 1000 > clk_rate) {
8e22d792	199	/* clock required by mode not supported by hardware */
b96151ed	200	return MODE_NOCLOCK;
8e22d792 LD	201	}
8e22d792 LD	202
b96151ed	203	return MODE_OK;
8e22d792 LD	204	}
	205
	206	static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
f6ebe9f9	207	struct drm_atomic_state *state)
8e22d792	208	{
38c8c22c	209	struct drm_pending_vblank_event *event = crtc->state->event;
8e22d792	210
38c8c22c	211	if (event) {
8e22d792	212	crtc->state->event = NULL;
8e22d792	213
38c8c22c DV	214	spin_lock_irq(&crtc->dev->event_lock);
	215	if (drm_crtc_vblank_get(crtc) == 0)
	216	drm_crtc_arm_vblank_event(crtc, event);
	217	else
	218	drm_crtc_send_vblank_event(crtc, event);
	219	spin_unlock_irq(&crtc->dev->event_lock);
8e22d792 LD	220	}
	221	}
	222
8e22d792	223	static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
b96151ed	224	.mode_valid = hdlcd_crtc_mode_valid,
8e22d792	225	.atomic_begin = hdlcd_crtc_atomic_begin,
0b20a0f8	226	.atomic_enable = hdlcd_crtc_atomic_enable,
64581714	227	.atomic_disable = hdlcd_crtc_atomic_disable,
8e22d792 LD	228	};
	229
	230	static int hdlcd_plane_atomic_check(struct drm_plane *plane,
7c11b99a	231	struct drm_atomic_state *state)
8e22d792	232	{
7c11b99a MR	233	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
7c11b99a MR	234	plane);
d664b851 LD	235	int i;
d664b851 LD	236	struct drm_crtc *crtc;
1de3cd4f	237	struct drm_crtc_state *crtc_state;
ba5c1649	238	u32 src_h = new_plane_state->src_h >> 16;
96ebb1f3	239
1de3cd4f LD	240	/* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
	241	if (src_h >= HDLCD_MAX_YRES) {
	242	DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
	243	return -EINVAL;
	244	}
	245
dec92020	246	for_each_new_crtc_in_state(state, crtc, crtc_state,
ba5c1649	247	i) {
d664b851	248	/* we cannot disable the plane while the CRTC is active */
ba5c1649	249	if (!new_plane_state->fb && crtc_state->active)
d664b851	250	return -EINVAL;
ba5c1649 MR	251	return drm_atomic_helper_check_plane_state(new_plane_state,
ba5c1649 MR	252	crtc_state,
cce32e4e TZ	253	DRM_PLANE_NO_SCALING,
cce32e4e TZ	254	DRM_PLANE_NO_SCALING,
ba5c1649	255	false, true);
1de3cd4f	256	}
96ebb1f3	257
d664b851	258	return 0;
8e22d792 LD	259	}
	260
	261	static void hdlcd_plane_atomic_update(struct drm_plane *plane,
977697e2	262	struct drm_atomic_state *state)
8e22d792	263	{
37418bf1 MR	264	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
37418bf1 MR	265	plane);
e05162c0	266	struct drm_framebuffer *fb = new_plane_state->fb;
8e22d792	267	struct hdlcd_drm_private *hdlcd;
fee4964f	268	u32 dest_h;
8e22d792 LD	269	dma_addr_t scanout_start;
8e22d792 LD	270
59477fa9	271	if (!fb)
8e22d792 LD	272	return;
8e22d792 LD	273
e05162c0	274	dest_h = drm_rect_height(&new_plane_state->dst);
6bcfe8ea	275	scanout_start = drm_fb_dma_get_gem_addr(fb, new_plane_state, 0);
96ebb1f3	276
5f56e596	277	hdlcd = drm_to_hdlcd_priv(plane->dev);
59477fa9 VS	278	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
59477fa9 VS	279	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
96ebb1f3	280	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
8e22d792 LD	281	hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
	282	}
	283
	284	static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
8e22d792 LD	285	.atomic_check = hdlcd_plane_atomic_check,
	286	.atomic_update = hdlcd_plane_atomic_update,
	287	};
	288
8e22d792 LD	289	static const struct drm_plane_funcs hdlcd_plane_funcs = {
	290	.update_plane = drm_atomic_helper_update_plane,
	291	.disable_plane = drm_atomic_helper_disable_plane,
8e22d792 LD	292	.reset = drm_atomic_helper_plane_reset,
	293	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	294	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
	295	};
	296
	297	static struct drm_plane hdlcd_plane_init(struct drm_device drm)
	298	{
5f56e596	299	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
8e22d792 LD	300	struct drm_plane *plane = NULL;
8e22d792 LD	301	u32 formats[ARRAY_SIZE(supported_formats)], i;
8e22d792 LD	302
	303	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
	304	formats[i] = supported_formats[i].fourcc;
	305
8aa20195 DK	306	plane = drmm_universal_plane_alloc(drm, struct drm_plane, dev, 0xff,
	307	&hdlcd_plane_funcs,
	308	formats, ARRAY_SIZE(formats),
	309	NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
	310	if (IS_ERR(plane))
	311	return plane;
8e22d792 LD	312
	313	drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
	314	hdlcd->plane = plane;
	315
	316	return plane;
	317	}
	318
8e22d792 LD	319	int hdlcd_setup_crtc(struct drm_device *drm)
8e22d792 LD	320	{
5f56e596	321	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
8e22d792 LD	322	struct drm_plane *primary;
	323	int ret;
	324
	325	primary = hdlcd_plane_init(drm);
	326	if (IS_ERR(primary))
	327	return PTR_ERR(primary);
	328
	329	ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
	330	&hdlcd_crtc_funcs, NULL);
8df24d57	331	if (ret)
8e22d792	332	return ret;
8e22d792 LD	333
	334	drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
	335	return 0;
	336	}