Commit | Line | Data |
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8e22d792 LD |
1 | /* |
2 | * Copyright (C) 2013-2015 ARM Limited | |
3 | * Author: Liviu Dudau <Liviu.Dudau@arm.com> | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file COPYING in the main directory of this archive | |
7 | * for more details. | |
8 | * | |
9 | * Implementation of a CRTC class for the HDLCD driver. | |
10 | */ | |
11 | ||
12 | #include <drm/drmP.h> | |
1de3cd4f | 13 | #include <drm/drm_atomic.h> |
8e22d792 LD |
14 | #include <drm/drm_atomic_helper.h> |
15 | #include <drm/drm_crtc.h> | |
16 | #include <drm/drm_crtc_helper.h> | |
17 | #include <drm/drm_fb_helper.h> | |
18 | #include <drm/drm_fb_cma_helper.h> | |
19 | #include <drm/drm_gem_cma_helper.h> | |
20 | #include <drm/drm_of.h> | |
21 | #include <drm/drm_plane_helper.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/of_graph.h> | |
24 | #include <linux/platform_data/simplefb.h> | |
25 | #include <video/videomode.h> | |
26 | ||
27 | #include "hdlcd_drv.h" | |
28 | #include "hdlcd_regs.h" | |
29 | ||
30 | /* | |
31 | * The HDLCD controller is a dumb RGB streamer that gets connected to | |
32 | * a single HDMI transmitter or in the case of the ARM Models it gets | |
33 | * emulated by the software that does the actual rendering. | |
34 | * | |
35 | */ | |
36 | ||
a95acec1 LD |
37 | static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) |
38 | { | |
39 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
40 | ||
41 | /* stop the controller on cleanup */ | |
42 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); | |
43 | drm_crtc_cleanup(crtc); | |
44 | } | |
45 | ||
1fe25980 SG |
46 | static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc) |
47 | { | |
48 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
49 | unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); | |
50 | ||
51 | hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); | |
52 | ||
53 | return 0; | |
54 | } | |
55 | ||
56 | static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc) | |
57 | { | |
58 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
59 | unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); | |
60 | ||
61 | hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); | |
62 | } | |
63 | ||
8e22d792 | 64 | static const struct drm_crtc_funcs hdlcd_crtc_funcs = { |
a95acec1 | 65 | .destroy = hdlcd_crtc_cleanup, |
8e22d792 LD |
66 | .set_config = drm_atomic_helper_set_config, |
67 | .page_flip = drm_atomic_helper_page_flip, | |
68 | .reset = drm_atomic_helper_crtc_reset, | |
69 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
70 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
1fe25980 SG |
71 | .enable_vblank = hdlcd_crtc_enable_vblank, |
72 | .disable_vblank = hdlcd_crtc_disable_vblank, | |
8e22d792 LD |
73 | }; |
74 | ||
75 | static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS; | |
76 | ||
77 | /* | |
78 | * Setup the HDLCD registers for decoding the pixels out of the framebuffer | |
79 | */ | |
80 | static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) | |
81 | { | |
82 | unsigned int btpp; | |
83 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
59477fa9 | 84 | const struct drm_framebuffer *fb = crtc->primary->state->fb; |
8e22d792 LD |
85 | uint32_t pixel_format; |
86 | struct simplefb_format *format = NULL; | |
87 | int i; | |
88 | ||
438b74a5 | 89 | pixel_format = fb->format->format; |
8e22d792 LD |
90 | |
91 | for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { | |
92 | if (supported_formats[i].fourcc == pixel_format) | |
93 | format = &supported_formats[i]; | |
94 | } | |
95 | ||
96 | if (WARN_ON(!format)) | |
97 | return 0; | |
98 | ||
99 | /* HDLCD uses 'bytes per pixel', zero means 1 byte */ | |
100 | btpp = (format->bits_per_pixel + 7) / 8; | |
101 | hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3); | |
102 | ||
103 | /* | |
104 | * The format of the HDLCD_REG_<color>_SELECT register is: | |
105 | * - bits[23:16] - default value for that color component | |
106 | * - bits[11:8] - number of bits to extract for each color component | |
107 | * - bits[4:0] - index of the lowest bit to extract | |
108 | * | |
109 | * The default color value is used when bits[11:8] are zero, when the | |
110 | * pixel is outside the visible frame area or when there is a | |
111 | * buffer underrun. | |
112 | */ | |
113 | hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset | | |
114 | #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN | |
115 | 0x00ff0000 | /* show underruns in red */ | |
116 | #endif | |
117 | ((format->red.length & 0xf) << 8)); | |
118 | hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset | | |
119 | ((format->green.length & 0xf) << 8)); | |
120 | hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset | | |
121 | ((format->blue.length & 0xf) << 8)); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
127 | { | |
128 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
129 | struct drm_display_mode *m = &crtc->state->adjusted_mode; | |
130 | struct videomode vm; | |
96ebb1f3 | 131 | unsigned int polarities, err; |
8e22d792 LD |
132 | |
133 | vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; | |
134 | vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; | |
135 | vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; | |
136 | vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; | |
137 | vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; | |
138 | vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; | |
139 | ||
140 | polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; | |
141 | ||
142 | if (m->flags & DRM_MODE_FLAG_PHSYNC) | |
143 | polarities |= HDLCD_POLARITY_HSYNC; | |
144 | if (m->flags & DRM_MODE_FLAG_PVSYNC) | |
145 | polarities |= HDLCD_POLARITY_VSYNC; | |
146 | ||
8e22d792 LD |
147 | /* Allow max number of outstanding requests and largest burst size */ |
148 | hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS, | |
149 | HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16); | |
150 | ||
8e22d792 LD |
151 | hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1); |
152 | hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1); | |
153 | hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1); | |
154 | hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1); | |
96ebb1f3 | 155 | hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1); |
8e22d792 LD |
156 | hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1); |
157 | hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1); | |
158 | hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); | |
8e22d792 LD |
159 | hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); |
160 | ||
161 | err = hdlcd_set_pxl_fmt(crtc); | |
162 | if (err) | |
163 | return; | |
164 | ||
165 | clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); | |
166 | } | |
167 | ||
0b20a0f8 LP |
168 | static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, |
169 | struct drm_crtc_state *old_state) | |
8e22d792 LD |
170 | { |
171 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
172 | ||
173 | clk_prepare_enable(hdlcd->clk); | |
96ebb1f3 | 174 | hdlcd_crtc_mode_set_nofb(crtc); |
8e22d792 | 175 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); |
7a79279e | 176 | drm_crtc_vblank_on(crtc); |
8e22d792 LD |
177 | } |
178 | ||
64581714 LP |
179 | static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, |
180 | struct drm_crtc_state *old_state) | |
8e22d792 LD |
181 | { |
182 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
183 | ||
7a79279e | 184 | drm_crtc_vblank_off(crtc); |
8e22d792 | 185 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); |
a95acec1 | 186 | clk_disable_unprepare(hdlcd->clk); |
8e22d792 LD |
187 | } |
188 | ||
189 | static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc, | |
190 | struct drm_crtc_state *state) | |
191 | { | |
192 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
193 | struct drm_display_mode *mode = &state->adjusted_mode; | |
194 | long rate, clk_rate = mode->clock * 1000; | |
195 | ||
196 | rate = clk_round_rate(hdlcd->clk, clk_rate); | |
197 | if (rate != clk_rate) { | |
198 | /* clock required by mode not supported by hardware */ | |
199 | return -EINVAL; | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, | |
206 | struct drm_crtc_state *state) | |
207 | { | |
38c8c22c | 208 | struct drm_pending_vblank_event *event = crtc->state->event; |
8e22d792 | 209 | |
38c8c22c | 210 | if (event) { |
8e22d792 | 211 | crtc->state->event = NULL; |
8e22d792 | 212 | |
38c8c22c DV |
213 | spin_lock_irq(&crtc->dev->event_lock); |
214 | if (drm_crtc_vblank_get(crtc) == 0) | |
215 | drm_crtc_arm_vblank_event(crtc, event); | |
216 | else | |
217 | drm_crtc_send_vblank_event(crtc, event); | |
218 | spin_unlock_irq(&crtc->dev->event_lock); | |
8e22d792 LD |
219 | } |
220 | } | |
221 | ||
8e22d792 | 222 | static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { |
8e22d792 LD |
223 | .atomic_check = hdlcd_crtc_atomic_check, |
224 | .atomic_begin = hdlcd_crtc_atomic_begin, | |
0b20a0f8 | 225 | .atomic_enable = hdlcd_crtc_atomic_enable, |
64581714 | 226 | .atomic_disable = hdlcd_crtc_atomic_disable, |
8e22d792 LD |
227 | }; |
228 | ||
229 | static int hdlcd_plane_atomic_check(struct drm_plane *plane, | |
230 | struct drm_plane_state *state) | |
231 | { | |
1de3cd4f LD |
232 | struct drm_rect clip = { 0 }; |
233 | struct drm_crtc_state *crtc_state; | |
234 | u32 src_h = state->src_h >> 16; | |
96ebb1f3 | 235 | |
1de3cd4f LD |
236 | /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */ |
237 | if (src_h >= HDLCD_MAX_YRES) { | |
238 | DRM_DEBUG_KMS("Invalid source width: %d\n", src_h); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | if (!state->fb || !state->crtc) | |
243 | return 0; | |
96ebb1f3 | 244 | |
1de3cd4f LD |
245 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, |
246 | state->crtc); | |
247 | if (!crtc_state) { | |
248 | DRM_DEBUG_KMS("Invalid crtc state\n"); | |
96ebb1f3 | 249 | return -EINVAL; |
1de3cd4f | 250 | } |
96ebb1f3 | 251 | |
1de3cd4f LD |
252 | clip.x2 = crtc_state->adjusted_mode.hdisplay; |
253 | clip.y2 = crtc_state->adjusted_mode.vdisplay; | |
254 | ||
255 | return drm_plane_helper_check_state(state, &clip, | |
256 | DRM_PLANE_HELPER_NO_SCALING, | |
257 | DRM_PLANE_HELPER_NO_SCALING, | |
258 | false, true); | |
8e22d792 LD |
259 | } |
260 | ||
261 | static void hdlcd_plane_atomic_update(struct drm_plane *plane, | |
262 | struct drm_plane_state *state) | |
263 | { | |
59477fa9 | 264 | struct drm_framebuffer *fb = plane->state->fb; |
8e22d792 | 265 | struct hdlcd_drm_private *hdlcd; |
fee4964f | 266 | u32 dest_h; |
8e22d792 LD |
267 | dma_addr_t scanout_start; |
268 | ||
59477fa9 | 269 | if (!fb) |
8e22d792 LD |
270 | return; |
271 | ||
1de3cd4f | 272 | dest_h = drm_rect_height(&plane->state->dst); |
49a58f26 | 273 | scanout_start = drm_fb_cma_get_gem_addr(fb, plane->state, 0); |
96ebb1f3 LD |
274 | |
275 | hdlcd = plane->dev->dev_private; | |
59477fa9 VS |
276 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]); |
277 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]); | |
96ebb1f3 | 278 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); |
8e22d792 LD |
279 | hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); |
280 | } | |
281 | ||
282 | static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { | |
8e22d792 LD |
283 | .atomic_check = hdlcd_plane_atomic_check, |
284 | .atomic_update = hdlcd_plane_atomic_update, | |
285 | }; | |
286 | ||
287 | static void hdlcd_plane_destroy(struct drm_plane *plane) | |
288 | { | |
289 | drm_plane_helper_disable(plane); | |
290 | drm_plane_cleanup(plane); | |
291 | } | |
292 | ||
293 | static const struct drm_plane_funcs hdlcd_plane_funcs = { | |
294 | .update_plane = drm_atomic_helper_update_plane, | |
295 | .disable_plane = drm_atomic_helper_disable_plane, | |
296 | .destroy = hdlcd_plane_destroy, | |
297 | .reset = drm_atomic_helper_plane_reset, | |
298 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
299 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
300 | }; | |
301 | ||
302 | static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) | |
303 | { | |
304 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
305 | struct drm_plane *plane = NULL; | |
306 | u32 formats[ARRAY_SIZE(supported_formats)], i; | |
307 | int ret; | |
308 | ||
309 | plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); | |
310 | if (!plane) | |
311 | return ERR_PTR(-ENOMEM); | |
312 | ||
313 | for (i = 0; i < ARRAY_SIZE(supported_formats); i++) | |
314 | formats[i] = supported_formats[i].fourcc; | |
315 | ||
316 | ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs, | |
317 | formats, ARRAY_SIZE(formats), | |
318 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
319 | if (ret) { | |
8e22d792 LD |
320 | return ERR_PTR(ret); |
321 | } | |
322 | ||
323 | drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs); | |
324 | hdlcd->plane = plane; | |
325 | ||
326 | return plane; | |
327 | } | |
328 | ||
8e22d792 LD |
329 | int hdlcd_setup_crtc(struct drm_device *drm) |
330 | { | |
331 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
332 | struct drm_plane *primary; | |
333 | int ret; | |
334 | ||
335 | primary = hdlcd_plane_init(drm); | |
336 | if (IS_ERR(primary)) | |
337 | return PTR_ERR(primary); | |
338 | ||
339 | ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, | |
340 | &hdlcd_crtc_funcs, NULL); | |
341 | if (ret) { | |
342 | hdlcd_plane_destroy(primary); | |
8e22d792 LD |
343 | return ret; |
344 | } | |
345 | ||
346 | drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs); | |
347 | return 0; | |
348 | } |