Commit | Line | Data |
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8e22d792 LD |
1 | /* |
2 | * Copyright (C) 2013-2015 ARM Limited | |
3 | * Author: Liviu Dudau <Liviu.Dudau@arm.com> | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file COPYING in the main directory of this archive | |
7 | * for more details. | |
8 | * | |
9 | * Implementation of a CRTC class for the HDLCD driver. | |
10 | */ | |
11 | ||
12 | #include <drm/drmP.h> | |
13 | #include <drm/drm_atomic_helper.h> | |
14 | #include <drm/drm_crtc.h> | |
15 | #include <drm/drm_crtc_helper.h> | |
16 | #include <drm/drm_fb_helper.h> | |
17 | #include <drm/drm_fb_cma_helper.h> | |
18 | #include <drm/drm_gem_cma_helper.h> | |
19 | #include <drm/drm_of.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/of_graph.h> | |
23 | #include <linux/platform_data/simplefb.h> | |
24 | #include <video/videomode.h> | |
25 | ||
26 | #include "hdlcd_drv.h" | |
27 | #include "hdlcd_regs.h" | |
28 | ||
29 | /* | |
30 | * The HDLCD controller is a dumb RGB streamer that gets connected to | |
31 | * a single HDMI transmitter or in the case of the ARM Models it gets | |
32 | * emulated by the software that does the actual rendering. | |
33 | * | |
34 | */ | |
35 | ||
a95acec1 LD |
36 | static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) |
37 | { | |
38 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
39 | ||
40 | /* stop the controller on cleanup */ | |
41 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); | |
42 | drm_crtc_cleanup(crtc); | |
43 | } | |
44 | ||
8e22d792 | 45 | static const struct drm_crtc_funcs hdlcd_crtc_funcs = { |
a95acec1 | 46 | .destroy = hdlcd_crtc_cleanup, |
8e22d792 LD |
47 | .set_config = drm_atomic_helper_set_config, |
48 | .page_flip = drm_atomic_helper_page_flip, | |
49 | .reset = drm_atomic_helper_crtc_reset, | |
50 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
51 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
52 | }; | |
53 | ||
54 | static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS; | |
55 | ||
56 | /* | |
57 | * Setup the HDLCD registers for decoding the pixels out of the framebuffer | |
58 | */ | |
59 | static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) | |
60 | { | |
61 | unsigned int btpp; | |
62 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
59477fa9 | 63 | const struct drm_framebuffer *fb = crtc->primary->state->fb; |
8e22d792 LD |
64 | uint32_t pixel_format; |
65 | struct simplefb_format *format = NULL; | |
66 | int i; | |
67 | ||
438b74a5 | 68 | pixel_format = fb->format->format; |
8e22d792 LD |
69 | |
70 | for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { | |
71 | if (supported_formats[i].fourcc == pixel_format) | |
72 | format = &supported_formats[i]; | |
73 | } | |
74 | ||
75 | if (WARN_ON(!format)) | |
76 | return 0; | |
77 | ||
78 | /* HDLCD uses 'bytes per pixel', zero means 1 byte */ | |
79 | btpp = (format->bits_per_pixel + 7) / 8; | |
80 | hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3); | |
81 | ||
82 | /* | |
83 | * The format of the HDLCD_REG_<color>_SELECT register is: | |
84 | * - bits[23:16] - default value for that color component | |
85 | * - bits[11:8] - number of bits to extract for each color component | |
86 | * - bits[4:0] - index of the lowest bit to extract | |
87 | * | |
88 | * The default color value is used when bits[11:8] are zero, when the | |
89 | * pixel is outside the visible frame area or when there is a | |
90 | * buffer underrun. | |
91 | */ | |
92 | hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset | | |
93 | #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN | |
94 | 0x00ff0000 | /* show underruns in red */ | |
95 | #endif | |
96 | ((format->red.length & 0xf) << 8)); | |
97 | hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset | | |
98 | ((format->green.length & 0xf) << 8)); | |
99 | hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset | | |
100 | ((format->blue.length & 0xf) << 8)); | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
106 | { | |
107 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
108 | struct drm_display_mode *m = &crtc->state->adjusted_mode; | |
109 | struct videomode vm; | |
96ebb1f3 | 110 | unsigned int polarities, err; |
8e22d792 LD |
111 | |
112 | vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; | |
113 | vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; | |
114 | vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; | |
115 | vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; | |
116 | vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; | |
117 | vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; | |
118 | ||
119 | polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; | |
120 | ||
121 | if (m->flags & DRM_MODE_FLAG_PHSYNC) | |
122 | polarities |= HDLCD_POLARITY_HSYNC; | |
123 | if (m->flags & DRM_MODE_FLAG_PVSYNC) | |
124 | polarities |= HDLCD_POLARITY_VSYNC; | |
125 | ||
8e22d792 LD |
126 | /* Allow max number of outstanding requests and largest burst size */ |
127 | hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS, | |
128 | HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16); | |
129 | ||
8e22d792 LD |
130 | hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1); |
131 | hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1); | |
132 | hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1); | |
133 | hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1); | |
96ebb1f3 | 134 | hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1); |
8e22d792 LD |
135 | hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1); |
136 | hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1); | |
137 | hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); | |
8e22d792 LD |
138 | hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); |
139 | ||
140 | err = hdlcd_set_pxl_fmt(crtc); | |
141 | if (err) | |
142 | return; | |
143 | ||
144 | clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); | |
145 | } | |
146 | ||
147 | static void hdlcd_crtc_enable(struct drm_crtc *crtc) | |
148 | { | |
149 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
150 | ||
151 | clk_prepare_enable(hdlcd->clk); | |
96ebb1f3 | 152 | hdlcd_crtc_mode_set_nofb(crtc); |
8e22d792 | 153 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); |
7a79279e | 154 | drm_crtc_vblank_on(crtc); |
8e22d792 LD |
155 | } |
156 | ||
157 | static void hdlcd_crtc_disable(struct drm_crtc *crtc) | |
158 | { | |
159 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
160 | ||
7a79279e | 161 | drm_crtc_vblank_off(crtc); |
8e22d792 | 162 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); |
a95acec1 | 163 | clk_disable_unprepare(hdlcd->clk); |
8e22d792 LD |
164 | } |
165 | ||
166 | static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc, | |
167 | struct drm_crtc_state *state) | |
168 | { | |
169 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
170 | struct drm_display_mode *mode = &state->adjusted_mode; | |
171 | long rate, clk_rate = mode->clock * 1000; | |
172 | ||
173 | rate = clk_round_rate(hdlcd->clk, clk_rate); | |
174 | if (rate != clk_rate) { | |
175 | /* clock required by mode not supported by hardware */ | |
176 | return -EINVAL; | |
177 | } | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, | |
183 | struct drm_crtc_state *state) | |
184 | { | |
38c8c22c | 185 | struct drm_pending_vblank_event *event = crtc->state->event; |
8e22d792 | 186 | |
38c8c22c | 187 | if (event) { |
8e22d792 | 188 | crtc->state->event = NULL; |
8e22d792 | 189 | |
38c8c22c DV |
190 | spin_lock_irq(&crtc->dev->event_lock); |
191 | if (drm_crtc_vblank_get(crtc) == 0) | |
192 | drm_crtc_arm_vblank_event(crtc, event); | |
193 | else | |
194 | drm_crtc_send_vblank_event(crtc, event); | |
195 | spin_unlock_irq(&crtc->dev->event_lock); | |
8e22d792 LD |
196 | } |
197 | } | |
198 | ||
8e22d792 | 199 | static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { |
8e22d792 LD |
200 | .enable = hdlcd_crtc_enable, |
201 | .disable = hdlcd_crtc_disable, | |
8e22d792 LD |
202 | .atomic_check = hdlcd_crtc_atomic_check, |
203 | .atomic_begin = hdlcd_crtc_atomic_begin, | |
8e22d792 LD |
204 | }; |
205 | ||
206 | static int hdlcd_plane_atomic_check(struct drm_plane *plane, | |
207 | struct drm_plane_state *state) | |
208 | { | |
96ebb1f3 LD |
209 | u32 src_w, src_h; |
210 | ||
211 | src_w = state->src_w >> 16; | |
212 | src_h = state->src_h >> 16; | |
213 | ||
214 | /* we can't do any scaling of the plane source */ | |
215 | if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) | |
216 | return -EINVAL; | |
217 | ||
8e22d792 LD |
218 | return 0; |
219 | } | |
220 | ||
221 | static void hdlcd_plane_atomic_update(struct drm_plane *plane, | |
222 | struct drm_plane_state *state) | |
223 | { | |
59477fa9 | 224 | struct drm_framebuffer *fb = plane->state->fb; |
8e22d792 LD |
225 | struct hdlcd_drm_private *hdlcd; |
226 | struct drm_gem_cma_object *gem; | |
96ebb1f3 | 227 | u32 src_w, src_h, dest_w, dest_h; |
8e22d792 LD |
228 | dma_addr_t scanout_start; |
229 | ||
59477fa9 | 230 | if (!fb) |
8e22d792 LD |
231 | return; |
232 | ||
96ebb1f3 LD |
233 | src_w = plane->state->src_w >> 16; |
234 | src_h = plane->state->src_h >> 16; | |
235 | dest_w = plane->state->crtc_w; | |
236 | dest_h = plane->state->crtc_h; | |
59477fa9 VS |
237 | gem = drm_fb_cma_get_gem_obj(fb, 0); |
238 | scanout_start = gem->paddr + fb->offsets[0] + | |
239 | plane->state->crtc_y * fb->pitches[0] + | |
ba0891d1 | 240 | plane->state->crtc_x * |
353c8598 | 241 | fb->format->cpp[0]; |
96ebb1f3 LD |
242 | |
243 | hdlcd = plane->dev->dev_private; | |
59477fa9 VS |
244 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]); |
245 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]); | |
96ebb1f3 | 246 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); |
8e22d792 LD |
247 | hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); |
248 | } | |
249 | ||
250 | static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { | |
8e22d792 LD |
251 | .atomic_check = hdlcd_plane_atomic_check, |
252 | .atomic_update = hdlcd_plane_atomic_update, | |
253 | }; | |
254 | ||
255 | static void hdlcd_plane_destroy(struct drm_plane *plane) | |
256 | { | |
257 | drm_plane_helper_disable(plane); | |
258 | drm_plane_cleanup(plane); | |
259 | } | |
260 | ||
261 | static const struct drm_plane_funcs hdlcd_plane_funcs = { | |
262 | .update_plane = drm_atomic_helper_update_plane, | |
263 | .disable_plane = drm_atomic_helper_disable_plane, | |
264 | .destroy = hdlcd_plane_destroy, | |
265 | .reset = drm_atomic_helper_plane_reset, | |
266 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
267 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
268 | }; | |
269 | ||
270 | static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) | |
271 | { | |
272 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
273 | struct drm_plane *plane = NULL; | |
274 | u32 formats[ARRAY_SIZE(supported_formats)], i; | |
275 | int ret; | |
276 | ||
277 | plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); | |
278 | if (!plane) | |
279 | return ERR_PTR(-ENOMEM); | |
280 | ||
281 | for (i = 0; i < ARRAY_SIZE(supported_formats); i++) | |
282 | formats[i] = supported_formats[i].fourcc; | |
283 | ||
284 | ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs, | |
285 | formats, ARRAY_SIZE(formats), | |
286 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
287 | if (ret) { | |
288 | devm_kfree(drm->dev, plane); | |
289 | return ERR_PTR(ret); | |
290 | } | |
291 | ||
292 | drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs); | |
293 | hdlcd->plane = plane; | |
294 | ||
295 | return plane; | |
296 | } | |
297 | ||
8e22d792 LD |
298 | int hdlcd_setup_crtc(struct drm_device *drm) |
299 | { | |
300 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
301 | struct drm_plane *primary; | |
302 | int ret; | |
303 | ||
304 | primary = hdlcd_plane_init(drm); | |
305 | if (IS_ERR(primary)) | |
306 | return PTR_ERR(primary); | |
307 | ||
308 | ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, | |
309 | &hdlcd_crtc_funcs, NULL); | |
310 | if (ret) { | |
311 | hdlcd_plane_destroy(primary); | |
312 | devm_kfree(drm->dev, primary); | |
313 | return ret; | |
314 | } | |
315 | ||
316 | drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs); | |
317 | return 0; | |
318 | } |