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8e22d792 LD |
1 | /* |
2 | * Copyright (C) 2013-2015 ARM Limited | |
3 | * Author: Liviu Dudau <Liviu.Dudau@arm.com> | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file COPYING in the main directory of this archive | |
7 | * for more details. | |
8 | * | |
9 | * Implementation of a CRTC class for the HDLCD driver. | |
10 | */ | |
11 | ||
12 | #include <drm/drmP.h> | |
13 | #include <drm/drm_atomic_helper.h> | |
14 | #include <drm/drm_crtc.h> | |
15 | #include <drm/drm_crtc_helper.h> | |
16 | #include <drm/drm_fb_helper.h> | |
17 | #include <drm/drm_fb_cma_helper.h> | |
18 | #include <drm/drm_gem_cma_helper.h> | |
19 | #include <drm/drm_of.h> | |
20 | #include <drm/drm_plane_helper.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/of_graph.h> | |
23 | #include <linux/platform_data/simplefb.h> | |
24 | #include <video/videomode.h> | |
25 | ||
26 | #include "hdlcd_drv.h" | |
27 | #include "hdlcd_regs.h" | |
28 | ||
29 | /* | |
30 | * The HDLCD controller is a dumb RGB streamer that gets connected to | |
31 | * a single HDMI transmitter or in the case of the ARM Models it gets | |
32 | * emulated by the software that does the actual rendering. | |
33 | * | |
34 | */ | |
35 | ||
a95acec1 LD |
36 | static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) |
37 | { | |
38 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
39 | ||
40 | /* stop the controller on cleanup */ | |
41 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); | |
42 | drm_crtc_cleanup(crtc); | |
43 | } | |
44 | ||
8e22d792 | 45 | static const struct drm_crtc_funcs hdlcd_crtc_funcs = { |
a95acec1 | 46 | .destroy = hdlcd_crtc_cleanup, |
8e22d792 LD |
47 | .set_config = drm_atomic_helper_set_config, |
48 | .page_flip = drm_atomic_helper_page_flip, | |
49 | .reset = drm_atomic_helper_crtc_reset, | |
50 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
51 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
52 | }; | |
53 | ||
54 | static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS; | |
55 | ||
56 | /* | |
57 | * Setup the HDLCD registers for decoding the pixels out of the framebuffer | |
58 | */ | |
59 | static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) | |
60 | { | |
61 | unsigned int btpp; | |
62 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
63 | uint32_t pixel_format; | |
64 | struct simplefb_format *format = NULL; | |
65 | int i; | |
66 | ||
67 | pixel_format = crtc->primary->state->fb->pixel_format; | |
68 | ||
69 | for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { | |
70 | if (supported_formats[i].fourcc == pixel_format) | |
71 | format = &supported_formats[i]; | |
72 | } | |
73 | ||
74 | if (WARN_ON(!format)) | |
75 | return 0; | |
76 | ||
77 | /* HDLCD uses 'bytes per pixel', zero means 1 byte */ | |
78 | btpp = (format->bits_per_pixel + 7) / 8; | |
79 | hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3); | |
80 | ||
81 | /* | |
82 | * The format of the HDLCD_REG_<color>_SELECT register is: | |
83 | * - bits[23:16] - default value for that color component | |
84 | * - bits[11:8] - number of bits to extract for each color component | |
85 | * - bits[4:0] - index of the lowest bit to extract | |
86 | * | |
87 | * The default color value is used when bits[11:8] are zero, when the | |
88 | * pixel is outside the visible frame area or when there is a | |
89 | * buffer underrun. | |
90 | */ | |
91 | hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset | | |
92 | #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN | |
93 | 0x00ff0000 | /* show underruns in red */ | |
94 | #endif | |
95 | ((format->red.length & 0xf) << 8)); | |
96 | hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset | | |
97 | ((format->green.length & 0xf) << 8)); | |
98 | hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset | | |
99 | ((format->blue.length & 0xf) << 8)); | |
100 | ||
101 | return 0; | |
102 | } | |
103 | ||
104 | static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
105 | { | |
106 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
107 | struct drm_display_mode *m = &crtc->state->adjusted_mode; | |
108 | struct videomode vm; | |
96ebb1f3 | 109 | unsigned int polarities, err; |
8e22d792 LD |
110 | |
111 | vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; | |
112 | vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; | |
113 | vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; | |
114 | vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; | |
115 | vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; | |
116 | vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; | |
117 | ||
118 | polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; | |
119 | ||
120 | if (m->flags & DRM_MODE_FLAG_PHSYNC) | |
121 | polarities |= HDLCD_POLARITY_HSYNC; | |
122 | if (m->flags & DRM_MODE_FLAG_PVSYNC) | |
123 | polarities |= HDLCD_POLARITY_VSYNC; | |
124 | ||
8e22d792 LD |
125 | /* Allow max number of outstanding requests and largest burst size */ |
126 | hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS, | |
127 | HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16); | |
128 | ||
8e22d792 LD |
129 | hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1); |
130 | hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1); | |
131 | hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1); | |
132 | hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1); | |
96ebb1f3 | 133 | hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1); |
8e22d792 LD |
134 | hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1); |
135 | hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1); | |
136 | hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); | |
8e22d792 LD |
137 | hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); |
138 | ||
139 | err = hdlcd_set_pxl_fmt(crtc); | |
140 | if (err) | |
141 | return; | |
142 | ||
143 | clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); | |
144 | } | |
145 | ||
146 | static void hdlcd_crtc_enable(struct drm_crtc *crtc) | |
147 | { | |
148 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
149 | ||
150 | clk_prepare_enable(hdlcd->clk); | |
96ebb1f3 | 151 | hdlcd_crtc_mode_set_nofb(crtc); |
8e22d792 | 152 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); |
8e22d792 LD |
153 | } |
154 | ||
155 | static void hdlcd_crtc_disable(struct drm_crtc *crtc) | |
156 | { | |
157 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
158 | ||
96ebb1f3 | 159 | if (!crtc->state->active) |
8e22d792 LD |
160 | return; |
161 | ||
8e22d792 | 162 | hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); |
a95acec1 | 163 | clk_disable_unprepare(hdlcd->clk); |
8e22d792 LD |
164 | } |
165 | ||
166 | static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc, | |
167 | struct drm_crtc_state *state) | |
168 | { | |
169 | struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); | |
170 | struct drm_display_mode *mode = &state->adjusted_mode; | |
171 | long rate, clk_rate = mode->clock * 1000; | |
172 | ||
173 | rate = clk_round_rate(hdlcd->clk, clk_rate); | |
174 | if (rate != clk_rate) { | |
175 | /* clock required by mode not supported by hardware */ | |
176 | return -EINVAL; | |
177 | } | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, | |
183 | struct drm_crtc_state *state) | |
184 | { | |
38c8c22c | 185 | struct drm_pending_vblank_event *event = crtc->state->event; |
8e22d792 | 186 | |
38c8c22c | 187 | if (event) { |
8e22d792 | 188 | crtc->state->event = NULL; |
8e22d792 | 189 | |
38c8c22c DV |
190 | spin_lock_irq(&crtc->dev->event_lock); |
191 | if (drm_crtc_vblank_get(crtc) == 0) | |
192 | drm_crtc_arm_vblank_event(crtc, event); | |
193 | else | |
194 | drm_crtc_send_vblank_event(crtc, event); | |
195 | spin_unlock_irq(&crtc->dev->event_lock); | |
8e22d792 LD |
196 | } |
197 | } | |
198 | ||
199 | static void hdlcd_crtc_atomic_flush(struct drm_crtc *crtc, | |
200 | struct drm_crtc_state *state) | |
201 | { | |
202 | } | |
203 | ||
204 | static bool hdlcd_crtc_mode_fixup(struct drm_crtc *crtc, | |
205 | const struct drm_display_mode *mode, | |
206 | struct drm_display_mode *adjusted_mode) | |
207 | { | |
208 | return true; | |
209 | } | |
210 | ||
211 | static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { | |
212 | .mode_fixup = hdlcd_crtc_mode_fixup, | |
213 | .mode_set = drm_helper_crtc_mode_set, | |
214 | .mode_set_base = drm_helper_crtc_mode_set_base, | |
215 | .mode_set_nofb = hdlcd_crtc_mode_set_nofb, | |
216 | .enable = hdlcd_crtc_enable, | |
217 | .disable = hdlcd_crtc_disable, | |
218 | .prepare = hdlcd_crtc_disable, | |
219 | .commit = hdlcd_crtc_enable, | |
220 | .atomic_check = hdlcd_crtc_atomic_check, | |
221 | .atomic_begin = hdlcd_crtc_atomic_begin, | |
222 | .atomic_flush = hdlcd_crtc_atomic_flush, | |
223 | }; | |
224 | ||
225 | static int hdlcd_plane_atomic_check(struct drm_plane *plane, | |
226 | struct drm_plane_state *state) | |
227 | { | |
96ebb1f3 LD |
228 | u32 src_w, src_h; |
229 | ||
230 | src_w = state->src_w >> 16; | |
231 | src_h = state->src_h >> 16; | |
232 | ||
233 | /* we can't do any scaling of the plane source */ | |
234 | if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) | |
235 | return -EINVAL; | |
236 | ||
8e22d792 LD |
237 | return 0; |
238 | } | |
239 | ||
240 | static void hdlcd_plane_atomic_update(struct drm_plane *plane, | |
241 | struct drm_plane_state *state) | |
242 | { | |
243 | struct hdlcd_drm_private *hdlcd; | |
244 | struct drm_gem_cma_object *gem; | |
96ebb1f3 LD |
245 | unsigned int depth, bpp; |
246 | u32 src_w, src_h, dest_w, dest_h; | |
8e22d792 LD |
247 | dma_addr_t scanout_start; |
248 | ||
96ebb1f3 | 249 | if (!plane->state->fb) |
8e22d792 LD |
250 | return; |
251 | ||
96ebb1f3 LD |
252 | drm_fb_get_bpp_depth(plane->state->fb->pixel_format, &depth, &bpp); |
253 | src_w = plane->state->src_w >> 16; | |
254 | src_h = plane->state->src_h >> 16; | |
255 | dest_w = plane->state->crtc_w; | |
256 | dest_h = plane->state->crtc_h; | |
8e22d792 | 257 | gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0); |
96ebb1f3 LD |
258 | scanout_start = gem->paddr + plane->state->fb->offsets[0] + |
259 | plane->state->crtc_y * plane->state->fb->pitches[0] + | |
260 | plane->state->crtc_x * bpp / 8; | |
261 | ||
262 | hdlcd = plane->dev->dev_private; | |
263 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, plane->state->fb->pitches[0]); | |
264 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, plane->state->fb->pitches[0]); | |
265 | hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); | |
8e22d792 LD |
266 | hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); |
267 | } | |
268 | ||
269 | static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { | |
8e22d792 LD |
270 | .atomic_check = hdlcd_plane_atomic_check, |
271 | .atomic_update = hdlcd_plane_atomic_update, | |
272 | }; | |
273 | ||
274 | static void hdlcd_plane_destroy(struct drm_plane *plane) | |
275 | { | |
276 | drm_plane_helper_disable(plane); | |
277 | drm_plane_cleanup(plane); | |
278 | } | |
279 | ||
280 | static const struct drm_plane_funcs hdlcd_plane_funcs = { | |
281 | .update_plane = drm_atomic_helper_update_plane, | |
282 | .disable_plane = drm_atomic_helper_disable_plane, | |
283 | .destroy = hdlcd_plane_destroy, | |
284 | .reset = drm_atomic_helper_plane_reset, | |
285 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
286 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
287 | }; | |
288 | ||
289 | static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) | |
290 | { | |
291 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
292 | struct drm_plane *plane = NULL; | |
293 | u32 formats[ARRAY_SIZE(supported_formats)], i; | |
294 | int ret; | |
295 | ||
296 | plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); | |
297 | if (!plane) | |
298 | return ERR_PTR(-ENOMEM); | |
299 | ||
300 | for (i = 0; i < ARRAY_SIZE(supported_formats); i++) | |
301 | formats[i] = supported_formats[i].fourcc; | |
302 | ||
303 | ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs, | |
304 | formats, ARRAY_SIZE(formats), | |
305 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
306 | if (ret) { | |
307 | devm_kfree(drm->dev, plane); | |
308 | return ERR_PTR(ret); | |
309 | } | |
310 | ||
311 | drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs); | |
312 | hdlcd->plane = plane; | |
313 | ||
314 | return plane; | |
315 | } | |
316 | ||
8e22d792 LD |
317 | int hdlcd_setup_crtc(struct drm_device *drm) |
318 | { | |
319 | struct hdlcd_drm_private *hdlcd = drm->dev_private; | |
320 | struct drm_plane *primary; | |
321 | int ret; | |
322 | ||
323 | primary = hdlcd_plane_init(drm); | |
324 | if (IS_ERR(primary)) | |
325 | return PTR_ERR(primary); | |
326 | ||
327 | ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, | |
328 | &hdlcd_crtc_funcs, NULL); | |
329 | if (ret) { | |
330 | hdlcd_plane_destroy(primary); | |
331 | devm_kfree(drm->dev, primary); | |
332 | return ret; | |
333 | } | |
334 | ||
335 | drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs); | |
336 | return 0; | |
337 | } |