[linux-2.6-block.git] / drivers / gpu / drm / arm / hdlcd_crtc.c

/*
 * Copyright (C) 2013-2015 ARM Limited
 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 *
 *  Implementation of a CRTC class for the HDLCD driver.
 */

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_plane_helper.h>
#include <linux/clk.h>
#include <linux/of_graph.h>
#include <linux/platform_data/simplefb.h>
#include <video/videomode.h>

#include "hdlcd_drv.h"
#include "hdlcd_regs.h"

/*
 * The HDLCD controller is a dumb RGB streamer that gets connected to
 * a single HDMI transmitter or in the case of the ARM Models it gets
 * emulated by the software that does the actual rendering.
 *
 */

static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);

	/* stop the controller on cleanup */
	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
	drm_crtc_cleanup(crtc);
}

static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);

	return 0;
}

static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);

	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
}

static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
	.destroy = hdlcd_crtc_cleanup,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	.enable_vblank = hdlcd_crtc_enable_vblank,
	.disable_vblank = hdlcd_crtc_disable_vblank,
};

static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;

/*
 * Setup the HDLCD registers for decoding the pixels out of the framebuffer
 */
static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
{
	unsigned int btpp;
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	const struct drm_framebuffer *fb = crtc->primary->state->fb;
	uint32_t pixel_format;
	struct simplefb_format *format = NULL;
	int i;

	pixel_format = fb->format->format;

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
		if (supported_formats[i].fourcc == pixel_format)
			format = &supported_formats[i];
	}

	if (WARN_ON(!format))
		return 0;

	/* HDLCD uses 'bytes per pixel', zero means 1 byte */
	btpp = (format->bits_per_pixel + 7) / 8;
	hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);

	/*
	 * The format of the HDLCD_REG_<color>_SELECT register is:
	 *   - bits[23:16] - default value for that color component
	 *   - bits[11:8]  - number of bits to extract for each color component
	 *   - bits[4:0]   - index of the lowest bit to extract
	 *
	 * The default color value is used when bits[11:8] are zero, when the
	 * pixel is outside the visible frame area or when there is a
	 * buffer underrun.
	 */
	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
#ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
		    0x00ff0000 |	/* show underruns in red */
#endif
		    ((format->red.length & 0xf) << 8));
	hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
		    ((format->green.length & 0xf) << 8));
	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
		    ((format->blue.length & 0xf) << 8));

	return 0;
}

static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	struct videomode vm;
	unsigned int polarities, err;

	vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
	vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
	vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
	vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
	vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
	vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;

	polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;

	if (m->flags & DRM_MODE_FLAG_PHSYNC)
		polarities |= HDLCD_POLARITY_HSYNC;
	if (m->flags & DRM_MODE_FLAG_PVSYNC)
		polarities |= HDLCD_POLARITY_VSYNC;

	/* Allow max number of outstanding requests and largest burst size */
	hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
		    HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);

	hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
	hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
	hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
	hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);

	err = hdlcd_set_pxl_fmt(crtc);
	if (err)
		return;

	clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
}

static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
				     struct drm_crtc_state *old_state)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);

	clk_prepare_enable(hdlcd->clk);
	hdlcd_crtc_mode_set_nofb(crtc);
	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
	drm_crtc_vblank_on(crtc);
}

static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,
				      struct drm_crtc_state *old_state)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);

	drm_crtc_vblank_off(crtc);
	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
	clk_disable_unprepare(hdlcd->clk);
}

static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
				   struct drm_crtc_state *state)
{
	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	struct drm_display_mode *mode = &state->adjusted_mode;
	long rate, clk_rate = mode->clock * 1000;

	rate = clk_round_rate(hdlcd->clk, clk_rate);
	if (rate != clk_rate) {
		/* clock required by mode not supported by hardware */
		return -EINVAL;
	}

	return 0;
}

static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
				    struct drm_crtc_state *state)
{
	struct drm_pending_vblank_event *event = crtc->state->event;

	if (event) {
		crtc->state->event = NULL;

		spin_lock_irq(&crtc->dev->event_lock);
		if (drm_crtc_vblank_get(crtc) == 0)
			drm_crtc_arm_vblank_event(crtc, event);
		else
			drm_crtc_send_vblank_event(crtc, event);
		spin_unlock_irq(&crtc->dev->event_lock);
	}
}

static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
	.atomic_check	= hdlcd_crtc_atomic_check,
	.atomic_begin	= hdlcd_crtc_atomic_begin,
	.atomic_enable	= hdlcd_crtc_atomic_enable,
	.atomic_disable	= hdlcd_crtc_atomic_disable,
};

static int hdlcd_plane_atomic_check(struct drm_plane *plane,
				    struct drm_plane_state *state)
{
	int i;
	struct drm_crtc *crtc;
	struct drm_crtc_state *crtc_state;
	u32 src_h = state->src_h >> 16;

	/* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
	if (src_h >= HDLCD_MAX_YRES) {
		DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
		return -EINVAL;
	}

	for_each_new_crtc_in_state(state->state, crtc, crtc_state, i) {
		/* we cannot disable the plane while the CRTC is active */
		if (!state->fb && crtc_state->active)
			return -EINVAL;
		return drm_atomic_helper_check_plane_state(state, crtc_state,
						DRM_PLANE_HELPER_NO_SCALING,
						DRM_PLANE_HELPER_NO_SCALING,
						false, true);
	}

	return 0;
}

static void hdlcd_plane_atomic_update(struct drm_plane *plane,
				      struct drm_plane_state *state)
{
	struct drm_framebuffer *fb = plane->state->fb;
	struct hdlcd_drm_private *hdlcd;
	u32 dest_h;
	dma_addr_t scanout_start;

	if (!fb)
		return;

	dest_h = drm_rect_height(&plane->state->dst);
	scanout_start = drm_fb_cma_get_gem_addr(fb, plane->state, 0);

	hdlcd = plane->dev->dev_private;
	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
	hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
}

static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
	.atomic_check = hdlcd_plane_atomic_check,
	.atomic_update = hdlcd_plane_atomic_update,
};

static const struct drm_plane_funcs hdlcd_plane_funcs = {
	.update_plane		= drm_atomic_helper_update_plane,
	.disable_plane		= drm_atomic_helper_disable_plane,
	.destroy		= drm_plane_cleanup,
	.reset			= drm_atomic_helper_plane_reset,
	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
};

static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	struct drm_plane *plane = NULL;
	u32 formats[ARRAY_SIZE(supported_formats)], i;
	int ret;

	plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
	if (!plane)
		return ERR_PTR(-ENOMEM);

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
		formats[i] = supported_formats[i].fourcc;

	ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
				       formats, ARRAY_SIZE(formats),
				       NULL,
				       DRM_PLANE_TYPE_PRIMARY, NULL);
	if (ret)
		return ERR_PTR(ret);

	drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
	hdlcd->plane = plane;

	return plane;
}

int hdlcd_setup_crtc(struct drm_device *drm)
{
	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	struct drm_plane *primary;
	int ret;

	primary = hdlcd_plane_init(drm);
	if (IS_ERR(primary))
		return PTR_ERR(primary);

	ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
					&hdlcd_crtc_funcs, NULL);
	if (ret)
		return ret;

	drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
	return 0;
}
Commit	Line	Data
8e22d792 LD	1	/*
	2	* Copyright (C) 2013-2015 ARM Limited
	3	* Author: Liviu Dudau <Liviu.Dudau@arm.com>
	4	*
	5	* This file is subject to the terms and conditions of the GNU General Public
	6	* License. See the file COPYING in the main directory of this archive
	7	* for more details.
	8	*
	9	* Implementation of a CRTC class for the HDLCD driver.
	10	*/
	11
	12	#include <drm/drmP.h>
1de3cd4f	13	#include <drm/drm_atomic.h>
8e22d792 LD	14	#include <drm/drm_atomic_helper.h>
	15	#include <drm/drm_crtc.h>
	16	#include <drm/drm_crtc_helper.h>
	17	#include <drm/drm_fb_helper.h>
	18	#include <drm/drm_fb_cma_helper.h>
	19	#include <drm/drm_gem_cma_helper.h>
	20	#include <drm/drm_of.h>
	21	#include <drm/drm_plane_helper.h>
	22	#include <linux/clk.h>
	23	#include <linux/of_graph.h>
	24	#include <linux/platform_data/simplefb.h>
	25	#include <video/videomode.h>
	26
	27	#include "hdlcd_drv.h"
	28	#include "hdlcd_regs.h"
	29
	30	/*
	31	* The HDLCD controller is a dumb RGB streamer that gets connected to
	32	* a single HDMI transmitter or in the case of the ARM Models it gets
	33	* emulated by the software that does the actual rendering.
	34	*
	35	*/
	36
a95acec1 LD	37	static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
	38	{
	39	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	40
	41	/* stop the controller on cleanup */
	42	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
	43	drm_crtc_cleanup(crtc);
	44	}
	45
1fe25980 SG	46	static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
	47	{
	48	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	49	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	50
	51	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask \| HDLCD_INTERRUPT_VSYNC);
	52
	53	return 0;
	54	}
	55
	56	static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
	57	{
	58	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	59	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
	60
	61	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
	62	}
	63
8e22d792	64	static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
a95acec1	65	.destroy = hdlcd_crtc_cleanup,
8e22d792 LD	66	.set_config = drm_atomic_helper_set_config,
	67	.page_flip = drm_atomic_helper_page_flip,
	68	.reset = drm_atomic_helper_crtc_reset,
	69	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	70	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1fe25980 SG	71	.enable_vblank = hdlcd_crtc_enable_vblank,
1fe25980 SG	72	.disable_vblank = hdlcd_crtc_disable_vblank,
8e22d792 LD	73	};
	74
	75	static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;
	76
	77	/*
	78	* Setup the HDLCD registers for decoding the pixels out of the framebuffer
	79	*/
	80	static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
	81	{
	82	unsigned int btpp;
	83	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
59477fa9	84	const struct drm_framebuffer *fb = crtc->primary->state->fb;
8e22d792 LD	85	uint32_t pixel_format;
	86	struct simplefb_format *format = NULL;
	87	int i;
	88
438b74a5	89	pixel_format = fb->format->format;
8e22d792 LD	90
	91	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
	92	if (supported_formats[i].fourcc == pixel_format)
	93	format = &supported_formats[i];
	94	}
	95
	96	if (WARN_ON(!format))
	97	return 0;
	98
	99	/* HDLCD uses 'bytes per pixel', zero means 1 byte */
	100	btpp = (format->bits_per_pixel + 7) / 8;
	101	hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
	102
	103	/*
	104	* The format of the HDLCD_REG_<color>_SELECT register is:
	105	* - bits[23:16] - default value for that color component
	106	* - bits[11:8] - number of bits to extract for each color component
	107	* - bits[4:0] - index of the lowest bit to extract
	108	*
	109	* The default color value is used when bits[11:8] are zero, when the
	110	* pixel is outside the visible frame area or when there is a
	111	* buffer underrun.
	112	*/
	113	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset \|
	114	#ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
	115	0x00ff0000 \| /* show underruns in red */
	116	#endif
	117	((format->red.length & 0xf) << 8));
	118	hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset \|
	119	((format->green.length & 0xf) << 8));
	120	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset \|
	121	((format->blue.length & 0xf) << 8));
	122
	123	return 0;
	124	}
	125
	126	static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
	127	{
	128	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	129	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	130	struct videomode vm;
96ebb1f3	131	unsigned int polarities, err;
8e22d792 LD	132
	133	vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
	134	vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
	135	vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
	136	vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
	137	vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
	138	vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
	139
	140	polarities = HDLCD_POLARITY_DATAEN \| HDLCD_POLARITY_DATA;
	141
	142	if (m->flags & DRM_MODE_FLAG_PHSYNC)
	143	polarities \|= HDLCD_POLARITY_HSYNC;
	144	if (m->flags & DRM_MODE_FLAG_PVSYNC)
	145	polarities \|= HDLCD_POLARITY_VSYNC;
	146
8e22d792 LD	147	/* Allow max number of outstanding requests and largest burst size */
	148	hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
	149	HDLCD_BUS_MAX_OUTSTAND \| HDLCD_BUS_BURST_16);
	150
8e22d792 LD	151	hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
	152	hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
	153	hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
	154	hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
96ebb1f3	155	hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
8e22d792 LD	156	hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
	157	hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
	158	hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
8e22d792 LD	159	hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
	160
	161	err = hdlcd_set_pxl_fmt(crtc);
	162	if (err)
	163	return;
	164
	165	clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
	166	}
	167
0b20a0f8 LP	168	static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
0b20a0f8 LP	169	struct drm_crtc_state *old_state)
8e22d792 LD	170	{
	171	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	172
	173	clk_prepare_enable(hdlcd->clk);
96ebb1f3	174	hdlcd_crtc_mode_set_nofb(crtc);
8e22d792	175	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
7a79279e	176	drm_crtc_vblank_on(crtc);
8e22d792 LD	177	}
8e22d792 LD	178
64581714 LP	179	static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,
64581714 LP	180	struct drm_crtc_state *old_state)
8e22d792 LD	181	{
	182	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	183
7a79279e	184	drm_crtc_vblank_off(crtc);
8e22d792	185	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
a95acec1	186	clk_disable_unprepare(hdlcd->clk);
8e22d792 LD	187	}
	188
	189	static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
	190	struct drm_crtc_state *state)
	191	{
	192	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
	193	struct drm_display_mode *mode = &state->adjusted_mode;
	194	long rate, clk_rate = mode->clock * 1000;
	195
	196	rate = clk_round_rate(hdlcd->clk, clk_rate);
	197	if (rate != clk_rate) {
	198	/* clock required by mode not supported by hardware */
	199	return -EINVAL;
	200	}
	201
	202	return 0;
	203	}
	204
	205	static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
	206	struct drm_crtc_state *state)
	207	{
38c8c22c	208	struct drm_pending_vblank_event *event = crtc->state->event;
8e22d792	209
38c8c22c	210	if (event) {
8e22d792	211	crtc->state->event = NULL;
8e22d792	212
38c8c22c DV	213	spin_lock_irq(&crtc->dev->event_lock);
	214	if (drm_crtc_vblank_get(crtc) == 0)
	215	drm_crtc_arm_vblank_event(crtc, event);
	216	else
	217	drm_crtc_send_vblank_event(crtc, event);
	218	spin_unlock_irq(&crtc->dev->event_lock);
8e22d792 LD	219	}
	220	}
	221
8e22d792	222	static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
8e22d792 LD	223	.atomic_check = hdlcd_crtc_atomic_check,
8e22d792 LD	224	.atomic_begin = hdlcd_crtc_atomic_begin,
0b20a0f8	225	.atomic_enable = hdlcd_crtc_atomic_enable,
64581714	226	.atomic_disable = hdlcd_crtc_atomic_disable,
8e22d792 LD	227	};
	228
	229	static int hdlcd_plane_atomic_check(struct drm_plane *plane,
	230	struct drm_plane_state *state)
	231	{
d664b851 LD	232	int i;
d664b851 LD	233	struct drm_crtc *crtc;
1de3cd4f LD	234	struct drm_crtc_state *crtc_state;
1de3cd4f LD	235	u32 src_h = state->src_h >> 16;
96ebb1f3	236
1de3cd4f LD	237	/* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
	238	if (src_h >= HDLCD_MAX_YRES) {
	239	DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
	240	return -EINVAL;
	241	}
	242
d664b851 LD	243	for_each_new_crtc_in_state(state->state, crtc, crtc_state, i) {
	244	/* we cannot disable the plane while the CRTC is active */
	245	if (!state->fb && crtc_state->active)
	246	return -EINVAL;
	247	return drm_atomic_helper_check_plane_state(state, crtc_state,
	248	DRM_PLANE_HELPER_NO_SCALING,
	249	DRM_PLANE_HELPER_NO_SCALING,
	250	false, true);
1de3cd4f	251	}
96ebb1f3	252
d664b851	253	return 0;
8e22d792 LD	254	}
	255
	256	static void hdlcd_plane_atomic_update(struct drm_plane *plane,
	257	struct drm_plane_state *state)
	258	{
59477fa9	259	struct drm_framebuffer *fb = plane->state->fb;
8e22d792	260	struct hdlcd_drm_private *hdlcd;
fee4964f	261	u32 dest_h;
8e22d792 LD	262	dma_addr_t scanout_start;
8e22d792 LD	263
59477fa9	264	if (!fb)
8e22d792 LD	265	return;
8e22d792 LD	266
1de3cd4f	267	dest_h = drm_rect_height(&plane->state->dst);
49a58f26	268	scanout_start = drm_fb_cma_get_gem_addr(fb, plane->state, 0);
96ebb1f3 LD	269
96ebb1f3 LD	270	hdlcd = plane->dev->dev_private;
59477fa9 VS	271	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
59477fa9 VS	272	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
96ebb1f3	273	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
8e22d792 LD	274	hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
	275	}
	276
	277	static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
8e22d792 LD	278	.atomic_check = hdlcd_plane_atomic_check,
	279	.atomic_update = hdlcd_plane_atomic_update,
	280	};
	281
8e22d792 LD	282	static const struct drm_plane_funcs hdlcd_plane_funcs = {
	283	.update_plane = drm_atomic_helper_update_plane,
	284	.disable_plane = drm_atomic_helper_disable_plane,
9fd466f5	285	.destroy = drm_plane_cleanup,
8e22d792 LD	286	.reset = drm_atomic_helper_plane_reset,
	287	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	288	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
	289	};
	290
	291	static struct drm_plane hdlcd_plane_init(struct drm_device drm)
	292	{
	293	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	294	struct drm_plane *plane = NULL;
	295	u32 formats[ARRAY_SIZE(supported_formats)], i;
	296	int ret;
	297
	298	plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
	299	if (!plane)
	300	return ERR_PTR(-ENOMEM);
	301
	302	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
	303	formats[i] = supported_formats[i].fourcc;
	304
	305	ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
	306	formats, ARRAY_SIZE(formats),
e6fc3b68	307	NULL,
8e22d792	308	DRM_PLANE_TYPE_PRIMARY, NULL);
fa56b3f8	309	if (ret)
8e22d792	310	return ERR_PTR(ret);
8e22d792 LD	311
	312	drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
	313	hdlcd->plane = plane;
	314
	315	return plane;
	316	}
	317
8e22d792 LD	318	int hdlcd_setup_crtc(struct drm_device *drm)
	319	{
	320	struct hdlcd_drm_private *hdlcd = drm->dev_private;
	321	struct drm_plane *primary;
	322	int ret;
	323
	324	primary = hdlcd_plane_init(drm);
	325	if (IS_ERR(primary))
	326	return PTR_ERR(primary);
	327
	328	ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
	329	&hdlcd_crtc_funcs, NULL);
8df24d57	330	if (ret)
8e22d792	331	return ret;
8e22d792 LD	332
	333	drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
	334	return 0;
	335	}