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2435b054 HR |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Author: Huang Rui <ray.huang@amd.com> | |
23 | * | |
24 | */ | |
7bd55429 | 25 | #include "pp_debug.h" |
2435b054 HR |
26 | #include <linux/types.h> |
27 | #include <linux/kernel.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/gfp.h> | |
30 | ||
31 | #include "smumgr.h" | |
32 | #include "iceland_smumgr.h" | |
907bfec7 | 33 | |
2435b054 | 34 | #include "ppsmc.h" |
907bfec7 RZ |
35 | |
36 | #include "cgs_common.h" | |
37 | ||
38 | #include "smu7_dyn_defaults.h" | |
39 | #include "smu7_hwmgr.h" | |
40 | #include "hardwaremanager.h" | |
41 | #include "ppatomctrl.h" | |
42 | #include "atombios.h" | |
43 | #include "pppcielanes.h" | |
44 | #include "pp_endian.h" | |
45 | #include "processpptables.h" | |
46 | ||
47 | ||
2435b054 HR |
48 | #include "smu/smu_7_1_1_d.h" |
49 | #include "smu/smu_7_1_1_sh_mask.h" | |
907bfec7 RZ |
50 | #include "smu71_discrete.h" |
51 | ||
52 | #include "smu_ucode_xfer_vi.h" | |
53 | #include "gmc/gmc_8_1_d.h" | |
54 | #include "gmc/gmc_8_1_sh_mask.h" | |
55 | #include "bif/bif_5_0_d.h" | |
56 | #include "bif/bif_5_0_sh_mask.h" | |
57 | #include "dce/dce_10_0_d.h" | |
58 | #include "dce/dce_10_0_sh_mask.h" | |
59 | ||
2435b054 | 60 | |
9c6d4956 | 61 | #define ICELAND_SMC_SIZE 0x20000 |
2435b054 | 62 | |
907bfec7 RZ |
63 | #define VOLTAGE_SCALE 4 |
64 | #define POWERTUNE_DEFAULT_SET_MAX 1 | |
65 | #define VOLTAGE_VID_OFFSET_SCALE1 625 | |
66 | #define VOLTAGE_VID_OFFSET_SCALE2 100 | |
67 | #define MC_CG_ARB_FREQ_F1 0x0b | |
68 | #define VDDC_VDDCI_DELTA 200 | |
69 | ||
70 | #define DEVICE_ID_VI_ICELAND_M_6900 0x6900 | |
71 | #define DEVICE_ID_VI_ICELAND_M_6901 0x6901 | |
72 | #define DEVICE_ID_VI_ICELAND_M_6902 0x6902 | |
73 | #define DEVICE_ID_VI_ICELAND_M_6903 0x6903 | |
74 | ||
75 | static const struct iceland_pt_defaults defaults_iceland = { | |
76 | /* | |
77 | * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, | |
78 | * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT | |
79 | */ | |
80 | 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, | |
81 | { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, | |
82 | { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } | |
83 | }; | |
84 | ||
85 | /* 35W - XT, XTL */ | |
86 | static const struct iceland_pt_defaults defaults_icelandxt = { | |
87 | /* | |
88 | * sviLoadLIneEn, SviLoadLineVddC, | |
89 | * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, | |
90 | * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, | |
91 | * BAPM_TEMP_GRADIENT | |
92 | */ | |
93 | 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0, | |
94 | { 0xA7, 0x0, 0x0, 0xB5, 0x0, 0x0, 0x9F, 0x0, 0x0, 0xD6, 0x0, 0x0, 0xD7, 0x0, 0x0}, | |
95 | { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0} | |
96 | }; | |
97 | ||
98 | /* 25W - PRO, LE */ | |
99 | static const struct iceland_pt_defaults defaults_icelandpro = { | |
100 | /* | |
101 | * sviLoadLIneEn, SviLoadLineVddC, | |
102 | * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, | |
103 | * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, | |
104 | * BAPM_TEMP_GRADIENT | |
105 | */ | |
106 | 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0, | |
107 | { 0xB7, 0x0, 0x0, 0xC3, 0x0, 0x0, 0xB5, 0x0, 0x0, 0xEA, 0x0, 0x0, 0xE6, 0x0, 0x0}, | |
108 | { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0} | |
109 | }; | |
110 | ||
d3f8c0ab | 111 | static int iceland_start_smc(struct pp_hwmgr *hwmgr) |
2435b054 | 112 | { |
fbabae46 | 113 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
2435b054 HR |
114 | SMC_SYSCON_RESET_CNTL, rst_reg, 0); |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
d3f8c0ab | 119 | static void iceland_reset_smc(struct pp_hwmgr *hwmgr) |
2435b054 | 120 | { |
fbabae46 | 121 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
2435b054 HR |
122 | SMC_SYSCON_RESET_CNTL, |
123 | rst_reg, 1); | |
124 | } | |
125 | ||
2435b054 | 126 | |
d3f8c0ab | 127 | static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr) |
2435b054 | 128 | { |
fbabae46 | 129 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
2435b054 HR |
130 | SMC_SYSCON_CLOCK_CNTL_0, |
131 | ck_disable, 1); | |
132 | } | |
133 | ||
d3f8c0ab | 134 | static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr) |
2435b054 | 135 | { |
fbabae46 | 136 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
2435b054 HR |
137 | SMC_SYSCON_CLOCK_CNTL_0, |
138 | ck_disable, 0); | |
139 | } | |
140 | ||
d3f8c0ab | 141 | static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr) |
2435b054 HR |
142 | { |
143 | /* set smc instruct start point at 0x0 */ | |
d3f8c0ab | 144 | smu7_program_jump_on_start(hwmgr); |
2435b054 HR |
145 | |
146 | /* enable smc clock */ | |
d3f8c0ab | 147 | iceland_start_smc_clock(hwmgr); |
2435b054 HR |
148 | |
149 | /* de-assert reset */ | |
d3f8c0ab | 150 | iceland_start_smc(hwmgr); |
2435b054 | 151 | |
0041e600 | 152 | PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, |
2435b054 HR |
153 | INTERRUPTS_ENABLED, 1); |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
9c6d4956 | 158 | |
d3f8c0ab | 159 | static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, |
9c6d4956 RZ |
160 | uint32_t length, const uint8_t *src, |
161 | uint32_t limit, uint32_t start_addr) | |
2435b054 | 162 | { |
9c6d4956 | 163 | uint32_t byte_count = length; |
2435b054 | 164 | uint32_t data; |
9c6d4956 RZ |
165 | |
166 | PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); | |
167 | ||
d3f8c0ab | 168 | cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr); |
a9eca3a6 | 169 | PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); |
9c6d4956 RZ |
170 | |
171 | while (byte_count >= 4) { | |
172 | data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; | |
d3f8c0ab | 173 | cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); |
9c6d4956 RZ |
174 | src += 4; |
175 | byte_count -= 4; | |
176 | } | |
177 | ||
a9eca3a6 | 178 | PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); |
9c6d4956 | 179 | |
45b19706 | 180 | PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL); |
9c6d4956 RZ |
181 | |
182 | return 0; | |
183 | } | |
184 | ||
185 | ||
d3f8c0ab | 186 | static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr) |
9c6d4956 RZ |
187 | { |
188 | uint32_t val; | |
2435b054 HR |
189 | struct cgs_firmware_info info = {0}; |
190 | ||
d3f8c0ab | 191 | if (hwmgr == NULL || hwmgr->device == NULL) |
2435b054 HR |
192 | return -EINVAL; |
193 | ||
194 | /* load SMC firmware */ | |
d3f8c0ab | 195 | cgs_get_firmware_info(hwmgr->device, |
9c6d4956 | 196 | smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); |
2435b054 HR |
197 | |
198 | if (info.image_size & 3) { | |
199 | pr_err("[ powerplay ] SMC ucode is not 4 bytes aligned\n"); | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
203 | if (info.image_size > ICELAND_SMC_SIZE) { | |
204 | pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n"); | |
205 | return -EINVAL; | |
206 | } | |
207 | ||
208 | /* wait for smc boot up */ | |
b05720cb | 209 | PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, |
2435b054 HR |
210 | RCU_UC_EVENTS, boot_seq_done, 0); |
211 | ||
212 | /* clear firmware interrupt enable flag */ | |
d3f8c0ab | 213 | val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
2435b054 | 214 | ixSMC_SYSCON_MISC_CNTL); |
d3f8c0ab | 215 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
2435b054 HR |
216 | ixSMC_SYSCON_MISC_CNTL, val | 1); |
217 | ||
218 | /* stop smc clock */ | |
d3f8c0ab | 219 | iceland_stop_smc_clock(hwmgr); |
2435b054 HR |
220 | |
221 | /* reset smc */ | |
d3f8c0ab RZ |
222 | iceland_reset_smc(hwmgr); |
223 | iceland_upload_smc_firmware_data(hwmgr, info.image_size, | |
9c6d4956 RZ |
224 | (uint8_t *)info.kptr, ICELAND_SMC_SIZE, |
225 | info.ucode_start_address); | |
2435b054 HR |
226 | |
227 | return 0; | |
228 | } | |
229 | ||
d3f8c0ab | 230 | static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr, |
2435b054 HR |
231 | uint32_t firmwareType) |
232 | { | |
233 | return 0; | |
234 | } | |
235 | ||
d3f8c0ab | 236 | static int iceland_start_smu(struct pp_hwmgr *hwmgr) |
2435b054 HR |
237 | { |
238 | int result; | |
239 | ||
d3f8c0ab | 240 | result = iceland_smu_upload_firmware_image(hwmgr); |
2435b054 HR |
241 | if (result) |
242 | return result; | |
d3f8c0ab | 243 | result = iceland_smu_start_smc(hwmgr); |
2435b054 HR |
244 | if (result) |
245 | return result; | |
246 | ||
d3f8c0ab | 247 | if (!smu7_is_smc_ram_running(hwmgr)) { |
634a24d8 | 248 | pr_info("smu not running, upload firmware again \n"); |
d3f8c0ab | 249 | result = iceland_smu_upload_firmware_image(hwmgr); |
9c6d4956 RZ |
250 | if (result) |
251 | return result; | |
252 | ||
d3f8c0ab | 253 | result = iceland_smu_start_smc(hwmgr); |
9c6d4956 RZ |
254 | if (result) |
255 | return result; | |
256 | } | |
257 | ||
d3f8c0ab | 258 | result = smu7_request_smu_load_fw(hwmgr); |
2435b054 HR |
259 | |
260 | return result; | |
261 | } | |
262 | ||
d3f8c0ab | 263 | static int iceland_smu_init(struct pp_hwmgr *hwmgr) |
2435b054 | 264 | { |
18aafc59 | 265 | int i; |
63b55943 RZ |
266 | struct iceland_smumgr *iceland_priv = NULL; |
267 | ||
268 | iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL); | |
269 | ||
270 | if (iceland_priv == NULL) | |
271 | return -ENOMEM; | |
272 | ||
b3b03052 | 273 | hwmgr->smu_backend = iceland_priv; |
63b55943 | 274 | |
d3f8c0ab | 275 | if (smu7_init(hwmgr)) |
18aafc59 RZ |
276 | return -EINVAL; |
277 | ||
278 | for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++) | |
63b55943 | 279 | iceland_priv->activity_target[i] = 30; |
18aafc59 RZ |
280 | |
281 | return 0; | |
2435b054 HR |
282 | } |
283 | ||
907bfec7 RZ |
284 | |
285 | static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) | |
286 | { | |
287 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
288 | struct cgs_system_info sys_info = {0}; | |
289 | uint32_t dev_id; | |
290 | ||
291 | sys_info.size = sizeof(struct cgs_system_info); | |
292 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; | |
293 | cgs_query_system_info(hwmgr->device, &sys_info); | |
294 | dev_id = (uint32_t)sys_info.value; | |
295 | ||
296 | switch (dev_id) { | |
297 | case DEVICE_ID_VI_ICELAND_M_6900: | |
298 | case DEVICE_ID_VI_ICELAND_M_6903: | |
299 | smu_data->power_tune_defaults = &defaults_icelandxt; | |
300 | break; | |
301 | ||
302 | case DEVICE_ID_VI_ICELAND_M_6901: | |
303 | case DEVICE_ID_VI_ICELAND_M_6902: | |
304 | smu_data->power_tune_defaults = &defaults_icelandpro; | |
305 | break; | |
306 | default: | |
307 | smu_data->power_tune_defaults = &defaults_iceland; | |
308 | pr_warn("Unknown V.I. Device ID.\n"); | |
309 | break; | |
310 | } | |
311 | return; | |
312 | } | |
313 | ||
314 | static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr) | |
315 | { | |
316 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
317 | const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; | |
318 | ||
319 | smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; | |
320 | smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc; | |
321 | smu_data->power_tune_table.SviLoadLineTrimVddC = 3; | |
322 | smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr) | |
328 | { | |
329 | uint16_t tdc_limit; | |
330 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
331 | const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; | |
332 | ||
333 | tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); | |
334 | smu_data->power_tune_table.TDC_VDDC_PkgLimit = | |
335 | CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); | |
336 | smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = | |
337 | defaults->tdc_vddc_throttle_release_limit_perc; | |
338 | smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt; | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) | |
344 | { | |
345 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
346 | const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; | |
347 | uint32_t temp; | |
348 | ||
349 | if (smu7_read_smc_sram_dword(hwmgr, | |
350 | fuse_table_offset + | |
351 | offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl), | |
352 | (uint32_t *)&temp, SMC_RAM_END)) | |
353 | PP_ASSERT_WITH_CODE(false, | |
354 | "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!", | |
355 | return -EINVAL); | |
356 | else | |
357 | smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl; | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr) | |
363 | { | |
364 | return 0; | |
365 | } | |
366 | ||
367 | static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr) | |
368 | { | |
369 | int i; | |
370 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
371 | ||
372 | /* Currently not used. Set all to zero. */ | |
373 | for (i = 0; i < 8; i++) | |
374 | smu_data->power_tune_table.GnbLPML[i] = 0; | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) | |
380 | { | |
381 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
382 | uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; | |
383 | uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; | |
384 | struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; | |
385 | ||
386 | HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); | |
387 | LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); | |
388 | ||
389 | smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd = | |
390 | CONVERT_FROM_HOST_TO_SMC_US(HiSidd); | |
391 | smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd = | |
392 | CONVERT_FROM_HOST_TO_SMC_US(LoSidd); | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) | |
398 | { | |
399 | int i; | |
400 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
401 | uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; | |
402 | uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; | |
403 | ||
404 | PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, | |
405 | "The CAC Leakage table does not exist!", return -EINVAL); | |
406 | PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, | |
407 | "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL); | |
408 | PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, | |
409 | "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL); | |
410 | ||
411 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) { | |
412 | for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { | |
413 | lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); | |
414 | hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); | |
415 | } | |
416 | } else { | |
417 | PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL); | |
418 | } | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) | |
424 | { | |
425 | int i; | |
426 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
427 | uint8_t *vid = smu_data->power_tune_table.VddCVid; | |
428 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
429 | ||
430 | PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, | |
431 | "There should never be more than 8 entries for VddcVid!!!", | |
432 | return -EINVAL); | |
433 | ||
434 | for (i = 0; i < (int)data->vddc_voltage_table.count; i++) { | |
435 | vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value); | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | ||
442 | ||
443 | static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) | |
444 | { | |
445 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
446 | uint32_t pm_fuse_table_offset; | |
447 | ||
448 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
449 | PHM_PlatformCaps_PowerContainment)) { | |
450 | if (smu7_read_smc_sram_dword(hwmgr, | |
451 | SMU71_FIRMWARE_HEADER_LOCATION + | |
452 | offsetof(SMU71_Firmware_Header, PmFuseTable), | |
453 | &pm_fuse_table_offset, SMC_RAM_END)) | |
454 | PP_ASSERT_WITH_CODE(false, | |
455 | "Attempt to get pm_fuse_table_offset Failed!", | |
456 | return -EINVAL); | |
457 | ||
458 | /* DW0 - DW3 */ | |
459 | if (iceland_populate_bapm_vddc_vid_sidd(hwmgr)) | |
460 | PP_ASSERT_WITH_CODE(false, | |
461 | "Attempt to populate bapm vddc vid Failed!", | |
462 | return -EINVAL); | |
463 | ||
464 | /* DW4 - DW5 */ | |
465 | if (iceland_populate_vddc_vid(hwmgr)) | |
466 | PP_ASSERT_WITH_CODE(false, | |
467 | "Attempt to populate vddc vid Failed!", | |
468 | return -EINVAL); | |
469 | ||
470 | /* DW6 */ | |
471 | if (iceland_populate_svi_load_line(hwmgr)) | |
472 | PP_ASSERT_WITH_CODE(false, | |
473 | "Attempt to populate SviLoadLine Failed!", | |
474 | return -EINVAL); | |
475 | /* DW7 */ | |
476 | if (iceland_populate_tdc_limit(hwmgr)) | |
477 | PP_ASSERT_WITH_CODE(false, | |
478 | "Attempt to populate TDCLimit Failed!", return -EINVAL); | |
479 | /* DW8 */ | |
480 | if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset)) | |
481 | PP_ASSERT_WITH_CODE(false, | |
482 | "Attempt to populate TdcWaterfallCtl, " | |
483 | "LPMLTemperature Min and Max Failed!", | |
484 | return -EINVAL); | |
485 | ||
486 | /* DW9-DW12 */ | |
487 | if (0 != iceland_populate_temperature_scaler(hwmgr)) | |
488 | PP_ASSERT_WITH_CODE(false, | |
489 | "Attempt to populate LPMLTemperatureScaler Failed!", | |
490 | return -EINVAL); | |
491 | ||
492 | /* DW13-DW16 */ | |
493 | if (iceland_populate_gnb_lpml(hwmgr)) | |
494 | PP_ASSERT_WITH_CODE(false, | |
495 | "Attempt to populate GnbLPML Failed!", | |
496 | return -EINVAL); | |
497 | ||
498 | /* DW18 */ | |
499 | if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr)) | |
500 | PP_ASSERT_WITH_CODE(false, | |
501 | "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!", | |
502 | return -EINVAL); | |
503 | ||
504 | if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, | |
505 | (uint8_t *)&smu_data->power_tune_table, | |
506 | sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END)) | |
507 | PP_ASSERT_WITH_CODE(false, | |
508 | "Attempt to download PmFuseTable Failed!", | |
509 | return -EINVAL); | |
510 | } | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, | |
515 | struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table, | |
516 | uint32_t clock, uint32_t *vol) | |
517 | { | |
518 | uint32_t i = 0; | |
519 | ||
520 | /* clock - voltage dependency table is empty table */ | |
521 | if (allowed_clock_voltage_table->count == 0) | |
522 | return -EINVAL; | |
523 | ||
524 | for (i = 0; i < allowed_clock_voltage_table->count; i++) { | |
525 | /* find first sclk bigger than request */ | |
526 | if (allowed_clock_voltage_table->entries[i].clk >= clock) { | |
527 | *vol = allowed_clock_voltage_table->entries[i].v; | |
528 | return 0; | |
529 | } | |
530 | } | |
531 | ||
532 | /* sclk is bigger than max sclk in the dependence table */ | |
533 | *vol = allowed_clock_voltage_table->entries[i - 1].v; | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr, | |
539 | pp_atomctrl_voltage_table_entry *tab, uint16_t *hi, | |
540 | uint16_t *lo) | |
541 | { | |
542 | uint16_t v_index; | |
543 | bool vol_found = false; | |
544 | *hi = tab->value * VOLTAGE_SCALE; | |
545 | *lo = tab->value * VOLTAGE_SCALE; | |
546 | ||
547 | /* SCLK/VDDC Dependency Table has to exist. */ | |
548 | PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, | |
549 | "The SCLK/VDDC Dependency Table does not exist.\n", | |
550 | return -EINVAL); | |
551 | ||
552 | if (NULL == hwmgr->dyn_state.cac_leakage_table) { | |
553 | pr_warn("CAC Leakage Table does not exist, using vddc.\n"); | |
554 | return 0; | |
555 | } | |
556 | ||
557 | /* | |
558 | * Since voltage in the sclk/vddc dependency table is not | |
559 | * necessarily in ascending order because of ELB voltage | |
560 | * patching, loop through entire list to find exact voltage. | |
561 | */ | |
562 | for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { | |
563 | if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { | |
564 | vol_found = true; | |
565 | if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { | |
566 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; | |
567 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE); | |
568 | } else { | |
569 | pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n"); | |
570 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; | |
571 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); | |
572 | } | |
573 | break; | |
574 | } | |
575 | } | |
576 | ||
577 | /* | |
578 | * If voltage is not found in the first pass, loop again to | |
579 | * find the best match, equal or higher value. | |
580 | */ | |
581 | if (!vol_found) { | |
582 | for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { | |
583 | if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { | |
584 | vol_found = true; | |
585 | if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { | |
586 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; | |
587 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE; | |
588 | } else { | |
589 | pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table."); | |
590 | *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; | |
591 | *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); | |
592 | } | |
593 | break; | |
594 | } | |
595 | } | |
596 | ||
597 | if (!vol_found) | |
598 | pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n"); | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr, | |
605 | pp_atomctrl_voltage_table_entry *tab, | |
606 | SMU71_Discrete_VoltageLevel *smc_voltage_tab) | |
607 | { | |
608 | int result; | |
609 | ||
610 | result = iceland_get_std_voltage_value_sidd(hwmgr, tab, | |
611 | &smc_voltage_tab->StdVoltageHiSidd, | |
612 | &smc_voltage_tab->StdVoltageLoSidd); | |
613 | if (0 != result) { | |
614 | smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE; | |
615 | smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE; | |
616 | } | |
617 | ||
618 | smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE); | |
619 | CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd); | |
620 | CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd); | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
625 | static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, | |
626 | SMU71_Discrete_DpmTable *table) | |
627 | { | |
628 | unsigned int count; | |
629 | int result; | |
630 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
631 | ||
632 | table->VddcLevelCount = data->vddc_voltage_table.count; | |
633 | for (count = 0; count < table->VddcLevelCount; count++) { | |
634 | result = iceland_populate_smc_voltage_table(hwmgr, | |
635 | &(data->vddc_voltage_table.entries[count]), | |
636 | &(table->VddcLevel[count])); | |
637 | PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); | |
638 | ||
639 | /* GPIO voltage control */ | |
640 | if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) | |
641 | table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low; | |
642 | else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) | |
643 | table->VddcLevel[count].Smio = 0; | |
644 | } | |
645 | ||
646 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, | |
652 | SMU71_Discrete_DpmTable *table) | |
653 | { | |
654 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
655 | uint32_t count; | |
656 | int result; | |
657 | ||
658 | table->VddciLevelCount = data->vddci_voltage_table.count; | |
659 | ||
660 | for (count = 0; count < table->VddciLevelCount; count++) { | |
661 | result = iceland_populate_smc_voltage_table(hwmgr, | |
662 | &(data->vddci_voltage_table.entries[count]), | |
663 | &(table->VddciLevel[count])); | |
664 | PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); | |
665 | if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) | |
666 | table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low; | |
667 | else | |
668 | table->VddciLevel[count].Smio |= 0; | |
669 | } | |
670 | ||
671 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, | |
677 | SMU71_Discrete_DpmTable *table) | |
678 | { | |
679 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
680 | uint32_t count; | |
681 | int result; | |
682 | ||
683 | table->MvddLevelCount = data->mvdd_voltage_table.count; | |
684 | ||
685 | for (count = 0; count < table->VddciLevelCount; count++) { | |
686 | result = iceland_populate_smc_voltage_table(hwmgr, | |
687 | &(data->mvdd_voltage_table.entries[count]), | |
688 | &table->MvddLevel[count]); | |
689 | PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); | |
690 | if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) | |
691 | table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low; | |
692 | else | |
693 | table->MvddLevel[count].Smio |= 0; | |
694 | } | |
695 | ||
696 | CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | ||
702 | static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, | |
703 | SMU71_Discrete_DpmTable *table) | |
704 | { | |
705 | int result; | |
706 | ||
707 | result = iceland_populate_smc_vddc_table(hwmgr, table); | |
708 | PP_ASSERT_WITH_CODE(0 == result, | |
709 | "can not populate VDDC voltage table to SMC", return -EINVAL); | |
710 | ||
711 | result = iceland_populate_smc_vdd_ci_table(hwmgr, table); | |
712 | PP_ASSERT_WITH_CODE(0 == result, | |
713 | "can not populate VDDCI voltage table to SMC", return -EINVAL); | |
714 | ||
715 | result = iceland_populate_smc_mvdd_table(hwmgr, table); | |
716 | PP_ASSERT_WITH_CODE(0 == result, | |
717 | "can not populate MVDD voltage table to SMC", return -EINVAL); | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
722 | static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr, | |
723 | struct SMU71_Discrete_Ulv *state) | |
724 | { | |
725 | uint32_t voltage_response_time, ulv_voltage; | |
726 | int result; | |
727 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
728 | ||
729 | state->CcPwrDynRm = 0; | |
730 | state->CcPwrDynRm1 = 0; | |
731 | ||
732 | result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage); | |
733 | PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;); | |
734 | ||
735 | if (ulv_voltage == 0) { | |
736 | data->ulv_supported = false; | |
737 | return 0; | |
738 | } | |
739 | ||
740 | if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) { | |
741 | /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */ | |
742 | if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) | |
743 | state->VddcOffset = 0; | |
744 | else | |
745 | /* used in SMIO Mode. not implemented for now. this is backup only for CI. */ | |
746 | state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage); | |
747 | } else { | |
748 | /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */ | |
749 | if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) | |
750 | state->VddcOffsetVid = 0; | |
751 | else /* used in SVI2 Mode */ | |
752 | state->VddcOffsetVid = (uint8_t)( | |
753 | (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) | |
754 | * VOLTAGE_VID_OFFSET_SCALE2 | |
755 | / VOLTAGE_VID_OFFSET_SCALE1); | |
756 | } | |
757 | state->VddcPhase = 1; | |
758 | ||
759 | CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); | |
760 | CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); | |
761 | CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr, | |
767 | SMU71_Discrete_Ulv *ulv_level) | |
768 | { | |
769 | return iceland_populate_ulv_level(hwmgr, ulv_level); | |
770 | } | |
771 | ||
772 | static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table) | |
773 | { | |
774 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
775 | struct smu7_dpm_table *dpm_table = &data->dpm_table; | |
776 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
777 | uint32_t i; | |
778 | ||
779 | /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ | |
780 | for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { | |
781 | table->LinkLevel[i].PcieGenSpeed = | |
782 | (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; | |
783 | table->LinkLevel[i].PcieLaneCount = | |
784 | (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); | |
785 | table->LinkLevel[i].EnabledForActivity = | |
786 | 1; | |
787 | table->LinkLevel[i].SPC = | |
788 | (uint8_t)(data->pcie_spc_cap & 0xff); | |
789 | table->LinkLevel[i].DownThreshold = | |
790 | PP_HOST_TO_SMC_UL(5); | |
791 | table->LinkLevel[i].UpThreshold = | |
792 | PP_HOST_TO_SMC_UL(30); | |
793 | } | |
794 | ||
795 | smu_data->smc_state_table.LinkLevelCount = | |
796 | (uint8_t)dpm_table->pcie_speed_table.count; | |
797 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = | |
798 | phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr, | |
804 | uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) | |
805 | { | |
806 | const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
807 | pp_atomctrl_clock_dividers_vi dividers; | |
808 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; | |
809 | uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; | |
810 | uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; | |
811 | uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; | |
812 | uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; | |
813 | uint32_t reference_clock; | |
814 | uint32_t reference_divider; | |
815 | uint32_t fbdiv; | |
816 | int result; | |
817 | ||
818 | /* get the engine clock dividers for this clock value*/ | |
819 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); | |
820 | ||
821 | PP_ASSERT_WITH_CODE(result == 0, | |
822 | "Error retrieving Engine Clock dividers from VBIOS.", return result); | |
823 | ||
824 | /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/ | |
825 | reference_clock = atomctrl_get_reference_clock(hwmgr); | |
826 | ||
827 | reference_divider = 1 + dividers.uc_pll_ref_div; | |
828 | ||
829 | /* low 14 bits is fraction and high 12 bits is divider*/ | |
830 | fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; | |
831 | ||
832 | /* SPLL_FUNC_CNTL setup*/ | |
833 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
834 | CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); | |
835 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
836 | CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); | |
837 | ||
838 | /* SPLL_FUNC_CNTL_3 setup*/ | |
839 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, | |
840 | CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); | |
841 | ||
842 | /* set to use fractional accumulation*/ | |
843 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, | |
844 | CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); | |
845 | ||
846 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
847 | PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { | |
848 | pp_atomctrl_internal_ss_info ss_info; | |
849 | ||
850 | uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; | |
851 | if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { | |
852 | /* | |
853 | * ss_info.speed_spectrum_percentage -- in unit of 0.01% | |
854 | * ss_info.speed_spectrum_rate -- in unit of khz | |
855 | */ | |
856 | /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */ | |
857 | uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); | |
858 | ||
859 | /* clkv = 2 * D * fbdiv / NS */ | |
860 | uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); | |
861 | ||
862 | cg_spll_spread_spectrum = | |
863 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS); | |
864 | cg_spll_spread_spectrum = | |
865 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); | |
866 | cg_spll_spread_spectrum_2 = | |
867 | PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV); | |
868 | } | |
869 | } | |
870 | ||
871 | sclk->SclkFrequency = engine_clock; | |
872 | sclk->CgSpllFuncCntl3 = spll_func_cntl_3; | |
873 | sclk->CgSpllFuncCntl4 = spll_func_cntl_4; | |
874 | sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; | |
875 | sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; | |
876 | sclk->SclkDid = (uint8_t)dividers.pll_post_divider; | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, | |
882 | const struct phm_phase_shedding_limits_table *pl, | |
883 | uint32_t sclk, uint32_t *p_shed) | |
884 | { | |
885 | unsigned int i; | |
886 | ||
887 | /* use the minimum phase shedding */ | |
888 | *p_shed = 1; | |
889 | ||
890 | for (i = 0; i < pl->count; i++) { | |
891 | if (sclk < pl->entries[i].Sclk) { | |
892 | *p_shed = i; | |
893 | break; | |
894 | } | |
895 | } | |
896 | return 0; | |
897 | } | |
898 | ||
899 | static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, | |
900 | uint32_t engine_clock, | |
901 | uint16_t sclk_activity_level_threshold, | |
902 | SMU71_Discrete_GraphicsLevel *graphic_level) | |
903 | { | |
904 | int result; | |
905 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
906 | ||
907 | result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); | |
908 | ||
909 | /* populate graphics levels*/ | |
910 | result = iceland_get_dependency_volt_by_clk(hwmgr, | |
911 | hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, | |
912 | &graphic_level->MinVddc); | |
913 | PP_ASSERT_WITH_CODE((0 == result), | |
4f42a2dd | 914 | "can not find VDDC voltage value for VDDC engine clock dependency table", return result); |
907bfec7 RZ |
915 | |
916 | /* SCLK frequency in units of 10KHz*/ | |
917 | graphic_level->SclkFrequency = engine_clock; | |
918 | graphic_level->MinVddcPhases = 1; | |
919 | ||
920 | if (data->vddc_phase_shed_control) | |
921 | iceland_populate_phase_value_based_on_sclk(hwmgr, | |
922 | hwmgr->dyn_state.vddc_phase_shed_limits_table, | |
923 | engine_clock, | |
924 | &graphic_level->MinVddcPhases); | |
925 | ||
926 | /* Indicates maximum activity level for this performance level. 50% for now*/ | |
927 | graphic_level->ActivityLevel = sclk_activity_level_threshold; | |
928 | ||
929 | graphic_level->CcPwrDynRm = 0; | |
930 | graphic_level->CcPwrDynRm1 = 0; | |
931 | /* this level can be used if activity is high enough.*/ | |
932 | graphic_level->EnabledForActivity = 0; | |
933 | /* this level can be used for throttling.*/ | |
934 | graphic_level->EnabledForThrottle = 1; | |
935 | graphic_level->UpHyst = 0; | |
936 | graphic_level->DownHyst = 100; | |
937 | graphic_level->VoltageDownHyst = 0; | |
938 | graphic_level->PowerThrottle = 0; | |
939 | ||
940 | data->display_timing.min_clock_in_sr = | |
941 | hwmgr->display_config.min_core_set_clock_in_sr; | |
942 | ||
943 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
944 | PHM_PlatformCaps_SclkDeepSleep)) | |
945 | graphic_level->DeepSleepDivId = | |
946 | smu7_get_sleep_divider_id_from_clock(engine_clock, | |
947 | data->display_timing.min_clock_in_sr); | |
948 | ||
949 | /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ | |
950 | graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
951 | ||
952 | if (0 == result) { | |
953 | graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE); | |
954 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases); | |
955 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); | |
956 | CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); | |
957 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); | |
958 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); | |
959 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); | |
960 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); | |
961 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); | |
962 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); | |
963 | } | |
964 | ||
965 | return result; | |
966 | } | |
967 | ||
968 | static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) | |
969 | { | |
970 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
971 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
972 | struct smu7_dpm_table *dpm_table = &data->dpm_table; | |
973 | uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + | |
974 | offsetof(SMU71_Discrete_DpmTable, GraphicsLevel); | |
975 | ||
976 | uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) * | |
977 | SMU71_MAX_LEVELS_GRAPHICS; | |
978 | ||
979 | SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; | |
980 | ||
981 | uint32_t i; | |
982 | uint8_t highest_pcie_level_enabled = 0; | |
983 | uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0; | |
984 | uint8_t count = 0; | |
985 | int result = 0; | |
986 | ||
987 | memset(levels, 0x00, level_array_size); | |
988 | ||
989 | for (i = 0; i < dpm_table->sclk_table.count; i++) { | |
990 | result = iceland_populate_single_graphic_level(hwmgr, | |
991 | dpm_table->sclk_table.dpm_levels[i].value, | |
992 | (uint16_t)smu_data->activity_target[i], | |
993 | &(smu_data->smc_state_table.GraphicsLevel[i])); | |
994 | if (result != 0) | |
995 | return result; | |
996 | ||
997 | /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ | |
998 | if (i > 1) | |
999 | smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; | |
1000 | } | |
1001 | ||
1002 | /* Only enable level 0 for now. */ | |
1003 | smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; | |
1004 | ||
1005 | /* set highest level watermark to high */ | |
1006 | if (dpm_table->sclk_table.count > 1) | |
1007 | smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = | |
1008 | PPSMC_DISPLAY_WATERMARK_HIGH; | |
1009 | ||
1010 | smu_data->smc_state_table.GraphicsDpmLevelCount = | |
1011 | (uint8_t)dpm_table->sclk_table.count; | |
1012 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = | |
1013 | phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); | |
1014 | ||
1015 | while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
1016 | (1 << (highest_pcie_level_enabled + 1))) != 0) { | |
1017 | highest_pcie_level_enabled++; | |
1018 | } | |
1019 | ||
1020 | while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
1021 | (1 << lowest_pcie_level_enabled)) == 0) { | |
1022 | lowest_pcie_level_enabled++; | |
1023 | } | |
1024 | ||
1025 | while ((count < highest_pcie_level_enabled) && | |
1026 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & | |
1027 | (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) { | |
1028 | count++; | |
1029 | } | |
1030 | ||
1031 | mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ? | |
1032 | (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled; | |
1033 | ||
1034 | ||
1035 | /* set pcieDpmLevel to highest_pcie_level_enabled*/ | |
1036 | for (i = 2; i < dpm_table->sclk_table.count; i++) { | |
1037 | smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; | |
1038 | } | |
1039 | ||
1040 | /* set pcieDpmLevel to lowest_pcie_level_enabled*/ | |
1041 | smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; | |
1042 | ||
1043 | /* set pcieDpmLevel to mid_pcie_level_enabled*/ | |
1044 | smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; | |
1045 | ||
1046 | /* level count will send to smc once at init smc table and never change*/ | |
1047 | result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress, | |
1048 | (uint8_t *)levels, (uint32_t)level_array_size, | |
1049 | SMC_RAM_END); | |
1050 | ||
1051 | return result; | |
1052 | } | |
1053 | ||
1054 | static int iceland_calculate_mclk_params( | |
1055 | struct pp_hwmgr *hwmgr, | |
1056 | uint32_t memory_clock, | |
1057 | SMU71_Discrete_MemoryLevel *mclk, | |
1058 | bool strobe_mode, | |
1059 | bool dllStateOn | |
1060 | ) | |
1061 | { | |
1062 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1063 | ||
1064 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; | |
1065 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; | |
1066 | uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; | |
1067 | uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; | |
1068 | uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; | |
1069 | uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; | |
1070 | uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; | |
1071 | uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; | |
1072 | uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; | |
1073 | ||
1074 | pp_atomctrl_memory_clock_param mpll_param; | |
1075 | int result; | |
1076 | ||
1077 | result = atomctrl_get_memory_pll_dividers_si(hwmgr, | |
1078 | memory_clock, &mpll_param, strobe_mode); | |
1079 | PP_ASSERT_WITH_CODE(0 == result, | |
1080 | "Error retrieving Memory Clock Parameters from VBIOS.", return result); | |
1081 | ||
1082 | /* MPLL_FUNC_CNTL setup*/ | |
1083 | mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); | |
1084 | ||
1085 | /* MPLL_FUNC_CNTL_1 setup*/ | |
1086 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1087 | MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); | |
1088 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1089 | MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); | |
1090 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, | |
1091 | MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); | |
1092 | ||
1093 | /* MPLL_AD_FUNC_CNTL setup*/ | |
1094 | mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl, | |
1095 | MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); | |
1096 | ||
1097 | if (data->is_memory_gddr5) { | |
1098 | /* MPLL_DQ_FUNC_CNTL setup*/ | |
1099 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, | |
1100 | MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); | |
1101 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, | |
1102 | MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); | |
1103 | } | |
1104 | ||
1105 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
1106 | PHM_PlatformCaps_MemorySpreadSpectrumSupport)) { | |
1107 | /* | |
1108 | ************************************ | |
1109 | Fref = Reference Frequency | |
1110 | NF = Feedback divider ratio | |
1111 | NR = Reference divider ratio | |
1112 | Fnom = Nominal VCO output frequency = Fref * NF / NR | |
1113 | Fs = Spreading Rate | |
1114 | D = Percentage down-spread / 2 | |
1115 | Fint = Reference input frequency to PFD = Fref / NR | |
1116 | NS = Spreading rate divider ratio = int(Fint / (2 * Fs)) | |
1117 | CLKS = NS - 1 = ISS_STEP_NUM[11:0] | |
1118 | NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2) | |
1119 | CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] | |
1120 | ************************************* | |
1121 | */ | |
1122 | pp_atomctrl_internal_ss_info ss_info; | |
1123 | uint32_t freq_nom; | |
1124 | uint32_t tmp; | |
1125 | uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); | |
1126 | ||
1127 | /* for GDDR5 for all modes and DDR3 */ | |
1128 | if (1 == mpll_param.qdr) | |
1129 | freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); | |
1130 | else | |
1131 | freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); | |
1132 | ||
1133 | /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/ | |
1134 | tmp = (freq_nom / reference_clock); | |
1135 | tmp = tmp * tmp; | |
1136 | ||
1137 | if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { | |
1138 | /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */ | |
1139 | /* ss.Info.speed_spectrum_rate -- in unit of khz */ | |
1140 | /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */ | |
1141 | /* = reference_clock * 5 / speed_spectrum_rate */ | |
1142 | uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; | |
1143 | ||
1144 | /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */ | |
1145 | /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */ | |
1146 | uint32_t clkv = | |
1147 | (uint32_t)((((131 * ss_info.speed_spectrum_percentage * | |
1148 | ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom); | |
1149 | ||
1150 | mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); | |
1151 | mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | /* MCLK_PWRMGT_CNTL setup */ | |
1156 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1157 | MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); | |
1158 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1159 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); | |
1160 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1161 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); | |
1162 | ||
1163 | ||
1164 | /* Save the result data to outpupt memory level structure */ | |
1165 | mclk->MclkFrequency = memory_clock; | |
1166 | mclk->MpllFuncCntl = mpll_func_cntl; | |
1167 | mclk->MpllFuncCntl_1 = mpll_func_cntl_1; | |
1168 | mclk->MpllFuncCntl_2 = mpll_func_cntl_2; | |
1169 | mclk->MpllAdFuncCntl = mpll_ad_func_cntl; | |
1170 | mclk->MpllDqFuncCntl = mpll_dq_func_cntl; | |
1171 | mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; | |
1172 | mclk->DllCntl = dll_cntl; | |
1173 | mclk->MpllSs1 = mpll_ss1; | |
1174 | mclk->MpllSs2 = mpll_ss2; | |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, | |
1180 | bool strobe_mode) | |
1181 | { | |
1182 | uint8_t mc_para_index; | |
1183 | ||
1184 | if (strobe_mode) { | |
1185 | if (memory_clock < 12500) { | |
1186 | mc_para_index = 0x00; | |
1187 | } else if (memory_clock > 47500) { | |
1188 | mc_para_index = 0x0f; | |
1189 | } else { | |
1190 | mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); | |
1191 | } | |
1192 | } else { | |
1193 | if (memory_clock < 65000) { | |
1194 | mc_para_index = 0x00; | |
1195 | } else if (memory_clock > 135000) { | |
1196 | mc_para_index = 0x0f; | |
1197 | } else { | |
1198 | mc_para_index = (uint8_t)((memory_clock - 60000) / 5000); | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | return mc_para_index; | |
1203 | } | |
1204 | ||
1205 | static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) | |
1206 | { | |
1207 | uint8_t mc_para_index; | |
1208 | ||
1209 | if (memory_clock < 10000) { | |
1210 | mc_para_index = 0; | |
1211 | } else if (memory_clock >= 80000) { | |
1212 | mc_para_index = 0x0f; | |
1213 | } else { | |
1214 | mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1); | |
1215 | } | |
1216 | ||
1217 | return mc_para_index; | |
1218 | } | |
1219 | ||
1220 | static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, | |
1221 | uint32_t memory_clock, uint32_t *p_shed) | |
1222 | { | |
1223 | unsigned int i; | |
1224 | ||
1225 | *p_shed = 1; | |
1226 | ||
1227 | for (i = 0; i < pl->count; i++) { | |
1228 | if (memory_clock < pl->entries[i].Mclk) { | |
1229 | *p_shed = i; | |
1230 | break; | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | static int iceland_populate_single_memory_level( | |
1238 | struct pp_hwmgr *hwmgr, | |
1239 | uint32_t memory_clock, | |
1240 | SMU71_Discrete_MemoryLevel *memory_level | |
1241 | ) | |
1242 | { | |
1243 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1244 | int result = 0; | |
1245 | bool dll_state_on; | |
1246 | struct cgs_display_info info = {0}; | |
1247 | uint32_t mclk_edc_wr_enable_threshold = 40000; | |
1248 | uint32_t mclk_edc_enable_threshold = 40000; | |
1249 | uint32_t mclk_strobe_mode_threshold = 40000; | |
1250 | ||
1251 | if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { | |
1252 | result = iceland_get_dependency_volt_by_clk(hwmgr, | |
1253 | hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); | |
1254 | PP_ASSERT_WITH_CODE((0 == result), | |
1255 | "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); | |
1256 | } | |
1257 | ||
1258 | if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) { | |
1259 | memory_level->MinVddci = memory_level->MinVddc; | |
1260 | } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { | |
1261 | result = iceland_get_dependency_volt_by_clk(hwmgr, | |
1262 | hwmgr->dyn_state.vddci_dependency_on_mclk, | |
1263 | memory_clock, | |
1264 | &memory_level->MinVddci); | |
1265 | PP_ASSERT_WITH_CODE((0 == result), | |
1266 | "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result); | |
1267 | } | |
1268 | ||
1269 | memory_level->MinVddcPhases = 1; | |
1270 | ||
1271 | if (data->vddc_phase_shed_control) { | |
1272 | iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table, | |
1273 | memory_clock, &memory_level->MinVddcPhases); | |
1274 | } | |
1275 | ||
1276 | memory_level->EnabledForThrottle = 1; | |
1277 | memory_level->EnabledForActivity = 0; | |
1278 | memory_level->UpHyst = 0; | |
1279 | memory_level->DownHyst = 100; | |
1280 | memory_level->VoltageDownHyst = 0; | |
1281 | ||
1282 | /* Indicates maximum activity level for this performance level.*/ | |
1283 | memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target; | |
1284 | memory_level->StutterEnable = 0; | |
1285 | memory_level->StrobeEnable = 0; | |
1286 | memory_level->EdcReadEnable = 0; | |
1287 | memory_level->EdcWriteEnable = 0; | |
1288 | memory_level->RttEnable = 0; | |
1289 | ||
1290 | /* default set to low watermark. Highest level will be set to high later.*/ | |
1291 | memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
1292 | ||
1293 | cgs_get_active_displays_info(hwmgr->device, &info); | |
1294 | data->display_timing.num_existing_displays = info.display_count; | |
1295 | ||
1296 | /* stutter mode not support on iceland */ | |
1297 | ||
1298 | /* decide strobe mode*/ | |
1299 | memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && | |
1300 | (memory_clock <= mclk_strobe_mode_threshold); | |
1301 | ||
1302 | /* decide EDC mode and memory clock ratio*/ | |
1303 | if (data->is_memory_gddr5) { | |
1304 | memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock, | |
1305 | memory_level->StrobeEnable); | |
1306 | ||
1307 | if ((mclk_edc_enable_threshold != 0) && | |
1308 | (memory_clock > mclk_edc_enable_threshold)) { | |
1309 | memory_level->EdcReadEnable = 1; | |
1310 | } | |
1311 | ||
1312 | if ((mclk_edc_wr_enable_threshold != 0) && | |
1313 | (memory_clock > mclk_edc_wr_enable_threshold)) { | |
1314 | memory_level->EdcWriteEnable = 1; | |
1315 | } | |
1316 | ||
1317 | if (memory_level->StrobeEnable) { | |
1318 | if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >= | |
1319 | ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) | |
1320 | dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; | |
1321 | else | |
1322 | dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; | |
1323 | } else | |
1324 | dll_state_on = data->dll_default_on; | |
1325 | } else { | |
1326 | memory_level->StrobeRatio = | |
1327 | iceland_get_ddr3_mclk_frequency_ratio(memory_clock); | |
1328 | dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; | |
1329 | } | |
1330 | ||
1331 | result = iceland_calculate_mclk_params(hwmgr, | |
1332 | memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); | |
1333 | ||
1334 | if (0 == result) { | |
1335 | memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE); | |
1336 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); | |
1337 | memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE); | |
1338 | memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE); | |
1339 | /* MCLK frequency in units of 10KHz*/ | |
1340 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); | |
1341 | /* Indicates maximum activity level for this performance level.*/ | |
1342 | CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); | |
1343 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); | |
1344 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); | |
1345 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); | |
1346 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); | |
1347 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); | |
1348 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); | |
1349 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); | |
1350 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); | |
1351 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); | |
1352 | } | |
1353 | ||
1354 | return result; | |
1355 | } | |
1356 | ||
1357 | static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr) | |
1358 | { | |
1359 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1360 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1361 | struct smu7_dpm_table *dpm_table = &data->dpm_table; | |
1362 | int result; | |
1363 | ||
1364 | /* populate MCLK dpm table to SMU7 */ | |
1365 | uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel); | |
1366 | uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY; | |
1367 | SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; | |
1368 | uint32_t i; | |
1369 | ||
1370 | memset(levels, 0x00, level_array_size); | |
1371 | ||
1372 | for (i = 0; i < dpm_table->mclk_table.count; i++) { | |
1373 | PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), | |
1374 | "can not populate memory level as memory clock is zero", return -EINVAL); | |
1375 | result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, | |
1376 | &(smu_data->smc_state_table.MemoryLevel[i])); | |
1377 | if (0 != result) { | |
1378 | return result; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | /* Only enable level 0 for now.*/ | |
1383 | smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; | |
1384 | ||
1385 | /* | |
1386 | * in order to prevent MC activity from stutter mode to push DPM up. | |
1387 | * the UVD change complements this by putting the MCLK in a higher state | |
1388 | * by default such that we are not effected by up threshold or and MCLK DPM latency. | |
1389 | */ | |
1390 | smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; | |
1391 | CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); | |
1392 | ||
1393 | smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; | |
1394 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); | |
1395 | /* set highest level watermark to high*/ | |
1396 | smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; | |
1397 | ||
1398 | /* level count will send to smc once at init smc table and never change*/ | |
1399 | result = smu7_copy_bytes_to_smc(hwmgr, | |
1400 | level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, | |
1401 | SMC_RAM_END); | |
1402 | ||
1403 | return result; | |
1404 | } | |
1405 | ||
1406 | static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, | |
1407 | SMU71_Discrete_VoltageLevel *voltage) | |
1408 | { | |
1409 | const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1410 | ||
1411 | uint32_t i = 0; | |
1412 | ||
1413 | if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { | |
1414 | /* find mvdd value which clock is more than request */ | |
1415 | for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { | |
1416 | if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { | |
1417 | /* Always round to higher voltage. */ | |
1418 | voltage->Voltage = data->mvdd_voltage_table.entries[i].value; | |
1419 | break; | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, | |
1424 | "MVDD Voltage is outside the supported range.", return -EINVAL); | |
1425 | ||
1426 | } else { | |
1427 | return -EINVAL; | |
1428 | } | |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
1433 | static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, | |
1434 | SMU71_Discrete_DpmTable *table) | |
1435 | { | |
1436 | int result = 0; | |
1437 | const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1438 | struct pp_atomctrl_clock_dividers_vi dividers; | |
1439 | uint32_t vddc_phase_shed_control = 0; | |
1440 | ||
1441 | SMU71_Discrete_VoltageLevel voltage_level; | |
1442 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; | |
1443 | uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; | |
1444 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; | |
1445 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; | |
1446 | ||
1447 | ||
1448 | /* The ACPI state should not do DPM on DC (or ever).*/ | |
1449 | table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; | |
1450 | ||
1451 | if (data->acpi_vddc) | |
1452 | table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); | |
1453 | else | |
1454 | table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); | |
1455 | ||
1456 | table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1; | |
1457 | /* assign zero for now*/ | |
1458 | table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); | |
1459 | ||
1460 | /* get the engine clock dividers for this clock value*/ | |
1461 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, | |
1462 | table->ACPILevel.SclkFrequency, ÷rs); | |
1463 | ||
1464 | PP_ASSERT_WITH_CODE(result == 0, | |
1465 | "Error retrieving Engine Clock dividers from VBIOS.", return result); | |
1466 | ||
1467 | /* divider ID for required SCLK*/ | |
1468 | table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; | |
1469 | table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; | |
1470 | table->ACPILevel.DeepSleepDivId = 0; | |
1471 | ||
1472 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
1473 | CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); | |
1474 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, | |
1475 | CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); | |
1476 | spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, | |
1477 | CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); | |
1478 | ||
1479 | table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; | |
1480 | table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; | |
1481 | table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; | |
1482 | table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; | |
1483 | table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; | |
1484 | table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; | |
1485 | table->ACPILevel.CcPwrDynRm = 0; | |
1486 | table->ACPILevel.CcPwrDynRm1 = 0; | |
1487 | ||
1488 | ||
1489 | /* For various features to be enabled/disabled while this level is active.*/ | |
1490 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); | |
1491 | /* SCLK frequency in units of 10KHz*/ | |
1492 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); | |
1493 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); | |
1494 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); | |
1495 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); | |
1496 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); | |
1497 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); | |
1498 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); | |
1499 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); | |
1500 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); | |
1501 | ||
1502 | /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ | |
1503 | table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; | |
1504 | table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; | |
1505 | ||
1506 | if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control) | |
1507 | table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc; | |
1508 | else { | |
1509 | if (data->acpi_vddci != 0) | |
1510 | table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE); | |
1511 | else | |
1512 | table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE); | |
1513 | } | |
1514 | ||
1515 | if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level)) | |
1516 | table->MemoryACPILevel.MinMvdd = | |
1517 | PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); | |
1518 | else | |
1519 | table->MemoryACPILevel.MinMvdd = 0; | |
1520 | ||
1521 | /* Force reset on DLL*/ | |
1522 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1523 | MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); | |
1524 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1525 | MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); | |
1526 | ||
1527 | /* Disable DLL in ACPIState*/ | |
1528 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1529 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); | |
1530 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, | |
1531 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); | |
1532 | ||
1533 | /* Enable DLL bypass signal*/ | |
1534 | dll_cntl = PHM_SET_FIELD(dll_cntl, | |
1535 | DLL_CNTL, MRDCK0_BYPASS, 0); | |
1536 | dll_cntl = PHM_SET_FIELD(dll_cntl, | |
1537 | DLL_CNTL, MRDCK1_BYPASS, 0); | |
1538 | ||
1539 | table->MemoryACPILevel.DllCntl = | |
1540 | PP_HOST_TO_SMC_UL(dll_cntl); | |
1541 | table->MemoryACPILevel.MclkPwrmgtCntl = | |
1542 | PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); | |
1543 | table->MemoryACPILevel.MpllAdFuncCntl = | |
1544 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); | |
1545 | table->MemoryACPILevel.MpllDqFuncCntl = | |
1546 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); | |
1547 | table->MemoryACPILevel.MpllFuncCntl = | |
1548 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); | |
1549 | table->MemoryACPILevel.MpllFuncCntl_1 = | |
1550 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); | |
1551 | table->MemoryACPILevel.MpllFuncCntl_2 = | |
1552 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); | |
1553 | table->MemoryACPILevel.MpllSs1 = | |
1554 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); | |
1555 | table->MemoryACPILevel.MpllSs2 = | |
1556 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); | |
1557 | ||
1558 | table->MemoryACPILevel.EnabledForThrottle = 0; | |
1559 | table->MemoryACPILevel.EnabledForActivity = 0; | |
1560 | table->MemoryACPILevel.UpHyst = 0; | |
1561 | table->MemoryACPILevel.DownHyst = 100; | |
1562 | table->MemoryACPILevel.VoltageDownHyst = 0; | |
1563 | /* Indicates maximum activity level for this performance level.*/ | |
1564 | table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); | |
1565 | ||
1566 | table->MemoryACPILevel.StutterEnable = 0; | |
1567 | table->MemoryACPILevel.StrobeEnable = 0; | |
1568 | table->MemoryACPILevel.EdcReadEnable = 0; | |
1569 | table->MemoryACPILevel.EdcWriteEnable = 0; | |
1570 | table->MemoryACPILevel.RttEnable = 0; | |
1571 | ||
1572 | return result; | |
1573 | } | |
1574 | ||
1575 | static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, | |
1576 | SMU71_Discrete_DpmTable *table) | |
1577 | { | |
1578 | return 0; | |
1579 | } | |
1580 | ||
1581 | static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr, | |
1582 | SMU71_Discrete_DpmTable *table) | |
1583 | { | |
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr, | |
1588 | SMU71_Discrete_DpmTable *table) | |
1589 | { | |
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr, | |
1594 | SMU71_Discrete_DpmTable *table) | |
1595 | { | |
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | static int iceland_populate_memory_timing_parameters( | |
1600 | struct pp_hwmgr *hwmgr, | |
1601 | uint32_t engine_clock, | |
1602 | uint32_t memory_clock, | |
1603 | struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs | |
1604 | ) | |
1605 | { | |
1606 | uint32_t dramTiming; | |
1607 | uint32_t dramTiming2; | |
1608 | uint32_t burstTime; | |
1609 | int result; | |
1610 | ||
1611 | result = atomctrl_set_engine_dram_timings_rv770(hwmgr, | |
1612 | engine_clock, memory_clock); | |
1613 | ||
1614 | PP_ASSERT_WITH_CODE(result == 0, | |
1615 | "Error calling VBIOS to set DRAM_TIMING.", return result); | |
1616 | ||
1617 | dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); | |
1618 | dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); | |
1619 | burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); | |
1620 | ||
1621 | arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); | |
1622 | arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); | |
1623 | arb_regs->McArbBurstTime = (uint8_t)burstTime; | |
1624 | ||
1625 | return 0; | |
1626 | } | |
1627 | ||
1628 | static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) | |
1629 | { | |
1630 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1631 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1632 | int result = 0; | |
1633 | SMU71_Discrete_MCArbDramTimingTable arb_regs; | |
1634 | uint32_t i, j; | |
1635 | ||
1636 | memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable)); | |
1637 | ||
1638 | for (i = 0; i < data->dpm_table.sclk_table.count; i++) { | |
1639 | for (j = 0; j < data->dpm_table.mclk_table.count; j++) { | |
1640 | result = iceland_populate_memory_timing_parameters | |
1641 | (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, | |
1642 | data->dpm_table.mclk_table.dpm_levels[j].value, | |
1643 | &arb_regs.entries[i][j]); | |
1644 | ||
1645 | if (0 != result) { | |
1646 | break; | |
1647 | } | |
1648 | } | |
1649 | } | |
1650 | ||
1651 | if (0 == result) { | |
1652 | result = smu7_copy_bytes_to_smc( | |
1653 | hwmgr, | |
1654 | smu_data->smu7_data.arb_table_start, | |
1655 | (uint8_t *)&arb_regs, | |
1656 | sizeof(SMU71_Discrete_MCArbDramTimingTable), | |
1657 | SMC_RAM_END | |
1658 | ); | |
1659 | } | |
1660 | ||
1661 | return result; | |
1662 | } | |
1663 | ||
1664 | static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, | |
1665 | SMU71_Discrete_DpmTable *table) | |
1666 | { | |
1667 | int result = 0; | |
1668 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1669 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1670 | table->GraphicsBootLevel = 0; | |
1671 | table->MemoryBootLevel = 0; | |
1672 | ||
1673 | /* find boot level from dpm table*/ | |
1674 | result = phm_find_boot_level(&(data->dpm_table.sclk_table), | |
1675 | data->vbios_boot_state.sclk_bootup_value, | |
1676 | (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); | |
1677 | ||
1678 | if (0 != result) { | |
1679 | smu_data->smc_state_table.GraphicsBootLevel = 0; | |
4f42a2dd | 1680 | pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); |
907bfec7 RZ |
1681 | result = 0; |
1682 | } | |
1683 | ||
1684 | result = phm_find_boot_level(&(data->dpm_table.mclk_table), | |
1685 | data->vbios_boot_state.mclk_bootup_value, | |
1686 | (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); | |
1687 | ||
1688 | if (0 != result) { | |
1689 | smu_data->smc_state_table.MemoryBootLevel = 0; | |
4f42a2dd | 1690 | pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); |
907bfec7 RZ |
1691 | result = 0; |
1692 | } | |
1693 | ||
1694 | table->BootVddc = data->vbios_boot_state.vddc_bootup_value; | |
1695 | if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control) | |
1696 | table->BootVddci = table->BootVddc; | |
1697 | else | |
1698 | table->BootVddci = data->vbios_boot_state.vddci_bootup_value; | |
1699 | ||
1700 | table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; | |
1701 | ||
1702 | return result; | |
1703 | } | |
1704 | ||
1705 | static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, | |
1706 | SMU71_Discrete_MCRegisters *mc_reg_table) | |
1707 | { | |
1708 | const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend; | |
1709 | ||
1710 | uint32_t i, j; | |
1711 | ||
1712 | for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { | |
1713 | if (smu_data->mc_reg_table.validflag & 1<<j) { | |
1714 | PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE, | |
1715 | "Index of mc_reg_table->address[] array out of boundary", return -EINVAL); | |
1716 | mc_reg_table->address[i].s0 = | |
1717 | PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); | |
1718 | mc_reg_table->address[i].s1 = | |
1719 | PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); | |
1720 | i++; | |
1721 | } | |
1722 | } | |
1723 | ||
1724 | mc_reg_table->last = (uint8_t)i; | |
1725 | ||
1726 | return 0; | |
1727 | } | |
1728 | ||
1729 | /*convert register values from driver to SMC format */ | |
1730 | static void iceland_convert_mc_registers( | |
1731 | const struct iceland_mc_reg_entry *entry, | |
1732 | SMU71_Discrete_MCRegisterSet *data, | |
1733 | uint32_t num_entries, uint32_t valid_flag) | |
1734 | { | |
1735 | uint32_t i, j; | |
1736 | ||
1737 | for (i = 0, j = 0; j < num_entries; j++) { | |
1738 | if (valid_flag & 1<<j) { | |
1739 | data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]); | |
1740 | i++; | |
1741 | } | |
1742 | } | |
1743 | } | |
1744 | ||
1745 | static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr, | |
1746 | const uint32_t memory_clock, | |
1747 | SMU71_Discrete_MCRegisterSet *mc_reg_table_data | |
1748 | ) | |
1749 | { | |
1750 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1751 | uint32_t i = 0; | |
1752 | ||
1753 | for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { | |
1754 | if (memory_clock <= | |
1755 | smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) { | |
1756 | break; | |
1757 | } | |
1758 | } | |
1759 | ||
1760 | if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) | |
1761 | --i; | |
1762 | ||
1763 | iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i], | |
1764 | mc_reg_table_data, smu_data->mc_reg_table.last, | |
1765 | smu_data->mc_reg_table.validflag); | |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, | |
1771 | SMU71_Discrete_MCRegisters *mc_regs) | |
1772 | { | |
1773 | int result = 0; | |
1774 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1775 | int res; | |
1776 | uint32_t i; | |
1777 | ||
1778 | for (i = 0; i < data->dpm_table.mclk_table.count; i++) { | |
1779 | res = iceland_convert_mc_reg_table_entry_to_smc( | |
1780 | hwmgr, | |
1781 | data->dpm_table.mclk_table.dpm_levels[i].value, | |
1782 | &mc_regs->data[i] | |
1783 | ); | |
1784 | ||
1785 | if (0 != res) | |
1786 | result = res; | |
1787 | } | |
1788 | ||
1789 | return result; | |
1790 | } | |
1791 | ||
1792 | static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) | |
1793 | { | |
1794 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1795 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1796 | uint32_t address; | |
1797 | int32_t result; | |
1798 | ||
1799 | if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) | |
1800 | return 0; | |
1801 | ||
1802 | ||
1803 | memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters)); | |
1804 | ||
1805 | result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs)); | |
1806 | ||
1807 | if (result != 0) | |
1808 | return result; | |
1809 | ||
1810 | ||
1811 | address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]); | |
1812 | ||
1813 | return smu7_copy_bytes_to_smc(hwmgr, address, | |
1814 | (uint8_t *)&smu_data->mc_regs.data[0], | |
1815 | sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, | |
1816 | SMC_RAM_END); | |
1817 | } | |
1818 | ||
1819 | static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) | |
1820 | { | |
1821 | int result; | |
1822 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1823 | ||
1824 | memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters)); | |
1825 | result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); | |
1826 | PP_ASSERT_WITH_CODE(0 == result, | |
1827 | "Failed to initialize MCRegTable for the MC register addresses!", return result;); | |
1828 | ||
1829 | result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs); | |
1830 | PP_ASSERT_WITH_CODE(0 == result, | |
1831 | "Failed to initialize MCRegTable for driver state!", return result;); | |
1832 | ||
1833 | return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start, | |
1834 | (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END); | |
1835 | } | |
1836 | ||
1837 | static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) | |
1838 | { | |
1839 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1840 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1841 | uint8_t count, level; | |
1842 | ||
1843 | count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); | |
1844 | ||
1845 | for (level = 0; level < count; level++) { | |
1846 | if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk | |
1847 | >= data->vbios_boot_state.sclk_bootup_value) { | |
1848 | smu_data->smc_state_table.GraphicsBootLevel = level; | |
1849 | break; | |
1850 | } | |
1851 | } | |
1852 | ||
1853 | count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); | |
1854 | ||
1855 | for (level = 0; level < count; level++) { | |
1856 | if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk | |
1857 | >= data->vbios_boot_state.mclk_bootup_value) { | |
1858 | smu_data->smc_state_table.MemoryBootLevel = level; | |
1859 | break; | |
1860 | } | |
1861 | } | |
1862 | ||
1863 | return 0; | |
1864 | } | |
1865 | ||
1866 | static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) | |
1867 | { | |
1868 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1869 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1870 | const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; | |
1871 | SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); | |
1872 | struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; | |
1873 | struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; | |
1874 | const uint16_t *def1, *def2; | |
1875 | int i, j, k; | |
1876 | ||
1877 | ||
1878 | /* | |
1879 | * TDP number of fraction bits are changed from 8 to 7 for Iceland | |
1880 | * as requested by SMC team | |
1881 | */ | |
1882 | ||
1883 | dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); | |
1884 | dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); | |
1885 | ||
1886 | ||
1887 | dpm_table->DTETjOffset = 0; | |
1888 | ||
1889 | dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES); | |
1890 | dpm_table->GpuTjHyst = 8; | |
1891 | ||
1892 | dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base; | |
1893 | ||
1894 | /* The following are for new Iceland Multi-input fan/thermal control */ | |
1895 | if (NULL != ppm) { | |
1896 | dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000; | |
1897 | dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256; | |
1898 | } else { | |
1899 | dpm_table->PPM_PkgPwrLimit = 0; | |
1900 | dpm_table->PPM_TemperatureLimit = 0; | |
1901 | } | |
1902 | ||
1903 | CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit); | |
1904 | CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit); | |
1905 | ||
1906 | dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); | |
1907 | def1 = defaults->bapmti_r; | |
1908 | def2 = defaults->bapmti_rc; | |
1909 | ||
1910 | for (i = 0; i < SMU71_DTE_ITERATIONS; i++) { | |
1911 | for (j = 0; j < SMU71_DTE_SOURCES; j++) { | |
1912 | for (k = 0; k < SMU71_DTE_SINKS; k++) { | |
1913 | dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1); | |
1914 | dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2); | |
1915 | def1++; | |
1916 | def2++; | |
1917 | } | |
1918 | } | |
1919 | } | |
1920 | ||
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr, | |
1925 | SMU71_Discrete_DpmTable *tab) | |
1926 | { | |
1927 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1928 | ||
1929 | if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) | |
1930 | tab->SVI2Enable |= VDDC_ON_SVI2; | |
1931 | ||
1932 | if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) | |
1933 | tab->SVI2Enable |= VDDCI_ON_SVI2; | |
1934 | else | |
1935 | tab->MergedVddci = 1; | |
1936 | ||
1937 | if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) | |
1938 | tab->SVI2Enable |= MVDD_ON_SVI2; | |
1939 | ||
1940 | PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) && | |
1941 | (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL); | |
1942 | ||
1943 | return 0; | |
1944 | } | |
1945 | ||
1946 | static int iceland_init_smc_table(struct pp_hwmgr *hwmgr) | |
1947 | { | |
1948 | int result; | |
1949 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
1950 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
1951 | SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table); | |
1952 | ||
1953 | ||
1954 | iceland_initialize_power_tune_defaults(hwmgr); | |
1955 | memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); | |
1956 | ||
1957 | if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) { | |
1958 | iceland_populate_smc_voltage_tables(hwmgr, table); | |
1959 | } | |
1960 | ||
1961 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
1962 | PHM_PlatformCaps_AutomaticDCTransition)) | |
1963 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; | |
1964 | ||
1965 | ||
1966 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
1967 | PHM_PlatformCaps_StepVddc)) | |
1968 | table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; | |
1969 | ||
1970 | if (data->is_memory_gddr5) | |
1971 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; | |
1972 | ||
1973 | ||
1974 | if (data->ulv_supported) { | |
1975 | result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting)); | |
1976 | PP_ASSERT_WITH_CODE(0 == result, | |
1977 | "Failed to initialize ULV state!", return result;); | |
1978 | ||
1979 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, | |
1980 | ixCG_ULV_PARAMETER, 0x40035); | |
1981 | } | |
1982 | ||
1983 | result = iceland_populate_smc_link_level(hwmgr, table); | |
1984 | PP_ASSERT_WITH_CODE(0 == result, | |
1985 | "Failed to initialize Link Level!", return result;); | |
1986 | ||
1987 | result = iceland_populate_all_graphic_levels(hwmgr); | |
1988 | PP_ASSERT_WITH_CODE(0 == result, | |
1989 | "Failed to initialize Graphics Level!", return result;); | |
1990 | ||
1991 | result = iceland_populate_all_memory_levels(hwmgr); | |
1992 | PP_ASSERT_WITH_CODE(0 == result, | |
1993 | "Failed to initialize Memory Level!", return result;); | |
1994 | ||
1995 | result = iceland_populate_smc_acpi_level(hwmgr, table); | |
1996 | PP_ASSERT_WITH_CODE(0 == result, | |
1997 | "Failed to initialize ACPI Level!", return result;); | |
1998 | ||
1999 | result = iceland_populate_smc_vce_level(hwmgr, table); | |
2000 | PP_ASSERT_WITH_CODE(0 == result, | |
2001 | "Failed to initialize VCE Level!", return result;); | |
2002 | ||
2003 | result = iceland_populate_smc_acp_level(hwmgr, table); | |
2004 | PP_ASSERT_WITH_CODE(0 == result, | |
2005 | "Failed to initialize ACP Level!", return result;); | |
2006 | ||
2007 | result = iceland_populate_smc_samu_level(hwmgr, table); | |
2008 | PP_ASSERT_WITH_CODE(0 == result, | |
2009 | "Failed to initialize SAMU Level!", return result;); | |
2010 | ||
2011 | /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */ | |
2012 | /* need to populate the ARB settings for the initial state. */ | |
2013 | result = iceland_program_memory_timing_parameters(hwmgr); | |
2014 | PP_ASSERT_WITH_CODE(0 == result, | |
2015 | "Failed to Write ARB settings for the initial state.", return result;); | |
2016 | ||
2017 | result = iceland_populate_smc_uvd_level(hwmgr, table); | |
2018 | PP_ASSERT_WITH_CODE(0 == result, | |
2019 | "Failed to initialize UVD Level!", return result;); | |
2020 | ||
2021 | table->GraphicsBootLevel = 0; | |
2022 | table->MemoryBootLevel = 0; | |
2023 | ||
2024 | result = iceland_populate_smc_boot_level(hwmgr, table); | |
2025 | PP_ASSERT_WITH_CODE(0 == result, | |
2026 | "Failed to initialize Boot Level!", return result;); | |
2027 | ||
2028 | result = iceland_populate_smc_initial_state(hwmgr); | |
2029 | PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); | |
2030 | ||
2031 | result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr); | |
2032 | PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); | |
2033 | ||
2034 | table->GraphicsVoltageChangeEnable = 1; | |
2035 | table->GraphicsThermThrottleEnable = 1; | |
2036 | table->GraphicsInterval = 1; | |
2037 | table->VoltageInterval = 1; | |
2038 | table->ThermalInterval = 1; | |
2039 | ||
2040 | table->TemperatureLimitHigh = | |
2041 | (data->thermal_temp_setting.temperature_high * | |
2042 | SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
2043 | table->TemperatureLimitLow = | |
2044 | (data->thermal_temp_setting.temperature_low * | |
2045 | SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
2046 | ||
2047 | table->MemoryVoltageChangeEnable = 1; | |
2048 | table->MemoryInterval = 1; | |
2049 | table->VoltageResponseTime = 0; | |
2050 | table->PhaseResponseTime = 0; | |
2051 | table->MemoryThermThrottleEnable = 1; | |
2052 | table->PCIeBootLinkLevel = 0; | |
2053 | table->PCIeGenInterval = 1; | |
2054 | ||
2055 | result = iceland_populate_smc_svi2_config(hwmgr, table); | |
2056 | PP_ASSERT_WITH_CODE(0 == result, | |
2057 | "Failed to populate SVI2 setting!", return result); | |
2058 | ||
2059 | table->ThermGpio = 17; | |
2060 | table->SclkStepSize = 0x4000; | |
2061 | ||
2062 | CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); | |
2063 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid); | |
2064 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase); | |
2065 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid); | |
2066 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid); | |
2067 | CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); | |
2068 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); | |
2069 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); | |
2070 | CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); | |
2071 | CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); | |
2072 | ||
2073 | table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE); | |
2074 | table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE); | |
2075 | table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); | |
2076 | ||
2077 | /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ | |
2078 | result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start + | |
2079 | offsetof(SMU71_Discrete_DpmTable, SystemFlags), | |
2080 | (uint8_t *)&(table->SystemFlags), | |
2081 | sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController), | |
2082 | SMC_RAM_END); | |
2083 | ||
2084 | PP_ASSERT_WITH_CODE(0 == result, | |
2085 | "Failed to upload dpm data to SMC memory!", return result;); | |
2086 | ||
2087 | /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */ | |
2088 | result = smu7_copy_bytes_to_smc(hwmgr, | |
2089 | smu_data->smu7_data.ulv_setting_starts, | |
2090 | (uint8_t *)&(smu_data->ulv_setting), | |
2091 | sizeof(SMU71_Discrete_Ulv), | |
2092 | SMC_RAM_END); | |
2093 | ||
2094 | ||
2095 | result = iceland_populate_initial_mc_reg_table(hwmgr); | |
2096 | PP_ASSERT_WITH_CODE((0 == result), | |
2097 | "Failed to populate initialize MC Reg table!", return result); | |
2098 | ||
2099 | result = iceland_populate_pm_fuses(hwmgr); | |
2100 | PP_ASSERT_WITH_CODE(0 == result, | |
2101 | "Failed to populate PM fuses to SMC memory!", return result); | |
2102 | ||
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) | |
2107 | { | |
2108 | struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); | |
2109 | SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; | |
2110 | uint32_t duty100; | |
2111 | uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; | |
2112 | uint16_t fdo_min, slope1, slope2; | |
2113 | uint32_t reference_clock; | |
2114 | int res; | |
2115 | uint64_t tmp64; | |
2116 | ||
2117 | if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) | |
2118 | return 0; | |
2119 | ||
2120 | if (hwmgr->thermal_controller.fanInfo.bNoFan) { | |
2121 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | |
2122 | PHM_PlatformCaps_MicrocodeFanControl); | |
2123 | return 0; | |
2124 | } | |
2125 | ||
2126 | if (0 == smu7_data->fan_table_start) { | |
2127 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); | |
2128 | return 0; | |
2129 | } | |
2130 | ||
2131 | duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100); | |
2132 | ||
2133 | if (0 == duty100) { | |
2134 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); | |
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100; | |
2139 | do_div(tmp64, 10000); | |
2140 | fdo_min = (uint16_t)tmp64; | |
2141 | ||
2142 | t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin; | |
2143 | t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed; | |
2144 | ||
2145 | pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin; | |
2146 | pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed; | |
2147 | ||
2148 | slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); | |
2149 | slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); | |
2150 | ||
2151 | fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100); | |
2152 | fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100); | |
2153 | fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100); | |
2154 | ||
2155 | fan_table.Slope1 = cpu_to_be16(slope1); | |
2156 | fan_table.Slope2 = cpu_to_be16(slope2); | |
2157 | ||
2158 | fan_table.FdoMin = cpu_to_be16(fdo_min); | |
2159 | ||
2160 | fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst); | |
2161 | ||
2162 | fan_table.HystUp = cpu_to_be16(1); | |
2163 | ||
2164 | fan_table.HystSlope = cpu_to_be16(1); | |
2165 | ||
2166 | fan_table.TempRespLim = cpu_to_be16(5); | |
2167 | ||
2168 | reference_clock = smu7_get_xclk(hwmgr); | |
2169 | ||
2170 | fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600); | |
2171 | ||
2172 | fan_table.FdoMax = cpu_to_be16((uint16_t)duty100); | |
2173 | ||
2174 | fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); | |
2175 | ||
2176 | /* fan_table.FanControl_GL_Flag = 1; */ | |
2177 | ||
2178 | res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); | |
2179 | ||
2180 | return 0; | |
2181 | } | |
2182 | ||
2183 | ||
2184 | static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) | |
2185 | { | |
2186 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
2187 | ||
2188 | if (data->need_update_smu7_dpm_table & | |
2189 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) | |
2190 | return iceland_program_memory_timing_parameters(hwmgr); | |
2191 | ||
2192 | return 0; | |
2193 | } | |
2194 | ||
2195 | static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) | |
2196 | { | |
2197 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
2198 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
2199 | ||
2200 | int result = 0; | |
2201 | uint32_t low_sclk_interrupt_threshold = 0; | |
2202 | ||
2203 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | |
2204 | PHM_PlatformCaps_SclkThrottleLowNotification) | |
29411f05 | 2205 | && (data->low_sclk_interrupt_threshold != 0)) { |
907bfec7 RZ |
2206 | low_sclk_interrupt_threshold = |
2207 | data->low_sclk_interrupt_threshold; | |
2208 | ||
2209 | CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); | |
2210 | ||
2211 | result = smu7_copy_bytes_to_smc( | |
2212 | hwmgr, | |
2213 | smu_data->smu7_data.dpm_table_start + | |
2214 | offsetof(SMU71_Discrete_DpmTable, | |
2215 | LowSclkInterruptThreshold), | |
2216 | (uint8_t *)&low_sclk_interrupt_threshold, | |
2217 | sizeof(uint32_t), | |
2218 | SMC_RAM_END); | |
2219 | } | |
2220 | ||
2221 | result = iceland_update_and_upload_mc_reg_table(hwmgr); | |
2222 | ||
2223 | PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); | |
2224 | ||
2225 | result = iceland_program_mem_timing_parameters(hwmgr); | |
2226 | PP_ASSERT_WITH_CODE((result == 0), | |
2227 | "Failed to program memory timing parameters!", | |
2228 | ); | |
2229 | ||
2230 | return result; | |
2231 | } | |
2232 | ||
2233 | static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member) | |
2234 | { | |
2235 | switch (type) { | |
2236 | case SMU_SoftRegisters: | |
2237 | switch (member) { | |
2238 | case HandshakeDisables: | |
2239 | return offsetof(SMU71_SoftRegisters, HandshakeDisables); | |
2240 | case VoltageChangeTimeout: | |
2241 | return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout); | |
2242 | case AverageGraphicsActivity: | |
2243 | return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity); | |
2244 | case PreVBlankGap: | |
2245 | return offsetof(SMU71_SoftRegisters, PreVBlankGap); | |
2246 | case VBlankTimeout: | |
2247 | return offsetof(SMU71_SoftRegisters, VBlankTimeout); | |
2248 | case UcodeLoadStatus: | |
2249 | return offsetof(SMU71_SoftRegisters, UcodeLoadStatus); | |
2250 | case DRAM_LOG_ADDR_H: | |
2251 | return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H); | |
2252 | case DRAM_LOG_ADDR_L: | |
2253 | return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L); | |
2254 | case DRAM_LOG_PHY_ADDR_H: | |
2255 | return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H); | |
2256 | case DRAM_LOG_PHY_ADDR_L: | |
2257 | return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L); | |
2258 | case DRAM_LOG_BUFF_SIZE: | |
2259 | return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE); | |
2260 | } | |
2261 | case SMU_Discrete_DpmTable: | |
2262 | switch (member) { | |
2263 | case LowSclkInterruptThreshold: | |
2264 | return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold); | |
2265 | } | |
2266 | } | |
2267 | pr_warn("can't get the offset of type %x member %x\n", type, member); | |
2268 | return 0; | |
2269 | } | |
2270 | ||
2271 | static uint32_t iceland_get_mac_definition(uint32_t value) | |
2272 | { | |
2273 | switch (value) { | |
2274 | case SMU_MAX_LEVELS_GRAPHICS: | |
2275 | return SMU71_MAX_LEVELS_GRAPHICS; | |
2276 | case SMU_MAX_LEVELS_MEMORY: | |
2277 | return SMU71_MAX_LEVELS_MEMORY; | |
2278 | case SMU_MAX_LEVELS_LINK: | |
2279 | return SMU71_MAX_LEVELS_LINK; | |
2280 | case SMU_MAX_ENTRIES_SMIO: | |
2281 | return SMU71_MAX_ENTRIES_SMIO; | |
2282 | case SMU_MAX_LEVELS_VDDC: | |
2283 | return SMU71_MAX_LEVELS_VDDC; | |
2284 | case SMU_MAX_LEVELS_VDDCI: | |
2285 | return SMU71_MAX_LEVELS_VDDCI; | |
2286 | case SMU_MAX_LEVELS_MVDD: | |
2287 | return SMU71_MAX_LEVELS_MVDD; | |
2288 | } | |
2289 | ||
2290 | pr_warn("can't get the mac of %x\n", value); | |
2291 | return 0; | |
2292 | } | |
2293 | ||
2294 | static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) | |
2295 | { | |
2296 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
2297 | struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); | |
2298 | ||
2299 | uint32_t tmp; | |
2300 | int result; | |
2301 | bool error = false; | |
2302 | ||
2303 | result = smu7_read_smc_sram_dword(hwmgr, | |
2304 | SMU71_FIRMWARE_HEADER_LOCATION + | |
2305 | offsetof(SMU71_Firmware_Header, DpmTable), | |
2306 | &tmp, SMC_RAM_END); | |
2307 | ||
2308 | if (0 == result) { | |
2309 | smu7_data->dpm_table_start = tmp; | |
2310 | } | |
2311 | ||
2312 | error |= (0 != result); | |
2313 | ||
2314 | result = smu7_read_smc_sram_dword(hwmgr, | |
2315 | SMU71_FIRMWARE_HEADER_LOCATION + | |
2316 | offsetof(SMU71_Firmware_Header, SoftRegisters), | |
2317 | &tmp, SMC_RAM_END); | |
2318 | ||
2319 | if (0 == result) { | |
2320 | data->soft_regs_start = tmp; | |
2321 | smu7_data->soft_regs_start = tmp; | |
2322 | } | |
2323 | ||
2324 | error |= (0 != result); | |
2325 | ||
2326 | ||
2327 | result = smu7_read_smc_sram_dword(hwmgr, | |
2328 | SMU71_FIRMWARE_HEADER_LOCATION + | |
2329 | offsetof(SMU71_Firmware_Header, mcRegisterTable), | |
2330 | &tmp, SMC_RAM_END); | |
2331 | ||
2332 | if (0 == result) { | |
2333 | smu7_data->mc_reg_table_start = tmp; | |
2334 | } | |
2335 | ||
2336 | result = smu7_read_smc_sram_dword(hwmgr, | |
2337 | SMU71_FIRMWARE_HEADER_LOCATION + | |
2338 | offsetof(SMU71_Firmware_Header, FanTable), | |
2339 | &tmp, SMC_RAM_END); | |
2340 | ||
2341 | if (0 == result) { | |
2342 | smu7_data->fan_table_start = tmp; | |
2343 | } | |
2344 | ||
2345 | error |= (0 != result); | |
2346 | ||
2347 | result = smu7_read_smc_sram_dword(hwmgr, | |
2348 | SMU71_FIRMWARE_HEADER_LOCATION + | |
2349 | offsetof(SMU71_Firmware_Header, mcArbDramTimingTable), | |
2350 | &tmp, SMC_RAM_END); | |
2351 | ||
2352 | if (0 == result) { | |
2353 | smu7_data->arb_table_start = tmp; | |
2354 | } | |
2355 | ||
2356 | error |= (0 != result); | |
2357 | ||
2358 | ||
2359 | result = smu7_read_smc_sram_dword(hwmgr, | |
2360 | SMU71_FIRMWARE_HEADER_LOCATION + | |
2361 | offsetof(SMU71_Firmware_Header, Version), | |
2362 | &tmp, SMC_RAM_END); | |
2363 | ||
2364 | if (0 == result) { | |
2365 | hwmgr->microcode_version_info.SMC = tmp; | |
2366 | } | |
2367 | ||
2368 | error |= (0 != result); | |
2369 | ||
2370 | result = smu7_read_smc_sram_dword(hwmgr, | |
2371 | SMU71_FIRMWARE_HEADER_LOCATION + | |
2372 | offsetof(SMU71_Firmware_Header, UlvSettings), | |
2373 | &tmp, SMC_RAM_END); | |
2374 | ||
2375 | if (0 == result) { | |
2376 | smu7_data->ulv_setting_starts = tmp; | |
2377 | } | |
2378 | ||
2379 | error |= (0 != result); | |
2380 | ||
2381 | return error ? 1 : 0; | |
2382 | } | |
2383 | ||
2384 | /*---------------------------MC----------------------------*/ | |
2385 | ||
2386 | static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr) | |
2387 | { | |
2388 | return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); | |
2389 | } | |
2390 | ||
2391 | static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg) | |
2392 | { | |
2393 | bool result = true; | |
2394 | ||
2395 | switch (in_reg) { | |
2396 | case mmMC_SEQ_RAS_TIMING: | |
2397 | *out_reg = mmMC_SEQ_RAS_TIMING_LP; | |
2398 | break; | |
2399 | ||
2400 | case mmMC_SEQ_DLL_STBY: | |
2401 | *out_reg = mmMC_SEQ_DLL_STBY_LP; | |
2402 | break; | |
2403 | ||
2404 | case mmMC_SEQ_G5PDX_CMD0: | |
2405 | *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; | |
2406 | break; | |
2407 | ||
2408 | case mmMC_SEQ_G5PDX_CMD1: | |
2409 | *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; | |
2410 | break; | |
2411 | ||
2412 | case mmMC_SEQ_G5PDX_CTRL: | |
2413 | *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; | |
2414 | break; | |
2415 | ||
2416 | case mmMC_SEQ_CAS_TIMING: | |
2417 | *out_reg = mmMC_SEQ_CAS_TIMING_LP; | |
2418 | break; | |
2419 | ||
2420 | case mmMC_SEQ_MISC_TIMING: | |
2421 | *out_reg = mmMC_SEQ_MISC_TIMING_LP; | |
2422 | break; | |
2423 | ||
2424 | case mmMC_SEQ_MISC_TIMING2: | |
2425 | *out_reg = mmMC_SEQ_MISC_TIMING2_LP; | |
2426 | break; | |
2427 | ||
2428 | case mmMC_SEQ_PMG_DVS_CMD: | |
2429 | *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP; | |
2430 | break; | |
2431 | ||
2432 | case mmMC_SEQ_PMG_DVS_CTL: | |
2433 | *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP; | |
2434 | break; | |
2435 | ||
2436 | case mmMC_SEQ_RD_CTL_D0: | |
2437 | *out_reg = mmMC_SEQ_RD_CTL_D0_LP; | |
2438 | break; | |
2439 | ||
2440 | case mmMC_SEQ_RD_CTL_D1: | |
2441 | *out_reg = mmMC_SEQ_RD_CTL_D1_LP; | |
2442 | break; | |
2443 | ||
2444 | case mmMC_SEQ_WR_CTL_D0: | |
2445 | *out_reg = mmMC_SEQ_WR_CTL_D0_LP; | |
2446 | break; | |
2447 | ||
2448 | case mmMC_SEQ_WR_CTL_D1: | |
2449 | *out_reg = mmMC_SEQ_WR_CTL_D1_LP; | |
2450 | break; | |
2451 | ||
2452 | case mmMC_PMG_CMD_EMRS: | |
2453 | *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP; | |
2454 | break; | |
2455 | ||
2456 | case mmMC_PMG_CMD_MRS: | |
2457 | *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP; | |
2458 | break; | |
2459 | ||
2460 | case mmMC_PMG_CMD_MRS1: | |
2461 | *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP; | |
2462 | break; | |
2463 | ||
2464 | case mmMC_SEQ_PMG_TIMING: | |
2465 | *out_reg = mmMC_SEQ_PMG_TIMING_LP; | |
2466 | break; | |
2467 | ||
2468 | case mmMC_PMG_CMD_MRS2: | |
2469 | *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP; | |
2470 | break; | |
2471 | ||
2472 | case mmMC_SEQ_WR_CTL_2: | |
2473 | *out_reg = mmMC_SEQ_WR_CTL_2_LP; | |
2474 | break; | |
2475 | ||
2476 | default: | |
2477 | result = false; | |
2478 | break; | |
2479 | } | |
2480 | ||
2481 | return result; | |
2482 | } | |
2483 | ||
2484 | static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table) | |
2485 | { | |
2486 | uint32_t i; | |
2487 | uint16_t address; | |
2488 | ||
2489 | for (i = 0; i < table->last; i++) { | |
2490 | table->mc_reg_address[i].s0 = | |
2491 | iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) | |
2492 | ? address : table->mc_reg_address[i].s1; | |
2493 | } | |
2494 | return 0; | |
2495 | } | |
2496 | ||
2497 | static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, | |
2498 | struct iceland_mc_reg_table *ni_table) | |
2499 | { | |
2500 | uint8_t i, j; | |
2501 | ||
2502 | PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
2503 | "Invalid VramInfo table.", return -EINVAL); | |
2504 | PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), | |
2505 | "Invalid VramInfo table.", return -EINVAL); | |
2506 | ||
2507 | for (i = 0; i < table->last; i++) { | |
2508 | ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; | |
2509 | } | |
2510 | ni_table->last = table->last; | |
2511 | ||
2512 | for (i = 0; i < table->num_entries; i++) { | |
2513 | ni_table->mc_reg_table_entry[i].mclk_max = | |
2514 | table->mc_reg_table_entry[i].mclk_max; | |
2515 | for (j = 0; j < table->last; j++) { | |
2516 | ni_table->mc_reg_table_entry[i].mc_data[j] = | |
2517 | table->mc_reg_table_entry[i].mc_data[j]; | |
2518 | } | |
2519 | } | |
2520 | ||
2521 | ni_table->num_entries = table->num_entries; | |
2522 | ||
2523 | return 0; | |
2524 | } | |
2525 | ||
2526 | static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, | |
2527 | struct iceland_mc_reg_table *table) | |
2528 | { | |
2529 | uint8_t i, j, k; | |
2530 | uint32_t temp_reg; | |
2531 | struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); | |
2532 | ||
2533 | for (i = 0, j = table->last; i < table->last; i++) { | |
2534 | PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
2535 | "Invalid VramInfo table.", return -EINVAL); | |
2536 | ||
2537 | switch (table->mc_reg_address[i].s1) { | |
2538 | ||
2539 | case mmMC_SEQ_MISC1: | |
2540 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); | |
2541 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; | |
2542 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; | |
2543 | for (k = 0; k < table->num_entries; k++) { | |
2544 | table->mc_reg_table_entry[k].mc_data[j] = | |
2545 | ((temp_reg & 0xffff0000)) | | |
2546 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); | |
2547 | } | |
2548 | j++; | |
8cdbad98 | 2549 | |
907bfec7 RZ |
2550 | PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
2551 | "Invalid VramInfo table.", return -EINVAL); | |
907bfec7 RZ |
2552 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); |
2553 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; | |
2554 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; | |
2555 | for (k = 0; k < table->num_entries; k++) { | |
2556 | table->mc_reg_table_entry[k].mc_data[j] = | |
2557 | (temp_reg & 0xffff0000) | | |
2558 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
2559 | ||
2560 | if (!data->is_memory_gddr5) { | |
2561 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; | |
2562 | } | |
2563 | } | |
2564 | j++; | |
907bfec7 | 2565 | |
8cdbad98 ES |
2566 | if (!data->is_memory_gddr5) { |
2567 | PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), | |
2568 | "Invalid VramInfo table.", return -EINVAL); | |
907bfec7 RZ |
2569 | table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; |
2570 | table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; | |
2571 | for (k = 0; k < table->num_entries; k++) { | |
2572 | table->mc_reg_table_entry[k].mc_data[j] = | |
2573 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; | |
2574 | } | |
2575 | j++; | |
907bfec7 RZ |
2576 | } |
2577 | ||
2578 | break; | |
2579 | ||
2580 | case mmMC_SEQ_RESERVE_M: | |
2581 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); | |
2582 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; | |
2583 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; | |
2584 | for (k = 0; k < table->num_entries; k++) { | |
2585 | table->mc_reg_table_entry[k].mc_data[j] = | |
2586 | (temp_reg & 0xffff0000) | | |
2587 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
2588 | } | |
2589 | j++; | |
907bfec7 RZ |
2590 | break; |
2591 | ||
2592 | default: | |
2593 | break; | |
2594 | } | |
2595 | ||
2596 | } | |
2597 | ||
2598 | table->last = j; | |
2599 | ||
2600 | return 0; | |
2601 | } | |
2602 | ||
2603 | static int iceland_set_valid_flag(struct iceland_mc_reg_table *table) | |
2604 | { | |
2605 | uint8_t i, j; | |
2606 | for (i = 0; i < table->last; i++) { | |
2607 | for (j = 1; j < table->num_entries; j++) { | |
2608 | if (table->mc_reg_table_entry[j-1].mc_data[i] != | |
2609 | table->mc_reg_table_entry[j].mc_data[i]) { | |
2610 | table->validflag |= (1<<i); | |
2611 | break; | |
2612 | } | |
2613 | } | |
2614 | } | |
2615 | ||
2616 | return 0; | |
2617 | } | |
2618 | ||
2619 | static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) | |
2620 | { | |
2621 | int result; | |
2622 | struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); | |
2623 | pp_atomctrl_mc_reg_table *table; | |
2624 | struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table; | |
2625 | uint8_t module_index = iceland_get_memory_modile_index(hwmgr); | |
2626 | ||
2627 | table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); | |
2628 | ||
2629 | if (NULL == table) | |
2630 | return -ENOMEM; | |
2631 | ||
2632 | /* Program additional LP registers that are no longer programmed by VBIOS */ | |
2633 | cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); | |
2634 | cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); | |
2635 | cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); | |
2636 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0)); | |
2637 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1)); | |
2638 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL)); | |
2639 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD)); | |
2640 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL)); | |
2641 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING)); | |
2642 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); | |
2643 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); | |
2644 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); | |
2645 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); | |
2646 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); | |
2647 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); | |
2648 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); | |
2649 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); | |
2650 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); | |
2651 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); | |
2652 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); | |
2653 | ||
2654 | memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); | |
2655 | ||
2656 | result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); | |
2657 | ||
2658 | if (0 == result) | |
2659 | result = iceland_copy_vbios_smc_reg_table(table, ni_table); | |
2660 | ||
2661 | if (0 == result) { | |
2662 | iceland_set_s0_mc_reg_index(ni_table); | |
2663 | result = iceland_set_mc_special_registers(hwmgr, ni_table); | |
2664 | } | |
2665 | ||
2666 | if (0 == result) | |
2667 | iceland_set_valid_flag(ni_table); | |
2668 | ||
2669 | kfree(table); | |
2670 | ||
2671 | return result; | |
2672 | } | |
2673 | ||
2674 | static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr) | |
2675 | { | |
2676 | return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, | |
2677 | CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) | |
2678 | ? true : false; | |
2679 | } | |
2680 | ||
63b55943 | 2681 | const struct pp_smumgr_func iceland_smu_funcs = { |
2435b054 | 2682 | .smu_init = &iceland_smu_init, |
9c6d4956 | 2683 | .smu_fini = &smu7_smu_fini, |
2435b054 | 2684 | .start_smu = &iceland_start_smu, |
9c6d4956 RZ |
2685 | .check_fw_load_finish = &smu7_check_fw_load_finish, |
2686 | .request_smu_load_fw = &smu7_reload_firmware, | |
2435b054 | 2687 | .request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw, |
9c6d4956 RZ |
2688 | .send_msg_to_smc = &smu7_send_msg_to_smc, |
2689 | .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter, | |
2435b054 HR |
2690 | .download_pptable_settings = NULL, |
2691 | .upload_pptable_settings = NULL, | |
18aafc59 RZ |
2692 | .get_offsetof = iceland_get_offsetof, |
2693 | .process_firmware_header = iceland_process_firmware_header, | |
2694 | .init_smc_table = iceland_init_smc_table, | |
2695 | .update_sclk_threshold = iceland_update_sclk_threshold, | |
2696 | .thermal_setup_fan_table = iceland_thermal_setup_fan_table, | |
2697 | .populate_all_graphic_levels = iceland_populate_all_graphic_levels, | |
2698 | .populate_all_memory_levels = iceland_populate_all_memory_levels, | |
2699 | .get_mac_definition = iceland_get_mac_definition, | |
2700 | .initialize_mc_reg_table = iceland_initialize_mc_reg_table, | |
2701 | .is_dpm_running = iceland_is_dpm_running, | |
2435b054 HR |
2702 | }; |
2703 |