Commit | Line | Data |
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07845526 HR |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
07845526 | 23 | #include <linux/firmware.h> |
841d0023 | 24 | #include <linux/module.h> |
d7929c1e | 25 | #include <linux/pci.h> |
94952205 | 26 | #include <linux/reboot.h> |
841d0023 | 27 | |
73abde4d MC |
28 | #define SMU_11_0_PARTIAL_PPTABLE |
29 | ||
07845526 HR |
30 | #include "amdgpu.h" |
31 | #include "amdgpu_smu.h" | |
18c1d3ce | 32 | #include "smu_internal.h" |
eaf02a4d | 33 | #include "atomfirmware.h" |
244f3449 | 34 | #include "amdgpu_atomfirmware.h" |
e11c4fd5 | 35 | #include "smu_v11_0.h" |
73abde4d | 36 | #include "smu_v11_0_pptable.h" |
b0b4b413 | 37 | #include "soc15_common.h" |
08115f87 | 38 | #include "atom.h" |
372120f0 | 39 | #include "amd_pcie.h" |
32cc3bf0 | 40 | #include "amdgpu_ras.h" |
b0b4b413 KW |
41 | |
42 | #include "asic_reg/thm/thm_11_0_2_offset.h" | |
43 | #include "asic_reg/thm/thm_11_0_2_sh_mask.h" | |
980e04ec HR |
44 | #include "asic_reg/mp/mp_11_0_offset.h" |
45 | #include "asic_reg/mp/mp_11_0_sh_mask.h" | |
980e04ec HR |
46 | #include "asic_reg/smuio/smuio_11_0_0_offset.h" |
47 | #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h" | |
07845526 | 48 | |
e7773c1c | 49 | MODULE_FIRMWARE("amdgpu/arcturus_smc.bin"); |
879af1c6 | 50 | MODULE_FIRMWARE("amdgpu/navi10_smc.bin"); |
b02ff126 | 51 | MODULE_FIRMWARE("amdgpu/navi14_smc.bin"); |
9ea8da75 | 52 | MODULE_FIRMWARE("amdgpu/navi12_smc.bin"); |
b455159c | 53 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); |
59abab5a | 54 | |
77d1eef4 | 55 | #define SMU11_VOLTAGE_SCALE 4 |
2f613c70 | 56 | |
b0b4b413 KW |
57 | static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu, |
58 | uint16_t msg) | |
59 | { | |
60 | struct amdgpu_device *adev = smu->adev; | |
38748ad8 | 61 | WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); |
b0b4b413 KW |
62 | return 0; |
63 | } | |
64 | ||
ae458c7b | 65 | static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg) |
765c50cb KW |
66 | { |
67 | struct amdgpu_device *adev = smu->adev; | |
68 | ||
38748ad8 | 69 | *arg = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82); |
765c50cb KW |
70 | return 0; |
71 | } | |
72 | ||
b0b4b413 KW |
73 | static int smu_v11_0_wait_for_response(struct smu_context *smu) |
74 | { | |
75 | struct amdgpu_device *adev = smu->adev; | |
e3000669 | 76 | uint32_t cur_value, i, timeout = adev->usec_timeout * 10; |
b0b4b413 | 77 | |
e3000669 | 78 | for (i = 0; i < timeout; i++) { |
38748ad8 | 79 | cur_value = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90); |
b0b4b413 | 80 | if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0) |
fcb1fe9c EQ |
81 | return cur_value == 0x1 ? 0 : -EIO; |
82 | ||
b0b4b413 KW |
83 | udelay(1); |
84 | } | |
85 | ||
86 | /* timeout means wrong logic */ | |
38748ad8 ML |
87 | if (i == timeout) |
88 | return -ETIME; | |
89 | ||
90 | return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO; | |
b0b4b413 KW |
91 | } |
92 | ||
6c45e480 | 93 | int |
f275cde7 LG |
94 | smu_v11_0_send_msg_with_param(struct smu_context *smu, |
95 | enum smu_message_type msg, | |
1c58267c MC |
96 | uint32_t param, |
97 | uint32_t *read_arg) | |
b0b4b413 | 98 | { |
b0b4b413 | 99 | struct amdgpu_device *adev = smu->adev; |
5c45103f KW |
100 | int ret = 0, index = 0; |
101 | ||
102 | index = smu_msg_get_index(smu, msg); | |
103 | if (index < 0) | |
4ea5081c | 104 | return index == -EACCES ? 0 : index; |
b0b4b413 | 105 | |
eb696d04 | 106 | mutex_lock(&smu->message_lock); |
b0b4b413 | 107 | ret = smu_v11_0_wait_for_response(smu); |
fcb1fe9c EQ |
108 | if (ret) { |
109 | pr_err("Msg issuing pre-check failed and " | |
110 | "SMU may be not in the right state!\n"); | |
eb696d04 | 111 | goto out; |
fcb1fe9c | 112 | } |
b0b4b413 | 113 | |
38748ad8 | 114 | WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); |
b0b4b413 | 115 | |
38748ad8 | 116 | WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param); |
b0b4b413 | 117 | |
5c45103f | 118 | smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index); |
b0b4b413 KW |
119 | |
120 | ret = smu_v11_0_wait_for_response(smu); | |
1c58267c | 121 | if (ret) { |
6b294793 KW |
122 | pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n", |
123 | smu_get_message_name(smu, msg), index, param, ret); | |
eb696d04 | 124 | goto out; |
1c58267c | 125 | } |
38748ad8 | 126 | |
1c58267c MC |
127 | if (read_arg) { |
128 | ret = smu_v11_0_read_arg(smu, read_arg); | |
129 | if (ret) { | |
130 | pr_err("failed to read message arg: %10s (%d) \tparam: 0x%08x response %#x\n", | |
131 | smu_get_message_name(smu, msg), index, param, ret); | |
eb696d04 | 132 | goto out; |
1c58267c MC |
133 | } |
134 | } | |
eb696d04 MC |
135 | out: |
136 | mutex_unlock(&smu->message_lock); | |
137 | return ret; | |
b0b4b413 KW |
138 | } |
139 | ||
6c45e480 | 140 | int smu_v11_0_init_microcode(struct smu_context *smu) |
07845526 HR |
141 | { |
142 | struct amdgpu_device *adev = smu->adev; | |
59abab5a LG |
143 | const char *chip_name; |
144 | char fw_name[30]; | |
145 | int err = 0; | |
146 | const struct smc_firmware_header_v1_0 *hdr; | |
147 | const struct common_firmware_header *header; | |
148 | struct amdgpu_firmware_info *ucode = NULL; | |
07845526 | 149 | |
59abab5a | 150 | switch (adev->asic_type) { |
e7773c1c CG |
151 | case CHIP_ARCTURUS: |
152 | chip_name = "arcturus"; | |
153 | break; | |
31528650 HR |
154 | case CHIP_NAVI10: |
155 | chip_name = "navi10"; | |
156 | break; | |
b02ff126 XY |
157 | case CHIP_NAVI14: |
158 | chip_name = "navi14"; | |
159 | break; | |
9ea8da75 XY |
160 | case CHIP_NAVI12: |
161 | chip_name = "navi12"; | |
162 | break; | |
b455159c LG |
163 | case CHIP_SIENNA_CICHLID: |
164 | chip_name = "sienna_cichlid"; | |
165 | break; | |
59abab5a LG |
166 | default: |
167 | BUG(); | |
168 | } | |
169 | ||
170 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); | |
171 | ||
172 | err = request_firmware(&adev->pm.fw, fw_name, adev->dev); | |
173 | if (err) | |
174 | goto out; | |
175 | err = amdgpu_ucode_validate(adev->pm.fw); | |
176 | if (err) | |
177 | goto out; | |
178 | ||
179 | hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; | |
180 | amdgpu_ucode_print_smc_hdr(&hdr->header); | |
181 | adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); | |
182 | ||
183 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
184 | ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; | |
185 | ucode->ucode_id = AMDGPU_UCODE_ID_SMC; | |
186 | ucode->fw = adev->pm.fw; | |
187 | header = (const struct common_firmware_header *)ucode->fw->data; | |
188 | adev->firmware.fw_size += | |
189 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
190 | } | |
191 | ||
192 | out: | |
193 | if (err) { | |
194 | DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n", | |
195 | fw_name); | |
196 | release_firmware(adev->pm.fw); | |
197 | adev->pm.fw = NULL; | |
198 | } | |
199 | return err; | |
07845526 HR |
200 | } |
201 | ||
6c45e480 | 202 | int smu_v11_0_load_microcode(struct smu_context *smu) |
3d2f5200 | 203 | { |
827440a9 KF |
204 | struct amdgpu_device *adev = smu->adev; |
205 | const uint32_t *src; | |
206 | const struct smc_firmware_header_v1_0 *hdr; | |
207 | uint32_t addr_start = MP1_SRAM; | |
208 | uint32_t i; | |
e8663832 | 209 | uint32_t smc_fw_size; |
827440a9 KF |
210 | uint32_t mp1_fw_flags; |
211 | ||
e7773c1c | 212 | hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; |
827440a9 KF |
213 | src = (const uint32_t *)(adev->pm.fw->data + |
214 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
e8663832 | 215 | smc_fw_size = hdr->header.ucode_size_bytes; |
827440a9 | 216 | |
e8663832 | 217 | for (i = 1; i < smc_fw_size/4 - 1; i++) { |
827440a9 KF |
218 | WREG32_PCIE(addr_start, src[i]); |
219 | addr_start += 4; | |
220 | } | |
221 | ||
222 | WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), | |
223 | 1 & MP1_SMN_PUB_CTRL__RESET_MASK); | |
224 | WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), | |
225 | 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); | |
226 | ||
227 | for (i = 0; i < adev->usec_timeout; i++) { | |
228 | mp1_fw_flags = RREG32_PCIE(MP1_Public | | |
229 | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); | |
230 | if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> | |
231 | MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) | |
232 | break; | |
233 | udelay(1); | |
234 | } | |
235 | ||
236 | if (i == adev->usec_timeout) | |
237 | return -ETIME; | |
238 | ||
3d2f5200 HR |
239 | return 0; |
240 | } | |
241 | ||
6c45e480 | 242 | int smu_v11_0_check_fw_status(struct smu_context *smu) |
e11c4fd5 | 243 | { |
7b0031b6 KW |
244 | struct amdgpu_device *adev = smu->adev; |
245 | uint32_t mp1_fw_flags; | |
246 | ||
a8394cfa HR |
247 | mp1_fw_flags = RREG32_PCIE(MP1_Public | |
248 | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); | |
7b0031b6 KW |
249 | |
250 | if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> | |
251 | MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) | |
252 | return 0; | |
a8394cfa | 253 | |
7b0031b6 | 254 | return -EIO; |
e11c4fd5 HR |
255 | } |
256 | ||
6c45e480 | 257 | int smu_v11_0_check_fw_version(struct smu_context *smu) |
765c50cb | 258 | { |
4fde03a7 KW |
259 | uint32_t if_version = 0xff, smu_version = 0xff; |
260 | uint16_t smu_major; | |
261 | uint8_t smu_minor, smu_debug; | |
765c50cb KW |
262 | int ret = 0; |
263 | ||
4fde03a7 | 264 | ret = smu_get_smc_version(smu, &if_version, &smu_version); |
765c50cb | 265 | if (ret) |
4fde03a7 | 266 | return ret; |
765c50cb | 267 | |
4fde03a7 KW |
268 | smu_major = (smu_version >> 16) & 0xffff; |
269 | smu_minor = (smu_version >> 8) & 0xff; | |
270 | smu_debug = (smu_version >> 0) & 0xff; | |
271 | ||
1b41b769 | 272 | switch (smu->adev->asic_type) { |
e34640e2 | 273 | case CHIP_ARCTURUS: |
e57761c6 | 274 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT; |
e34640e2 | 275 | break; |
1b41b769 | 276 | case CHIP_NAVI10: |
e57761c6 | 277 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10; |
1b41b769 | 278 | break; |
c1b69212 | 279 | case CHIP_NAVI12: |
e57761c6 | 280 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12; |
c1b69212 | 281 | break; |
1b41b769 | 282 | case CHIP_NAVI14: |
e57761c6 | 283 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14; |
1b41b769 | 284 | break; |
b455159c LG |
285 | case CHIP_SIENNA_CICHLID: |
286 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid; | |
287 | break; | |
1b41b769 | 288 | default: |
dec4f137 | 289 | pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type); |
e57761c6 | 290 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; |
1b41b769 | 291 | break; |
292 | } | |
293 | ||
93002849 EQ |
294 | /* |
295 | * 1. if_version mismatch is not critical as our fw is designed | |
296 | * to be backward compatible. | |
297 | * 2. New fw usually brings some optimizations. But that's visible | |
298 | * only on the paired driver. | |
299 | * Considering above, we just leave user a warning message instead | |
300 | * of halt driver loading. | |
301 | */ | |
e57761c6 | 302 | if (if_version != smu->smc_driver_if_version) { |
f3121d3d KW |
303 | pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, " |
304 | "smu fw version = 0x%08x (%d.%d.%d)\n", | |
e57761c6 | 305 | smu->smc_driver_if_version, if_version, |
f3121d3d | 306 | smu_version, smu_major, smu_minor, smu_debug); |
93002849 | 307 | pr_warn("SMU driver if version not matched\n"); |
4fde03a7 KW |
308 | } |
309 | ||
765c50cb KW |
310 | return ret; |
311 | } | |
312 | ||
b55c83a7 KW |
313 | static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) |
314 | { | |
315 | struct amdgpu_device *adev = smu->adev; | |
316 | uint32_t ppt_offset_bytes; | |
317 | const struct smc_firmware_header_v2_0 *v2; | |
318 | ||
319 | v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; | |
320 | ||
321 | ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); | |
322 | *size = le32_to_cpu(v2->ppt_size_bytes); | |
323 | *table = (uint8_t *)v2 + ppt_offset_bytes; | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
e7773c1c CG |
328 | static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, |
329 | uint32_t *size, uint32_t pptable_id) | |
b55c83a7 KW |
330 | { |
331 | struct amdgpu_device *adev = smu->adev; | |
332 | const struct smc_firmware_header_v2_1 *v2_1; | |
333 | struct smc_soft_pptable_entry *entries; | |
334 | uint32_t pptable_count = 0; | |
335 | int i = 0; | |
336 | ||
337 | v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; | |
338 | entries = (struct smc_soft_pptable_entry *) | |
339 | ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); | |
340 | pptable_count = le32_to_cpu(v2_1->pptable_count); | |
341 | for (i = 0; i < pptable_count; i++) { | |
342 | if (le32_to_cpu(entries[i].id) == pptable_id) { | |
343 | *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); | |
344 | *size = le32_to_cpu(entries[i].ppt_size_bytes); | |
345 | break; | |
346 | } | |
347 | } | |
348 | ||
349 | if (i == pptable_count) | |
350 | return -EINVAL; | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
6c45e480 | 355 | int smu_v11_0_setup_pptable(struct smu_context *smu) |
244f3449 | 356 | { |
b55c83a7 KW |
357 | struct amdgpu_device *adev = smu->adev; |
358 | const struct smc_firmware_header_v1_0 *hdr; | |
244f3449 | 359 | int ret, index; |
c4e1da5e | 360 | uint32_t size = 0; |
ebecc6c4 | 361 | uint16_t atom_table_size; |
244f3449 | 362 | uint8_t frev, crev; |
ce6f7fa8 | 363 | void *table; |
b55c83a7 KW |
364 | uint16_t version_major, version_minor; |
365 | ||
366 | hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; | |
367 | version_major = le16_to_cpu(hdr->header.header_version_major); | |
368 | version_minor = le16_to_cpu(hdr->header.header_version_minor); | |
e2c14b2c | 369 | if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) { |
91872960 | 370 | pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id); |
b55c83a7 KW |
371 | switch (version_minor) { |
372 | case 0: | |
373 | ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size); | |
374 | break; | |
375 | case 1: | |
376 | ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size, | |
377 | smu->smu_table.boot_values.pp_table_id); | |
378 | break; | |
379 | default: | |
380 | ret = -EINVAL; | |
381 | break; | |
382 | } | |
383 | if (ret) | |
384 | return ret; | |
244f3449 | 385 | |
879af1c6 | 386 | } else { |
91872960 | 387 | pr_info("use vbios provided pptable\n"); |
879af1c6 HR |
388 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, |
389 | powerplayinfo); | |
244f3449 | 390 | |
ebecc6c4 | 391 | ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev, |
879af1c6 HR |
392 | (uint8_t **)&table); |
393 | if (ret) | |
394 | return ret; | |
ebecc6c4 | 395 | size = atom_table_size; |
879af1c6 | 396 | } |
244f3449 | 397 | |
289921b0 KW |
398 | if (!smu->smu_table.power_play_table) |
399 | smu->smu_table.power_play_table = table; | |
400 | if (!smu->smu_table.power_play_table_size) | |
401 | smu->smu_table.power_play_table_size = size; | |
244f3449 HR |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
142dec62 KW |
406 | static int smu_v11_0_init_dpm_context(struct smu_context *smu) |
407 | { | |
408 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
409 | ||
410 | if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0) | |
411 | return -EINVAL; | |
412 | ||
d76c9e24 | 413 | return smu_alloc_dpm_context(smu); |
142dec62 KW |
414 | } |
415 | ||
416 | static int smu_v11_0_fini_dpm_context(struct smu_context *smu) | |
417 | { | |
418 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
419 | ||
420 | if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0) | |
421 | return -EINVAL; | |
422 | ||
423 | kfree(smu_dpm->dpm_context); | |
95add959 | 424 | kfree(smu_dpm->golden_dpm_context); |
8554e67d CG |
425 | kfree(smu_dpm->dpm_current_power_state); |
426 | kfree(smu_dpm->dpm_request_power_state); | |
142dec62 | 427 | smu_dpm->dpm_context = NULL; |
95add959 | 428 | smu_dpm->golden_dpm_context = NULL; |
142dec62 | 429 | smu_dpm->dpm_context_size = 0; |
8554e67d CG |
430 | smu_dpm->dpm_current_power_state = NULL; |
431 | smu_dpm->dpm_request_power_state = NULL; | |
142dec62 KW |
432 | |
433 | return 0; | |
434 | } | |
435 | ||
6c45e480 | 436 | int smu_v11_0_init_smc_tables(struct smu_context *smu) |
813ce279 KW |
437 | { |
438 | struct smu_table_context *smu_table = &smu->smu_table; | |
439 | struct smu_table *tables = NULL; | |
142dec62 | 440 | int ret = 0; |
813ce279 | 441 | |
cdb0c632 HR |
442 | tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table), |
443 | GFP_KERNEL); | |
78eb4a36 EQ |
444 | if (!tables) { |
445 | ret = -ENOMEM; | |
446 | goto err0_out; | |
447 | } | |
813ce279 | 448 | smu_table->tables = tables; |
813ce279 | 449 | |
62b9a88c KW |
450 | ret = smu_tables_init(smu, tables); |
451 | if (ret) | |
78eb4a36 | 452 | goto err1_out; |
813ce279 | 453 | |
142dec62 KW |
454 | ret = smu_v11_0_init_dpm_context(smu); |
455 | if (ret) | |
78eb4a36 EQ |
456 | goto err1_out; |
457 | ||
458 | smu_table->driver_pptable = | |
459 | kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); | |
460 | if (!smu_table->driver_pptable) { | |
461 | ret = -ENOMEM; | |
462 | goto err2_out; | |
463 | } | |
464 | ||
465 | smu_table->max_sustainable_clocks = | |
466 | kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL); | |
467 | if (!smu_table->max_sustainable_clocks) { | |
468 | ret = -ENOMEM; | |
469 | goto err3_out; | |
470 | } | |
471 | ||
472 | /* Arcturus does not support OVERDRIVE */ | |
473 | if (tables[SMU_TABLE_OVERDRIVE].size) { | |
474 | smu_table->overdrive_table = | |
475 | kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); | |
476 | if (!smu_table->overdrive_table) { | |
477 | ret = -ENOMEM; | |
478 | goto err4_out; | |
479 | } | |
480 | ||
481 | smu_table->boot_overdrive_table = | |
482 | kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); | |
483 | if (!smu_table->boot_overdrive_table) { | |
484 | ret = -ENOMEM; | |
485 | goto err5_out; | |
486 | } | |
487 | } | |
142dec62 | 488 | |
813ce279 | 489 | return 0; |
78eb4a36 EQ |
490 | |
491 | err5_out: | |
492 | kfree(smu_table->overdrive_table); | |
493 | err4_out: | |
494 | kfree(smu_table->max_sustainable_clocks); | |
495 | err3_out: | |
496 | kfree(smu_table->driver_pptable); | |
497 | err2_out: | |
498 | smu_v11_0_fini_dpm_context(smu); | |
499 | err1_out: | |
500 | kfree(tables); | |
501 | err0_out: | |
502 | return ret; | |
813ce279 KW |
503 | } |
504 | ||
6c45e480 | 505 | int smu_v11_0_fini_smc_tables(struct smu_context *smu) |
813ce279 KW |
506 | { |
507 | struct smu_table_context *smu_table = &smu->smu_table; | |
142dec62 | 508 | int ret = 0; |
813ce279 | 509 | |
871e5e72 | 510 | if (!smu_table->tables) |
813ce279 KW |
511 | return -EINVAL; |
512 | ||
78eb4a36 EQ |
513 | kfree(smu_table->boot_overdrive_table); |
514 | kfree(smu_table->overdrive_table); | |
515 | kfree(smu_table->max_sustainable_clocks); | |
516 | kfree(smu_table->driver_pptable); | |
517 | smu_table->boot_overdrive_table = NULL; | |
518 | smu_table->overdrive_table = NULL; | |
519 | smu_table->max_sustainable_clocks = NULL; | |
520 | smu_table->driver_pptable = NULL; | |
521 | kfree(smu_table->hardcode_pptable); | |
522 | smu_table->hardcode_pptable = NULL; | |
523 | ||
813ce279 | 524 | kfree(smu_table->tables); |
62b9a88c | 525 | kfree(smu_table->metrics_table); |
9fa1ed5b | 526 | kfree(smu_table->watermarks_table); |
813ce279 | 527 | smu_table->tables = NULL; |
62b9a88c | 528 | smu_table->metrics_table = NULL; |
9fa1ed5b | 529 | smu_table->watermarks_table = NULL; |
62b9a88c | 530 | smu_table->metrics_time = 0; |
813ce279 | 531 | |
142dec62 KW |
532 | ret = smu_v11_0_fini_dpm_context(smu); |
533 | if (ret) | |
534 | return ret; | |
813ce279 | 535 | return 0; |
813ce279 | 536 | } |
8bf16963 | 537 | |
6c45e480 | 538 | int smu_v11_0_init_power(struct smu_context *smu) |
8bf16963 KW |
539 | { |
540 | struct smu_power_context *smu_power = &smu->smu_power; | |
541 | ||
542 | if (smu_power->power_context || smu_power->power_context_size != 0) | |
543 | return -EINVAL; | |
544 | ||
545 | smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context), | |
546 | GFP_KERNEL); | |
547 | if (!smu_power->power_context) | |
548 | return -ENOMEM; | |
549 | smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context); | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
6c45e480 | 554 | int smu_v11_0_fini_power(struct smu_context *smu) |
8bf16963 KW |
555 | { |
556 | struct smu_power_context *smu_power = &smu->smu_power; | |
557 | ||
558 | if (!smu_power->power_context || smu_power->power_context_size == 0) | |
559 | return -EINVAL; | |
560 | ||
561 | kfree(smu_power->power_context); | |
562 | smu_power->power_context = NULL; | |
563 | smu_power->power_context_size = 0; | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
12ea3449 EQ |
568 | static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, |
569 | uint8_t clk_id, | |
570 | uint8_t syspll_id, | |
571 | uint32_t *clk_freq) | |
572 | { | |
573 | struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; | |
574 | struct atom_get_smu_clock_info_output_parameters_v3_1 *output; | |
575 | int ret, index; | |
576 | ||
577 | input.clk_id = clk_id; | |
578 | input.syspll_id = syspll_id; | |
579 | input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; | |
580 | index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, | |
581 | getsmuclockinfo); | |
582 | ||
583 | ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, | |
584 | (uint32_t *)&input); | |
585 | if (ret) | |
586 | return -EINVAL; | |
587 | ||
588 | output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; | |
589 | *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
846f1a03 HR |
594 | int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) |
595 | { | |
596 | int ret, index; | |
597 | uint16_t size; | |
598 | uint8_t frev, crev; | |
599 | struct atom_common_table_header *header; | |
600 | struct atom_firmware_info_v3_3 *v_3_3; | |
601 | struct atom_firmware_info_v3_1 *v_3_1; | |
602 | ||
603 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, | |
604 | firmwareinfo); | |
605 | ||
606 | ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev, | |
607 | (uint8_t **)&header); | |
608 | if (ret) | |
609 | return ret; | |
610 | ||
611 | if (header->format_revision != 3) { | |
612 | pr_err("unknown atom_firmware_info version! for smu11\n"); | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
616 | switch (header->content_revision) { | |
617 | case 0: | |
618 | case 1: | |
619 | case 2: | |
620 | v_3_1 = (struct atom_firmware_info_v3_1 *)header; | |
621 | smu->smu_table.boot_values.revision = v_3_1->firmware_revision; | |
622 | smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; | |
623 | smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; | |
624 | smu->smu_table.boot_values.socclk = 0; | |
625 | smu->smu_table.boot_values.dcefclk = 0; | |
626 | smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; | |
627 | smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; | |
628 | smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; | |
629 | smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; | |
630 | smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; | |
631 | smu->smu_table.boot_values.pp_table_id = 0; | |
632 | break; | |
633 | case 3: | |
634 | default: | |
635 | v_3_3 = (struct atom_firmware_info_v3_3 *)header; | |
636 | smu->smu_table.boot_values.revision = v_3_3->firmware_revision; | |
637 | smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; | |
638 | smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; | |
639 | smu->smu_table.boot_values.socclk = 0; | |
640 | smu->smu_table.boot_values.dcefclk = 0; | |
641 | smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; | |
642 | smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; | |
643 | smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; | |
644 | smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; | |
645 | smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; | |
646 | smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; | |
647 | } | |
648 | ||
88810f90 EQ |
649 | smu->smu_table.boot_values.format_revision = header->format_revision; |
650 | smu->smu_table.boot_values.content_revision = header->content_revision; | |
651 | ||
12ea3449 EQ |
652 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
653 | (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, | |
654 | (uint8_t)0, | |
655 | &smu->smu_table.boot_values.socclk); | |
846f1a03 | 656 | |
12ea3449 EQ |
657 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
658 | (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, | |
659 | (uint8_t)0, | |
660 | &smu->smu_table.boot_values.dcefclk); | |
08115f87 | 661 | |
12ea3449 EQ |
662 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
663 | (uint8_t)SMU11_SYSPLL0_ECLK_ID, | |
664 | (uint8_t)0, | |
665 | &smu->smu_table.boot_values.eclk); | |
08115f87 | 666 | |
12ea3449 EQ |
667 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
668 | (uint8_t)SMU11_SYSPLL0_VCLK_ID, | |
669 | (uint8_t)0, | |
670 | &smu->smu_table.boot_values.vclk); | |
08115f87 | 671 | |
12ea3449 EQ |
672 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
673 | (uint8_t)SMU11_SYSPLL0_DCLK_ID, | |
674 | (uint8_t)0, | |
675 | &smu->smu_table.boot_values.dclk); | |
83e21f57 | 676 | |
88810f90 | 677 | if ((smu->smu_table.boot_values.format_revision == 3) && |
12ea3449 EQ |
678 | (smu->smu_table.boot_values.content_revision >= 2)) |
679 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, | |
680 | (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, | |
681 | (uint8_t)SMU11_SYSPLL1_2_ID, | |
682 | &smu->smu_table.boot_values.fclk); | |
88810f90 | 683 | |
08115f87 HR |
684 | return 0; |
685 | } | |
686 | ||
6c45e480 | 687 | int smu_v11_0_notify_memory_pool_location(struct smu_context *smu) |
d72e91c5 KW |
688 | { |
689 | struct smu_table_context *smu_table = &smu->smu_table; | |
690 | struct smu_table *memory_pool = &smu_table->memory_pool; | |
691 | int ret = 0; | |
692 | uint64_t address; | |
693 | uint32_t address_low, address_high; | |
694 | ||
695 | if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) | |
696 | return ret; | |
697 | ||
7a65bdc6 | 698 | address = (uintptr_t)memory_pool->cpu_addr; |
d72e91c5 KW |
699 | address_high = (uint32_t)upper_32_bits(address); |
700 | address_low = (uint32_t)lower_32_bits(address); | |
701 | ||
702 | ret = smu_send_smc_msg_with_param(smu, | |
0914f1c6 | 703 | SMU_MSG_SetSystemVirtualDramAddrHigh, |
1c58267c MC |
704 | address_high, |
705 | NULL); | |
d72e91c5 KW |
706 | if (ret) |
707 | return ret; | |
708 | ret = smu_send_smc_msg_with_param(smu, | |
0914f1c6 | 709 | SMU_MSG_SetSystemVirtualDramAddrLow, |
1c58267c MC |
710 | address_low, |
711 | NULL); | |
d72e91c5 KW |
712 | if (ret) |
713 | return ret; | |
714 | ||
715 | address = memory_pool->mc_address; | |
716 | address_high = (uint32_t)upper_32_bits(address); | |
717 | address_low = (uint32_t)lower_32_bits(address); | |
718 | ||
0914f1c6 | 719 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, |
1c58267c | 720 | address_high, NULL); |
d72e91c5 KW |
721 | if (ret) |
722 | return ret; | |
0914f1c6 | 723 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, |
1c58267c | 724 | address_low, NULL); |
d72e91c5 KW |
725 | if (ret) |
726 | return ret; | |
0914f1c6 | 727 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, |
1c58267c | 728 | (uint32_t)memory_pool->size, NULL); |
d72e91c5 KW |
729 | if (ret) |
730 | return ret; | |
731 | ||
732 | return ret; | |
733 | } | |
734 | ||
6c45e480 | 735 | int smu_v11_0_populate_smc_pptable(struct smu_context *smu) |
29eed6fa | 736 | { |
d6a4aa82 | 737 | int ret; |
29eed6fa | 738 | |
d6a4aa82 | 739 | ret = smu_set_default_dpm_table(smu); |
29eed6fa | 740 | |
d6a4aa82 | 741 | return ret; |
29eed6fa LG |
742 | } |
743 | ||
6c45e480 | 744 | int smu_v11_0_write_pptable(struct smu_context *smu) |
863651b6 | 745 | { |
2c80abe3 | 746 | struct smu_table_context *table_context = &smu->smu_table; |
863651b6 LG |
747 | int ret = 0; |
748 | ||
0d9d78b5 | 749 | ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0, |
33bd73ae | 750 | table_context->driver_pptable, true); |
863651b6 LG |
751 | |
752 | return ret; | |
753 | } | |
754 | ||
6c45e480 | 755 | int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) |
e73cf108 HR |
756 | { |
757 | int ret; | |
758 | ||
759 | ret = smu_send_smc_msg_with_param(smu, | |
1c58267c | 760 | SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); |
e73cf108 HR |
761 | if (ret) |
762 | pr_err("SMU11 attempt to set divider for DCEFCLK Failed!"); | |
763 | ||
764 | return ret; | |
765 | } | |
766 | ||
6c45e480 | 767 | int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu) |
44619596 | 768 | { |
44619596 LG |
769 | struct smu_table_context *table_context = &smu->smu_table; |
770 | ||
771 | if (!table_context) | |
772 | return -EINVAL; | |
773 | ||
6c45e480 | 774 | return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100); |
44619596 LG |
775 | } |
776 | ||
ce0d0ec3 EQ |
777 | int smu_v11_0_set_driver_table_location(struct smu_context *smu) |
778 | { | |
779 | struct smu_table *driver_table = &smu->smu_table.driver_table; | |
780 | int ret = 0; | |
781 | ||
782 | if (driver_table->mc_address) { | |
783 | ret = smu_send_smc_msg_with_param(smu, | |
784 | SMU_MSG_SetDriverDramAddrHigh, | |
1c58267c MC |
785 | upper_32_bits(driver_table->mc_address), |
786 | NULL); | |
ce0d0ec3 EQ |
787 | if (!ret) |
788 | ret = smu_send_smc_msg_with_param(smu, | |
789 | SMU_MSG_SetDriverDramAddrLow, | |
1c58267c MC |
790 | lower_32_bits(driver_table->mc_address), |
791 | NULL); | |
ce0d0ec3 EQ |
792 | } |
793 | ||
794 | return ret; | |
795 | } | |
796 | ||
6c45e480 | 797 | int smu_v11_0_set_tool_table_location(struct smu_context *smu) |
e88e4f83 LG |
798 | { |
799 | int ret = 0; | |
33bd73ae | 800 | struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; |
e88e4f83 LG |
801 | |
802 | if (tool_table->mc_address) { | |
803 | ret = smu_send_smc_msg_with_param(smu, | |
0914f1c6 | 804 | SMU_MSG_SetToolsDramAddrHigh, |
1c58267c MC |
805 | upper_32_bits(tool_table->mc_address), |
806 | NULL); | |
e88e4f83 LG |
807 | if (!ret) |
808 | ret = smu_send_smc_msg_with_param(smu, | |
0914f1c6 | 809 | SMU_MSG_SetToolsDramAddrLow, |
1c58267c MC |
810 | lower_32_bits(tool_table->mc_address), |
811 | NULL); | |
e88e4f83 LG |
812 | } |
813 | ||
814 | return ret; | |
815 | } | |
816 | ||
6c45e480 | 817 | int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) |
56c53ad6 KW |
818 | { |
819 | int ret = 0; | |
a254bfa2 | 820 | |
38748ad8 ML |
821 | if (!smu->pm_enabled) |
822 | return ret; | |
823 | ||
1c58267c | 824 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL); |
56c53ad6 KW |
825 | return ret; |
826 | } | |
827 | ||
f14a323d | 828 | |
6c45e480 | 829 | int smu_v11_0_set_allowed_mask(struct smu_context *smu) |
6b816d73 KW |
830 | { |
831 | struct smu_feature *feature = &smu->smu_feature; | |
832 | int ret = 0; | |
833 | uint32_t feature_mask[2]; | |
834 | ||
f14a323d | 835 | mutex_lock(&feature->mutex); |
6b816d73 | 836 | if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) |
f14a323d | 837 | goto failed; |
6b816d73 KW |
838 | |
839 | bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64); | |
840 | ||
841 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, | |
1c58267c | 842 | feature_mask[1], NULL); |
6b816d73 | 843 | if (ret) |
f14a323d | 844 | goto failed; |
6b816d73 KW |
845 | |
846 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow, | |
1c58267c | 847 | feature_mask[0], NULL); |
6b816d73 | 848 | if (ret) |
f14a323d | 849 | goto failed; |
6b816d73 | 850 | |
f14a323d KW |
851 | failed: |
852 | mutex_unlock(&feature->mutex); | |
6b816d73 KW |
853 | return ret; |
854 | } | |
855 | ||
6c45e480 | 856 | int smu_v11_0_get_enabled_mask(struct smu_context *smu, |
6b816d73 KW |
857 | uint32_t *feature_mask, uint32_t num) |
858 | { | |
859 | uint32_t feature_mask_high = 0, feature_mask_low = 0; | |
6a876844 | 860 | struct smu_feature *feature = &smu->smu_feature; |
6b816d73 KW |
861 | int ret = 0; |
862 | ||
863 | if (!feature_mask || num < 2) | |
864 | return -EINVAL; | |
865 | ||
6a876844 | 866 | if (bitmap_empty(feature->enabled, feature->feature_num)) { |
1c58267c | 867 | ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &feature_mask_high); |
6a876844 EQ |
868 | if (ret) |
869 | return ret; | |
6b816d73 | 870 | |
1c58267c | 871 | ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow, &feature_mask_low); |
6a876844 EQ |
872 | if (ret) |
873 | return ret; | |
6b816d73 | 874 | |
6a876844 EQ |
875 | feature_mask[0] = feature_mask_low; |
876 | feature_mask[1] = feature_mask_high; | |
877 | } else { | |
878 | bitmap_copy((unsigned long *)feature_mask, feature->enabled, | |
879 | feature->feature_num); | |
880 | } | |
6b816d73 KW |
881 | |
882 | return ret; | |
883 | } | |
884 | ||
6c45e480 | 885 | int smu_v11_0_system_features_control(struct smu_context *smu, |
f067499b | 886 | bool en) |
6b816d73 KW |
887 | { |
888 | struct smu_feature *feature = &smu->smu_feature; | |
889 | uint32_t feature_mask[2]; | |
890 | int ret = 0; | |
891 | ||
6a876844 | 892 | ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : |
1c58267c | 893 | SMU_MSG_DisableAllSmuFeatures), NULL); |
6b816d73 KW |
894 | if (ret) |
895 | return ret; | |
896 | ||
79275af6 EQ |
897 | bitmap_zero(feature->enabled, feature->feature_num); |
898 | bitmap_zero(feature->supported, feature->feature_num); | |
899 | ||
6a876844 EQ |
900 | if (en) { |
901 | ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); | |
902 | if (ret) | |
903 | return ret; | |
904 | ||
905 | bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, | |
906 | feature->feature_num); | |
907 | bitmap_copy(feature->supported, (unsigned long *)&feature_mask, | |
908 | feature->feature_num); | |
6a876844 | 909 | } |
6b816d73 KW |
910 | |
911 | return ret; | |
912 | } | |
913 | ||
6c45e480 | 914 | int smu_v11_0_notify_display_change(struct smu_context *smu) |
e1c6f86a KW |
915 | { |
916 | int ret = 0; | |
917 | ||
38748ad8 ML |
918 | if (!smu->pm_enabled) |
919 | return ret; | |
920 | ||
687e8ad0 KF |
921 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && |
922 | smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) | |
1c58267c | 923 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); |
e1c6f86a KW |
924 | |
925 | return ret; | |
926 | } | |
927 | ||
7457cf02 HR |
928 | static int |
929 | smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, | |
0de94acf | 930 | enum smu_clk_type clock_select) |
7457cf02 HR |
931 | { |
932 | int ret = 0; | |
c0640304 | 933 | int clk_id; |
7457cf02 | 934 | |
8dd45504 EQ |
935 | if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || |
936 | (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0)) | |
937 | return 0; | |
938 | ||
c0640304 EQ |
939 | clk_id = smu_clk_get_index(smu, clock_select); |
940 | if (clk_id < 0) | |
941 | return -EINVAL; | |
942 | ||
7457cf02 | 943 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, |
1c58267c | 944 | clk_id << 16, clock); |
7457cf02 HR |
945 | if (ret) { |
946 | pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); | |
947 | return ret; | |
948 | } | |
949 | ||
7457cf02 HR |
950 | if (*clock != 0) |
951 | return 0; | |
952 | ||
953 | /* if DC limit is zero, return AC limit */ | |
954 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, | |
1c58267c | 955 | clk_id << 16, clock); |
7457cf02 HR |
956 | if (ret) { |
957 | pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!"); | |
958 | return ret; | |
959 | } | |
960 | ||
1c58267c | 961 | return 0; |
7457cf02 HR |
962 | } |
963 | ||
6c45e480 | 964 | int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu) |
7457cf02 | 965 | { |
78eb4a36 EQ |
966 | struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = |
967 | smu->smu_table.max_sustainable_clocks; | |
7457cf02 HR |
968 | int ret = 0; |
969 | ||
7457cf02 HR |
970 | max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; |
971 | max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; | |
972 | max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; | |
973 | max_sustainable_clocks->display_clock = 0xFFFFFFFF; | |
974 | max_sustainable_clocks->phy_clock = 0xFFFFFFFF; | |
975 | max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; | |
976 | ||
ffcb08df | 977 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { |
7457cf02 HR |
978 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
979 | &(max_sustainable_clocks->uclock), | |
0de94acf | 980 | SMU_UCLK); |
7457cf02 HR |
981 | if (ret) { |
982 | pr_err("[%s] failed to get max UCLK from SMC!", | |
983 | __func__); | |
984 | return ret; | |
985 | } | |
986 | } | |
987 | ||
ffcb08df | 988 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { |
7457cf02 HR |
989 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
990 | &(max_sustainable_clocks->soc_clock), | |
0de94acf | 991 | SMU_SOCCLK); |
7457cf02 HR |
992 | if (ret) { |
993 | pr_err("[%s] failed to get max SOCCLK from SMC!", | |
994 | __func__); | |
995 | return ret; | |
996 | } | |
997 | } | |
998 | ||
ffcb08df | 999 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { |
7457cf02 HR |
1000 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
1001 | &(max_sustainable_clocks->dcef_clock), | |
0de94acf | 1002 | SMU_DCEFCLK); |
7457cf02 HR |
1003 | if (ret) { |
1004 | pr_err("[%s] failed to get max DCEFCLK from SMC!", | |
1005 | __func__); | |
1006 | return ret; | |
1007 | } | |
1008 | ||
1009 | ret = smu_v11_0_get_max_sustainable_clock(smu, | |
1010 | &(max_sustainable_clocks->display_clock), | |
0de94acf | 1011 | SMU_DISPCLK); |
7457cf02 HR |
1012 | if (ret) { |
1013 | pr_err("[%s] failed to get max DISPCLK from SMC!", | |
1014 | __func__); | |
1015 | return ret; | |
1016 | } | |
1017 | ret = smu_v11_0_get_max_sustainable_clock(smu, | |
1018 | &(max_sustainable_clocks->phy_clock), | |
0de94acf | 1019 | SMU_PHYCLK); |
7457cf02 HR |
1020 | if (ret) { |
1021 | pr_err("[%s] failed to get max PHYCLK from SMC!", | |
1022 | __func__); | |
1023 | return ret; | |
1024 | } | |
1025 | ret = smu_v11_0_get_max_sustainable_clock(smu, | |
1026 | &(max_sustainable_clocks->pixel_clock), | |
0de94acf | 1027 | SMU_PIXCLK); |
7457cf02 HR |
1028 | if (ret) { |
1029 | pr_err("[%s] failed to get max PIXCLK from SMC!", | |
1030 | __func__); | |
1031 | return ret; | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) | |
1036 | max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | ||
73abde4d MC |
1041 | uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) { |
1042 | uint32_t od_limit, max_power_limit; | |
1043 | struct smu_11_0_powerplay_table *powerplay_table = NULL; | |
1044 | struct smu_table_context *table_context = &smu->smu_table; | |
1045 | powerplay_table = table_context->power_play_table; | |
1046 | ||
1047 | max_power_limit = smu_get_pptable_power_limit(smu); | |
1048 | ||
1049 | if (!max_power_limit) { | |
1050 | // If we couldn't get the table limit, fall back on first-read value | |
1051 | if (!smu->default_power_limit) | |
1052 | smu->default_power_limit = smu->power_limit; | |
1053 | max_power_limit = smu->default_power_limit; | |
1054 | } | |
1055 | ||
1056 | if (smu->od_enabled) { | |
1057 | od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); | |
1058 | ||
1059 | pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit); | |
1060 | ||
1061 | max_power_limit *= (100 + od_limit); | |
1062 | max_power_limit /= 100; | |
1063 | } | |
1064 | ||
1065 | return max_power_limit; | |
1066 | } | |
1067 | ||
6c45e480 | 1068 | int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) |
e66adb1e | 1069 | { |
014c4440 | 1070 | int ret = 0; |
73abde4d MC |
1071 | uint32_t max_power_limit; |
1072 | ||
1073 | max_power_limit = smu_v11_0_get_max_power_limit(smu); | |
c0640304 | 1074 | |
73abde4d MC |
1075 | if (n > max_power_limit) { |
1076 | pr_err("New power limit (%d) is over the max allowed %d\n", | |
1077 | n, | |
1078 | max_power_limit); | |
c0640304 | 1079 | return -EINVAL; |
014c4440 CG |
1080 | } |
1081 | ||
07740adc LG |
1082 | if (n == 0) |
1083 | n = smu->default_power_limit; | |
1084 | ||
b4af964e EQ |
1085 | if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { |
1086 | pr_err("Setting new power limit is not supported!\n"); | |
1087 | return -EOPNOTSUPP; | |
07740adc LG |
1088 | } |
1089 | ||
1c58267c | 1090 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL); |
e66adb1e | 1091 | if (ret) { |
b4af964e | 1092 | pr_err("[%s] Set power limit Failed!\n", __func__); |
e66adb1e LG |
1093 | return ret; |
1094 | } | |
b4af964e | 1095 | smu->power_limit = n; |
e66adb1e | 1096 | |
b4af964e | 1097 | return 0; |
e66adb1e LG |
1098 | } |
1099 | ||
6c45e480 | 1100 | int smu_v11_0_get_current_clk_freq(struct smu_context *smu, |
0de94acf HR |
1101 | enum smu_clk_type clk_id, |
1102 | uint32_t *value) | |
bed3b3a1 KW |
1103 | { |
1104 | int ret = 0; | |
68c3bd95 | 1105 | uint32_t freq = 0; |
c0640304 | 1106 | int asic_clk_id; |
bed3b3a1 | 1107 | |
0de94acf | 1108 | if (clk_id >= SMU_CLK_COUNT || !value) |
bed3b3a1 KW |
1109 | return -EINVAL; |
1110 | ||
c0640304 EQ |
1111 | asic_clk_id = smu_clk_get_index(smu, clk_id); |
1112 | if (asic_clk_id < 0) | |
1113 | return -EINVAL; | |
1114 | ||
98e1a543 | 1115 | /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */ |
c0640304 | 1116 | if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0) |
e3618249 KW |
1117 | ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq); |
1118 | else { | |
1119 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq, | |
1c58267c | 1120 | (asic_clk_id << 16), &freq); |
e3618249 KW |
1121 | if (ret) |
1122 | return ret; | |
1123 | } | |
bed3b3a1 KW |
1124 | |
1125 | freq *= 100; | |
1126 | *value = freq; | |
1127 | ||
1128 | return ret; | |
1129 | } | |
1130 | ||
83e1ede6 | 1131 | static int smu_v11_0_set_thermal_range(struct smu_context *smu, |
a056ddce | 1132 | struct smu_temperature_range range) |
83e1ede6 LG |
1133 | { |
1134 | struct amdgpu_device *adev = smu->adev; | |
7a816371 KW |
1135 | int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; |
1136 | int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; | |
83e1ede6 | 1137 | uint32_t val; |
b1ffd1e3 KF |
1138 | struct smu_table_context *table_context = &smu->smu_table; |
1139 | struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; | |
83e1ede6 | 1140 | |
a056ddce EQ |
1141 | low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, |
1142 | range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); | |
40c9e7b5 | 1143 | high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); |
7a816371 | 1144 | |
83e1ede6 LG |
1145 | if (low > high) |
1146 | return -EINVAL; | |
1147 | ||
1148 | val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); | |
1149 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); | |
1150 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); | |
7a816371 KW |
1151 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); |
1152 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); | |
83e1ede6 LG |
1153 | val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); |
1154 | ||
1155 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
22f1e0e8 | 1160 | int smu_v11_0_enable_thermal_alert(struct smu_context *smu) |
74ba3553 LG |
1161 | { |
1162 | int ret = 0; | |
a056ddce | 1163 | struct smu_temperature_range range; |
74ba3553 LG |
1164 | struct amdgpu_device *adev = smu->adev; |
1165 | ||
a056ddce EQ |
1166 | memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); |
1167 | ||
e211580d | 1168 | ret = smu_get_thermal_temperature_range(smu, &range); |
7a816371 KW |
1169 | if (ret) |
1170 | return ret; | |
74ba3553 LG |
1171 | |
1172 | if (smu->smu_table.thermal_controller_type) { | |
a056ddce | 1173 | ret = smu_v11_0_set_thermal_range(smu, range); |
74ba3553 LG |
1174 | if (ret) |
1175 | return ret; | |
1176 | ||
be80b431 | 1177 | ret = amdgpu_irq_get(adev, smu->irq_source, 0); |
74ba3553 LG |
1178 | if (ret) |
1179 | return ret; | |
5e6d2665 | 1180 | |
ee0db820 | 1181 | ret = smu_set_thermal_fan_table(smu); |
74ba3553 LG |
1182 | if (ret) |
1183 | return ret; | |
1184 | } | |
1185 | ||
a056ddce EQ |
1186 | adev->pm.dpm.thermal.min_temp = range.min; |
1187 | adev->pm.dpm.thermal.max_temp = range.max; | |
1188 | adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max; | |
1189 | adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; | |
1190 | adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max; | |
1191 | adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max; | |
1192 | adev->pm.dpm.thermal.min_mem_temp = range.mem_min; | |
1193 | adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max; | |
1194 | adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max; | |
74ba3553 LG |
1195 | |
1196 | return ret; | |
1197 | } | |
1198 | ||
22f1e0e8 | 1199 | int smu_v11_0_disable_thermal_alert(struct smu_context *smu) |
faa695c7 | 1200 | { |
be80b431 | 1201 | return amdgpu_irq_put(smu->adev, smu->irq_source, 0); |
faa695c7 EQ |
1202 | } |
1203 | ||
77d1eef4 KW |
1204 | static uint16_t convert_to_vddc(uint8_t vid) |
1205 | { | |
1206 | return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE); | |
1207 | } | |
1208 | ||
1209 | static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) | |
1210 | { | |
1211 | struct amdgpu_device *adev = smu->adev; | |
1212 | uint32_t vdd = 0, val_vid = 0; | |
1213 | ||
1214 | if (!value) | |
1215 | return -EINVAL; | |
1216 | val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & | |
1217 | SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> | |
1218 | SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; | |
1219 | ||
1220 | vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); | |
1221 | ||
1222 | *value = vdd; | |
1223 | ||
1224 | return 0; | |
1225 | ||
1226 | } | |
1227 | ||
6c45e480 | 1228 | int smu_v11_0_read_sensor(struct smu_context *smu, |
4a5a2de6 KW |
1229 | enum amd_pp_sensors sensor, |
1230 | void *data, uint32_t *size) | |
1231 | { | |
1232 | int ret = 0; | |
9b4e63f4 KF |
1233 | |
1234 | if(!data || !size) | |
1235 | return -EINVAL; | |
1236 | ||
4a5a2de6 | 1237 | switch (sensor) { |
c9b66043 | 1238 | case AMDGPU_PP_SENSOR_GFX_MCLK: |
0de94acf | 1239 | ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data); |
c9b66043 KW |
1240 | *size = 4; |
1241 | break; | |
1242 | case AMDGPU_PP_SENSOR_GFX_SCLK: | |
0de94acf | 1243 | ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data); |
c9b66043 | 1244 | *size = 4; |
2f613c70 | 1245 | break; |
77d1eef4 KW |
1246 | case AMDGPU_PP_SENSOR_VDDGFX: |
1247 | ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); | |
1248 | *size = 4; | |
4a5a2de6 | 1249 | break; |
637c1c66 LG |
1250 | case AMDGPU_PP_SENSOR_MIN_FAN_RPM: |
1251 | *(uint32_t *)data = 0; | |
1252 | *size = 4; | |
1253 | break; | |
4a5a2de6 | 1254 | default: |
143c75d6 | 1255 | ret = smu_common_read_sensor(smu, sensor, data, size); |
4a5a2de6 KW |
1256 | break; |
1257 | } | |
1258 | ||
1259 | if (ret) | |
1260 | *size = 0; | |
1261 | ||
1262 | return ret; | |
1263 | } | |
1264 | ||
6c45e480 | 1265 | int |
04885368 HR |
1266 | smu_v11_0_display_clock_voltage_request(struct smu_context *smu, |
1267 | struct pp_display_clock_request | |
1268 | *clock_req) | |
1269 | { | |
1270 | enum amd_pp_clock_type clk_type = clock_req->clock_type; | |
1271 | int ret = 0; | |
0de94acf | 1272 | enum smu_clk_type clk_select = 0; |
04885368 HR |
1273 | uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; |
1274 | ||
382fb778 | 1275 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || |
5c170a59 | 1276 | smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { |
04885368 HR |
1277 | switch (clk_type) { |
1278 | case amd_pp_dcef_clock: | |
0de94acf | 1279 | clk_select = SMU_DCEFCLK; |
04885368 HR |
1280 | break; |
1281 | case amd_pp_disp_clock: | |
0de94acf | 1282 | clk_select = SMU_DISPCLK; |
04885368 HR |
1283 | break; |
1284 | case amd_pp_pixel_clock: | |
0de94acf | 1285 | clk_select = SMU_PIXCLK; |
04885368 HR |
1286 | break; |
1287 | case amd_pp_phy_clock: | |
0de94acf | 1288 | clk_select = SMU_PHYCLK; |
04885368 | 1289 | break; |
382fb778 | 1290 | case amd_pp_mem_clock: |
1291 | clk_select = SMU_UCLK; | |
1292 | break; | |
04885368 HR |
1293 | default: |
1294 | pr_info("[%s] Invalid Clock Type!", __func__); | |
1295 | ret = -EINVAL; | |
1296 | break; | |
1297 | } | |
1298 | ||
1299 | if (ret) | |
1300 | goto failed; | |
1301 | ||
6e92e156 KF |
1302 | if (clk_select == SMU_UCLK && smu->disable_uclk_switch) |
1303 | return 0; | |
1304 | ||
60adad6f | 1305 | ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0); |
6e92e156 KF |
1306 | |
1307 | if(clk_select == SMU_UCLK) | |
1308 | smu->hard_min_uclk_req_from_dal = clk_freq; | |
04885368 HR |
1309 | } |
1310 | ||
1311 | failed: | |
04885368 HR |
1312 | return ret; |
1313 | } | |
1314 | ||
6c45e480 | 1315 | int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) |
bca32528 KF |
1316 | { |
1317 | int ret = 0; | |
acbcc111 | 1318 | struct amdgpu_device *adev = smu->adev; |
bca32528 | 1319 | |
acbcc111 | 1320 | switch (adev->asic_type) { |
acbcc111 | 1321 | case CHIP_NAVI10: |
ba02636d | 1322 | case CHIP_NAVI14: |
9ea8da75 | 1323 | case CHIP_NAVI12: |
e0da123a | 1324 | case CHIP_SIENNA_CICHLID: |
acbcc111 KF |
1325 | if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) |
1326 | return 0; | |
acbcc111 | 1327 | if (enable) |
1c58267c | 1328 | ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); |
acbcc111 | 1329 | else |
1c58267c | 1330 | ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); |
acbcc111 KF |
1331 | break; |
1332 | default: | |
1333 | break; | |
1334 | } | |
bca32528 KF |
1335 | |
1336 | return ret; | |
1337 | } | |
1338 | ||
6c45e480 | 1339 | uint32_t |
008a9524 CG |
1340 | smu_v11_0_get_fan_control_mode(struct smu_context *smu) |
1341 | { | |
ffcb08df | 1342 | if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) |
008a9524 CG |
1343 | return AMD_FAN_CTRL_MANUAL; |
1344 | else | |
1345 | return AMD_FAN_CTRL_AUTO; | |
1346 | } | |
1347 | ||
008a9524 | 1348 | static int |
fcd90fee | 1349 | smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) |
008a9524 CG |
1350 | { |
1351 | int ret = 0; | |
1352 | ||
f0ced3f6 | 1353 | if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) |
008a9524 CG |
1354 | return 0; |
1355 | ||
fcd90fee | 1356 | ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); |
008a9524 CG |
1357 | if (ret) |
1358 | pr_err("[%s]%s smc FAN CONTROL feature failed!", | |
fcd90fee | 1359 | __func__, (auto_fan_control ? "Start" : "Stop")); |
008a9524 CG |
1360 | |
1361 | return ret; | |
1362 | } | |
1363 | ||
1364 | static int | |
1365 | smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) | |
1366 | { | |
1367 | struct amdgpu_device *adev = smu->adev; | |
1368 | ||
1369 | WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, | |
1370 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), | |
1371 | CG_FDO_CTRL2, TMIN, 0)); | |
1372 | WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, | |
1373 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), | |
1374 | CG_FDO_CTRL2, FDO_PWM_MODE, mode)); | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
6c45e480 | 1379 | int |
008a9524 CG |
1380 | smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) |
1381 | { | |
1382 | struct amdgpu_device *adev = smu->adev; | |
fcd90fee | 1383 | uint32_t duty100, duty; |
008a9524 | 1384 | uint64_t tmp64; |
008a9524 CG |
1385 | |
1386 | if (speed > 100) | |
1387 | speed = 100; | |
1388 | ||
fcd90fee | 1389 | if (smu_v11_0_auto_fan_control(smu, 0)) |
008a9524 | 1390 | return -EINVAL; |
fcd90fee | 1391 | |
008a9524 CG |
1392 | duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), |
1393 | CG_FDO_CTRL1, FMAX_DUTY100); | |
1394 | if (!duty100) | |
1395 | return -EINVAL; | |
1396 | ||
1397 | tmp64 = (uint64_t)speed * duty100; | |
1398 | do_div(tmp64, 100); | |
1399 | duty = (uint32_t)tmp64; | |
1400 | ||
1401 | WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, | |
1402 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), | |
1403 | CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); | |
1404 | ||
1405 | return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); | |
1406 | } | |
1407 | ||
6c45e480 | 1408 | int |
a76ff5af CG |
1409 | smu_v11_0_set_fan_control_mode(struct smu_context *smu, |
1410 | uint32_t mode) | |
1411 | { | |
1412 | int ret = 0; | |
a76ff5af CG |
1413 | |
1414 | switch (mode) { | |
1415 | case AMD_FAN_CTRL_NONE: | |
1416 | ret = smu_v11_0_set_fan_speed_percent(smu, 100); | |
1417 | break; | |
1418 | case AMD_FAN_CTRL_MANUAL: | |
fcd90fee | 1419 | ret = smu_v11_0_auto_fan_control(smu, 0); |
a76ff5af CG |
1420 | break; |
1421 | case AMD_FAN_CTRL_AUTO: | |
fcd90fee | 1422 | ret = smu_v11_0_auto_fan_control(smu, 1); |
a76ff5af CG |
1423 | break; |
1424 | default: | |
1425 | break; | |
1426 | } | |
1427 | ||
1428 | if (ret) { | |
da5f18e8 | 1429 | pr_err("[%s]Set fan control mode failed!", __func__); |
a76ff5af CG |
1430 | return -EINVAL; |
1431 | } | |
1432 | ||
1433 | return ret; | |
1434 | } | |
1435 | ||
6c45e480 | 1436 | int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, |
96026ce0 LG |
1437 | uint32_t speed) |
1438 | { | |
1439 | struct amdgpu_device *adev = smu->adev; | |
1440 | int ret; | |
1441 | uint32_t tach_period, crystal_clock_freq; | |
96026ce0 LG |
1442 | |
1443 | if (!speed) | |
1444 | return -EINVAL; | |
1445 | ||
fcd90fee | 1446 | ret = smu_v11_0_auto_fan_control(smu, 0); |
96026ce0 | 1447 | if (ret) |
3697b339 | 1448 | return ret; |
96026ce0 LG |
1449 | |
1450 | crystal_clock_freq = amdgpu_asic_get_xclk(adev); | |
1451 | tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); | |
1452 | WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, | |
1453 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), | |
1454 | CG_TACH_CTRL, TARGET_PERIOD, | |
1455 | tach_period)); | |
1456 | ||
1457 | ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); | |
1458 | ||
96026ce0 LG |
1459 | return ret; |
1460 | } | |
1461 | ||
6c45e480 | 1462 | int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, |
e911671c | 1463 | uint32_t pstate) |
1464 | { | |
a1b11201 | 1465 | int ret = 0; |
a1b11201 | 1466 | ret = smu_send_smc_msg_with_param(smu, |
1467 | SMU_MSG_SetXgmiMode, | |
1c58267c MC |
1468 | pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, |
1469 | NULL); | |
a1b11201 | 1470 | return ret; |
e911671c | 1471 | } |
1472 | ||
be80b431 EQ |
1473 | static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, |
1474 | struct amdgpu_irq_src *source, | |
1475 | unsigned tyep, | |
1476 | enum amdgpu_interrupt_state state) | |
1477 | { | |
1478 | uint32_t val = 0; | |
1479 | ||
1480 | switch (state) { | |
1481 | case AMDGPU_IRQ_STATE_DISABLE: | |
1482 | /* For THM irqs */ | |
1483 | val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); | |
1484 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); | |
1485 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); | |
1486 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); | |
1487 | ||
1488 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); | |
1489 | ||
1490 | /* For MP1 SW irqs */ | |
1491 | val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); | |
1492 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); | |
1493 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); | |
1494 | ||
1495 | break; | |
1496 | case AMDGPU_IRQ_STATE_ENABLE: | |
1497 | /* For THM irqs */ | |
1498 | val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); | |
1499 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); | |
1500 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); | |
1501 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); | |
1502 | ||
1503 | val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); | |
1504 | val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); | |
1505 | val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); | |
1506 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); | |
1507 | ||
1508 | /* For MP1 SW irqs */ | |
1509 | val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); | |
1510 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); | |
1511 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); | |
1512 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); | |
1513 | ||
1514 | val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); | |
1515 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); | |
1516 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); | |
1517 | ||
1518 | break; | |
1519 | default: | |
1520 | break; | |
1521 | } | |
1522 | ||
1523 | return 0; | |
1524 | } | |
1525 | ||
e1188aac AD |
1526 | static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu) |
1527 | { | |
1528 | return smu_send_smc_msg(smu, | |
1529 | SMU_MSG_ReenableAcDcInterrupt, | |
1530 | NULL); | |
1531 | } | |
1532 | ||
5e6d2665 KW |
1533 | #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ |
1534 | #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ | |
1535 | ||
e528ccf9 EQ |
1536 | #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 |
1537 | ||
5e6d2665 KW |
1538 | static int smu_v11_0_irq_process(struct amdgpu_device *adev, |
1539 | struct amdgpu_irq_src *source, | |
1540 | struct amdgpu_iv_entry *entry) | |
1541 | { | |
bcdc7c05 | 1542 | struct smu_context *smu = &adev->smu; |
5e6d2665 KW |
1543 | uint32_t client_id = entry->client_id; |
1544 | uint32_t src_id = entry->src_id; | |
cd598d6c EQ |
1545 | /* |
1546 | * ctxid is used to distinguish different | |
1547 | * events for SMCToHost interrupt. | |
1548 | */ | |
1549 | uint32_t ctxid = entry->src_data[0]; | |
d559aba8 | 1550 | uint32_t data; |
5e6d2665 KW |
1551 | |
1552 | if (client_id == SOC15_IH_CLIENTID_THM) { | |
1553 | switch (src_id) { | |
1554 | case THM_11_0__SRCID__THM_DIG_THERM_L2H: | |
27a468ea | 1555 | dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); |
94952205 EQ |
1556 | /* |
1557 | * SW CTF just occurred. | |
1558 | * Try to do a graceful shutdown to prevent further damage. | |
1559 | */ | |
27a468ea | 1560 | dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); |
94952205 | 1561 | orderly_poweroff(true); |
5e6d2665 KW |
1562 | break; |
1563 | case THM_11_0__SRCID__THM_DIG_THERM_H2L: | |
27a468ea | 1564 | dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); |
5e6d2665 KW |
1565 | break; |
1566 | default: | |
27a468ea EQ |
1567 | dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", |
1568 | src_id); | |
5e6d2665 | 1569 | break; |
5e6d2665 | 1570 | } |
e528ccf9 | 1571 | } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { |
27a468ea | 1572 | dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); |
e528ccf9 EQ |
1573 | /* |
1574 | * HW CTF just occurred. Shutdown to prevent further damage. | |
1575 | */ | |
27a468ea | 1576 | dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); |
e528ccf9 | 1577 | orderly_poweroff(true); |
e1188aac | 1578 | } else if (client_id == SOC15_IH_CLIENTID_MP1) { |
cd598d6c | 1579 | if (src_id == 0xfe) { |
d559aba8 EQ |
1580 | /* ACK SMUToHost interrupt */ |
1581 | data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); | |
1582 | data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); | |
1583 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data); | |
1584 | ||
cd598d6c EQ |
1585 | switch (ctxid) { |
1586 | case 0x3: | |
1587 | dev_dbg(adev->dev, "Switched to AC mode!\n"); | |
1588 | smu_v11_0_ack_ac_dc_interrupt(&adev->smu); | |
1589 | break; | |
1590 | case 0x4: | |
1591 | dev_dbg(adev->dev, "Switched to DC mode!\n"); | |
1592 | smu_v11_0_ack_ac_dc_interrupt(&adev->smu); | |
1593 | break; | |
bcdc7c05 | 1594 | case 0x7: |
b265bdbd EQ |
1595 | if (!atomic_read(&adev->throttling_logging_enabled)) |
1596 | return 0; | |
1597 | ||
1598 | if (__ratelimit(&adev->throttling_logging_rs)) | |
bcdc7c05 EQ |
1599 | smu_log_thermal_throttling(smu); |
1600 | ||
1601 | break; | |
cd598d6c EQ |
1602 | } |
1603 | } | |
5e6d2665 KW |
1604 | } |
1605 | ||
1606 | return 0; | |
1607 | } | |
1608 | ||
1609 | static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs = | |
1610 | { | |
be80b431 | 1611 | .set = smu_v11_0_set_irq_state, |
5e6d2665 KW |
1612 | .process = smu_v11_0_irq_process, |
1613 | }; | |
1614 | ||
6c45e480 | 1615 | int smu_v11_0_register_irq_handler(struct smu_context *smu) |
5e6d2665 KW |
1616 | { |
1617 | struct amdgpu_device *adev = smu->adev; | |
1618 | struct amdgpu_irq_src *irq_src = smu->irq_source; | |
1619 | int ret = 0; | |
1620 | ||
1621 | /* already register */ | |
1622 | if (irq_src) | |
1623 | return 0; | |
1624 | ||
1625 | irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); | |
1626 | if (!irq_src) | |
1627 | return -ENOMEM; | |
1628 | smu->irq_source = irq_src; | |
1629 | ||
be80b431 | 1630 | irq_src->num_types = 1; |
5e6d2665 KW |
1631 | irq_src->funcs = &smu_v11_0_irq_funcs; |
1632 | ||
1633 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, | |
1634 | THM_11_0__SRCID__THM_DIG_THERM_L2H, | |
1635 | irq_src); | |
1636 | if (ret) | |
1637 | return ret; | |
1638 | ||
1639 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, | |
1640 | THM_11_0__SRCID__THM_DIG_THERM_H2L, | |
1641 | irq_src); | |
1642 | if (ret) | |
1643 | return ret; | |
1644 | ||
e528ccf9 EQ |
1645 | /* Register CTF(GPIO_19) interrupt */ |
1646 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, | |
1647 | SMUIO_11_0__SRCID__SMUIO_GPIO19, | |
1648 | irq_src); | |
1649 | if (ret) | |
1650 | return ret; | |
1651 | ||
e1188aac AD |
1652 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, |
1653 | 0xfe, | |
1654 | irq_src); | |
1655 | if (ret) | |
1656 | return ret; | |
1657 | ||
5e6d2665 KW |
1658 | return ret; |
1659 | } | |
1660 | ||
6c45e480 | 1661 | int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, |
a18bf0ca | 1662 | struct pp_smu_nv_clock_table *max_clocks) |
1663 | { | |
1664 | struct smu_table_context *table_context = &smu->smu_table; | |
1665 | struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL; | |
1666 | ||
1667 | if (!max_clocks || !table_context->max_sustainable_clocks) | |
1668 | return -EINVAL; | |
1669 | ||
1670 | sustainable_clocks = table_context->max_sustainable_clocks; | |
1671 | ||
1672 | max_clocks->dcfClockInKhz = | |
1673 | (unsigned int) sustainable_clocks->dcef_clock * 1000; | |
1674 | max_clocks->displayClockInKhz = | |
1675 | (unsigned int) sustainable_clocks->display_clock * 1000; | |
1676 | max_clocks->phyClockInKhz = | |
1677 | (unsigned int) sustainable_clocks->phy_clock * 1000; | |
1678 | max_clocks->pixelClockInKhz = | |
1679 | (unsigned int) sustainable_clocks->pixel_clock * 1000; | |
1680 | max_clocks->uClockInKhz = | |
1681 | (unsigned int) sustainable_clocks->uclock * 1000; | |
1682 | max_clocks->socClockInKhz = | |
1683 | (unsigned int) sustainable_clocks->soc_clock * 1000; | |
1684 | max_clocks->dscClockInKhz = 0; | |
1685 | max_clocks->dppClockInKhz = 0; | |
1686 | max_clocks->fabricClockInKhz = 0; | |
1687 | ||
1688 | return 0; | |
1689 | } | |
1690 | ||
6c45e480 | 1691 | int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu) |
26e2b581 | 1692 | { |
1693 | int ret = 0; | |
1694 | ||
1c58267c | 1695 | ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); |
26e2b581 | 1696 | |
1697 | return ret; | |
1698 | } | |
1699 | ||
767acabd KW |
1700 | static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq) |
1701 | { | |
1c58267c | 1702 | return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL); |
767acabd KW |
1703 | } |
1704 | ||
6c45e480 | 1705 | bool smu_v11_0_baco_is_support(struct smu_context *smu) |
767acabd | 1706 | { |
767acabd | 1707 | struct smu_baco_context *smu_baco = &smu->smu_baco; |
767acabd KW |
1708 | bool baco_support; |
1709 | ||
1710 | mutex_lock(&smu_baco->mutex); | |
1711 | baco_support = smu_baco->platform_support; | |
1712 | mutex_unlock(&smu_baco->mutex); | |
1713 | ||
1714 | if (!baco_support) | |
1715 | return false; | |
1716 | ||
0a650c1d EQ |
1717 | /* Arcturus does not support this bit mask */ |
1718 | if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && | |
1719 | !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) | |
767acabd KW |
1720 | return false; |
1721 | ||
49e78c82 | 1722 | return true; |
767acabd KW |
1723 | } |
1724 | ||
6c45e480 | 1725 | enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu) |
767acabd KW |
1726 | { |
1727 | struct smu_baco_context *smu_baco = &smu->smu_baco; | |
a13362c1 | 1728 | enum smu_baco_state baco_state; |
767acabd KW |
1729 | |
1730 | mutex_lock(&smu_baco->mutex); | |
1731 | baco_state = smu_baco->state; | |
1732 | mutex_unlock(&smu_baco->mutex); | |
1733 | ||
1734 | return baco_state; | |
1735 | } | |
1736 | ||
6c45e480 | 1737 | int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) |
767acabd | 1738 | { |
767acabd | 1739 | struct smu_baco_context *smu_baco = &smu->smu_baco; |
b4f8285a EQ |
1740 | struct amdgpu_device *adev = smu->adev; |
1741 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
b4f8285a | 1742 | uint32_t data; |
767acabd KW |
1743 | int ret = 0; |
1744 | ||
1745 | if (smu_v11_0_baco_get_state(smu) == state) | |
1746 | return 0; | |
1747 | ||
1748 | mutex_lock(&smu_baco->mutex); | |
1749 | ||
b4f8285a | 1750 | if (state == SMU_BACO_STATE_ENTER) { |
b4f8285a EQ |
1751 | if (!ras || !ras->supported) { |
1752 | data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); | |
1753 | data |= 0x80000000; | |
1754 | WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); | |
1755 | ||
1c58267c | 1756 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL); |
b4f8285a | 1757 | } else { |
1c58267c | 1758 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL); |
b4f8285a EQ |
1759 | } |
1760 | } else { | |
1c58267c | 1761 | ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL); |
ae46533b EQ |
1762 | if (ret) |
1763 | goto out; | |
1764 | ||
4f7d010f EQ |
1765 | if (ras && ras->supported) { |
1766 | ret = smu_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); | |
1767 | if (ret) | |
1768 | goto out; | |
1769 | } | |
1770 | ||
ae46533b EQ |
1771 | /* clear vbios scratch 6 and 7 for coming asic reinit */ |
1772 | WREG32(adev->bios_scratch_reg_offset + 6, 0); | |
1773 | WREG32(adev->bios_scratch_reg_offset + 7, 0); | |
b4f8285a | 1774 | } |
767acabd KW |
1775 | if (ret) |
1776 | goto out; | |
1777 | ||
1778 | smu_baco->state = state; | |
1779 | out: | |
1780 | mutex_unlock(&smu_baco->mutex); | |
1781 | return ret; | |
1782 | } | |
1783 | ||
11520f27 | 1784 | int smu_v11_0_baco_enter(struct smu_context *smu) |
767acabd | 1785 | { |
0a650c1d | 1786 | struct amdgpu_device *adev = smu->adev; |
767acabd KW |
1787 | int ret = 0; |
1788 | ||
0a650c1d EQ |
1789 | /* Arcturus does not need this audio workaround */ |
1790 | if (adev->asic_type != CHIP_ARCTURUS) { | |
1791 | ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); | |
1792 | if (ret) | |
1793 | return ret; | |
1794 | } | |
767acabd KW |
1795 | |
1796 | ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); | |
1797 | if (ret) | |
1798 | return ret; | |
1799 | ||
1800 | msleep(10); | |
1801 | ||
11520f27 AD |
1802 | return ret; |
1803 | } | |
1804 | ||
1805 | int smu_v11_0_baco_exit(struct smu_context *smu) | |
1806 | { | |
1807 | int ret = 0; | |
1808 | ||
767acabd KW |
1809 | ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT); |
1810 | if (ret) | |
1811 | return ret; | |
1812 | ||
1813 | return ret; | |
1814 | } | |
1815 | ||
6c45e480 | 1816 | int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, |
eee3258e PL |
1817 | uint32_t *min, uint32_t *max) |
1818 | { | |
1819 | int ret = 0, clk_id = 0; | |
1820 | uint32_t param = 0; | |
1821 | ||
eee3258e PL |
1822 | clk_id = smu_clk_get_index(smu, clk_type); |
1823 | if (clk_id < 0) { | |
1824 | ret = -EINVAL; | |
1825 | goto failed; | |
1826 | } | |
1827 | param = (clk_id & 0xffff) << 16; | |
1828 | ||
1829 | if (max) { | |
1c58267c | 1830 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max); |
eee3258e PL |
1831 | if (ret) |
1832 | goto failed; | |
1833 | } | |
1834 | ||
1835 | if (min) { | |
1c58267c | 1836 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); |
eee3258e PL |
1837 | if (ret) |
1838 | goto failed; | |
1839 | } | |
1840 | ||
1841 | failed: | |
eee3258e PL |
1842 | return ret; |
1843 | } | |
1844 | ||
6c45e480 | 1845 | int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, |
4045f36f PL |
1846 | uint32_t min, uint32_t max) |
1847 | { | |
1848 | int ret = 0, clk_id = 0; | |
1849 | uint32_t param; | |
1850 | ||
1851 | clk_id = smu_clk_get_index(smu, clk_type); | |
1852 | if (clk_id < 0) | |
1853 | return clk_id; | |
1854 | ||
1855 | if (max > 0) { | |
1856 | param = (uint32_t)((clk_id << 16) | (max & 0xffff)); | |
1857 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, | |
1c58267c | 1858 | param, NULL); |
4045f36f PL |
1859 | if (ret) |
1860 | return ret; | |
1861 | } | |
1862 | ||
1863 | if (min > 0) { | |
1864 | param = (uint32_t)((clk_id << 16) | (min & 0xffff)); | |
1865 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, | |
1c58267c | 1866 | param, NULL); |
4045f36f PL |
1867 | if (ret) |
1868 | return ret; | |
1869 | } | |
1870 | ||
1871 | return ret; | |
1872 | } | |
1873 | ||
6c45e480 | 1874 | int smu_v11_0_override_pcie_parameters(struct smu_context *smu) |
372120f0 KF |
1875 | { |
1876 | struct amdgpu_device *adev = smu->adev; | |
1877 | uint32_t pcie_gen = 0, pcie_width = 0; | |
1878 | int ret; | |
1879 | ||
1880 | if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) | |
1881 | pcie_gen = 3; | |
1882 | else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) | |
1883 | pcie_gen = 2; | |
1884 | else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) | |
1885 | pcie_gen = 1; | |
1886 | else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) | |
1887 | pcie_gen = 0; | |
1888 | ||
1889 | /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 | |
1890 | * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 | |
1891 | * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 | |
1892 | */ | |
1893 | if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) | |
1894 | pcie_width = 6; | |
1895 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) | |
1896 | pcie_width = 5; | |
1897 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) | |
1898 | pcie_width = 4; | |
1899 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) | |
1900 | pcie_width = 3; | |
1901 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) | |
1902 | pcie_width = 2; | |
1903 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) | |
1904 | pcie_width = 1; | |
1905 | ||
1906 | ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); | |
1907 | ||
1908 | if (ret) | |
1909 | pr_err("[%s] Attempt to override pcie params failed!\n", __func__); | |
1910 | ||
1911 | return ret; | |
1912 | ||
1913 | } | |
21677d08 MC |
1914 | |
1915 | int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size) | |
1916 | { | |
1917 | struct smu_table_context *table_context = &smu->smu_table; | |
1918 | int ret = 0; | |
1919 | ||
1920 | if (initialize) { | |
21677d08 MC |
1921 | ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); |
1922 | if (ret) { | |
1923 | pr_err("Failed to export overdrive table!\n"); | |
1924 | return ret; | |
1925 | } | |
1926 | } | |
1927 | ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true); | |
1928 | if (ret) { | |
1929 | pr_err("Failed to import overdrive table!\n"); | |
1930 | return ret; | |
1931 | } | |
1932 | return ret; | |
1933 | } | |
337443d0 AD |
1934 | |
1935 | int smu_v11_0_set_performance_level(struct smu_context *smu, | |
1936 | enum amd_dpm_forced_level level) | |
1937 | { | |
1938 | int ret = 0; | |
1939 | uint32_t sclk_mask, mclk_mask, soc_mask; | |
1940 | ||
1941 | switch (level) { | |
1942 | case AMD_DPM_FORCED_LEVEL_HIGH: | |
1943 | ret = smu_force_dpm_limit_value(smu, true); | |
1944 | break; | |
1945 | case AMD_DPM_FORCED_LEVEL_LOW: | |
1946 | ret = smu_force_dpm_limit_value(smu, false); | |
1947 | break; | |
1948 | case AMD_DPM_FORCED_LEVEL_AUTO: | |
1949 | case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: | |
1950 | ret = smu_unforce_dpm_levels(smu); | |
1951 | break; | |
1952 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: | |
1953 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: | |
1954 | case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: | |
1955 | ret = smu_get_profiling_clk_mask(smu, level, | |
1956 | &sclk_mask, | |
1957 | &mclk_mask, | |
1958 | &soc_mask); | |
1959 | if (ret) | |
1960 | return ret; | |
1961 | smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false); | |
1962 | smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false); | |
1963 | smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false); | |
1964 | break; | |
1965 | case AMD_DPM_FORCED_LEVEL_MANUAL: | |
1966 | case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: | |
1967 | default: | |
1968 | break; | |
1969 | } | |
1970 | return ret; | |
1971 | } | |
1972 | ||
f8c83215 AD |
1973 | int smu_v11_0_set_power_source(struct smu_context *smu, |
1974 | enum smu_power_src_type power_src) | |
1975 | { | |
1976 | int pwr_source; | |
1977 | ||
1978 | pwr_source = smu_power_get_index(smu, (uint32_t)power_src); | |
1979 | if (pwr_source < 0) | |
1980 | return -EINVAL; | |
1981 | ||
1982 | return smu_send_smc_msg_with_param(smu, | |
1983 | SMU_MSG_NotifyPowerSource, | |
1984 | pwr_source, | |
1985 | NULL); | |
1986 | } | |
1987 |