Commit | Line | Data |
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b455159c LG |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
b455159c LG |
24 | #include <linux/firmware.h> |
25 | #include <linux/pci.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_smu.h" | |
28 | #include "smu_internal.h" | |
29 | #include "atomfirmware.h" | |
30 | #include "amdgpu_atomfirmware.h" | |
22f2447c | 31 | #include "amdgpu_atombios.h" |
b455159c LG |
32 | #include "smu_v11_0.h" |
33 | #include "smu11_driver_if_sienna_cichlid.h" | |
34 | #include "soc15_common.h" | |
35 | #include "atom.h" | |
36 | #include "sienna_cichlid_ppt.h" | |
e05acd78 | 37 | #include "smu_v11_0_7_pptable.h" |
b455159c | 38 | #include "smu_v11_0_7_ppsmc.h" |
40d3b8db | 39 | #include "nbio/nbio_2_3_offset.h" |
b7d25b5f | 40 | #include "nbio/nbio_2_3_sh_mask.h" |
e05acd78 LG |
41 | #include "thm/thm_11_0_2_offset.h" |
42 | #include "thm/thm_11_0_2_sh_mask.h" | |
ea8139d8 WS |
43 | #include "mp/mp_11_0_offset.h" |
44 | #include "mp/mp_11_0_sh_mask.h" | |
b455159c | 45 | |
6c339f37 EQ |
46 | #include "asic_reg/mp/mp_11_0_sh_mask.h" |
47 | #include "smu_cmn.h" | |
48 | ||
55084d7f EQ |
49 | /* |
50 | * DO NOT use these for err/warn/info/debug messages. | |
51 | * Use dev_err, dev_warn, dev_info and dev_dbg instead. | |
52 | * They are more MGPU friendly. | |
53 | */ | |
54 | #undef pr_err | |
55 | #undef pr_warn | |
56 | #undef pr_info | |
57 | #undef pr_debug | |
58 | ||
b455159c LG |
59 | #define FEATURE_MASK(feature) (1ULL << feature) |
60 | #define SMC_DPM_FEATURE ( \ | |
61 | FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ | |
fea905d4 | 62 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ |
65297d50 | 63 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ |
5cb74353 | 64 | FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ |
4cd4f45b | 65 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ |
5f338f70 LG |
66 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ |
67 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) | |
b455159c | 68 | |
6c339f37 EQ |
69 | static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { |
70 | MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), | |
71 | MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), | |
72 | MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), | |
73 | MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 1), | |
74 | MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 1), | |
75 | MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 1), | |
76 | MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 1), | |
77 | MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), | |
78 | MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), | |
79 | MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), | |
80 | MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), | |
81 | MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), | |
82 | MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), | |
83 | MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), | |
84 | MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 1), | |
85 | MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), | |
86 | MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), | |
87 | MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 1), | |
88 | MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 1), | |
89 | MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), | |
90 | MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), | |
91 | MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 1), | |
92 | MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 1), | |
93 | MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), | |
94 | MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), | |
95 | MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), | |
96 | MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 1), | |
97 | MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), | |
98 | MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), | |
99 | MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), | |
100 | MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 1), | |
101 | MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 1), | |
102 | MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 1), | |
103 | MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 1), | |
104 | MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 1), | |
105 | MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 1), | |
106 | MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 1), | |
107 | MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), | |
108 | MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), | |
109 | MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), | |
110 | MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), | |
111 | MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), | |
112 | MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), | |
113 | MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 1), | |
114 | MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), | |
115 | MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), | |
116 | MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), | |
117 | MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), | |
118 | MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 1), | |
119 | MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 1), | |
b455159c LG |
120 | }; |
121 | ||
6c339f37 | 122 | static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { |
b455159c LG |
123 | CLK_MAP(GFXCLK, PPCLK_GFXCLK), |
124 | CLK_MAP(SCLK, PPCLK_GFXCLK), | |
125 | CLK_MAP(SOCCLK, PPCLK_SOCCLK), | |
126 | CLK_MAP(FCLK, PPCLK_FCLK), | |
127 | CLK_MAP(UCLK, PPCLK_UCLK), | |
128 | CLK_MAP(MCLK, PPCLK_UCLK), | |
129 | CLK_MAP(DCLK, PPCLK_DCLK_0), | |
130 | CLK_MAP(DCLK1, PPCLK_DCLK_0), | |
131 | CLK_MAP(VCLK, PPCLK_VCLK_1), | |
132 | CLK_MAP(VCLK1, PPCLK_VCLK_1), | |
133 | CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), | |
134 | CLK_MAP(DISPCLK, PPCLK_DISPCLK), | |
135 | CLK_MAP(PIXCLK, PPCLK_PIXCLK), | |
136 | CLK_MAP(PHYCLK, PPCLK_PHYCLK), | |
137 | }; | |
138 | ||
6c339f37 | 139 | static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { |
b455159c LG |
140 | FEA_MAP(DPM_PREFETCHER), |
141 | FEA_MAP(DPM_GFXCLK), | |
31cb0dd9 | 142 | FEA_MAP(DPM_GFX_GPO), |
b455159c LG |
143 | FEA_MAP(DPM_UCLK), |
144 | FEA_MAP(DPM_SOCCLK), | |
145 | FEA_MAP(DPM_MP0CLK), | |
146 | FEA_MAP(DPM_LINK), | |
147 | FEA_MAP(DPM_DCEFCLK), | |
148 | FEA_MAP(MEM_VDDCI_SCALING), | |
149 | FEA_MAP(MEM_MVDD_SCALING), | |
150 | FEA_MAP(DS_GFXCLK), | |
151 | FEA_MAP(DS_SOCCLK), | |
152 | FEA_MAP(DS_LCLK), | |
153 | FEA_MAP(DS_DCEFCLK), | |
154 | FEA_MAP(DS_UCLK), | |
155 | FEA_MAP(GFX_ULV), | |
156 | FEA_MAP(FW_DSTATE), | |
157 | FEA_MAP(GFXOFF), | |
158 | FEA_MAP(BACO), | |
6fb176a7 | 159 | FEA_MAP(MM_DPM_PG), |
b455159c LG |
160 | FEA_MAP(RSMU_SMN_CG), |
161 | FEA_MAP(PPT), | |
162 | FEA_MAP(TDC), | |
163 | FEA_MAP(APCC_PLUS), | |
164 | FEA_MAP(GTHR), | |
165 | FEA_MAP(ACDC), | |
166 | FEA_MAP(VR0HOT), | |
167 | FEA_MAP(VR1HOT), | |
168 | FEA_MAP(FW_CTF), | |
169 | FEA_MAP(FAN_CONTROL), | |
170 | FEA_MAP(THERMAL), | |
171 | FEA_MAP(GFX_DCS), | |
172 | FEA_MAP(RM), | |
173 | FEA_MAP(LED_DISPLAY), | |
174 | FEA_MAP(GFX_SS), | |
175 | FEA_MAP(OUT_OF_BAND_MONITOR), | |
176 | FEA_MAP(TEMP_DEPENDENT_VMIN), | |
177 | FEA_MAP(MMHUB_PG), | |
178 | FEA_MAP(ATHUB_PG), | |
cf06331f | 179 | FEA_MAP(APCC_DFLL), |
b455159c LG |
180 | }; |
181 | ||
6c339f37 | 182 | static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { |
b455159c LG |
183 | TAB_MAP(PPTABLE), |
184 | TAB_MAP(WATERMARKS), | |
185 | TAB_MAP(AVFS_PSM_DEBUG), | |
186 | TAB_MAP(AVFS_FUSE_OVERRIDE), | |
187 | TAB_MAP(PMSTATUSLOG), | |
188 | TAB_MAP(SMU_METRICS), | |
189 | TAB_MAP(DRIVER_SMU_CONFIG), | |
190 | TAB_MAP(ACTIVITY_MONITOR_COEFF), | |
191 | TAB_MAP(OVERDRIVE), | |
192 | TAB_MAP(I2C_COMMANDS), | |
193 | TAB_MAP(PACE), | |
194 | }; | |
195 | ||
6c339f37 | 196 | static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { |
1d5ca713 LG |
197 | PWR_MAP(AC), |
198 | PWR_MAP(DC), | |
199 | }; | |
200 | ||
6c339f37 | 201 | static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { |
b455159c LG |
202 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), |
203 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), | |
204 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), | |
205 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), | |
206 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), | |
207 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), | |
208 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), | |
209 | }; | |
210 | ||
b455159c LG |
211 | static int |
212 | sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, | |
213 | uint32_t *feature_mask, uint32_t num) | |
214 | { | |
fea905d4 LG |
215 | struct amdgpu_device *adev = smu->adev; |
216 | ||
b455159c LG |
217 | if (num > 2) |
218 | return -EINVAL; | |
219 | ||
220 | memset(feature_mask, 0, sizeof(uint32_t) * num); | |
221 | ||
4cd4f45b | 222 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) |
15dbe18f | 223 | | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) |
094cdf15 | 224 | | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) |
5f338f70 | 225 | | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) |
86a9eb3f | 226 | | FEATURE_MASK(FEATURE_DS_FCLK_BIT) |
80c36f86 | 227 | | FEATURE_MASK(FEATURE_DS_UCLK_BIT) |
9aa60213 LG |
228 | | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) |
229 | | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) | |
d28f4aa1 | 230 | | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) |
20d71dcc | 231 | | FEATURE_MASK(FEATURE_GFX_SS_BIT) |
d0d71970 | 232 | | FEATURE_MASK(FEATURE_VR0HOT_BIT) |
886c8bc6 LG |
233 | | FEATURE_MASK(FEATURE_PPT_BIT) |
234 | | FEATURE_MASK(FEATURE_TDC_BIT) | |
3fc006f5 | 235 | | FEATURE_MASK(FEATURE_BACO_BIT) |
cf06331f | 236 | | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) |
35ed946c | 237 | | FEATURE_MASK(FEATURE_FW_CTF_BIT) |
1c58d429 | 238 | | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) |
b971df70 LG |
239 | | FEATURE_MASK(FEATURE_THERMAL_BIT) |
240 | | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); | |
fea905d4 | 241 | |
c96721eb | 242 | if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { |
fea905d4 | 243 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); |
c96721eb KF |
244 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); |
245 | } | |
fea905d4 | 246 | |
65297d50 | 247 | if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) |
fc17cd3f LG |
248 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) |
249 | | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) | |
250 | | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); | |
65297d50 | 251 | |
5cb74353 LG |
252 | if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) |
253 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); | |
254 | ||
5f338f70 LG |
255 | if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) |
256 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); | |
257 | ||
fea905d4 LG |
258 | if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) |
259 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); | |
b455159c | 260 | |
62c1ea6b LG |
261 | if (adev->pm.pp_feature & PP_ULV_MASK) |
262 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); | |
263 | ||
02bb391d LG |
264 | if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) |
265 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); | |
266 | ||
e0da123a LG |
267 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) |
268 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); | |
269 | ||
b794616d KF |
270 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) |
271 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); | |
272 | ||
846938c2 KF |
273 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) |
274 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); | |
275 | ||
6fb176a7 LG |
276 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || |
277 | smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) | |
278 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); | |
279 | ||
b455159c LG |
280 | return 0; |
281 | } | |
282 | ||
283 | static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) | |
284 | { | |
4a13b4ce | 285 | struct smu_table_context *table_context = &smu->smu_table; |
e05acd78 | 286 | struct smu_11_0_7_powerplay_table *powerplay_table = |
4a13b4ce EQ |
287 | table_context->power_play_table; |
288 | struct smu_baco_context *smu_baco = &smu->smu_baco; | |
289 | ||
290 | mutex_lock(&smu_baco->mutex); | |
e05acd78 LG |
291 | if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || |
292 | powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) | |
4a13b4ce EQ |
293 | smu_baco->platform_support = true; |
294 | mutex_unlock(&smu_baco->mutex); | |
295 | ||
296 | table_context->thermal_controller_type = | |
297 | powerplay_table->thermal_controller_type; | |
298 | ||
b455159c LG |
299 | return 0; |
300 | } | |
301 | ||
302 | static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) | |
303 | { | |
dccc7c21 LG |
304 | struct smu_table_context *table_context = &smu->smu_table; |
305 | PPTable_t *smc_pptable = table_context->driver_pptable; | |
306 | struct atom_smc_dpm_info_v4_9 *smc_dpm_table; | |
307 | int index, ret; | |
dccc7c21 LG |
308 | |
309 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, | |
310 | smc_dpm_info); | |
311 | ||
22f2447c | 312 | ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, |
dccc7c21 LG |
313 | (uint8_t **)&smc_dpm_table); |
314 | if (ret) | |
315 | return ret; | |
316 | ||
317 | memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, | |
969c8d16 LG |
318 | sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); |
319 | ||
b455159c LG |
320 | return 0; |
321 | } | |
322 | ||
323 | static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) | |
324 | { | |
b455159c | 325 | struct smu_table_context *table_context = &smu->smu_table; |
e05acd78 | 326 | struct smu_11_0_7_powerplay_table *powerplay_table = |
4a13b4ce | 327 | table_context->power_play_table; |
b455159c LG |
328 | |
329 | memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, | |
330 | sizeof(PPTable_t)); | |
331 | ||
4a13b4ce EQ |
332 | return 0; |
333 | } | |
b455159c | 334 | |
4a13b4ce EQ |
335 | static int sienna_cichlid_setup_pptable(struct smu_context *smu) |
336 | { | |
337 | int ret = 0; | |
b455159c | 338 | |
4a13b4ce EQ |
339 | ret = smu_v11_0_setup_pptable(smu); |
340 | if (ret) | |
341 | return ret; | |
342 | ||
343 | ret = sienna_cichlid_store_powerplay_table(smu); | |
344 | if (ret) | |
345 | return ret; | |
346 | ||
347 | ret = sienna_cichlid_append_powerplay_table(smu); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
351 | ret = sienna_cichlid_check_powerplay_table(smu); | |
352 | if (ret) | |
353 | return ret; | |
354 | ||
355 | return ret; | |
b455159c LG |
356 | } |
357 | ||
358 | static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables) | |
359 | { | |
360 | struct smu_table_context *smu_table = &smu->smu_table; | |
361 | ||
362 | SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), | |
363 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
364 | SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), | |
365 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
366 | SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), | |
367 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
368 | SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), | |
369 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
370 | SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, | |
371 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
372 | SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, | |
373 | sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, | |
374 | AMDGPU_GEM_DOMAIN_VRAM); | |
375 | ||
376 | smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); | |
377 | if (!smu_table->metrics_table) | |
378 | return -ENOMEM; | |
379 | smu_table->metrics_time = 0; | |
380 | ||
40d3b8db LG |
381 | smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); |
382 | if (!smu_table->watermarks_table) | |
383 | return -ENOMEM; | |
384 | ||
b455159c LG |
385 | return 0; |
386 | } | |
387 | ||
8c686254 EQ |
388 | static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, |
389 | MetricsMember_t member, | |
390 | uint32_t *value) | |
b455159c LG |
391 | { |
392 | struct smu_table_context *smu_table= &smu->smu_table; | |
8c686254 | 393 | SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; |
b455159c LG |
394 | int ret = 0; |
395 | ||
396 | mutex_lock(&smu->metrics_lock); | |
8c686254 | 397 | if (!smu_table->metrics_time || |
df06583d | 398 | time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) { |
8c686254 EQ |
399 | ret = smu_update_table(smu, |
400 | SMU_TABLE_SMU_METRICS, | |
401 | 0, | |
402 | smu_table->metrics_table, | |
403 | false); | |
b455159c | 404 | if (ret) { |
d9811cfc | 405 | dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n"); |
b455159c LG |
406 | mutex_unlock(&smu->metrics_lock); |
407 | return ret; | |
408 | } | |
409 | smu_table->metrics_time = jiffies; | |
410 | } | |
411 | ||
8c686254 EQ |
412 | switch (member) { |
413 | case METRICS_CURR_GFXCLK: | |
414 | *value = metrics->CurrClock[PPCLK_GFXCLK]; | |
415 | break; | |
416 | case METRICS_CURR_SOCCLK: | |
417 | *value = metrics->CurrClock[PPCLK_SOCCLK]; | |
418 | break; | |
419 | case METRICS_CURR_UCLK: | |
420 | *value = metrics->CurrClock[PPCLK_UCLK]; | |
421 | break; | |
422 | case METRICS_CURR_VCLK: | |
423 | *value = metrics->CurrClock[PPCLK_VCLK_0]; | |
424 | break; | |
425 | case METRICS_CURR_VCLK1: | |
426 | *value = metrics->CurrClock[PPCLK_VCLK_1]; | |
427 | break; | |
428 | case METRICS_CURR_DCLK: | |
429 | *value = metrics->CurrClock[PPCLK_DCLK_0]; | |
430 | break; | |
431 | case METRICS_CURR_DCLK1: | |
432 | *value = metrics->CurrClock[PPCLK_DCLK_1]; | |
433 | break; | |
9d09fa6f ND |
434 | case METRICS_CURR_DCEFCLK: |
435 | *value = metrics->CurrClock[PPCLK_DCEFCLK]; | |
436 | break; | |
8c686254 EQ |
437 | case METRICS_AVERAGE_GFXCLK: |
438 | *value = metrics->AverageGfxclkFrequency; | |
439 | break; | |
440 | case METRICS_AVERAGE_FCLK: | |
441 | *value = metrics->AverageFclkFrequency; | |
442 | break; | |
443 | case METRICS_AVERAGE_UCLK: | |
444 | *value = metrics->AverageUclkFrequency; | |
445 | break; | |
446 | case METRICS_AVERAGE_GFXACTIVITY: | |
447 | *value = metrics->AverageGfxActivity; | |
448 | break; | |
449 | case METRICS_AVERAGE_MEMACTIVITY: | |
450 | *value = metrics->AverageUclkActivity; | |
451 | break; | |
452 | case METRICS_AVERAGE_SOCKETPOWER: | |
453 | *value = metrics->AverageSocketPower << 8; | |
454 | break; | |
455 | case METRICS_TEMPERATURE_EDGE: | |
456 | *value = metrics->TemperatureEdge * | |
457 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
458 | break; | |
459 | case METRICS_TEMPERATURE_HOTSPOT: | |
460 | *value = metrics->TemperatureHotspot * | |
461 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
462 | break; | |
463 | case METRICS_TEMPERATURE_MEM: | |
464 | *value = metrics->TemperatureMem * | |
465 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
466 | break; | |
467 | case METRICS_TEMPERATURE_VRGFX: | |
468 | *value = metrics->TemperatureVrGfx * | |
469 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
470 | break; | |
471 | case METRICS_TEMPERATURE_VRSOC: | |
472 | *value = metrics->TemperatureVrSoc * | |
473 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
474 | break; | |
475 | case METRICS_THROTTLER_STATUS: | |
476 | *value = metrics->ThrottlerStatus; | |
477 | break; | |
478 | case METRICS_CURR_FANSPEED: | |
479 | *value = metrics->CurrFanSpeed; | |
480 | break; | |
481 | default: | |
482 | *value = UINT_MAX; | |
483 | break; | |
484 | } | |
485 | ||
b455159c LG |
486 | mutex_unlock(&smu->metrics_lock); |
487 | ||
488 | return ret; | |
8c686254 | 489 | |
b455159c LG |
490 | } |
491 | ||
492 | static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) | |
493 | { | |
494 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
495 | ||
496 | if (smu_dpm->dpm_context) | |
497 | return -EINVAL; | |
498 | ||
499 | smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), | |
500 | GFP_KERNEL); | |
501 | if (!smu_dpm->dpm_context) | |
502 | return -ENOMEM; | |
503 | ||
504 | smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
509 | static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) | |
510 | { | |
90a89c31 EQ |
511 | struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; |
512 | PPTable_t *driver_ppt = smu->smu_table.driver_pptable; | |
513 | struct smu_11_0_dpm_table *dpm_table; | |
514 | int ret = 0; | |
b455159c | 515 | |
90a89c31 EQ |
516 | /* socclk dpm table setup */ |
517 | dpm_table = &dpm_context->dpm_tables.soc_table; | |
b4bb3aaf | 518 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { |
90a89c31 EQ |
519 | ret = smu_v11_0_set_single_dpm_table(smu, |
520 | SMU_SOCCLK, | |
521 | dpm_table); | |
522 | if (ret) | |
523 | return ret; | |
524 | dpm_table->is_fine_grained = | |
525 | !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; | |
526 | } else { | |
527 | dpm_table->count = 1; | |
528 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; | |
529 | dpm_table->dpm_levels[0].enabled = true; | |
530 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
531 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
532 | } | |
b455159c | 533 | |
90a89c31 EQ |
534 | /* gfxclk dpm table setup */ |
535 | dpm_table = &dpm_context->dpm_tables.gfx_table; | |
b4bb3aaf | 536 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { |
90a89c31 EQ |
537 | ret = smu_v11_0_set_single_dpm_table(smu, |
538 | SMU_GFXCLK, | |
539 | dpm_table); | |
540 | if (ret) | |
541 | return ret; | |
542 | dpm_table->is_fine_grained = | |
543 | !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; | |
544 | } else { | |
545 | dpm_table->count = 1; | |
546 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; | |
547 | dpm_table->dpm_levels[0].enabled = true; | |
548 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
549 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
550 | } | |
b455159c | 551 | |
90a89c31 EQ |
552 | /* uclk dpm table setup */ |
553 | dpm_table = &dpm_context->dpm_tables.uclk_table; | |
b4bb3aaf | 554 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { |
90a89c31 EQ |
555 | ret = smu_v11_0_set_single_dpm_table(smu, |
556 | SMU_UCLK, | |
557 | dpm_table); | |
558 | if (ret) | |
559 | return ret; | |
560 | dpm_table->is_fine_grained = | |
561 | !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; | |
562 | } else { | |
563 | dpm_table->count = 1; | |
564 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; | |
565 | dpm_table->dpm_levels[0].enabled = true; | |
566 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
567 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
568 | } | |
b455159c | 569 | |
90a89c31 EQ |
570 | /* fclk dpm table setup */ |
571 | dpm_table = &dpm_context->dpm_tables.fclk_table; | |
b4bb3aaf | 572 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { |
90a89c31 EQ |
573 | ret = smu_v11_0_set_single_dpm_table(smu, |
574 | SMU_FCLK, | |
575 | dpm_table); | |
576 | if (ret) | |
577 | return ret; | |
578 | dpm_table->is_fine_grained = | |
579 | !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; | |
580 | } else { | |
581 | dpm_table->count = 1; | |
582 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; | |
583 | dpm_table->dpm_levels[0].enabled = true; | |
584 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
585 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
586 | } | |
b455159c | 587 | |
90a89c31 EQ |
588 | /* vclk0 dpm table setup */ |
589 | dpm_table = &dpm_context->dpm_tables.vclk_table; | |
b4bb3aaf | 590 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
90a89c31 EQ |
591 | ret = smu_v11_0_set_single_dpm_table(smu, |
592 | SMU_VCLK, | |
593 | dpm_table); | |
594 | if (ret) | |
595 | return ret; | |
596 | dpm_table->is_fine_grained = | |
597 | !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete; | |
598 | } else { | |
599 | dpm_table->count = 1; | |
600 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; | |
601 | dpm_table->dpm_levels[0].enabled = true; | |
602 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
603 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
604 | } | |
b455159c | 605 | |
90a89c31 EQ |
606 | /* vclk1 dpm table setup */ |
607 | dpm_table = &dpm_context->dpm_tables.vclk1_table; | |
b4bb3aaf | 608 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
90a89c31 EQ |
609 | ret = smu_v11_0_set_single_dpm_table(smu, |
610 | SMU_VCLK1, | |
611 | dpm_table); | |
612 | if (ret) | |
613 | return ret; | |
614 | dpm_table->is_fine_grained = | |
615 | !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete; | |
616 | } else { | |
617 | dpm_table->count = 1; | |
618 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; | |
619 | dpm_table->dpm_levels[0].enabled = true; | |
620 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
621 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
622 | } | |
b455159c | 623 | |
90a89c31 EQ |
624 | /* dclk0 dpm table setup */ |
625 | dpm_table = &dpm_context->dpm_tables.dclk_table; | |
b4bb3aaf | 626 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
90a89c31 EQ |
627 | ret = smu_v11_0_set_single_dpm_table(smu, |
628 | SMU_DCLK, | |
629 | dpm_table); | |
630 | if (ret) | |
631 | return ret; | |
632 | dpm_table->is_fine_grained = | |
633 | !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete; | |
634 | } else { | |
635 | dpm_table->count = 1; | |
636 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; | |
637 | dpm_table->dpm_levels[0].enabled = true; | |
638 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
639 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
640 | } | |
641 | ||
642 | /* dclk1 dpm table setup */ | |
643 | dpm_table = &dpm_context->dpm_tables.dclk1_table; | |
b4bb3aaf | 644 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
90a89c31 EQ |
645 | ret = smu_v11_0_set_single_dpm_table(smu, |
646 | SMU_DCLK1, | |
647 | dpm_table); | |
648 | if (ret) | |
649 | return ret; | |
650 | dpm_table->is_fine_grained = | |
651 | !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete; | |
652 | } else { | |
653 | dpm_table->count = 1; | |
654 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; | |
655 | dpm_table->dpm_levels[0].enabled = true; | |
656 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
657 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
658 | } | |
659 | ||
660 | /* dcefclk dpm table setup */ | |
661 | dpm_table = &dpm_context->dpm_tables.dcef_table; | |
b4bb3aaf | 662 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { |
90a89c31 EQ |
663 | ret = smu_v11_0_set_single_dpm_table(smu, |
664 | SMU_DCEFCLK, | |
665 | dpm_table); | |
666 | if (ret) | |
667 | return ret; | |
668 | dpm_table->is_fine_grained = | |
669 | !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; | |
670 | } else { | |
671 | dpm_table->count = 1; | |
672 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |
673 | dpm_table->dpm_levels[0].enabled = true; | |
674 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
675 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
676 | } | |
b455159c | 677 | |
90a89c31 EQ |
678 | /* pixelclk dpm table setup */ |
679 | dpm_table = &dpm_context->dpm_tables.pixel_table; | |
b4bb3aaf | 680 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { |
90a89c31 EQ |
681 | ret = smu_v11_0_set_single_dpm_table(smu, |
682 | SMU_PIXCLK, | |
683 | dpm_table); | |
684 | if (ret) | |
685 | return ret; | |
686 | dpm_table->is_fine_grained = | |
687 | !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; | |
688 | } else { | |
689 | dpm_table->count = 1; | |
690 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |
691 | dpm_table->dpm_levels[0].enabled = true; | |
692 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
693 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
694 | } | |
b455159c | 695 | |
90a89c31 EQ |
696 | /* displayclk dpm table setup */ |
697 | dpm_table = &dpm_context->dpm_tables.display_table; | |
b4bb3aaf | 698 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { |
90a89c31 EQ |
699 | ret = smu_v11_0_set_single_dpm_table(smu, |
700 | SMU_DISPCLK, | |
701 | dpm_table); | |
702 | if (ret) | |
703 | return ret; | |
704 | dpm_table->is_fine_grained = | |
705 | !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; | |
706 | } else { | |
707 | dpm_table->count = 1; | |
708 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |
709 | dpm_table->dpm_levels[0].enabled = true; | |
710 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
711 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
712 | } | |
b455159c | 713 | |
90a89c31 EQ |
714 | /* phyclk dpm table setup */ |
715 | dpm_table = &dpm_context->dpm_tables.phy_table; | |
b4bb3aaf | 716 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { |
90a89c31 EQ |
717 | ret = smu_v11_0_set_single_dpm_table(smu, |
718 | SMU_PHYCLK, | |
719 | dpm_table); | |
720 | if (ret) | |
721 | return ret; | |
722 | dpm_table->is_fine_grained = | |
723 | !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; | |
724 | } else { | |
725 | dpm_table->count = 1; | |
726 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |
727 | dpm_table->dpm_levels[0].enabled = true; | |
728 | dpm_table->min = dpm_table->dpm_levels[0].value; | |
729 | dpm_table->max = dpm_table->dpm_levels[0].value; | |
730 | } | |
b455159c LG |
731 | |
732 | return 0; | |
733 | } | |
734 | ||
f6b4b4a1 | 735 | static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) |
b455159c LG |
736 | { |
737 | struct smu_power_context *smu_power = &smu->smu_power; | |
738 | struct smu_power_gate *power_gate = &smu_power->power_gate; | |
d51dc613 JC |
739 | struct amdgpu_device *adev = smu->adev; |
740 | ||
b455159c LG |
741 | int ret = 0; |
742 | ||
743 | if (enable) { | |
744 | /* vcn dpm on is a prerequisite for vcn power gate messages */ | |
b4bb3aaf | 745 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
6fb176a7 LG |
746 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); |
747 | if (ret) | |
748 | return ret; | |
d51dc613 JC |
749 | if (adev->asic_type == CHIP_SIENNA_CICHLID) { |
750 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, | |
751 | 0x10000, NULL); | |
752 | if (ret) | |
753 | return ret; | |
754 | } | |
b455159c LG |
755 | } |
756 | power_gate->vcn_gated = false; | |
757 | } else { | |
b4bb3aaf | 758 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
6fb176a7 LG |
759 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); |
760 | if (ret) | |
761 | return ret; | |
d51dc613 JC |
762 | if (adev->asic_type == CHIP_SIENNA_CICHLID) { |
763 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, | |
764 | 0x10000, NULL); | |
765 | if (ret) | |
766 | return ret; | |
767 | } | |
b455159c LG |
768 | } |
769 | power_gate->vcn_gated = true; | |
770 | } | |
771 | ||
772 | return ret; | |
773 | } | |
774 | ||
6fb176a7 LG |
775 | static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) |
776 | { | |
777 | struct smu_power_context *smu_power = &smu->smu_power; | |
778 | struct smu_power_gate *power_gate = &smu_power->power_gate; | |
779 | int ret = 0; | |
780 | ||
781 | if (enable) { | |
b4bb3aaf | 782 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
6fb176a7 LG |
783 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); |
784 | if (ret) | |
785 | return ret; | |
6fb176a7 LG |
786 | } |
787 | power_gate->jpeg_gated = false; | |
788 | } else { | |
b4bb3aaf | 789 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
6fb176a7 LG |
790 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); |
791 | if (ret) | |
792 | return ret; | |
6fb176a7 LG |
793 | } |
794 | power_gate->jpeg_gated = true; | |
795 | } | |
796 | ||
797 | return ret; | |
798 | } | |
799 | ||
b455159c LG |
800 | static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, |
801 | enum smu_clk_type clk_type, | |
802 | uint32_t *value) | |
803 | { | |
8c686254 EQ |
804 | MetricsMember_t member_type; |
805 | int clk_id = 0; | |
b455159c | 806 | |
6c339f37 EQ |
807 | clk_id = smu_cmn_to_asic_specific_index(smu, |
808 | CMN2ASIC_MAPPING_CLK, | |
809 | clk_type); | |
b455159c LG |
810 | if (clk_id < 0) |
811 | return clk_id; | |
812 | ||
8c686254 EQ |
813 | switch (clk_id) { |
814 | case PPCLK_GFXCLK: | |
815 | member_type = METRICS_CURR_GFXCLK; | |
816 | break; | |
817 | case PPCLK_UCLK: | |
818 | member_type = METRICS_CURR_UCLK; | |
819 | break; | |
820 | case PPCLK_SOCCLK: | |
821 | member_type = METRICS_CURR_SOCCLK; | |
822 | break; | |
823 | case PPCLK_FCLK: | |
824 | member_type = METRICS_CURR_FCLK; | |
825 | break; | |
826 | case PPCLK_VCLK_0: | |
827 | member_type = METRICS_CURR_VCLK; | |
828 | break; | |
829 | case PPCLK_VCLK_1: | |
830 | member_type = METRICS_CURR_VCLK1; | |
831 | break; | |
832 | case PPCLK_DCLK_0: | |
833 | member_type = METRICS_CURR_DCLK; | |
834 | break; | |
835 | case PPCLK_DCLK_1: | |
836 | member_type = METRICS_CURR_DCLK1; | |
837 | break; | |
838 | case PPCLK_DCEFCLK: | |
839 | member_type = METRICS_CURR_DCEFCLK; | |
840 | break; | |
841 | default: | |
842 | return -EINVAL; | |
843 | } | |
844 | ||
845 | return sienna_cichlid_get_smu_metrics_data(smu, | |
846 | member_type, | |
847 | value); | |
b455159c | 848 | |
b455159c LG |
849 | } |
850 | ||
851 | static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) | |
852 | { | |
853 | PPTable_t *pptable = smu->smu_table.driver_pptable; | |
854 | DpmDescriptor_t *dpm_desc = NULL; | |
855 | uint32_t clk_index = 0; | |
856 | ||
6c339f37 EQ |
857 | clk_index = smu_cmn_to_asic_specific_index(smu, |
858 | CMN2ASIC_MAPPING_CLK, | |
859 | clk_type); | |
b455159c LG |
860 | dpm_desc = &pptable->DpmDescriptor[clk_index]; |
861 | ||
862 | /* 0 - Fine grained DPM, 1 - Discrete DPM */ | |
863 | return dpm_desc->SnapToDiscrete == 0 ? true : false; | |
864 | } | |
865 | ||
866 | static int sienna_cichlid_print_clk_levels(struct smu_context *smu, | |
867 | enum smu_clk_type clk_type, char *buf) | |
868 | { | |
b7d25b5f LG |
869 | struct amdgpu_device *adev = smu->adev; |
870 | struct smu_table_context *table_context = &smu->smu_table; | |
871 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
872 | struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; | |
873 | PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; | |
b455159c LG |
874 | int i, size = 0, ret = 0; |
875 | uint32_t cur_value = 0, value = 0, count = 0; | |
876 | uint32_t freq_values[3] = {0}; | |
877 | uint32_t mark_index = 0; | |
b7d25b5f | 878 | uint32_t gen_speed, lane_width; |
b455159c LG |
879 | |
880 | switch (clk_type) { | |
881 | case SMU_GFXCLK: | |
882 | case SMU_SCLK: | |
883 | case SMU_SOCCLK: | |
884 | case SMU_MCLK: | |
885 | case SMU_UCLK: | |
886 | case SMU_FCLK: | |
887 | case SMU_DCEFCLK: | |
5e6dc8fe | 888 | ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); |
b455159c | 889 | if (ret) |
258d290c | 890 | goto print_clk_out; |
b455159c | 891 | |
ba818620 KF |
892 | /* no need to disable gfxoff when retrieving the current gfxclk */ |
893 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) | |
894 | amdgpu_gfx_off_ctrl(adev, false); | |
895 | ||
d8d3493a | 896 | ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); |
b455159c | 897 | if (ret) |
258d290c | 898 | goto print_clk_out; |
b455159c LG |
899 | |
900 | if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { | |
901 | for (i = 0; i < count; i++) { | |
d8d3493a | 902 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); |
b455159c | 903 | if (ret) |
258d290c | 904 | goto print_clk_out; |
b455159c LG |
905 | |
906 | size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, | |
907 | cur_value == value ? "*" : ""); | |
908 | } | |
909 | } else { | |
d8d3493a | 910 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); |
b455159c | 911 | if (ret) |
258d290c | 912 | goto print_clk_out; |
d8d3493a | 913 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); |
b455159c | 914 | if (ret) |
258d290c | 915 | goto print_clk_out; |
b455159c LG |
916 | |
917 | freq_values[1] = cur_value; | |
918 | mark_index = cur_value == freq_values[0] ? 0 : | |
919 | cur_value == freq_values[2] ? 2 : 1; | |
920 | if (mark_index != 1) | |
921 | freq_values[1] = (freq_values[0] + freq_values[2]) / 2; | |
922 | ||
923 | for (i = 0; i < 3; i++) { | |
924 | size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], | |
925 | i == mark_index ? "*" : ""); | |
926 | } | |
927 | ||
928 | } | |
929 | break; | |
b7d25b5f LG |
930 | case SMU_PCIE: |
931 | gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & | |
932 | PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) | |
933 | >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; | |
934 | lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & | |
935 | PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) | |
936 | >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; | |
937 | for (i = 0; i < NUM_LINK_LEVELS; i++) | |
938 | size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, | |
939 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : | |
940 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : | |
941 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : | |
942 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", | |
943 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : | |
944 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : | |
945 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : | |
946 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : | |
947 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : | |
948 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", | |
949 | pptable->LclkFreq[i], | |
950 | (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && | |
951 | (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? | |
952 | "*" : ""); | |
953 | break; | |
b455159c LG |
954 | default: |
955 | break; | |
956 | } | |
957 | ||
258d290c LG |
958 | print_clk_out: |
959 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) | |
960 | amdgpu_gfx_off_ctrl(adev, true); | |
961 | ||
b455159c LG |
962 | return size; |
963 | } | |
964 | ||
965 | static int sienna_cichlid_force_clk_levels(struct smu_context *smu, | |
966 | enum smu_clk_type clk_type, uint32_t mask) | |
967 | { | |
258d290c | 968 | struct amdgpu_device *adev = smu->adev; |
b455159c LG |
969 | int ret = 0, size = 0; |
970 | uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; | |
971 | ||
972 | soft_min_level = mask ? (ffs(mask) - 1) : 0; | |
973 | soft_max_level = mask ? (fls(mask) - 1) : 0; | |
974 | ||
258d290c LG |
975 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) |
976 | amdgpu_gfx_off_ctrl(adev, false); | |
977 | ||
b455159c LG |
978 | switch (clk_type) { |
979 | case SMU_GFXCLK: | |
980 | case SMU_SCLK: | |
981 | case SMU_SOCCLK: | |
982 | case SMU_MCLK: | |
983 | case SMU_UCLK: | |
984 | case SMU_DCEFCLK: | |
985 | case SMU_FCLK: | |
9ad9c8ac LG |
986 | /* There is only 2 levels for fine grained DPM */ |
987 | if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { | |
988 | soft_max_level = (soft_max_level >= 1 ? 1 : 0); | |
989 | soft_min_level = (soft_min_level >= 1 ? 1 : 0); | |
990 | } | |
991 | ||
d8d3493a | 992 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); |
b455159c | 993 | if (ret) |
258d290c | 994 | goto forec_level_out; |
b455159c | 995 | |
d8d3493a | 996 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); |
b455159c | 997 | if (ret) |
258d290c | 998 | goto forec_level_out; |
b455159c | 999 | |
10e96d89 | 1000 | ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); |
b455159c | 1001 | if (ret) |
258d290c | 1002 | goto forec_level_out; |
b455159c LG |
1003 | break; |
1004 | default: | |
1005 | break; | |
1006 | } | |
1007 | ||
258d290c LG |
1008 | forec_level_out: |
1009 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) | |
1010 | amdgpu_gfx_off_ctrl(adev, true); | |
1011 | ||
b455159c LG |
1012 | return size; |
1013 | } | |
1014 | ||
1015 | static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) | |
1016 | { | |
62cc9dd1 EQ |
1017 | struct smu_11_0_dpm_context *dpm_context = |
1018 | smu->smu_dpm.dpm_context; | |
1019 | struct smu_11_0_dpm_table *gfx_table = | |
1020 | &dpm_context->dpm_tables.gfx_table; | |
1021 | struct smu_11_0_dpm_table *mem_table = | |
1022 | &dpm_context->dpm_tables.uclk_table; | |
1023 | struct smu_11_0_dpm_table *soc_table = | |
1024 | &dpm_context->dpm_tables.soc_table; | |
1025 | struct smu_umd_pstate_table *pstate_table = | |
1026 | &smu->pstate_table; | |
1027 | ||
1028 | pstate_table->gfxclk_pstate.min = gfx_table->min; | |
1029 | pstate_table->gfxclk_pstate.peak = gfx_table->max; | |
1030 | ||
1031 | pstate_table->uclk_pstate.min = mem_table->min; | |
1032 | pstate_table->uclk_pstate.peak = mem_table->max; | |
1033 | ||
1034 | pstate_table->socclk_pstate.min = soc_table->min; | |
1035 | pstate_table->socclk_pstate.peak = soc_table->max; | |
b455159c | 1036 | |
62cc9dd1 | 1037 | return 0; |
b455159c LG |
1038 | } |
1039 | ||
b455159c LG |
1040 | static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) |
1041 | { | |
1042 | int ret = 0; | |
1043 | uint32_t max_freq = 0; | |
1044 | ||
1045 | /* Sienna_Cichlid do not support to change display num currently */ | |
1046 | return 0; | |
1047 | #if 0 | |
1048 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); | |
1049 | if (ret) | |
1050 | return ret; | |
1051 | #endif | |
1052 | ||
b4bb3aaf | 1053 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { |
e5ef784b | 1054 | ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); |
b455159c LG |
1055 | if (ret) |
1056 | return ret; | |
661b94f5 | 1057 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); |
b455159c LG |
1058 | if (ret) |
1059 | return ret; | |
1060 | } | |
1061 | ||
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | static int sienna_cichlid_display_config_changed(struct smu_context *smu) | |
1066 | { | |
1067 | int ret = 0; | |
1068 | ||
b455159c | 1069 | if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && |
4d942ae3 EQ |
1070 | smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && |
1071 | smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { | |
b455159c LG |
1072 | #if 0 |
1073 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, | |
40d3b8db LG |
1074 | smu->display_config->num_display, |
1075 | NULL); | |
b455159c LG |
1076 | #endif |
1077 | if (ret) | |
1078 | return ret; | |
1079 | } | |
1080 | ||
1081 | return ret; | |
1082 | } | |
1083 | ||
b455159c LG |
1084 | static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value) |
1085 | { | |
b455159c LG |
1086 | if (!value) |
1087 | return -EINVAL; | |
1088 | ||
8c686254 EQ |
1089 | return sienna_cichlid_get_smu_metrics_data(smu, |
1090 | METRICS_AVERAGE_SOCKETPOWER, | |
1091 | value); | |
b455159c LG |
1092 | } |
1093 | ||
1094 | static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu, | |
1095 | enum amd_pp_sensors sensor, | |
1096 | uint32_t *value) | |
1097 | { | |
1098 | int ret = 0; | |
b455159c LG |
1099 | |
1100 | if (!value) | |
1101 | return -EINVAL; | |
1102 | ||
b455159c LG |
1103 | switch (sensor) { |
1104 | case AMDGPU_PP_SENSOR_GPU_LOAD: | |
8c686254 EQ |
1105 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1106 | METRICS_AVERAGE_GFXACTIVITY, | |
1107 | value); | |
b455159c LG |
1108 | break; |
1109 | case AMDGPU_PP_SENSOR_MEM_LOAD: | |
8c686254 EQ |
1110 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1111 | METRICS_AVERAGE_MEMACTIVITY, | |
1112 | value); | |
b455159c LG |
1113 | break; |
1114 | default: | |
d9811cfc | 1115 | dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); |
b455159c LG |
1116 | return -EINVAL; |
1117 | } | |
1118 | ||
8c686254 | 1119 | return ret; |
b455159c LG |
1120 | } |
1121 | ||
1122 | static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) | |
1123 | { | |
1124 | int ret = 0; | |
1125 | uint32_t feature_mask[2]; | |
1126 | unsigned long feature_enabled; | |
28251d72 | 1127 | ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); |
b455159c LG |
1128 | feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | |
1129 | ((uint64_t)feature_mask[1] << 32)); | |
1130 | return !!(feature_enabled & SMC_DPM_FEATURE); | |
1131 | } | |
1132 | ||
1133 | static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, | |
1134 | uint32_t *speed) | |
1135 | { | |
b455159c LG |
1136 | if (!speed) |
1137 | return -EINVAL; | |
1138 | ||
8c686254 EQ |
1139 | return sienna_cichlid_get_smu_metrics_data(smu, |
1140 | METRICS_CURR_FANSPEED, | |
1141 | speed); | |
b455159c LG |
1142 | } |
1143 | ||
1144 | static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu, | |
1145 | uint32_t *speed) | |
1146 | { | |
1147 | int ret = 0; | |
1148 | uint32_t percent = 0; | |
1149 | uint32_t current_rpm; | |
1150 | PPTable_t *pptable = smu->smu_table.driver_pptable; | |
1151 | ||
1152 | ret = sienna_cichlid_get_fan_speed_rpm(smu, ¤t_rpm); | |
1153 | if (ret) | |
1154 | return ret; | |
1155 | ||
1156 | percent = current_rpm * 100 / pptable->FanMaximumRpm; | |
1157 | *speed = percent > 100 ? 100 : percent; | |
1158 | ||
1159 | return ret; | |
1160 | } | |
1161 | ||
1162 | static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) | |
1163 | { | |
1164 | DpmActivityMonitorCoeffInt_t activity_monitor; | |
1165 | uint32_t i, size = 0; | |
1166 | int16_t workload_type = 0; | |
1167 | static const char *profile_name[] = { | |
1168 | "BOOTUP_DEFAULT", | |
1169 | "3D_FULL_SCREEN", | |
1170 | "POWER_SAVING", | |
1171 | "VIDEO", | |
1172 | "VR", | |
1173 | "COMPUTE", | |
1174 | "CUSTOM"}; | |
1175 | static const char *title[] = { | |
1176 | "PROFILE_INDEX(NAME)", | |
1177 | "CLOCK_TYPE(NAME)", | |
1178 | "FPS", | |
1179 | "MinFreqType", | |
1180 | "MinActiveFreqType", | |
1181 | "MinActiveFreq", | |
1182 | "BoosterFreqType", | |
1183 | "BoosterFreq", | |
1184 | "PD_Data_limit_c", | |
1185 | "PD_Data_error_coeff", | |
1186 | "PD_Data_error_rate_coeff"}; | |
1187 | int result = 0; | |
1188 | ||
1189 | if (!buf) | |
1190 | return -EINVAL; | |
1191 | ||
1192 | size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", | |
1193 | title[0], title[1], title[2], title[3], title[4], title[5], | |
1194 | title[6], title[7], title[8], title[9], title[10]); | |
1195 | ||
1196 | for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { | |
1197 | /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ | |
6c339f37 EQ |
1198 | workload_type = smu_cmn_to_asic_specific_index(smu, |
1199 | CMN2ASIC_MAPPING_WORKLOAD, | |
1200 | i); | |
b455159c LG |
1201 | if (workload_type < 0) |
1202 | return -EINVAL; | |
1203 | ||
1204 | result = smu_update_table(smu, | |
1205 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, | |
1206 | (void *)(&activity_monitor), false); | |
1207 | if (result) { | |
d9811cfc | 1208 | dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); |
b455159c LG |
1209 | return result; |
1210 | } | |
1211 | ||
1212 | size += sprintf(buf + size, "%2d %14s%s:\n", | |
1213 | i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); | |
1214 | ||
1215 | size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |
1216 | " ", | |
1217 | 0, | |
1218 | "GFXCLK", | |
1219 | activity_monitor.Gfx_FPS, | |
1220 | activity_monitor.Gfx_MinFreqStep, | |
1221 | activity_monitor.Gfx_MinActiveFreqType, | |
1222 | activity_monitor.Gfx_MinActiveFreq, | |
1223 | activity_monitor.Gfx_BoosterFreqType, | |
1224 | activity_monitor.Gfx_BoosterFreq, | |
1225 | activity_monitor.Gfx_PD_Data_limit_c, | |
1226 | activity_monitor.Gfx_PD_Data_error_coeff, | |
1227 | activity_monitor.Gfx_PD_Data_error_rate_coeff); | |
1228 | ||
1229 | size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |
1230 | " ", | |
1231 | 1, | |
1232 | "SOCCLK", | |
1233 | activity_monitor.Fclk_FPS, | |
1234 | activity_monitor.Fclk_MinFreqStep, | |
1235 | activity_monitor.Fclk_MinActiveFreqType, | |
1236 | activity_monitor.Fclk_MinActiveFreq, | |
1237 | activity_monitor.Fclk_BoosterFreqType, | |
1238 | activity_monitor.Fclk_BoosterFreq, | |
1239 | activity_monitor.Fclk_PD_Data_limit_c, | |
1240 | activity_monitor.Fclk_PD_Data_error_coeff, | |
1241 | activity_monitor.Fclk_PD_Data_error_rate_coeff); | |
1242 | ||
1243 | size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |
1244 | " ", | |
1245 | 2, | |
1246 | "MEMLK", | |
1247 | activity_monitor.Mem_FPS, | |
1248 | activity_monitor.Mem_MinFreqStep, | |
1249 | activity_monitor.Mem_MinActiveFreqType, | |
1250 | activity_monitor.Mem_MinActiveFreq, | |
1251 | activity_monitor.Mem_BoosterFreqType, | |
1252 | activity_monitor.Mem_BoosterFreq, | |
1253 | activity_monitor.Mem_PD_Data_limit_c, | |
1254 | activity_monitor.Mem_PD_Data_error_coeff, | |
1255 | activity_monitor.Mem_PD_Data_error_rate_coeff); | |
1256 | } | |
1257 | ||
1258 | return size; | |
1259 | } | |
1260 | ||
1261 | static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) | |
1262 | { | |
1263 | DpmActivityMonitorCoeffInt_t activity_monitor; | |
1264 | int workload_type, ret = 0; | |
1265 | ||
1266 | smu->power_profile_mode = input[size]; | |
1267 | ||
1268 | if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { | |
d9811cfc | 1269 | dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); |
b455159c LG |
1270 | return -EINVAL; |
1271 | } | |
1272 | ||
1273 | if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { | |
b455159c LG |
1274 | |
1275 | ret = smu_update_table(smu, | |
1276 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, | |
1277 | (void *)(&activity_monitor), false); | |
1278 | if (ret) { | |
d9811cfc | 1279 | dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); |
b455159c LG |
1280 | return ret; |
1281 | } | |
1282 | ||
1283 | switch (input[0]) { | |
1284 | case 0: /* Gfxclk */ | |
1285 | activity_monitor.Gfx_FPS = input[1]; | |
1286 | activity_monitor.Gfx_MinFreqStep = input[2]; | |
1287 | activity_monitor.Gfx_MinActiveFreqType = input[3]; | |
1288 | activity_monitor.Gfx_MinActiveFreq = input[4]; | |
1289 | activity_monitor.Gfx_BoosterFreqType = input[5]; | |
1290 | activity_monitor.Gfx_BoosterFreq = input[6]; | |
1291 | activity_monitor.Gfx_PD_Data_limit_c = input[7]; | |
1292 | activity_monitor.Gfx_PD_Data_error_coeff = input[8]; | |
1293 | activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; | |
1294 | break; | |
1295 | case 1: /* Socclk */ | |
1296 | activity_monitor.Fclk_FPS = input[1]; | |
1297 | activity_monitor.Fclk_MinFreqStep = input[2]; | |
1298 | activity_monitor.Fclk_MinActiveFreqType = input[3]; | |
1299 | activity_monitor.Fclk_MinActiveFreq = input[4]; | |
1300 | activity_monitor.Fclk_BoosterFreqType = input[5]; | |
1301 | activity_monitor.Fclk_BoosterFreq = input[6]; | |
1302 | activity_monitor.Fclk_PD_Data_limit_c = input[7]; | |
1303 | activity_monitor.Fclk_PD_Data_error_coeff = input[8]; | |
1304 | activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9]; | |
1305 | break; | |
1306 | case 2: /* Memlk */ | |
1307 | activity_monitor.Mem_FPS = input[1]; | |
1308 | activity_monitor.Mem_MinFreqStep = input[2]; | |
1309 | activity_monitor.Mem_MinActiveFreqType = input[3]; | |
1310 | activity_monitor.Mem_MinActiveFreq = input[4]; | |
1311 | activity_monitor.Mem_BoosterFreqType = input[5]; | |
1312 | activity_monitor.Mem_BoosterFreq = input[6]; | |
1313 | activity_monitor.Mem_PD_Data_limit_c = input[7]; | |
1314 | activity_monitor.Mem_PD_Data_error_coeff = input[8]; | |
1315 | activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; | |
1316 | break; | |
1317 | } | |
1318 | ||
1319 | ret = smu_update_table(smu, | |
1320 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, | |
1321 | (void *)(&activity_monitor), true); | |
1322 | if (ret) { | |
d9811cfc | 1323 | dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); |
b455159c LG |
1324 | return ret; |
1325 | } | |
1326 | } | |
1327 | ||
1328 | /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ | |
6c339f37 EQ |
1329 | workload_type = smu_cmn_to_asic_specific_index(smu, |
1330 | CMN2ASIC_MAPPING_WORKLOAD, | |
1331 | smu->power_profile_mode); | |
b455159c LG |
1332 | if (workload_type < 0) |
1333 | return -EINVAL; | |
1334 | smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, | |
1335 | 1 << workload_type, NULL); | |
1336 | ||
1337 | return ret; | |
1338 | } | |
1339 | ||
b455159c LG |
1340 | static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) |
1341 | { | |
1342 | struct smu_clocks min_clocks = {0}; | |
1343 | struct pp_display_clock_request clock_req; | |
1344 | int ret = 0; | |
1345 | ||
1346 | min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; | |
1347 | min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; | |
1348 | min_clocks.memory_clock = smu->display_config->min_mem_set_clock; | |
1349 | ||
4d942ae3 | 1350 | if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { |
b455159c LG |
1351 | clock_req.clock_type = amd_pp_dcef_clock; |
1352 | clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; | |
1353 | ||
1354 | ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); | |
1355 | if (!ret) { | |
4d942ae3 | 1356 | if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { |
40d3b8db LG |
1357 | ret = smu_send_smc_msg_with_param(smu, |
1358 | SMU_MSG_SetMinDeepSleepDcefclk, | |
1359 | min_clocks.dcef_clock_in_sr/100, | |
1360 | NULL); | |
1361 | if (ret) { | |
d9811cfc | 1362 | dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); |
40d3b8db LG |
1363 | return ret; |
1364 | } | |
b455159c LG |
1365 | } |
1366 | } else { | |
d9811cfc | 1367 | dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); |
b455159c LG |
1368 | } |
1369 | } | |
1370 | ||
b4bb3aaf | 1371 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { |
661b94f5 | 1372 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); |
b455159c | 1373 | if (ret) { |
d9811cfc | 1374 | dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); |
b455159c LG |
1375 | return ret; |
1376 | } | |
1377 | } | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, | |
e7a95eea EQ |
1383 | struct dm_pp_wm_sets_with_clock_ranges_soc15 |
1384 | *clock_ranges) | |
b455159c | 1385 | { |
e7a95eea | 1386 | Watermarks_t *table = smu->smu_table.watermarks_table; |
40d3b8db | 1387 | int ret = 0; |
e7a95eea | 1388 | int i; |
b455159c | 1389 | |
e7a95eea EQ |
1390 | if (clock_ranges) { |
1391 | if (clock_ranges->num_wm_dmif_sets > 4 || | |
1392 | clock_ranges->num_wm_mcif_sets > 4) | |
1393 | return -EINVAL; | |
1394 | ||
1395 | for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { | |
1396 | table->WatermarkRow[1][i].MinClock = | |
1397 | cpu_to_le16((uint16_t) | |
1398 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / | |
1399 | 1000)); | |
1400 | table->WatermarkRow[1][i].MaxClock = | |
1401 | cpu_to_le16((uint16_t) | |
1402 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / | |
1403 | 1000)); | |
1404 | table->WatermarkRow[1][i].MinUclk = | |
1405 | cpu_to_le16((uint16_t) | |
1406 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / | |
1407 | 1000)); | |
1408 | table->WatermarkRow[1][i].MaxUclk = | |
1409 | cpu_to_le16((uint16_t) | |
1410 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / | |
1411 | 1000)); | |
1412 | table->WatermarkRow[1][i].WmSetting = (uint8_t) | |
1413 | clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; | |
1414 | } | |
b455159c | 1415 | |
e7a95eea EQ |
1416 | for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) { |
1417 | table->WatermarkRow[0][i].MinClock = | |
1418 | cpu_to_le16((uint16_t) | |
1419 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / | |
1420 | 1000)); | |
1421 | table->WatermarkRow[0][i].MaxClock = | |
1422 | cpu_to_le16((uint16_t) | |
1423 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / | |
1424 | 1000)); | |
1425 | table->WatermarkRow[0][i].MinUclk = | |
1426 | cpu_to_le16((uint16_t) | |
1427 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz / | |
1428 | 1000)); | |
1429 | table->WatermarkRow[0][i].MaxUclk = | |
1430 | cpu_to_le16((uint16_t) | |
1431 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / | |
1432 | 1000)); | |
1433 | table->WatermarkRow[0][i].WmSetting = (uint8_t) | |
1434 | clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; | |
1435 | } | |
1436 | ||
1437 | smu->watermarks_bitmap |= WATERMARKS_EXIST; | |
1438 | } | |
1439 | ||
1440 | if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && | |
1441 | !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { | |
40d3b8db LG |
1442 | ret = smu_write_watermarks_table(smu); |
1443 | if (ret) { | |
d9811cfc | 1444 | dev_err(smu->adev->dev, "Failed to update WMTABLE!"); |
40d3b8db LG |
1445 | return ret; |
1446 | } | |
1447 | smu->watermarks_bitmap |= WATERMARKS_LOADED; | |
1448 | } | |
1449 | ||
b455159c LG |
1450 | return 0; |
1451 | } | |
1452 | ||
1453 | static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu, | |
1454 | enum amd_pp_sensors sensor, | |
1455 | uint32_t *value) | |
1456 | { | |
b455159c LG |
1457 | int ret = 0; |
1458 | ||
1459 | if (!value) | |
1460 | return -EINVAL; | |
1461 | ||
b455159c LG |
1462 | switch (sensor) { |
1463 | case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: | |
8c686254 EQ |
1464 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1465 | METRICS_TEMPERATURE_HOTSPOT, | |
1466 | value); | |
b455159c LG |
1467 | break; |
1468 | case AMDGPU_PP_SENSOR_EDGE_TEMP: | |
8c686254 EQ |
1469 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1470 | METRICS_TEMPERATURE_EDGE, | |
1471 | value); | |
b455159c LG |
1472 | break; |
1473 | case AMDGPU_PP_SENSOR_MEM_TEMP: | |
8c686254 EQ |
1474 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1475 | METRICS_TEMPERATURE_MEM, | |
1476 | value); | |
b455159c LG |
1477 | break; |
1478 | default: | |
d9811cfc | 1479 | dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); |
b455159c LG |
1480 | return -EINVAL; |
1481 | } | |
1482 | ||
8c686254 | 1483 | return ret; |
b455159c LG |
1484 | } |
1485 | ||
1486 | static int sienna_cichlid_read_sensor(struct smu_context *smu, | |
1487 | enum amd_pp_sensors sensor, | |
1488 | void *data, uint32_t *size) | |
1489 | { | |
1490 | int ret = 0; | |
1491 | struct smu_table_context *table_context = &smu->smu_table; | |
1492 | PPTable_t *pptable = table_context->driver_pptable; | |
1493 | ||
1494 | if(!data || !size) | |
1495 | return -EINVAL; | |
1496 | ||
1497 | mutex_lock(&smu->sensor_lock); | |
1498 | switch (sensor) { | |
1499 | case AMDGPU_PP_SENSOR_MAX_FAN_RPM: | |
1500 | *(uint32_t *)data = pptable->FanMaximumRpm; | |
1501 | *size = 4; | |
1502 | break; | |
1503 | case AMDGPU_PP_SENSOR_MEM_LOAD: | |
1504 | case AMDGPU_PP_SENSOR_GPU_LOAD: | |
1505 | ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data); | |
1506 | *size = 4; | |
1507 | break; | |
1508 | case AMDGPU_PP_SENSOR_GPU_POWER: | |
1509 | ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data); | |
1510 | *size = 4; | |
1511 | break; | |
1512 | case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: | |
1513 | case AMDGPU_PP_SENSOR_EDGE_TEMP: | |
1514 | case AMDGPU_PP_SENSOR_MEM_TEMP: | |
1515 | ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data); | |
1516 | *size = 4; | |
1517 | break; | |
e0f9e936 EQ |
1518 | case AMDGPU_PP_SENSOR_GFX_MCLK: |
1519 | ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); | |
1520 | *(uint32_t *)data *= 100; | |
1521 | *size = 4; | |
1522 | break; | |
1523 | case AMDGPU_PP_SENSOR_GFX_SCLK: | |
1524 | ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); | |
1525 | *(uint32_t *)data *= 100; | |
1526 | *size = 4; | |
1527 | break; | |
b2febc99 EQ |
1528 | case AMDGPU_PP_SENSOR_VDDGFX: |
1529 | ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); | |
1530 | *size = 4; | |
1531 | break; | |
b455159c | 1532 | default: |
b2febc99 EQ |
1533 | ret = -EOPNOTSUPP; |
1534 | break; | |
b455159c LG |
1535 | } |
1536 | mutex_unlock(&smu->sensor_lock); | |
1537 | ||
1538 | return ret; | |
1539 | } | |
1540 | ||
1541 | static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) | |
1542 | { | |
1543 | uint32_t num_discrete_levels = 0; | |
1544 | uint16_t *dpm_levels = NULL; | |
1545 | uint16_t i = 0; | |
1546 | struct smu_table_context *table_context = &smu->smu_table; | |
1547 | PPTable_t *driver_ppt = NULL; | |
1548 | ||
1549 | if (!clocks_in_khz || !num_states || !table_context->driver_pptable) | |
1550 | return -EINVAL; | |
1551 | ||
1552 | driver_ppt = table_context->driver_pptable; | |
1553 | num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; | |
1554 | dpm_levels = driver_ppt->FreqTableUclk; | |
1555 | ||
1556 | if (num_discrete_levels == 0 || dpm_levels == NULL) | |
1557 | return -EINVAL; | |
1558 | ||
1559 | *num_states = num_discrete_levels; | |
1560 | for (i = 0; i < num_discrete_levels; i++) { | |
1561 | /* convert to khz */ | |
1562 | *clocks_in_khz = (*dpm_levels) * 1000; | |
1563 | clocks_in_khz++; | |
1564 | dpm_levels++; | |
1565 | } | |
1566 | ||
1567 | return 0; | |
1568 | } | |
1569 | ||
1570 | static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, | |
1571 | struct smu_temperature_range *range) | |
1572 | { | |
e02e4d51 EQ |
1573 | struct smu_table_context *table_context = &smu->smu_table; |
1574 | struct smu_11_0_7_powerplay_table *powerplay_table = | |
1575 | table_context->power_play_table; | |
2b1f12a2 | 1576 | PPTable_t *pptable = smu->smu_table.driver_pptable; |
b455159c | 1577 | |
2b1f12a2 | 1578 | if (!range) |
b455159c LG |
1579 | return -EINVAL; |
1580 | ||
0540eced EQ |
1581 | memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); |
1582 | ||
2b1f12a2 EQ |
1583 | range->max = pptable->TemperatureLimit[TEMP_EDGE] * |
1584 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
1585 | range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * | |
1586 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
1587 | range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] * | |
1588 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
1589 | range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * | |
1590 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
1591 | range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] * | |
1592 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
1593 | range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* | |
b455159c | 1594 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
e02e4d51 | 1595 | range->software_shutdown_temp = powerplay_table->software_shutdown_temp; |
b455159c LG |
1596 | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, | |
1601 | bool disable_memory_clock_switch) | |
1602 | { | |
1603 | int ret = 0; | |
1604 | struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = | |
1605 | (struct smu_11_0_max_sustainable_clocks *) | |
1606 | smu->smu_table.max_sustainable_clocks; | |
1607 | uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; | |
1608 | uint32_t max_memory_clock = max_sustainable_clocks->uclock; | |
1609 | ||
1610 | if(smu->disable_uclk_switch == disable_memory_clock_switch) | |
1611 | return 0; | |
1612 | ||
1613 | if(disable_memory_clock_switch) | |
661b94f5 | 1614 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); |
b455159c | 1615 | else |
661b94f5 | 1616 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); |
b455159c LG |
1617 | |
1618 | if(!ret) | |
1619 | smu->disable_uclk_switch = disable_memory_clock_switch; | |
1620 | ||
1621 | return ret; | |
1622 | } | |
1623 | ||
a141b4e3 | 1624 | static int sienna_cichlid_get_power_limit(struct smu_context *smu) |
b455159c | 1625 | { |
1e239fdd EQ |
1626 | struct smu_11_0_7_powerplay_table *powerplay_table = |
1627 | (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; | |
b455159c | 1628 | PPTable_t *pptable = smu->smu_table.driver_pptable; |
1e239fdd EQ |
1629 | uint32_t power_limit, od_percent; |
1630 | ||
1631 | if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { | |
1632 | /* the last hope to figure out the ppt limit */ | |
1633 | if (!pptable) { | |
1634 | dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); | |
1635 | return -EINVAL; | |
b455159c | 1636 | } |
1e239fdd EQ |
1637 | power_limit = |
1638 | pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; | |
1639 | } | |
1640 | smu->current_power_limit = power_limit; | |
b455159c | 1641 | |
1e239fdd EQ |
1642 | if (smu->od_enabled) { |
1643 | od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); | |
1644 | ||
1645 | dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); | |
1646 | ||
1647 | power_limit *= (100 + od_percent); | |
1648 | power_limit /= 100; | |
b455159c | 1649 | } |
1e239fdd | 1650 | smu->max_power_limit = power_limit; |
b455159c | 1651 | |
b455159c LG |
1652 | return 0; |
1653 | } | |
1654 | ||
08ccfe08 LG |
1655 | static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, |
1656 | uint32_t pcie_gen_cap, | |
1657 | uint32_t pcie_width_cap) | |
1658 | { | |
0b590970 | 1659 | struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; |
08ccfe08 | 1660 | PPTable_t *pptable = smu->smu_table.driver_pptable; |
08ccfe08 | 1661 | uint32_t smu_pcie_arg; |
0b590970 | 1662 | int ret, i; |
08ccfe08 | 1663 | |
0b590970 EQ |
1664 | /* lclk dpm table setup */ |
1665 | for (i = 0; i < MAX_PCIE_CONF; i++) { | |
1666 | dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; | |
1667 | dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; | |
1668 | } | |
08ccfe08 LG |
1669 | |
1670 | for (i = 0; i < NUM_LINK_LEVELS; i++) { | |
1671 | smu_pcie_arg = (i << 16) | | |
1672 | ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? | |
1673 | (pptable->PcieGenSpeed[i] << 8) : | |
1674 | (pcie_gen_cap << 8)) | | |
1675 | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? | |
1676 | pptable->PcieLaneCount[i] : | |
1677 | pcie_width_cap); | |
1678 | ||
1679 | ret = smu_send_smc_msg_with_param(smu, | |
40d3b8db LG |
1680 | SMU_MSG_OverridePcieParameters, |
1681 | smu_pcie_arg, | |
1682 | NULL); | |
1683 | ||
08ccfe08 LG |
1684 | if (ret) |
1685 | return ret; | |
1686 | ||
1687 | if (pptable->PcieGenSpeed[i] > pcie_gen_cap) | |
1688 | dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; | |
1689 | if (pptable->PcieLaneCount[i] > pcie_width_cap) | |
1690 | dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; | |
1691 | } | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
38ed7b09 | 1696 | static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, |
258d290c LG |
1697 | enum smu_clk_type clk_type, |
1698 | uint32_t *min, uint32_t *max) | |
1699 | { | |
1700 | struct amdgpu_device *adev = smu->adev; | |
1701 | int ret; | |
1702 | ||
1703 | if (clk_type == SMU_GFXCLK) | |
1704 | amdgpu_gfx_off_ctrl(adev, false); | |
1705 | ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); | |
1706 | if (clk_type == SMU_GFXCLK) | |
1707 | amdgpu_gfx_off_ctrl(adev, true); | |
1708 | ||
1709 | return ret; | |
1710 | } | |
1711 | ||
40d3b8db LG |
1712 | static bool sienna_cichlid_is_baco_supported(struct smu_context *smu) |
1713 | { | |
1714 | struct amdgpu_device *adev = smu->adev; | |
1715 | uint32_t val; | |
1716 | ||
311531f0 | 1717 | if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) |
40d3b8db LG |
1718 | return false; |
1719 | ||
1720 | val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); | |
1721 | return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; | |
1722 | } | |
1723 | ||
ea8139d8 WS |
1724 | static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) |
1725 | { | |
1726 | struct amdgpu_device *adev = smu->adev; | |
1727 | uint32_t val; | |
1728 | u32 smu_version; | |
1729 | ||
1730 | /** | |
1731 | * SRIOV env will not support SMU mode1 reset | |
1732 | * PM FW support mode1 reset from 58.26 | |
1733 | */ | |
a7bae061 | 1734 | smu_cmn_get_smc_version(smu, NULL, &smu_version); |
ea8139d8 WS |
1735 | if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) |
1736 | return false; | |
1737 | ||
1738 | /** | |
1739 | * mode1 reset relies on PSP, so we should check if | |
1740 | * PSP is alive. | |
1741 | */ | |
1742 | val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
1743 | return val != 0x0; | |
1744 | } | |
1745 | ||
b455159c LG |
1746 | static void sienna_cichlid_dump_pptable(struct smu_context *smu) |
1747 | { | |
1748 | struct smu_table_context *table_context = &smu->smu_table; | |
1749 | PPTable_t *pptable = table_context->driver_pptable; | |
1750 | int i; | |
1751 | ||
d9811cfc | 1752 | dev_info(smu->adev->dev, "Dumped PPTable:\n"); |
b455159c | 1753 | |
d9811cfc EQ |
1754 | dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); |
1755 | dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); | |
1756 | dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); | |
b455159c LG |
1757 | |
1758 | for (i = 0; i < PPT_THROTTLER_COUNT; i++) { | |
d9811cfc EQ |
1759 | dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); |
1760 | dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); | |
1761 | dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); | |
1762 | dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); | |
b455159c LG |
1763 | } |
1764 | ||
1765 | for (i = 0; i < TDC_THROTTLER_COUNT; i++) { | |
d9811cfc EQ |
1766 | dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); |
1767 | dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); | |
b455159c LG |
1768 | } |
1769 | ||
1770 | for (i = 0; i < TEMP_COUNT; i++) { | |
d9811cfc | 1771 | dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); |
b455159c LG |
1772 | } |
1773 | ||
d9811cfc EQ |
1774 | dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); |
1775 | dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); | |
1776 | dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); | |
1777 | dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); | |
1778 | dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); | |
b455159c | 1779 | |
d9811cfc | 1780 | dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); |
b455159c | 1781 | for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { |
d9811cfc EQ |
1782 | dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); |
1783 | dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); | |
b455159c | 1784 | } |
d9811cfc EQ |
1785 | dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]); |
1786 | dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]); | |
1787 | dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]); | |
1788 | dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]); | |
1789 | ||
1790 | dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); | |
1791 | ||
1792 | dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); | |
1793 | ||
1794 | dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); | |
1795 | dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); | |
1796 | dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); | |
1797 | dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); | |
1798 | ||
1799 | dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); | |
1800 | dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); | |
1801 | ||
1802 | dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); | |
1803 | dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); | |
1804 | dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); | |
1805 | dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); | |
1806 | ||
1807 | dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); | |
1808 | dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); | |
1809 | dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); | |
1810 | dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); | |
1811 | ||
1812 | dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); | |
1813 | dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); | |
1814 | ||
1815 | dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); | |
1816 | dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); | |
1817 | dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); | |
1818 | dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); | |
1819 | dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); | |
1820 | dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); | |
1821 | dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); | |
1822 | dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); | |
1823 | ||
1824 | dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" | |
b455159c LG |
1825 | " .VoltageMode = 0x%02x\n" |
1826 | " .SnapToDiscrete = 0x%02x\n" | |
1827 | " .NumDiscreteLevels = 0x%02x\n" | |
1828 | " .padding = 0x%02x\n" | |
1829 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1830 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1831 | " .SsFmin = 0x%04x\n" | |
1832 | " .Padding_16 = 0x%04x\n", | |
1833 | pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, | |
1834 | pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, | |
1835 | pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, | |
1836 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, | |
1837 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, | |
1838 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, | |
1839 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, | |
1840 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, | |
1841 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, | |
1842 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, | |
1843 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); | |
1844 | ||
d9811cfc | 1845 | dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" |
b455159c LG |
1846 | " .VoltageMode = 0x%02x\n" |
1847 | " .SnapToDiscrete = 0x%02x\n" | |
1848 | " .NumDiscreteLevels = 0x%02x\n" | |
1849 | " .padding = 0x%02x\n" | |
1850 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1851 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1852 | " .SsFmin = 0x%04x\n" | |
1853 | " .Padding_16 = 0x%04x\n", | |
1854 | pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, | |
1855 | pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, | |
1856 | pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, | |
1857 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, | |
1858 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, | |
1859 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, | |
1860 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, | |
1861 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, | |
1862 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, | |
1863 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, | |
1864 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); | |
1865 | ||
d9811cfc | 1866 | dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" |
b455159c LG |
1867 | " .VoltageMode = 0x%02x\n" |
1868 | " .SnapToDiscrete = 0x%02x\n" | |
1869 | " .NumDiscreteLevels = 0x%02x\n" | |
1870 | " .padding = 0x%02x\n" | |
1871 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1872 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1873 | " .SsFmin = 0x%04x\n" | |
1874 | " .Padding_16 = 0x%04x\n", | |
1875 | pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, | |
1876 | pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, | |
1877 | pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, | |
1878 | pptable->DpmDescriptor[PPCLK_UCLK].Padding, | |
1879 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, | |
1880 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, | |
1881 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, | |
1882 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, | |
1883 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, | |
1884 | pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, | |
1885 | pptable->DpmDescriptor[PPCLK_UCLK].Padding16); | |
1886 | ||
d9811cfc | 1887 | dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" |
b455159c LG |
1888 | " .VoltageMode = 0x%02x\n" |
1889 | " .SnapToDiscrete = 0x%02x\n" | |
1890 | " .NumDiscreteLevels = 0x%02x\n" | |
1891 | " .padding = 0x%02x\n" | |
1892 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1893 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1894 | " .SsFmin = 0x%04x\n" | |
1895 | " .Padding_16 = 0x%04x\n", | |
1896 | pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, | |
1897 | pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, | |
1898 | pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, | |
1899 | pptable->DpmDescriptor[PPCLK_FCLK].Padding, | |
1900 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, | |
1901 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, | |
1902 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, | |
1903 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, | |
1904 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, | |
1905 | pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, | |
1906 | pptable->DpmDescriptor[PPCLK_FCLK].Padding16); | |
1907 | ||
d9811cfc | 1908 | dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" |
b455159c LG |
1909 | " .VoltageMode = 0x%02x\n" |
1910 | " .SnapToDiscrete = 0x%02x\n" | |
1911 | " .NumDiscreteLevels = 0x%02x\n" | |
1912 | " .padding = 0x%02x\n" | |
1913 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1914 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1915 | " .SsFmin = 0x%04x\n" | |
1916 | " .Padding_16 = 0x%04x\n", | |
1917 | pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, | |
1918 | pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, | |
1919 | pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, | |
1920 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, | |
1921 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, | |
1922 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, | |
1923 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, | |
1924 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, | |
1925 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, | |
1926 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, | |
1927 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); | |
1928 | ||
d9811cfc | 1929 | dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" |
b455159c LG |
1930 | " .VoltageMode = 0x%02x\n" |
1931 | " .SnapToDiscrete = 0x%02x\n" | |
1932 | " .NumDiscreteLevels = 0x%02x\n" | |
1933 | " .padding = 0x%02x\n" | |
1934 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1935 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1936 | " .SsFmin = 0x%04x\n" | |
1937 | " .Padding_16 = 0x%04x\n", | |
1938 | pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, | |
1939 | pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, | |
1940 | pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, | |
1941 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, | |
1942 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, | |
1943 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, | |
1944 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, | |
1945 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, | |
1946 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, | |
1947 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, | |
1948 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); | |
1949 | ||
d9811cfc | 1950 | dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" |
b455159c LG |
1951 | " .VoltageMode = 0x%02x\n" |
1952 | " .SnapToDiscrete = 0x%02x\n" | |
1953 | " .NumDiscreteLevels = 0x%02x\n" | |
1954 | " .padding = 0x%02x\n" | |
1955 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1956 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1957 | " .SsFmin = 0x%04x\n" | |
1958 | " .Padding_16 = 0x%04x\n", | |
1959 | pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, | |
1960 | pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, | |
1961 | pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, | |
1962 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, | |
1963 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, | |
1964 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, | |
1965 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, | |
1966 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, | |
1967 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, | |
1968 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, | |
1969 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); | |
1970 | ||
d9811cfc | 1971 | dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" |
b455159c LG |
1972 | " .VoltageMode = 0x%02x\n" |
1973 | " .SnapToDiscrete = 0x%02x\n" | |
1974 | " .NumDiscreteLevels = 0x%02x\n" | |
1975 | " .padding = 0x%02x\n" | |
1976 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1977 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1978 | " .SsFmin = 0x%04x\n" | |
1979 | " .Padding_16 = 0x%04x\n", | |
1980 | pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, | |
1981 | pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, | |
1982 | pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, | |
1983 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, | |
1984 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, | |
1985 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, | |
1986 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, | |
1987 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, | |
1988 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, | |
1989 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, | |
1990 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); | |
1991 | ||
d9811cfc | 1992 | dev_info(smu->adev->dev, "FreqTableGfx\n"); |
b455159c | 1993 | for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) |
d9811cfc | 1994 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); |
b455159c | 1995 | |
d9811cfc | 1996 | dev_info(smu->adev->dev, "FreqTableVclk\n"); |
b455159c | 1997 | for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) |
d9811cfc | 1998 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); |
b455159c | 1999 | |
d9811cfc | 2000 | dev_info(smu->adev->dev, "FreqTableDclk\n"); |
b455159c | 2001 | for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) |
d9811cfc | 2002 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); |
b455159c | 2003 | |
d9811cfc | 2004 | dev_info(smu->adev->dev, "FreqTableSocclk\n"); |
b455159c | 2005 | for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) |
d9811cfc | 2006 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); |
b455159c | 2007 | |
d9811cfc | 2008 | dev_info(smu->adev->dev, "FreqTableUclk\n"); |
b455159c | 2009 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2010 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); |
b455159c | 2011 | |
d9811cfc | 2012 | dev_info(smu->adev->dev, "FreqTableFclk\n"); |
b455159c | 2013 | for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) |
d9811cfc EQ |
2014 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); |
2015 | ||
2016 | dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]); | |
2017 | dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]); | |
2018 | dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]); | |
2019 | dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]); | |
2020 | dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]); | |
2021 | dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]); | |
2022 | dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]); | |
2023 | dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]); | |
2024 | dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]); | |
2025 | dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]); | |
2026 | dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]); | |
2027 | dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]); | |
2028 | dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]); | |
2029 | dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]); | |
2030 | dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]); | |
2031 | dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]); | |
2032 | ||
2033 | dev_info(smu->adev->dev, "DcModeMaxFreq\n"); | |
2034 | dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); | |
2035 | dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); | |
2036 | dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); | |
2037 | dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); | |
2038 | dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); | |
2039 | dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); | |
2040 | dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); | |
2041 | dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); | |
2042 | ||
2043 | dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); | |
b455159c | 2044 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2045 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); |
b455159c | 2046 | |
d9811cfc EQ |
2047 | dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); |
2048 | dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); | |
b455159c | 2049 | |
d9811cfc | 2050 | dev_info(smu->adev->dev, "Mp0clkFreq\n"); |
b455159c | 2051 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) |
d9811cfc | 2052 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); |
b455159c | 2053 | |
d9811cfc | 2054 | dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); |
b455159c | 2055 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) |
d9811cfc | 2056 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); |
b455159c | 2057 | |
d9811cfc | 2058 | dev_info(smu->adev->dev, "MemVddciVoltage\n"); |
b455159c | 2059 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2060 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); |
b455159c | 2061 | |
d9811cfc | 2062 | dev_info(smu->adev->dev, "MemMvddVoltage\n"); |
b455159c | 2063 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc EQ |
2064 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); |
2065 | ||
2066 | dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); | |
2067 | dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); | |
2068 | dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); | |
2069 | dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); | |
2070 | dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); | |
2071 | ||
2072 | dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); | |
2073 | ||
2074 | dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); | |
2075 | dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); | |
2076 | dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); | |
2077 | dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); | |
2078 | dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); | |
2079 | dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); | |
2080 | dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); | |
2081 | dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); | |
2082 | dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); | |
2083 | dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); | |
2084 | dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); | |
2085 | ||
2086 | dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); | |
2087 | dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); | |
2088 | dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); | |
2089 | dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); | |
2090 | dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); | |
2091 | dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); | |
2092 | ||
2093 | dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); | |
2094 | dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); | |
2095 | dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); | |
2096 | dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); | |
2097 | dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); | |
2098 | ||
2099 | dev_info(smu->adev->dev, "FlopsPerByteTable\n"); | |
b455159c | 2100 | for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) |
d9811cfc | 2101 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); |
b455159c | 2102 | |
d9811cfc EQ |
2103 | dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); |
2104 | dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); | |
2105 | dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); | |
2106 | dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); | |
b455159c | 2107 | |
d9811cfc | 2108 | dev_info(smu->adev->dev, "UclkDpmPstates\n"); |
b455159c | 2109 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2110 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); |
b455159c | 2111 | |
d9811cfc EQ |
2112 | dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); |
2113 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n", | |
b455159c | 2114 | pptable->UclkDpmSrcFreqRange.Fmin); |
d9811cfc | 2115 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n", |
b455159c | 2116 | pptable->UclkDpmSrcFreqRange.Fmax); |
d9811cfc EQ |
2117 | dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); |
2118 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n", | |
b455159c | 2119 | pptable->UclkDpmTargFreqRange.Fmin); |
d9811cfc | 2120 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n", |
b455159c | 2121 | pptable->UclkDpmTargFreqRange.Fmax); |
d9811cfc EQ |
2122 | dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); |
2123 | dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); | |
b455159c | 2124 | |
d9811cfc | 2125 | dev_info(smu->adev->dev, "PcieGenSpeed\n"); |
b455159c | 2126 | for (i = 0; i < NUM_LINK_LEVELS; i++) |
d9811cfc | 2127 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); |
b455159c | 2128 | |
d9811cfc | 2129 | dev_info(smu->adev->dev, "PcieLaneCount\n"); |
b455159c | 2130 | for (i = 0; i < NUM_LINK_LEVELS; i++) |
d9811cfc | 2131 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); |
b455159c | 2132 | |
d9811cfc | 2133 | dev_info(smu->adev->dev, "LclkFreq\n"); |
b455159c | 2134 | for (i = 0; i < NUM_LINK_LEVELS; i++) |
d9811cfc | 2135 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); |
b455159c | 2136 | |
d9811cfc EQ |
2137 | dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); |
2138 | dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); | |
b455159c | 2139 | |
d9811cfc | 2140 | dev_info(smu->adev->dev, "FanGain\n"); |
b455159c | 2141 | for (i = 0; i < TEMP_COUNT; i++) |
d9811cfc EQ |
2142 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); |
2143 | ||
2144 | dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); | |
2145 | dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); | |
2146 | dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); | |
2147 | dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); | |
2148 | dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); | |
2149 | dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); | |
2150 | dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); | |
2151 | dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); | |
2152 | dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); | |
2153 | dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); | |
2154 | dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); | |
2155 | dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); | |
2156 | ||
2157 | dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); | |
2158 | dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); | |
2159 | dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); | |
2160 | dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); | |
2161 | ||
2162 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); | |
2163 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); | |
2164 | dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); | |
2165 | dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); | |
2166 | ||
2167 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", | |
b455159c LG |
2168 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, |
2169 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, | |
2170 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); | |
d9811cfc | 2171 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2172 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, |
2173 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, | |
2174 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); | |
d9811cfc | 2175 | dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2176 | pptable->dBtcGbGfxPll.a, |
2177 | pptable->dBtcGbGfxPll.b, | |
2178 | pptable->dBtcGbGfxPll.c); | |
d9811cfc | 2179 | dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2180 | pptable->dBtcGbGfxDfll.a, |
2181 | pptable->dBtcGbGfxDfll.b, | |
2182 | pptable->dBtcGbGfxDfll.c); | |
d9811cfc | 2183 | dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2184 | pptable->dBtcGbSoc.a, |
2185 | pptable->dBtcGbSoc.b, | |
2186 | pptable->dBtcGbSoc.c); | |
d9811cfc | 2187 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", |
b455159c LG |
2188 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, |
2189 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); | |
d9811cfc | 2190 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", |
b455159c LG |
2191 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, |
2192 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); | |
2193 | ||
d9811cfc | 2194 | dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); |
b455159c | 2195 | for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { |
d9811cfc | 2196 | dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", |
b455159c | 2197 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); |
d9811cfc | 2198 | dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", |
b455159c LG |
2199 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); |
2200 | } | |
2201 | ||
d9811cfc | 2202 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2203 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, |
2204 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, | |
2205 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); | |
d9811cfc | 2206 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2207 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, |
2208 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, | |
2209 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); | |
2210 | ||
d9811cfc EQ |
2211 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); |
2212 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); | |
b455159c | 2213 | |
d9811cfc EQ |
2214 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); |
2215 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); | |
2216 | dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); | |
2217 | dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); | |
b455159c | 2218 | |
d9811cfc EQ |
2219 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); |
2220 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); | |
2221 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); | |
2222 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); | |
b455159c | 2223 | |
d9811cfc EQ |
2224 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); |
2225 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); | |
b455159c | 2226 | |
d9811cfc | 2227 | dev_info(smu->adev->dev, "XgmiDpmPstates\n"); |
b455159c | 2228 | for (i = 0; i < NUM_XGMI_LEVELS; i++) |
d9811cfc EQ |
2229 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); |
2230 | dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); | |
2231 | dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); | |
b455159c | 2232 | |
d9811cfc EQ |
2233 | dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); |
2234 | dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", | |
b455159c LG |
2235 | pptable->ReservedEquation0.a, |
2236 | pptable->ReservedEquation0.b, | |
2237 | pptable->ReservedEquation0.c); | |
d9811cfc | 2238 | dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2239 | pptable->ReservedEquation1.a, |
2240 | pptable->ReservedEquation1.b, | |
2241 | pptable->ReservedEquation1.c); | |
d9811cfc | 2242 | dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2243 | pptable->ReservedEquation2.a, |
2244 | pptable->ReservedEquation2.b, | |
2245 | pptable->ReservedEquation2.c); | |
d9811cfc | 2246 | dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2247 | pptable->ReservedEquation3.a, |
2248 | pptable->ReservedEquation3.b, | |
2249 | pptable->ReservedEquation3.c); | |
2250 | ||
d9811cfc EQ |
2251 | dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); |
2252 | dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); | |
2253 | dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); | |
2254 | dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); | |
2255 | dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); | |
2256 | dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); | |
2257 | dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); | |
2258 | dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); | |
2259 | dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]); | |
2260 | dev_info(smu->adev->dev, "SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]); | |
2261 | dev_info(smu->adev->dev, "SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]); | |
2262 | dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]); | |
2263 | dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]); | |
2264 | dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]); | |
d9811cfc EQ |
2265 | |
2266 | dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); | |
2267 | dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); | |
2268 | dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); | |
2269 | dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); | |
2270 | dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); | |
2271 | dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); | |
b455159c LG |
2272 | |
2273 | for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { | |
d9811cfc EQ |
2274 | dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); |
2275 | dev_info(smu->adev->dev, " .Enabled = 0x%x\n", | |
b455159c | 2276 | pptable->I2cControllers[i].Enabled); |
d9811cfc | 2277 | dev_info(smu->adev->dev, " .Speed = 0x%x\n", |
b455159c | 2278 | pptable->I2cControllers[i].Speed); |
d9811cfc | 2279 | dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", |
b455159c | 2280 | pptable->I2cControllers[i].SlaveAddress); |
d9811cfc | 2281 | dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", |
b455159c | 2282 | pptable->I2cControllers[i].ControllerPort); |
d9811cfc | 2283 | dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", |
b455159c | 2284 | pptable->I2cControllers[i].ControllerName); |
d9811cfc | 2285 | dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", |
b455159c | 2286 | pptable->I2cControllers[i].ThermalThrotter); |
d9811cfc | 2287 | dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", |
b455159c | 2288 | pptable->I2cControllers[i].I2cProtocol); |
d9811cfc | 2289 | dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", |
b455159c LG |
2290 | pptable->I2cControllers[i].PaddingConfig); |
2291 | } | |
2292 | ||
d9811cfc EQ |
2293 | dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); |
2294 | dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); | |
2295 | dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); | |
2296 | dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); | |
2297 | ||
2298 | dev_info(smu->adev->dev, "Board Parameters:\n"); | |
2299 | dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); | |
2300 | dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); | |
2301 | dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); | |
2302 | dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); | |
2303 | dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); | |
2304 | dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); | |
2305 | dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); | |
2306 | dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); | |
2307 | ||
2308 | dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); | |
2309 | dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); | |
2310 | dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); | |
2311 | ||
2312 | dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); | |
2313 | dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); | |
2314 | dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); | |
2315 | ||
2316 | dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); | |
2317 | dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); | |
2318 | dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); | |
2319 | ||
2320 | dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); | |
2321 | dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); | |
2322 | dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); | |
2323 | ||
2324 | dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); | |
2325 | ||
2326 | dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); | |
2327 | dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); | |
2328 | dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); | |
2329 | dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); | |
2330 | dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); | |
2331 | dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); | |
2332 | dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); | |
2333 | dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); | |
2334 | dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); | |
2335 | dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); | |
2336 | dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); | |
2337 | dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); | |
2338 | dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); | |
2339 | dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); | |
2340 | dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); | |
2341 | dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); | |
2342 | ||
2343 | dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); | |
2344 | dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); | |
2345 | dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); | |
2346 | ||
2347 | dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); | |
2348 | dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); | |
2349 | dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); | |
2350 | ||
f0f3d68e | 2351 | dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); |
d9811cfc EQ |
2352 | dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); |
2353 | ||
2354 | dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); | |
2355 | dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); | |
2356 | dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); | |
2357 | ||
2358 | dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); | |
2359 | dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); | |
2360 | dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); | |
2361 | dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); | |
2362 | dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); | |
2363 | ||
2364 | dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); | |
2365 | dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); | |
2366 | ||
2367 | dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); | |
b455159c | 2368 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2369 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); |
2370 | dev_info(smu->adev->dev, "XgmiLinkWidth\n"); | |
b455159c | 2371 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2372 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); |
2373 | dev_info(smu->adev->dev, "XgmiFclkFreq\n"); | |
b455159c | 2374 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2375 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); |
2376 | dev_info(smu->adev->dev, "XgmiSocVoltage\n"); | |
b455159c | 2377 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2378 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); |
2379 | ||
2380 | dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); | |
2381 | dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); | |
2382 | dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); | |
2383 | dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); | |
2384 | ||
2385 | dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); | |
2386 | dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); | |
2387 | dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); | |
2388 | dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); | |
2389 | dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); | |
2390 | dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); | |
2391 | dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); | |
2392 | dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); | |
2393 | dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); | |
2394 | dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); | |
2395 | dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); | |
d9811cfc EQ |
2396 | |
2397 | dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); | |
2398 | dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); | |
2399 | dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); | |
2400 | dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); | |
2401 | dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); | |
2402 | dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); | |
2403 | dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); | |
2404 | dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); | |
b455159c LG |
2405 | } |
2406 | ||
2407 | static const struct pptable_funcs sienna_cichlid_ppt_funcs = { | |
2408 | .tables_init = sienna_cichlid_tables_init, | |
2409 | .alloc_dpm_context = sienna_cichlid_allocate_dpm_context, | |
b455159c LG |
2410 | .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, |
2411 | .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, | |
f6b4b4a1 | 2412 | .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, |
6fb176a7 | 2413 | .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, |
b455159c LG |
2414 | .print_clk_levels = sienna_cichlid_print_clk_levels, |
2415 | .force_clk_levels = sienna_cichlid_force_clk_levels, | |
2416 | .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, | |
b455159c LG |
2417 | .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, |
2418 | .display_config_changed = sienna_cichlid_display_config_changed, | |
2419 | .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, | |
b455159c LG |
2420 | .is_dpm_running = sienna_cichlid_is_dpm_running, |
2421 | .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent, | |
2422 | .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, | |
2423 | .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, | |
2424 | .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, | |
b455159c LG |
2425 | .set_watermarks_table = sienna_cichlid_set_watermarks_table, |
2426 | .read_sensor = sienna_cichlid_read_sensor, | |
2427 | .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, | |
b2785e25 | 2428 | .set_performance_level = smu_v11_0_set_performance_level, |
b455159c LG |
2429 | .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, |
2430 | .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, | |
2431 | .get_power_limit = sienna_cichlid_get_power_limit, | |
08ccfe08 | 2432 | .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, |
b455159c LG |
2433 | .dump_pptable = sienna_cichlid_dump_pptable, |
2434 | .init_microcode = smu_v11_0_init_microcode, | |
2435 | .load_microcode = smu_v11_0_load_microcode, | |
2436 | .init_smc_tables = smu_v11_0_init_smc_tables, | |
2437 | .fini_smc_tables = smu_v11_0_fini_smc_tables, | |
2438 | .init_power = smu_v11_0_init_power, | |
2439 | .fini_power = smu_v11_0_fini_power, | |
2440 | .check_fw_status = smu_v11_0_check_fw_status, | |
4a13b4ce | 2441 | .setup_pptable = sienna_cichlid_setup_pptable, |
b455159c | 2442 | .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, |
b455159c LG |
2443 | .check_fw_version = smu_v11_0_check_fw_version, |
2444 | .write_pptable = smu_v11_0_write_pptable, | |
b455159c LG |
2445 | .set_driver_table_location = smu_v11_0_set_driver_table_location, |
2446 | .set_tool_table_location = smu_v11_0_set_tool_table_location, | |
2447 | .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, | |
2448 | .system_features_control = smu_v11_0_system_features_control, | |
2449 | .send_smc_msg_with_param = smu_v11_0_send_msg_with_param, | |
31157341 | 2450 | .init_display_count = NULL, |
b455159c | 2451 | .set_allowed_mask = smu_v11_0_set_allowed_mask, |
28251d72 | 2452 | .get_enabled_mask = smu_cmn_get_enabled_mask, |
b4bb3aaf | 2453 | .feature_is_enabled = smu_cmn_feature_is_enabled, |
af5ba6d2 | 2454 | .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, |
31157341 | 2455 | .notify_display_change = NULL, |
b455159c | 2456 | .set_power_limit = smu_v11_0_set_power_limit, |
b455159c LG |
2457 | .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, |
2458 | .enable_thermal_alert = smu_v11_0_enable_thermal_alert, | |
2459 | .disable_thermal_alert = smu_v11_0_disable_thermal_alert, | |
ce63d8f8 | 2460 | .set_min_dcef_deep_sleep = NULL, |
b455159c LG |
2461 | .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, |
2462 | .get_fan_control_mode = smu_v11_0_get_fan_control_mode, | |
2463 | .set_fan_control_mode = smu_v11_0_set_fan_control_mode, | |
2464 | .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, | |
2465 | .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, | |
2466 | .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, | |
2467 | .gfx_off_control = smu_v11_0_gfx_off_control, | |
2468 | .register_irq_handler = smu_v11_0_register_irq_handler, | |
2469 | .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, | |
2470 | .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, | |
40d3b8db | 2471 | .baco_is_support= sienna_cichlid_is_baco_supported, |
b455159c LG |
2472 | .baco_get_state = smu_v11_0_baco_get_state, |
2473 | .baco_set_state = smu_v11_0_baco_set_state, | |
2474 | .baco_enter = smu_v11_0_baco_enter, | |
2475 | .baco_exit = smu_v11_0_baco_exit, | |
ea8139d8 WS |
2476 | .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, |
2477 | .mode1_reset = smu_v11_0_mode1_reset, | |
258d290c | 2478 | .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, |
10e96d89 | 2479 | .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, |
7dbf7805 EQ |
2480 | .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, |
2481 | .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, | |
b455159c LG |
2482 | }; |
2483 | ||
2484 | void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) | |
2485 | { | |
2486 | smu->ppt_funcs = &sienna_cichlid_ppt_funcs; | |
6c339f37 EQ |
2487 | smu->message_map = sienna_cichlid_message_map; |
2488 | smu->clock_map = sienna_cichlid_clk_map; | |
2489 | smu->feature_map = sienna_cichlid_feature_mask_map; | |
2490 | smu->table_map = sienna_cichlid_table_map; | |
2491 | smu->pwr_src_map = sienna_cichlid_pwr_src_map; | |
2492 | smu->workload_map = sienna_cichlid_workload_map; | |
b455159c | 2493 | } |