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drm/amd/powerplay: enable VR0HOT for sienna_cichlid
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include <linux/pci.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "smu_internal.h"
30#include "atomfirmware.h"
31#include "amdgpu_atomfirmware.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_sienna_cichlid.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "sienna_cichlid_ppt.h"
37#include "smu_v11_0_pptable.h"
38#include "smu_v11_0_7_ppsmc.h"
39
b7d25b5f 40#include "nbio/nbio_2_3_sh_mask.h"
b455159c
LG		 41#include "asic_reg/mp/mp_11_0_sh_mask.h"
42
43#define FEATURE_MASK(feature) (1ULL << feature)
44#define SMC_DPM_FEATURE ( \
45 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 46 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 47 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 48 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 49 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70
LG		 50 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
51 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
b455159c
LG		 52
53#define MSG_MAP(msg, index) \
54 [SMU_MSG_##msg] = {1, (index)}
55
56static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
57 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
58 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
59 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
60 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
61 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
62 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
63 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
64 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
65 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
66 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
67 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
68 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
69 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
70 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
71 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
72 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
73 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
74 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
75 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
76 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
77 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
78 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
79 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
80 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
81 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
82 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
83 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
84 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
85 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
86 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
87 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
88 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
89 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
90 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
91 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
92 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
93 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
94 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
95 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
96 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
97 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
98 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
99 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
100 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
101 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
102 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
103 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
104 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
105 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
106};
107
108static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
109 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
110 CLK_MAP(SCLK, PPCLK_GFXCLK),
111 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
112 CLK_MAP(FCLK, PPCLK_FCLK),
113 CLK_MAP(UCLK, PPCLK_UCLK),
114 CLK_MAP(MCLK, PPCLK_UCLK),
115 CLK_MAP(DCLK, PPCLK_DCLK_0),
116 CLK_MAP(DCLK1, PPCLK_DCLK_0),
117 CLK_MAP(VCLK, PPCLK_VCLK_1),
118 CLK_MAP(VCLK1, PPCLK_VCLK_1),
119 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
120 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
121 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
122 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
123};
124
125static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
126 FEA_MAP(DPM_PREFETCHER),
127 FEA_MAP(DPM_GFXCLK),
128 FEA_MAP(DPM_UCLK),
129 FEA_MAP(DPM_SOCCLK),
130 FEA_MAP(DPM_MP0CLK),
131 FEA_MAP(DPM_LINK),
132 FEA_MAP(DPM_DCEFCLK),
133 FEA_MAP(MEM_VDDCI_SCALING),
134 FEA_MAP(MEM_MVDD_SCALING),
135 FEA_MAP(DS_GFXCLK),
136 FEA_MAP(DS_SOCCLK),
137 FEA_MAP(DS_LCLK),
138 FEA_MAP(DS_DCEFCLK),
139 FEA_MAP(DS_UCLK),
140 FEA_MAP(GFX_ULV),
141 FEA_MAP(FW_DSTATE),
142 FEA_MAP(GFXOFF),
143 FEA_MAP(BACO),
144 FEA_MAP(RSMU_SMN_CG),
145 FEA_MAP(PPT),
146 FEA_MAP(TDC),
147 FEA_MAP(APCC_PLUS),
148 FEA_MAP(GTHR),
149 FEA_MAP(ACDC),
150 FEA_MAP(VR0HOT),
151 FEA_MAP(VR1HOT),
152 FEA_MAP(FW_CTF),
153 FEA_MAP(FAN_CONTROL),
154 FEA_MAP(THERMAL),
155 FEA_MAP(GFX_DCS),
156 FEA_MAP(RM),
157 FEA_MAP(LED_DISPLAY),
158 FEA_MAP(GFX_SS),
159 FEA_MAP(OUT_OF_BAND_MONITOR),
160 FEA_MAP(TEMP_DEPENDENT_VMIN),
161 FEA_MAP(MMHUB_PG),
162 FEA_MAP(ATHUB_PG),
163};
164
165static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
166 TAB_MAP(PPTABLE),
167 TAB_MAP(WATERMARKS),
168 TAB_MAP(AVFS_PSM_DEBUG),
169 TAB_MAP(AVFS_FUSE_OVERRIDE),
170 TAB_MAP(PMSTATUSLOG),
171 TAB_MAP(SMU_METRICS),
172 TAB_MAP(DRIVER_SMU_CONFIG),
173 TAB_MAP(ACTIVITY_MONITOR_COEFF),
174 TAB_MAP(OVERDRIVE),
175 TAB_MAP(I2C_COMMANDS),
176 TAB_MAP(PACE),
177};
178
1d5ca713
LG		 179static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
180 PWR_MAP(AC),
181 PWR_MAP(DC),
182};
183
b455159c
LG		 184static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
185 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
191 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
192};
193
194static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
195{
196 struct smu_11_0_cmn2aisc_mapping mapping;
197
198 if (index >= SMU_MSG_MAX_COUNT)
199 return -EINVAL;
200
201 mapping = sienna_cichlid_message_map[index];
202 if (!(mapping.valid_mapping)) {
203 return -EINVAL;
204 }
205
206 return mapping.map_to;
207}
208
209static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
210{
211 struct smu_11_0_cmn2aisc_mapping mapping;
212
213 if (index >= SMU_CLK_COUNT)
214 return -EINVAL;
215
216 mapping = sienna_cichlid_clk_map[index];
217 if (!(mapping.valid_mapping)) {
218 return -EINVAL;
219 }
220
221 return mapping.map_to;
222}
223
224static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
225{
226 struct smu_11_0_cmn2aisc_mapping mapping;
227
228 if (index >= SMU_FEATURE_COUNT)
229 return -EINVAL;
230
231 mapping = sienna_cichlid_feature_mask_map[index];
232 if (!(mapping.valid_mapping)) {
233 return -EINVAL;
234 }
235
236 return mapping.map_to;
237}
238
239static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
240{
241 struct smu_11_0_cmn2aisc_mapping mapping;
242
243 if (index >= SMU_TABLE_COUNT)
244 return -EINVAL;
245
246 mapping = sienna_cichlid_table_map[index];
247 if (!(mapping.valid_mapping)) {
248 return -EINVAL;
249 }
250
251 return mapping.map_to;
252}
253
1d5ca713
LG		 254static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index)
255{
256 struct smu_11_0_cmn2aisc_mapping mapping;
257
258 if (index >= SMU_POWER_SOURCE_COUNT)
259 return -EINVAL;
260
261 mapping = sienna_cichlid_pwr_src_map[index];
262 if (!(mapping.valid_mapping)) {
263 return -EINVAL;
264 }
265
266 return mapping.map_to;
267}
268
b455159c
LG		 269static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
270{
271 struct smu_11_0_cmn2aisc_mapping mapping;
272
273 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
274 return -EINVAL;
275
276 mapping = sienna_cichlid_workload_map[profile];
277 if (!(mapping.valid_mapping)) {
278 return -EINVAL;
279 }
280
281 return mapping.map_to;
282}
283
284static int
285sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
286 uint32_t *feature_mask, uint32_t num)
287{
fea905d4
LG		 288 struct amdgpu_device *adev = smu->adev;
289
b455159c
LG		 290 if (num > 2)
291 return -EINVAL;
292
293 memset(feature_mask, 0, sizeof(uint32_t) * num);
294
4cd4f45b 295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 296 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
094cdf15 297 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 298 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
9aa60213
LG		 299 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
300 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
20d71dcc 301 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 302 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 303 | FEATURE_MASK(FEATURE_PPT_BIT)
304 | FEATURE_MASK(FEATURE_TDC_BIT)
1c58d429 305 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
094cdf15 306 | FEATURE_MASK(FEATURE_THERMAL_BIT);
fea905d4
LG		 307
308 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
309 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
310
65297d50
LG		 311 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
313
5cb74353
LG		 314 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
315 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
316
5f338f70
LG		 317 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
319
fea905d4
LG		 320 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 322
62c1ea6b
LG		 323 if (adev->pm.pp_feature & PP_ULV_MASK)
324 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
325
02bb391d
LG		 326 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
327 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
328
b455159c
LG		 329 return 0;
330}
331
332static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
333{
334 return 0;
335}
336
337static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
338{
339 return 0;
340}
341
342static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
343{
344 struct smu_11_0_powerplay_table *powerplay_table = NULL;
345 struct smu_table_context *table_context = &smu->smu_table;
346 struct smu_baco_context *smu_baco = &smu->smu_baco;
347
348 if (!table_context->power_play_table)
349 return -EINVAL;
350
351 powerplay_table = table_context->power_play_table;
352
353 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
354 sizeof(PPTable_t));
355
356 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
357
358 mutex_lock(&smu_baco->mutex);
359 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
360 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
361 smu_baco->platform_support = true;
362 mutex_unlock(&smu_baco->mutex);
363
364 return 0;
365}
366
367static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
368{
369 struct smu_table_context *smu_table = &smu->smu_table;
370
371 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
372 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
373 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
374 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
375 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
376 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
377 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
378 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
379 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
380 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
381 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
382 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
383 AMDGPU_GEM_DOMAIN_VRAM);
384
385 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
386 if (!smu_table->metrics_table)
387 return -ENOMEM;
388 smu_table->metrics_time = 0;
389
390 return 0;
391}
392
393static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
394 SmuMetrics_t *metrics_table)
395{
396 struct smu_table_context *smu_table= &smu->smu_table;
397 int ret = 0;
398
399 mutex_lock(&smu->metrics_lock);
400 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
401 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
402 (void *)smu_table->metrics_table, false);
403 if (ret) {
404 pr_info("Failed to export SMU metrics table!\n");
405 mutex_unlock(&smu->metrics_lock);
406 return ret;
407 }
408 smu_table->metrics_time = jiffies;
409 }
410
411 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
412 mutex_unlock(&smu->metrics_lock);
413
414 return ret;
415}
416
417static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
418{
419 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
420
421 if (smu_dpm->dpm_context)
422 return -EINVAL;
423
424 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
425 GFP_KERNEL);
426 if (!smu_dpm->dpm_context)
427 return -ENOMEM;
428
429 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
430
431 return 0;
432}
433
434static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
435{
436 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
437 struct smu_table_context *table_context = &smu->smu_table;
438 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
439 PPTable_t *driver_ppt = NULL;
08ccfe08 440 int i;
b455159c
LG		 441
442 driver_ppt = table_context->driver_pptable;
443
444 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
445 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
446
447 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
448 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
449
450 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
451 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
452
453 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
454 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
455
456 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
457 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
458
459 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
460 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
461
462 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
463 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
464
465 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
466 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
467
468 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
469 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
470
08ccfe08
LG		 471 for (i = 0; i < MAX_PCIE_CONF; i++) {
472 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
473 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
474 }
475
b455159c
LG		 476 return 0;
477}
478
479static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
480{
481 struct smu_power_context *smu_power = &smu->smu_power;
482 struct smu_power_gate *power_gate = &smu_power->power_gate;
483 int ret = 0;
484
485 if (enable) {
486 /* vcn dpm on is a prerequisite for vcn power gate messages */
487 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
488 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
489 if (ret)
490 return ret;
491 }
492 power_gate->vcn_gated = false;
493 } else {
494 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
495 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
496 if (ret)
497 return ret;
498 }
499 power_gate->vcn_gated = true;
500 }
501
502 return ret;
503}
504
505static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
506 enum smu_clk_type clk_type,
507 uint32_t *value)
508{
509 int ret = 0, clk_id = 0;
510 SmuMetrics_t metrics;
511
512 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
513 if (ret)
514 return ret;
515
516 clk_id = smu_clk_get_index(smu, clk_type);
517 if (clk_id < 0)
518 return clk_id;
519
520 *value = metrics.CurrClock[clk_id];
521
522 return ret;
523}
524
525static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
526{
527 PPTable_t *pptable = smu->smu_table.driver_pptable;
528 DpmDescriptor_t *dpm_desc = NULL;
529 uint32_t clk_index = 0;
530
531 clk_index = smu_clk_get_index(smu, clk_type);
532 dpm_desc = &pptable->DpmDescriptor[clk_index];
533
534 /* 0 - Fine grained DPM, 1 - Discrete DPM */
535 return dpm_desc->SnapToDiscrete == 0 ? true : false;
536}
537
538static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
539 enum smu_clk_type clk_type, char *buf)
540{
b7d25b5f
LG		 541 struct amdgpu_device *adev = smu->adev;
542 struct smu_table_context *table_context = &smu->smu_table;
543 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
544 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
545 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
b455159c
LG		 546 int i, size = 0, ret = 0;
547 uint32_t cur_value = 0, value = 0, count = 0;
548 uint32_t freq_values[3] = {0};
549 uint32_t mark_index = 0;
b7d25b5f 550 uint32_t gen_speed, lane_width;
b455159c
LG		 551
552 switch (clk_type) {
553 case SMU_GFXCLK:
554 case SMU_SCLK:
555 case SMU_SOCCLK:
556 case SMU_MCLK:
557 case SMU_UCLK:
558 case SMU_FCLK:
559 case SMU_DCEFCLK:
560 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
561 if (ret)
562 return size;
563
564 /* 10KHz -> MHz */
565 cur_value = cur_value / 100;
566
567 ret = smu_get_dpm_level_count(smu, clk_type, &count);
568 if (ret)
569 return size;
570
571 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
572 for (i = 0; i < count; i++) {
573 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
574 if (ret)
575 return size;
576
577 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
578 cur_value == value ? "*" : "");
579 }
580 } else {
581 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
582 if (ret)
583 return size;
584 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
585 if (ret)
586 return size;
587
588 freq_values[1] = cur_value;
589 mark_index = cur_value == freq_values[0] ? 0 :
590 cur_value == freq_values[2] ? 2 : 1;
591 if (mark_index != 1)
592 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
593
594 for (i = 0; i < 3; i++) {
595 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
596 i == mark_index ? "*" : "");
597 }
598
599 }
600 break;
b7d25b5f
LG		 601 case SMU_PCIE:
602 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
603 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
604 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
605 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
606 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
607 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
608 for (i = 0; i < NUM_LINK_LEVELS; i++)
609 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
610 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
611 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
612 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
613 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
614 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
615 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
616 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
617 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
618 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
619 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
620 pptable->LclkFreq[i],
621 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
622 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
623 "*" : "");
624 break;
b455159c
LG		 625 default:
626 break;
627 }
628
629 return size;
630}
631
632static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
633 enum smu_clk_type clk_type, uint32_t mask)
634{
635
636 int ret = 0, size = 0;
637 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
638
639 soft_min_level = mask ? (ffs(mask) - 1) : 0;
640 soft_max_level = mask ? (fls(mask) - 1) : 0;
641
642 switch (clk_type) {
643 case SMU_GFXCLK:
644 case SMU_SCLK:
645 case SMU_SOCCLK:
646 case SMU_MCLK:
647 case SMU_UCLK:
648 case SMU_DCEFCLK:
649 case SMU_FCLK:
9ad9c8ac
LG		 650 /* There is only 2 levels for fine grained DPM */
651 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
652 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
653 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
654 }
655
b455159c
LG		 656 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
657 if (ret)
658 return size;
659
660 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
661 if (ret)
662 return size;
663
664 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
665 if (ret)
666 return size;
667 break;
668 default:
669 break;
670 }
671
672 return size;
673}
674
675static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
676{
677 int ret = 0;
678 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
679
680 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
681 if (ret)
682 return ret;
683
684 smu->pstate_sclk = min_sclk_freq * 100;
685
686 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
687 if (ret)
688 return ret;
689
690 smu->pstate_mclk = min_mclk_freq * 100;
691
692 return ret;
693}
694
695static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
696 enum smu_clk_type clk_type,
697 struct pp_clock_levels_with_latency *clocks)
698{
699 int ret = 0, i = 0;
700 uint32_t level_count = 0, freq = 0;
701
702 switch (clk_type) {
703 case SMU_GFXCLK:
704 case SMU_DCEFCLK:
705 case SMU_SOCCLK:
706 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
707 if (ret)
708 return ret;
709
710 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
711 clocks->num_levels = level_count;
712
713 for (i = 0; i < level_count; i++) {
714 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
715 if (ret)
716 return ret;
717
718 clocks->data[i].clocks_in_khz = freq * 1000;
719 clocks->data[i].latency_in_us = 0;
720 }
721 break;
722 default:
723 break;
724 }
725
726 return ret;
727}
728
729static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
730{
731 int ret = 0;
732 uint32_t max_freq = 0;
733
734 /* Sienna_Cichlid do not support to change display num currently */
735 return 0;
736#if 0
737 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
738 if (ret)
739 return ret;
740#endif
741
742 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
743 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
744 if (ret)
745 return ret;
746 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
747 if (ret)
748 return ret;
749 }
750
751 return ret;
752}
753
754static int sienna_cichlid_display_config_changed(struct smu_context *smu)
755{
756 int ret = 0;
757
758 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
759 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
760 ret = smu_write_watermarks_table(smu);
761 if (ret)
762 return ret;
763
764 smu->watermarks_bitmap |= WATERMARKS_LOADED;
765 }
766
767 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
768 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
769 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
770 /* Sienna_Cichlid do not support to change display num currently */
771 ret = 0;
772#if 0
773 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
774 smu->display_config->num_display, NULL);
775#endif
776 if (ret)
777 return ret;
778 }
779
780 return ret;
781}
782
783static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
784{
785 int ret = 0, i = 0;
786 uint32_t min_freq, max_freq, force_freq;
787 enum smu_clk_type clk_type;
788
789 enum smu_clk_type clks[] = {
790 SMU_GFXCLK,
791 };
792
793 for (i = 0; i < ARRAY_SIZE(clks); i++) {
794 clk_type = clks[i];
795 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
796 if (ret)
797 return ret;
798
799 force_freq = highest ? max_freq : min_freq;
800 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
801 if (ret)
802 return ret;
803 }
804
805 return ret;
806}
807
808static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
809{
810 int ret = 0, i = 0;
811 uint32_t min_freq, max_freq;
812 enum smu_clk_type clk_type;
813
814 enum smu_clk_type clks[] = {
815 SMU_GFXCLK,
816 };
817
818 for (i = 0; i < ARRAY_SIZE(clks); i++) {
819 clk_type = clks[i];
820 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
821 if (ret)
822 return ret;
823
824 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
825 if (ret)
826 return ret;
827 }
828
829 return ret;
830}
831
832static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
833{
834 int ret = 0;
835 SmuMetrics_t metrics;
836
837 if (!value)
838 return -EINVAL;
839
840 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
841 if (ret)
842 return ret;
843
844 *value = metrics.AverageSocketPower << 8;
845
846 return 0;
847}
848
849static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
850 enum amd_pp_sensors sensor,
851 uint32_t *value)
852{
853 int ret = 0;
854 SmuMetrics_t metrics;
855
856 if (!value)
857 return -EINVAL;
858
859 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
860 if (ret)
861 return ret;
862
863 switch (sensor) {
864 case AMDGPU_PP_SENSOR_GPU_LOAD:
865 *value = metrics.AverageGfxActivity;
866 break;
867 case AMDGPU_PP_SENSOR_MEM_LOAD:
868 *value = metrics.AverageUclkActivity;
869 break;
870 default:
871 pr_err("Invalid sensor for retrieving clock activity\n");
872 return -EINVAL;
873 }
874
875 return 0;
876}
877
878static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
879{
880 int ret = 0;
881 uint32_t feature_mask[2];
882 unsigned long feature_enabled;
883 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
884 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
885 ((uint64_t)feature_mask[1] << 32));
886 return !!(feature_enabled & SMC_DPM_FEATURE);
887}
888
889static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
890 uint32_t *speed)
891{
892 SmuMetrics_t metrics;
893 int ret = 0;
894
895 if (!speed)
896 return -EINVAL;
897
898 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
899 if (ret)
900 return ret;
901
902 *speed = metrics.CurrFanSpeed;
903
904 return ret;
905}
906
907static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
908 uint32_t *speed)
909{
910 int ret = 0;
911 uint32_t percent = 0;
912 uint32_t current_rpm;
913 PPTable_t *pptable = smu->smu_table.driver_pptable;
914
915 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
916 if (ret)
917 return ret;
918
919 percent = current_rpm * 100 / pptable->FanMaximumRpm;
920 *speed = percent > 100 ? 100 : percent;
921
922 return ret;
923}
924
925static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
926{
927 DpmActivityMonitorCoeffInt_t activity_monitor;
928 uint32_t i, size = 0;
929 int16_t workload_type = 0;
930 static const char *profile_name[] = {
931 "BOOTUP_DEFAULT",
932 "3D_FULL_SCREEN",
933 "POWER_SAVING",
934 "VIDEO",
935 "VR",
936 "COMPUTE",
937 "CUSTOM"};
938 static const char *title[] = {
939 "PROFILE_INDEX(NAME)",
940 "CLOCK_TYPE(NAME)",
941 "FPS",
942 "MinFreqType",
943 "MinActiveFreqType",
944 "MinActiveFreq",
945 "BoosterFreqType",
946 "BoosterFreq",
947 "PD_Data_limit_c",
948 "PD_Data_error_coeff",
949 "PD_Data_error_rate_coeff"};
950 int result = 0;
951
952 if (!buf)
953 return -EINVAL;
954
955 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
956 title[0], title[1], title[2], title[3], title[4], title[5],
957 title[6], title[7], title[8], title[9], title[10]);
958
959 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
960 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
961 workload_type = smu_workload_get_type(smu, i);
962 if (workload_type < 0)
963 return -EINVAL;
964
965 result = smu_update_table(smu,
966 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
967 (void *)(&activity_monitor), false);
968 if (result) {
969 pr_err("[%s] Failed to get activity monitor!", __func__);
970 return result;
971 }
972
973 size += sprintf(buf + size, "%2d %14s%s:\n",
974 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
975
976 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
977 " ",
978 0,
979 "GFXCLK",
980 activity_monitor.Gfx_FPS,
981 activity_monitor.Gfx_MinFreqStep,
982 activity_monitor.Gfx_MinActiveFreqType,
983 activity_monitor.Gfx_MinActiveFreq,
984 activity_monitor.Gfx_BoosterFreqType,
985 activity_monitor.Gfx_BoosterFreq,
986 activity_monitor.Gfx_PD_Data_limit_c,
987 activity_monitor.Gfx_PD_Data_error_coeff,
988 activity_monitor.Gfx_PD_Data_error_rate_coeff);
989
990 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
991 " ",
992 1,
993 "SOCCLK",
994 activity_monitor.Fclk_FPS,
995 activity_monitor.Fclk_MinFreqStep,
996 activity_monitor.Fclk_MinActiveFreqType,
997 activity_monitor.Fclk_MinActiveFreq,
998 activity_monitor.Fclk_BoosterFreqType,
999 activity_monitor.Fclk_BoosterFreq,
1000 activity_monitor.Fclk_PD_Data_limit_c,
1001 activity_monitor.Fclk_PD_Data_error_coeff,
1002 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1003
1004 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1005 " ",
1006 2,
1007 "MEMLK",
1008 activity_monitor.Mem_FPS,
1009 activity_monitor.Mem_MinFreqStep,
1010 activity_monitor.Mem_MinActiveFreqType,
1011 activity_monitor.Mem_MinActiveFreq,
1012 activity_monitor.Mem_BoosterFreqType,
1013 activity_monitor.Mem_BoosterFreq,
1014 activity_monitor.Mem_PD_Data_limit_c,
1015 activity_monitor.Mem_PD_Data_error_coeff,
1016 activity_monitor.Mem_PD_Data_error_rate_coeff);
1017 }
1018
1019 return size;
1020}
1021
1022static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1023{
1024 DpmActivityMonitorCoeffInt_t activity_monitor;
1025 int workload_type, ret = 0;
1026
1027 smu->power_profile_mode = input[size];
1028
1029 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1030 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1031 return -EINVAL;
1032 }
1033
1034 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1035 if (size < 0)
1036 return -EINVAL;
1037
1038 ret = smu_update_table(smu,
1039 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1040 (void *)(&activity_monitor), false);
1041 if (ret) {
1042 pr_err("[%s] Failed to get activity monitor!", __func__);
1043 return ret;
1044 }
1045
1046 switch (input[0]) {
1047 case 0: /* Gfxclk */
1048 activity_monitor.Gfx_FPS = input[1];
1049 activity_monitor.Gfx_MinFreqStep = input[2];
1050 activity_monitor.Gfx_MinActiveFreqType = input[3];
1051 activity_monitor.Gfx_MinActiveFreq = input[4];
1052 activity_monitor.Gfx_BoosterFreqType = input[5];
1053 activity_monitor.Gfx_BoosterFreq = input[6];
1054 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1055 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1056 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1057 break;
1058 case 1: /* Socclk */
1059 activity_monitor.Fclk_FPS = input[1];
1060 activity_monitor.Fclk_MinFreqStep = input[2];
1061 activity_monitor.Fclk_MinActiveFreqType = input[3];
1062 activity_monitor.Fclk_MinActiveFreq = input[4];
1063 activity_monitor.Fclk_BoosterFreqType = input[5];
1064 activity_monitor.Fclk_BoosterFreq = input[6];
1065 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1066 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1067 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1068 break;
1069 case 2: /* Memlk */
1070 activity_monitor.Mem_FPS = input[1];
1071 activity_monitor.Mem_MinFreqStep = input[2];
1072 activity_monitor.Mem_MinActiveFreqType = input[3];
1073 activity_monitor.Mem_MinActiveFreq = input[4];
1074 activity_monitor.Mem_BoosterFreqType = input[5];
1075 activity_monitor.Mem_BoosterFreq = input[6];
1076 activity_monitor.Mem_PD_Data_limit_c = input[7];
1077 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1078 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1079 break;
1080 }
1081
1082 ret = smu_update_table(smu,
1083 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1084 (void *)(&activity_monitor), true);
1085 if (ret) {
1086 pr_err("[%s] Failed to set activity monitor!", __func__);
1087 return ret;
1088 }
1089 }
1090
1091 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1092 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1093 if (workload_type < 0)
1094 return -EINVAL;
1095 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1096 1 << workload_type, NULL);
1097
1098 return ret;
1099}
1100
1101static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1102 enum amd_dpm_forced_level level,
1103 uint32_t *sclk_mask,
1104 uint32_t *mclk_mask,
1105 uint32_t *soc_mask)
1106{
1107 int ret = 0;
1108 uint32_t level_count = 0;
1109
1110 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1111 if (sclk_mask)
1112 *sclk_mask = 0;
1113 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1114 if (mclk_mask)
1115 *mclk_mask = 0;
1116 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1117 if(sclk_mask) {
1118 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1119 if (ret)
1120 return ret;
1121 *sclk_mask = level_count - 1;
1122 }
1123
1124 if(mclk_mask) {
1125 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1126 if (ret)
1127 return ret;
1128 *mclk_mask = level_count - 1;
1129 }
1130
1131 if(soc_mask) {
1132 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1133 if (ret)
1134 return ret;
1135 *soc_mask = level_count - 1;
1136 }
1137 }
1138
1139 return ret;
1140}
1141
1142static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1143{
1144 struct smu_clocks min_clocks = {0};
1145 struct pp_display_clock_request clock_req;
1146 int ret = 0;
1147
1148 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1149 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1150 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1151
1152 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1153 clock_req.clock_type = amd_pp_dcef_clock;
1154 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1155
1156 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1157 if (!ret) {
1158 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1159 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1160 return ret;
1161 }
1162 } else {
1163 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1164 }
1165 }
1166
1167 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1168 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1169 if (ret) {
1170 pr_err("[%s] Set hard min uclk failed!", __func__);
1171 return ret;
1172 }
1173 }
1174
1175 return 0;
1176}
1177
1178static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1179 void *watermarks, struct
1180 dm_pp_wm_sets_with_clock_ranges_soc15
1181 *clock_ranges)
1182{
1183 int i;
1184 Watermarks_t *table = watermarks;
1185
1186 if (!table || !clock_ranges)
1187 return -EINVAL;
1188
1189 if (clock_ranges->num_wm_dmif_sets > 4 ||
1190 clock_ranges->num_wm_mcif_sets > 4)
1191 return -EINVAL;
1192
1193 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1194 table->WatermarkRow[1][i].MinClock =
1195 cpu_to_le16((uint16_t)
1196 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1197 1000));
1198 table->WatermarkRow[1][i].MaxClock =
1199 cpu_to_le16((uint16_t)
1200 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1201 1000));
1202 table->WatermarkRow[1][i].MinUclk =
1203 cpu_to_le16((uint16_t)
1204 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1205 1000));
1206 table->WatermarkRow[1][i].MaxUclk =
1207 cpu_to_le16((uint16_t)
1208 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1209 1000));
1210 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1211 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1212 }
1213
1214 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1215 table->WatermarkRow[0][i].MinClock =
1216 cpu_to_le16((uint16_t)
1217 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1218 1000));
1219 table->WatermarkRow[0][i].MaxClock =
1220 cpu_to_le16((uint16_t)
1221 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1222 1000));
1223 table->WatermarkRow[0][i].MinUclk =
1224 cpu_to_le16((uint16_t)
1225 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1226 1000));
1227 table->WatermarkRow[0][i].MaxUclk =
1228 cpu_to_le16((uint16_t)
1229 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1230 1000));
1231 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1232 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1233 }
1234
1235 return 0;
1236}
1237
1238static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1239 enum amd_pp_sensors sensor,
1240 uint32_t *value)
1241{
1242 SmuMetrics_t metrics;
1243 int ret = 0;
1244
1245 if (!value)
1246 return -EINVAL;
1247
1248 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1249 if (ret)
1250 return ret;
1251
1252 switch (sensor) {
1253 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1254 *value = metrics.TemperatureHotspot *
1255 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1256 break;
1257 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1258 *value = metrics.TemperatureEdge *
1259 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1260 break;
1261 case AMDGPU_PP_SENSOR_MEM_TEMP:
1262 *value = metrics.TemperatureMem *
1263 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1264 break;
1265 default:
1266 pr_err("Invalid sensor for retrieving temp\n");
1267 return -EINVAL;
1268 }
1269
1270 return 0;
1271}
1272
1273static int sienna_cichlid_read_sensor(struct smu_context *smu,
1274 enum amd_pp_sensors sensor,
1275 void *data, uint32_t *size)
1276{
1277 int ret = 0;
1278 struct smu_table_context *table_context = &smu->smu_table;
1279 PPTable_t *pptable = table_context->driver_pptable;
1280
1281 if(!data || !size)
1282 return -EINVAL;
1283
1284 mutex_lock(&smu->sensor_lock);
1285 switch (sensor) {
1286 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1287 *(uint32_t *)data = pptable->FanMaximumRpm;
1288 *size = 4;
1289 break;
1290 case AMDGPU_PP_SENSOR_MEM_LOAD:
1291 case AMDGPU_PP_SENSOR_GPU_LOAD:
1292 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1293 *size = 4;
1294 break;
1295 case AMDGPU_PP_SENSOR_GPU_POWER:
1296 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1297 *size = 4;
1298 break;
1299 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1300 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1301 case AMDGPU_PP_SENSOR_MEM_TEMP:
1302 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1303 *size = 4;
1304 break;
1305 default:
1306 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1307 }
1308 mutex_unlock(&smu->sensor_lock);
1309
1310 return ret;
1311}
1312
1313static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1314{
1315 uint32_t num_discrete_levels = 0;
1316 uint16_t *dpm_levels = NULL;
1317 uint16_t i = 0;
1318 struct smu_table_context *table_context = &smu->smu_table;
1319 PPTable_t *driver_ppt = NULL;
1320
1321 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1322 return -EINVAL;
1323
1324 driver_ppt = table_context->driver_pptable;
1325 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1326 dpm_levels = driver_ppt->FreqTableUclk;
1327
1328 if (num_discrete_levels == 0 || dpm_levels == NULL)
1329 return -EINVAL;
1330
1331 *num_states = num_discrete_levels;
1332 for (i = 0; i < num_discrete_levels; i++) {
1333 /* convert to khz */
1334 *clocks_in_khz = (*dpm_levels) * 1000;
1335 clocks_in_khz++;
1336 dpm_levels++;
1337 }
1338
1339 return 0;
1340}
1341
9ad9c8ac
LG		 1342static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1343 enum amd_dpm_forced_level level);
1344
1345static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1346{
1347 struct amdgpu_device *adev = smu->adev;
1348 int ret = 0;
1349 uint32_t sclk_freq = 0, uclk_freq = 0;
1350
1351 switch (adev->asic_type) {
1352 /* TODO: need to set specify clk value by asic type, not support yet*/
1353 default:
1354 /* by default, this is same as auto performance level */
1355 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1356 }
1357
1358 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1359 if (ret)
1360 return ret;
1361 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1362 if (ret)
1363 return ret;
1364
1365 return ret;
1366}
1367
1368static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1369{
1370 int ret = 0;
1371
1372 /* TODO: not support yet*/
1373 return ret;
1374}
1375
1376static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1377 enum amd_dpm_forced_level level)
1378{
1379 int ret = 0;
1380 uint32_t sclk_mask, mclk_mask, soc_mask;
1381
1382 switch (level) {
1383 case AMD_DPM_FORCED_LEVEL_HIGH:
1384 ret = smu_force_dpm_limit_value(smu, true);
1385 break;
1386 case AMD_DPM_FORCED_LEVEL_LOW:
1387 ret = smu_force_dpm_limit_value(smu, false);
1388 break;
1389 case AMD_DPM_FORCED_LEVEL_AUTO:
1390 ret = smu_unforce_dpm_levels(smu);
1391 break;
1392 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1393 ret = sienna_cichlid_set_standard_performance_level(smu);
1394 break;
1395 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1396 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1397 ret = smu_get_profiling_clk_mask(smu, level,
1398 &sclk_mask,
1399 &mclk_mask,
1400 &soc_mask);
1401 if (ret)
1402 return ret;
1403 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1404 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1405 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1406 break;
1407 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1408 ret = sienna_cichlid_set_peak_performance_level(smu);
1409 break;
1410 case AMD_DPM_FORCED_LEVEL_MANUAL:
1411 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1412 default:
1413 break;
1414 }
1415 return ret;
1416}
1417
b455159c
LG		 1418static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1419 struct smu_temperature_range *range)
1420{
1421 struct smu_table_context *table_context = &smu->smu_table;
1422 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1423
1424 if (!range || !powerplay_table)
1425 return -EINVAL;
1426
1427 range->max = powerplay_table->software_shutdown_temp *
1428 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1429
1430 return 0;
1431}
1432
1433static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1434 bool disable_memory_clock_switch)
1435{
1436 int ret = 0;
1437 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1438 (struct smu_11_0_max_sustainable_clocks *)
1439 smu->smu_table.max_sustainable_clocks;
1440 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1441 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1442
1443 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1444 return 0;
1445
1446 if(disable_memory_clock_switch)
1447 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1448 else
1449 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1450
1451 if(!ret)
1452 smu->disable_uclk_switch = disable_memory_clock_switch;
1453
1454 return ret;
1455}
1456
1457static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1458 uint32_t *limit,
1459 bool cap)
1460{
1461 PPTable_t *pptable = smu->smu_table.driver_pptable;
1462 uint32_t asic_default_power_limit = 0;
1463 int ret = 0;
1464 int power_src;
1465
1466 if (!smu->power_limit) {
1467 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1468 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1469 if (power_src < 0)
1470 return -EINVAL;
1471
1472 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1473 power_src << 16, &asic_default_power_limit);
1474 if (ret) {
1475 pr_err("[%s] get PPT limit failed!", __func__);
1476 return ret;
1477 }
1478 } else {
1479 /* the last hope to figure out the ppt limit */
1480 if (!pptable) {
1481 pr_err("Cannot get PPT limit due to pptable missing!");
1482 return -EINVAL;
1483 }
1484 asic_default_power_limit =
1485 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1486 }
1487
1488 smu->power_limit = asic_default_power_limit;
1489 }
1490
1491 if (cap)
1492 *limit = smu_v11_0_get_max_power_limit(smu);
1493 else
1494 *limit = smu->power_limit;
1495
1496 return 0;
1497}
1498
08ccfe08
LG		 1499static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1500 uint32_t pcie_gen_cap,
1501 uint32_t pcie_width_cap)
1502{
1503 PPTable_t *pptable = smu->smu_table.driver_pptable;
1504 int ret, i;
1505 uint32_t smu_pcie_arg;
1506
1507 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1508 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1509
1510 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1511 smu_pcie_arg = (i << 16) |
1512 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1513 (pptable->PcieGenSpeed[i] << 8) :
1514 (pcie_gen_cap << 8)) |
1515 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1516 pptable->PcieLaneCount[i] :
1517 pcie_width_cap);
1518
1519 ret = smu_send_smc_msg_with_param(smu,
1520 SMU_MSG_OverridePcieParameters,
1521 smu_pcie_arg, NULL);
1522 if (ret)
1523 return ret;
1524
1525 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1526 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1527 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1528 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1529 }
1530
1531 return 0;
1532}
1533
b455159c
LG		 1534static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1535{
1536 struct smu_table_context *table_context = &smu->smu_table;
1537 PPTable_t *pptable = table_context->driver_pptable;
1538 int i;
1539
1540 pr_info("Dumped PPTable:\n");
1541
1542 pr_info("Version = 0x%08x\n", pptable->Version);
1543 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1544 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1545
1546 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1547 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1548 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1549 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1550 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1551 }
1552
1553 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1554 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1555 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1556 }
1557
1558 for (i = 0; i < TEMP_COUNT; i++) {
1559 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1560 }
1561
1562 pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1563 pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1564 pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1565 pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1566 pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1567
1568 pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1569 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1570 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1571 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1572 }
1573 pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1574 pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1575 pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1576 pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1577
1578 pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1579
1580 pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1581
1582 pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1583 pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1584 pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1585 pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1586
1587 pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1588 pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1589
1590 pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1591 pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1592 pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1593 pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1594
1595 pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1596 pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1597 pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1598 pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1599
1600 pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1601 pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1602
1603 pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1604 pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1605 pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1606 pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1607 pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1608 pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1609 pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1610 pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1611
1612 pr_info("[PPCLK_GFXCLK]\n"
1613 " .VoltageMode = 0x%02x\n"
1614 " .SnapToDiscrete = 0x%02x\n"
1615 " .NumDiscreteLevels = 0x%02x\n"
1616 " .padding = 0x%02x\n"
1617 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1618 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1619 " .SsFmin = 0x%04x\n"
1620 " .Padding_16 = 0x%04x\n",
1621 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1622 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1623 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1624 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1625 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1626 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1627 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1628 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1629 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1630 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1631 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1632
1633 pr_info("[PPCLK_SOCCLK]\n"
1634 " .VoltageMode = 0x%02x\n"
1635 " .SnapToDiscrete = 0x%02x\n"
1636 " .NumDiscreteLevels = 0x%02x\n"
1637 " .padding = 0x%02x\n"
1638 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1639 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1640 " .SsFmin = 0x%04x\n"
1641 " .Padding_16 = 0x%04x\n",
1642 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1643 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1644 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1645 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1646 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1647 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1648 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1649 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1650 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1651 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1652 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1653
1654 pr_info("[PPCLK_UCLK]\n"
1655 " .VoltageMode = 0x%02x\n"
1656 " .SnapToDiscrete = 0x%02x\n"
1657 " .NumDiscreteLevels = 0x%02x\n"
1658 " .padding = 0x%02x\n"
1659 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1660 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1661 " .SsFmin = 0x%04x\n"
1662 " .Padding_16 = 0x%04x\n",
1663 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1664 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1665 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1666 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1667 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1668 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1669 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1670 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1671 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1672 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1673 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1674
1675 pr_info("[PPCLK_FCLK]\n"
1676 " .VoltageMode = 0x%02x\n"
1677 " .SnapToDiscrete = 0x%02x\n"
1678 " .NumDiscreteLevels = 0x%02x\n"
1679 " .padding = 0x%02x\n"
1680 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1681 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1682 " .SsFmin = 0x%04x\n"
1683 " .Padding_16 = 0x%04x\n",
1684 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1685 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1686 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1687 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1688 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1689 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1690 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1691 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1692 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1693 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1694 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1695
1696 pr_info("[PPCLK_DCLK_0]\n"
1697 " .VoltageMode = 0x%02x\n"
1698 " .SnapToDiscrete = 0x%02x\n"
1699 " .NumDiscreteLevels = 0x%02x\n"
1700 " .padding = 0x%02x\n"
1701 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1702 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1703 " .SsFmin = 0x%04x\n"
1704 " .Padding_16 = 0x%04x\n",
1705 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1706 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1707 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1708 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1709 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1710 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1711 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1712 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1713 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1714 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1715 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1716
1717 pr_info("[PPCLK_VCLK_0]\n"
1718 " .VoltageMode = 0x%02x\n"
1719 " .SnapToDiscrete = 0x%02x\n"
1720 " .NumDiscreteLevels = 0x%02x\n"
1721 " .padding = 0x%02x\n"
1722 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1723 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1724 " .SsFmin = 0x%04x\n"
1725 " .Padding_16 = 0x%04x\n",
1726 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1727 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1728 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1729 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1730 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1731 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1732 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1733 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1734 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1735 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1736 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1737
1738 pr_info("[PPCLK_DCLK_1]\n"
1739 " .VoltageMode = 0x%02x\n"
1740 " .SnapToDiscrete = 0x%02x\n"
1741 " .NumDiscreteLevels = 0x%02x\n"
1742 " .padding = 0x%02x\n"
1743 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1744 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1745 " .SsFmin = 0x%04x\n"
1746 " .Padding_16 = 0x%04x\n",
1747 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1748 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1749 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1750 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1751 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1752 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1753 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1754 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1755 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1756 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1757 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1758
1759 pr_info("[PPCLK_VCLK_1]\n"
1760 " .VoltageMode = 0x%02x\n"
1761 " .SnapToDiscrete = 0x%02x\n"
1762 " .NumDiscreteLevels = 0x%02x\n"
1763 " .padding = 0x%02x\n"
1764 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1765 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1766 " .SsFmin = 0x%04x\n"
1767 " .Padding_16 = 0x%04x\n",
1768 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1769 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1770 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1771 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1772 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1773 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1774 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1775 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1776 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1777 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1778 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1779
1780 pr_info("FreqTableGfx\n");
1781 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1782 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1783
1784 pr_info("FreqTableVclk\n");
1785 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1786 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1787
1788 pr_info("FreqTableDclk\n");
1789 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1790 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1791
1792 pr_info("FreqTableSocclk\n");
1793 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1794 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1795
1796 pr_info("FreqTableUclk\n");
1797 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1798 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1799
1800 pr_info("FreqTableFclk\n");
1801 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1802 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1803
1804 pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
1805 pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
1806 pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
1807 pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
1808 pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
1809 pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
1810 pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
1811 pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
1812 pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
1813 pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
1814 pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1815 pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1816 pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1817 pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1818 pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1819 pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1820
1821 pr_info("DcModeMaxFreq\n");
1822 pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1823 pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1824 pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1825 pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1826 pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1827 pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1828 pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1829 pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1830
1831 pr_info("FreqTableUclkDiv\n");
1832 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1833 pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1834
1835 pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1836 pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1837
1838 pr_info("Mp0clkFreq\n");
1839 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1840 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1841
1842 pr_info("Mp0DpmVoltage\n");
1843 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1844 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1845
1846 pr_info("MemVddciVoltage\n");
1847 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1848 pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1849
1850 pr_info("MemMvddVoltage\n");
1851 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1852 pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1853
1854 pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1855 pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1856 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1857 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1858 pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1859
1860 pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1861
1862 pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1863 pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1864 pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1865 pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1866 pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1867 pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1868 pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1869 pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1870 pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1871 pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1872 pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1873
1874 pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1875 pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1876 pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1877 pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1878 pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1879 pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1880
1881 pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1882 pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1883 pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1884 pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1885 pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1886
1887 pr_info("FlopsPerByteTable\n");
1888 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1889 pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1890
1891 pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1892 pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1893 pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1894 pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1895
1896 pr_info("UclkDpmPstates\n");
1897 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1898 pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1899
1900 pr_info("UclkDpmSrcFreqRange\n");
1901 pr_info(" .Fmin = 0x%x\n",
1902 pptable->UclkDpmSrcFreqRange.Fmin);
1903 pr_info(" .Fmax = 0x%x\n",
1904 pptable->UclkDpmSrcFreqRange.Fmax);
1905 pr_info("UclkDpmTargFreqRange\n");
1906 pr_info(" .Fmin = 0x%x\n",
1907 pptable->UclkDpmTargFreqRange.Fmin);
1908 pr_info(" .Fmax = 0x%x\n",
1909 pptable->UclkDpmTargFreqRange.Fmax);
1910 pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1911 pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1912
1913 pr_info("PcieGenSpeed\n");
1914 for (i = 0; i < NUM_LINK_LEVELS; i++)
1915 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1916
1917 pr_info("PcieLaneCount\n");
1918 for (i = 0; i < NUM_LINK_LEVELS; i++)
1919 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1920
1921 pr_info("LclkFreq\n");
1922 for (i = 0; i < NUM_LINK_LEVELS; i++)
1923 pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1924
1925 pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1926 pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1927
1928 pr_info("FanGain\n");
1929 for (i = 0; i < TEMP_COUNT; i++)
1930 pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1931
1932 pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1933 pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1934 pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1935 pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1936 pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1937 pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1938 pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1939 pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1940 pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1941 pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1942 pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1943 pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1944
1945 pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1946 pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1947 pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1948 pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1949
1950 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1951 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1952 pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
1953 pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
1954
1955 pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1956 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
1957 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
1958 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
1959 pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1960 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
1961 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
1962 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
1963 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1964 pptable->dBtcGbGfxPll.a,
1965 pptable->dBtcGbGfxPll.b,
1966 pptable->dBtcGbGfxPll.c);
1967 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1968 pptable->dBtcGbGfxDfll.a,
1969 pptable->dBtcGbGfxDfll.b,
1970 pptable->dBtcGbGfxDfll.c);
1971 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1972 pptable->dBtcGbSoc.a,
1973 pptable->dBtcGbSoc.b,
1974 pptable->dBtcGbSoc.c);
1975 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1976 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1977 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1978 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1979 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1980 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1981
1982 pr_info("PiecewiseLinearDroopIntGfxDfll\n");
1983 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
1984 pr_info(" Fset[%d] = 0x%x\n",
1985 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
1986 pr_info(" Vdroop[%d] = 0x%x\n",
1987 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
1988 }
1989
1990 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1991 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1992 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1993 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1994 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1995 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1996 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1997 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1998
1999 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2000 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2001
2002 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2003 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2004 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2005 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2006
2007 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2008 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2009 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2010 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2011
2012 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2013 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2014
2015 pr_info("XgmiDpmPstates\n");
2016 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2017 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2018 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2019 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2020
2021 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2022 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2023 pptable->ReservedEquation0.a,
2024 pptable->ReservedEquation0.b,
2025 pptable->ReservedEquation0.c);
2026 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2027 pptable->ReservedEquation1.a,
2028 pptable->ReservedEquation1.b,
2029 pptable->ReservedEquation1.c);
2030 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2031 pptable->ReservedEquation2.a,
2032 pptable->ReservedEquation2.b,
2033 pptable->ReservedEquation2.c);
2034 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2035 pptable->ReservedEquation3.a,
2036 pptable->ReservedEquation3.b,
2037 pptable->ReservedEquation3.c);
2038
2039 pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2040 pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2041 pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2042 pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2043 pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2044 pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2045 pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2046 pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2047 pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2048 pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2049 pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2050 pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2051 pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2052 pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2053 pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
2054
2055 pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2056 pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2057 pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2058 pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2059 pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2060 pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2061
2062 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2063 pr_info("I2cControllers[%d]:\n", i);
2064 pr_info(" .Enabled = 0x%x\n",
2065 pptable->I2cControllers[i].Enabled);
2066 pr_info(" .Speed = 0x%x\n",
2067 pptable->I2cControllers[i].Speed);
2068 pr_info(" .SlaveAddress = 0x%x\n",
2069 pptable->I2cControllers[i].SlaveAddress);
2070 pr_info(" .ControllerPort = 0x%x\n",
2071 pptable->I2cControllers[i].ControllerPort);
2072 pr_info(" .ControllerName = 0x%x\n",
2073 pptable->I2cControllers[i].ControllerName);
2074 pr_info(" .ThermalThrottler = 0x%x\n",
2075 pptable->I2cControllers[i].ThermalThrotter);
2076 pr_info(" .I2cProtocol = 0x%x\n",
2077 pptable->I2cControllers[i].I2cProtocol);
2078 pr_info(" .PaddingConfig = 0x%x\n",
2079 pptable->I2cControllers[i].PaddingConfig);
2080 }
2081
2082 pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
2083 pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
2084 pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2085 pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2086
2087 pr_info("Board Parameters:\n");
2088 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2089 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2090 pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2091 pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2092 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2093 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2094 pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2095 pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2096
2097 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2098 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
2099 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2100
2101 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2102 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
2103 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2104
2105 pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2106 pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2107 pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2108
2109 pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2110 pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2111 pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2112
2113 pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2114
2115 pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2116 pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2117 pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2118 pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2119 pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2120 pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2121 pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2122 pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2123 pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2124 pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2125 pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2126 pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2127 pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2128 pr_info("LedError = 0x%x\n", pptable->LedError);
2129 pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2130 pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2131
2132 pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2133 pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2134 pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2135
2136 pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2137 pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2138 pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2139
2140 pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2141 pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2142 pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2143
2144 pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2145 pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2146 pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2147
2148 pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2149 pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2150 pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2151 pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2152 pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2153
2154 pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2155 pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2156
2157 pr_info("XgmiLinkSpeed\n");
2158 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2159 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2160 pr_info("XgmiLinkWidth\n");
2161 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2162 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2163 pr_info("XgmiFclkFreq\n");
2164 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2165 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2166 pr_info("XgmiSocVoltage\n");
2167 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2168 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2169
2170 pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2171 pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2172 pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2173 pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2174
2175 pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2176 pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2177 pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2178 pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2179 pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2180 pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2181 pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2182 pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2183 pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2184 pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2185 pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2186 pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2187 pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2188 pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2189 pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2190
2191 pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2192 pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2193 pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2194 pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2195 pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2196 pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2197 pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2198 pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2199}
2200
2201static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2202 .tables_init = sienna_cichlid_tables_init,
2203 .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2204 .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2205 .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2206 .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2207 .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2208 .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2209 .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2210 .get_smu_table_index = sienna_cichlid_get_smu_table_index,
1d5ca713 2211 .get_smu_power_index = sienna_cichlid_get_pwr_src_index,
b455159c
LG		 2212 .get_workload_type = sienna_cichlid_get_workload_type,
2213 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2214 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2215 .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2216 .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2217 .print_clk_levels = sienna_cichlid_print_clk_levels,
2218 .force_clk_levels = sienna_cichlid_force_clk_levels,
2219 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2220 .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2221 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2222 .display_config_changed = sienna_cichlid_display_config_changed,
2223 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2224 .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2225 .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2226 .is_dpm_running = sienna_cichlid_is_dpm_running,
2227 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2228 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2229 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2230 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2231 .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2232 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2233 .read_sensor = sienna_cichlid_read_sensor,
2234 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
9ad9c8ac 2235 .set_performance_level = sienna_cichlid_set_performance_level,
b455159c
LG		 2236 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2237 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2238 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2239 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2240 .dump_pptable = sienna_cichlid_dump_pptable,
2241 .init_microcode = smu_v11_0_init_microcode,
2242 .load_microcode = smu_v11_0_load_microcode,
2243 .init_smc_tables = smu_v11_0_init_smc_tables,
2244 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2245 .init_power = smu_v11_0_init_power,
2246 .fini_power = smu_v11_0_fini_power,
2247 .check_fw_status = smu_v11_0_check_fw_status,
2248 .setup_pptable = smu_v11_0_setup_pptable,
2249 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2250 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2251 .check_pptable = smu_v11_0_check_pptable,
2252 .parse_pptable = smu_v11_0_parse_pptable,
2253 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2254 .check_fw_version = smu_v11_0_check_fw_version,
2255 .write_pptable = smu_v11_0_write_pptable,
2256 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2257 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2258 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2259 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2260 .system_features_control = smu_v11_0_system_features_control,
2261 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2262 .init_display_count = smu_v11_0_init_display_count,
2263 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2264 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2265 .notify_display_change = smu_v11_0_notify_display_change,
2266 .set_power_limit = smu_v11_0_set_power_limit,
2267 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2268 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2269 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2270 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2271 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2272 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2273 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2274 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2275 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2276 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2277 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2278 .gfx_off_control = smu_v11_0_gfx_off_control,
2279 .register_irq_handler = smu_v11_0_register_irq_handler,
2280 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2281 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2282 .baco_is_support= smu_v11_0_baco_is_support,
2283 .baco_get_state = smu_v11_0_baco_get_state,
2284 .baco_set_state = smu_v11_0_baco_set_state,
2285 .baco_enter = smu_v11_0_baco_enter,
2286 .baco_exit = smu_v11_0_baco_exit,
2287 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2288 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2289 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2290};
2291
2292void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2293{
2294 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2295}
Linux 6.x block layer and io_uring tree(s)