projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/powerplay: enable athub pg
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include <linux/pci.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "smu_internal.h"
30#include "atomfirmware.h"
31#include "amdgpu_atomfirmware.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_sienna_cichlid.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "sienna_cichlid_ppt.h"
37#include "smu_v11_0_pptable.h"
38#include "smu_v11_0_7_ppsmc.h"
39
b7d25b5f 40#include "nbio/nbio_2_3_sh_mask.h"
b455159c
LG		 41#include "asic_reg/mp/mp_11_0_sh_mask.h"
42
43#define FEATURE_MASK(feature) (1ULL << feature)
44#define SMC_DPM_FEATURE ( \
45 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 46 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 47 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 48 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 49 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70
LG		 50 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
51 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
b455159c
LG		 52
53#define MSG_MAP(msg, index) \
54 [SMU_MSG_##msg] = {1, (index)}
55
56static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
57 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
58 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
59 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
60 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
61 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
62 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
63 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
64 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
65 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
66 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
67 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
68 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
69 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
70 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
71 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
72 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
73 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
74 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
75 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
76 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
77 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
78 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
79 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
80 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
81 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
82 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
83 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
84 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
85 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
86 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
87 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
88 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
89 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
90 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
91 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
92 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
93 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
94 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
95 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
96 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
97 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
98 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
99 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
100 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
101 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
102 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
103 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
104 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
105 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
3fc006f5 106 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
b455159c
LG		 107};
108
109static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
110 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
111 CLK_MAP(SCLK, PPCLK_GFXCLK),
112 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
113 CLK_MAP(FCLK, PPCLK_FCLK),
114 CLK_MAP(UCLK, PPCLK_UCLK),
115 CLK_MAP(MCLK, PPCLK_UCLK),
116 CLK_MAP(DCLK, PPCLK_DCLK_0),
117 CLK_MAP(DCLK1, PPCLK_DCLK_0),
118 CLK_MAP(VCLK, PPCLK_VCLK_1),
119 CLK_MAP(VCLK1, PPCLK_VCLK_1),
120 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
121 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
122 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
123 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
124};
125
126static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
127 FEA_MAP(DPM_PREFETCHER),
128 FEA_MAP(DPM_GFXCLK),
129 FEA_MAP(DPM_UCLK),
130 FEA_MAP(DPM_SOCCLK),
131 FEA_MAP(DPM_MP0CLK),
132 FEA_MAP(DPM_LINK),
133 FEA_MAP(DPM_DCEFCLK),
134 FEA_MAP(MEM_VDDCI_SCALING),
135 FEA_MAP(MEM_MVDD_SCALING),
136 FEA_MAP(DS_GFXCLK),
137 FEA_MAP(DS_SOCCLK),
138 FEA_MAP(DS_LCLK),
139 FEA_MAP(DS_DCEFCLK),
140 FEA_MAP(DS_UCLK),
141 FEA_MAP(GFX_ULV),
142 FEA_MAP(FW_DSTATE),
143 FEA_MAP(GFXOFF),
144 FEA_MAP(BACO),
6fb176a7 145 FEA_MAP(MM_DPM_PG),
b455159c
LG		 146 FEA_MAP(RSMU_SMN_CG),
147 FEA_MAP(PPT),
148 FEA_MAP(TDC),
149 FEA_MAP(APCC_PLUS),
150 FEA_MAP(GTHR),
151 FEA_MAP(ACDC),
152 FEA_MAP(VR0HOT),
153 FEA_MAP(VR1HOT),
154 FEA_MAP(FW_CTF),
155 FEA_MAP(FAN_CONTROL),
156 FEA_MAP(THERMAL),
157 FEA_MAP(GFX_DCS),
158 FEA_MAP(RM),
159 FEA_MAP(LED_DISPLAY),
160 FEA_MAP(GFX_SS),
161 FEA_MAP(OUT_OF_BAND_MONITOR),
162 FEA_MAP(TEMP_DEPENDENT_VMIN),
163 FEA_MAP(MMHUB_PG),
164 FEA_MAP(ATHUB_PG),
cf06331f 165 FEA_MAP(APCC_DFLL),
b455159c
LG		 166};
167
168static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
169 TAB_MAP(PPTABLE),
170 TAB_MAP(WATERMARKS),
171 TAB_MAP(AVFS_PSM_DEBUG),
172 TAB_MAP(AVFS_FUSE_OVERRIDE),
173 TAB_MAP(PMSTATUSLOG),
174 TAB_MAP(SMU_METRICS),
175 TAB_MAP(DRIVER_SMU_CONFIG),
176 TAB_MAP(ACTIVITY_MONITOR_COEFF),
177 TAB_MAP(OVERDRIVE),
178 TAB_MAP(I2C_COMMANDS),
179 TAB_MAP(PACE),
180};
181
1d5ca713
LG		 182static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
183 PWR_MAP(AC),
184 PWR_MAP(DC),
185};
186
b455159c
LG		 187static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
191 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
192 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
193 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
194 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
195};
196
197static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
198{
199 struct smu_11_0_cmn2aisc_mapping mapping;
200
201 if (index >= SMU_MSG_MAX_COUNT)
202 return -EINVAL;
203
204 mapping = sienna_cichlid_message_map[index];
205 if (!(mapping.valid_mapping)) {
206 return -EINVAL;
207 }
208
209 return mapping.map_to;
210}
211
212static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
213{
214 struct smu_11_0_cmn2aisc_mapping mapping;
215
216 if (index >= SMU_CLK_COUNT)
217 return -EINVAL;
218
219 mapping = sienna_cichlid_clk_map[index];
220 if (!(mapping.valid_mapping)) {
221 return -EINVAL;
222 }
223
224 return mapping.map_to;
225}
226
227static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
228{
229 struct smu_11_0_cmn2aisc_mapping mapping;
230
231 if (index >= SMU_FEATURE_COUNT)
232 return -EINVAL;
233
234 mapping = sienna_cichlid_feature_mask_map[index];
235 if (!(mapping.valid_mapping)) {
236 return -EINVAL;
237 }
238
239 return mapping.map_to;
240}
241
242static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
243{
244 struct smu_11_0_cmn2aisc_mapping mapping;
245
246 if (index >= SMU_TABLE_COUNT)
247 return -EINVAL;
248
249 mapping = sienna_cichlid_table_map[index];
250 if (!(mapping.valid_mapping)) {
251 return -EINVAL;
252 }
253
254 return mapping.map_to;
255}
256
1d5ca713
LG		 257static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index)
258{
259 struct smu_11_0_cmn2aisc_mapping mapping;
260
261 if (index >= SMU_POWER_SOURCE_COUNT)
262 return -EINVAL;
263
264 mapping = sienna_cichlid_pwr_src_map[index];
265 if (!(mapping.valid_mapping)) {
266 return -EINVAL;
267 }
268
269 return mapping.map_to;
270}
271
b455159c
LG		 272static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
273{
274 struct smu_11_0_cmn2aisc_mapping mapping;
275
276 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
277 return -EINVAL;
278
279 mapping = sienna_cichlid_workload_map[profile];
280 if (!(mapping.valid_mapping)) {
281 return -EINVAL;
282 }
283
284 return mapping.map_to;
285}
286
287static int
288sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
289 uint32_t *feature_mask, uint32_t num)
290{
fea905d4
LG		 291 struct amdgpu_device *adev = smu->adev;
292
b455159c
LG		 293 if (num > 2)
294 return -EINVAL;
295
296 memset(feature_mask, 0, sizeof(uint32_t) * num);
297
4cd4f45b 298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 299 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
094cdf15 300 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 302 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
9aa60213
LG		 303 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
304 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
20d71dcc 305 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 306 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 307 | FEATURE_MASK(FEATURE_PPT_BIT)
308 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 309 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 310 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
1c58d429 311 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
094cdf15 312 | FEATURE_MASK(FEATURE_THERMAL_BIT);
fea905d4
LG		 313
314 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
315 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
316
65297d50
LG		 317 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
319
5cb74353
LG		 320 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
322
5f338f70
LG		 323 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
324 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
325
fea905d4
LG		 326 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
327 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 328
62c1ea6b
LG		 329 if (adev->pm.pp_feature & PP_ULV_MASK)
330 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
331
02bb391d
LG		 332 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
333 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
334
b794616d
KF		 335 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
337
6fb176a7
LG		 338 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
339 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
341
b455159c
LG		 342 return 0;
343}
344
345static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
346{
347 return 0;
348}
349
350static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
351{
352 return 0;
353}
354
355static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
356{
357 struct smu_11_0_powerplay_table *powerplay_table = NULL;
358 struct smu_table_context *table_context = &smu->smu_table;
359 struct smu_baco_context *smu_baco = &smu->smu_baco;
360
361 if (!table_context->power_play_table)
362 return -EINVAL;
363
364 powerplay_table = table_context->power_play_table;
365
366 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
367 sizeof(PPTable_t));
368
369 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
370
371 mutex_lock(&smu_baco->mutex);
372 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
373 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
374 smu_baco->platform_support = true;
375 mutex_unlock(&smu_baco->mutex);
376
377 return 0;
378}
379
380static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
381{
382 struct smu_table_context *smu_table = &smu->smu_table;
383
384 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
385 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
386 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
387 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
388 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
389 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
390 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
391 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
392 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
393 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
394 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
395 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
396 AMDGPU_GEM_DOMAIN_VRAM);
397
398 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
399 if (!smu_table->metrics_table)
400 return -ENOMEM;
401 smu_table->metrics_time = 0;
402
403 return 0;
404}
405
406static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
407 SmuMetrics_t *metrics_table)
408{
409 struct smu_table_context *smu_table= &smu->smu_table;
410 int ret = 0;
411
412 mutex_lock(&smu->metrics_lock);
413 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
414 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
415 (void *)smu_table->metrics_table, false);
416 if (ret) {
417 pr_info("Failed to export SMU metrics table!\n");
418 mutex_unlock(&smu->metrics_lock);
419 return ret;
420 }
421 smu_table->metrics_time = jiffies;
422 }
423
424 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
425 mutex_unlock(&smu->metrics_lock);
426
427 return ret;
428}
429
430static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
431{
432 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
433
434 if (smu_dpm->dpm_context)
435 return -EINVAL;
436
437 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
438 GFP_KERNEL);
439 if (!smu_dpm->dpm_context)
440 return -ENOMEM;
441
442 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
443
444 return 0;
445}
446
447static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
448{
449 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
450 struct smu_table_context *table_context = &smu->smu_table;
451 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
452 PPTable_t *driver_ppt = NULL;
08ccfe08 453 int i;
b455159c
LG		 454
455 driver_ppt = table_context->driver_pptable;
456
457 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
458 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
459
460 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
461 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
462
463 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
464 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
465
466 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
467 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
468
469 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
470 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
471
472 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
473 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
474
475 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
476 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
477
478 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
479 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
480
481 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
482 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
483
08ccfe08
LG		 484 for (i = 0; i < MAX_PCIE_CONF; i++) {
485 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
486 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
487 }
488
b455159c
LG		 489 return 0;
490}
491
492static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
493{
494 struct smu_power_context *smu_power = &smu->smu_power;
495 struct smu_power_gate *power_gate = &smu_power->power_gate;
496 int ret = 0;
497
498 if (enable) {
499 /* vcn dpm on is a prerequisite for vcn power gate messages */
6fb176a7
LG		 500 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
501 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
502 if (ret)
503 return ret;
504 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL);
b455159c
LG		 505 if (ret)
506 return ret;
507 }
508 power_gate->vcn_gated = false;
509 } else {
6fb176a7
LG		 510 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
511 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
512 if (ret)
513 return ret;
514 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL);
b455159c
LG		 515 if (ret)
516 return ret;
517 }
518 power_gate->vcn_gated = true;
519 }
520
521 return ret;
522}
523
6fb176a7
LG		 524static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
525{
526 struct smu_power_context *smu_power = &smu->smu_power;
527 struct smu_power_gate *power_gate = &smu_power->power_gate;
528 int ret = 0;
529
530 if (enable) {
531 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
532 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
533 if (ret)
534 return ret;
535 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0x10000, NULL);
536 if (ret)
537 return ret;
538 }
539 power_gate->jpeg_gated = false;
540 } else {
541 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
542 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
543 if (ret)
544 return ret;
545 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0x10000, NULL);
546 if (ret)
547 return ret;
548 }
549 power_gate->jpeg_gated = true;
550 }
551
552 return ret;
553}
554
b455159c
LG		 555static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
556 enum smu_clk_type clk_type,
557 uint32_t *value)
558{
559 int ret = 0, clk_id = 0;
560 SmuMetrics_t metrics;
561
562 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
563 if (ret)
564 return ret;
565
566 clk_id = smu_clk_get_index(smu, clk_type);
567 if (clk_id < 0)
568 return clk_id;
569
570 *value = metrics.CurrClock[clk_id];
571
572 return ret;
573}
574
575static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
576{
577 PPTable_t *pptable = smu->smu_table.driver_pptable;
578 DpmDescriptor_t *dpm_desc = NULL;
579 uint32_t clk_index = 0;
580
581 clk_index = smu_clk_get_index(smu, clk_type);
582 dpm_desc = &pptable->DpmDescriptor[clk_index];
583
584 /* 0 - Fine grained DPM, 1 - Discrete DPM */
585 return dpm_desc->SnapToDiscrete == 0 ? true : false;
586}
587
588static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
589 enum smu_clk_type clk_type, char *buf)
590{
b7d25b5f
LG		 591 struct amdgpu_device *adev = smu->adev;
592 struct smu_table_context *table_context = &smu->smu_table;
593 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
594 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
595 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
b455159c
LG		 596 int i, size = 0, ret = 0;
597 uint32_t cur_value = 0, value = 0, count = 0;
598 uint32_t freq_values[3] = {0};
599 uint32_t mark_index = 0;
b7d25b5f 600 uint32_t gen_speed, lane_width;
b455159c
LG		 601
602 switch (clk_type) {
603 case SMU_GFXCLK:
604 case SMU_SCLK:
605 case SMU_SOCCLK:
606 case SMU_MCLK:
607 case SMU_UCLK:
608 case SMU_FCLK:
609 case SMU_DCEFCLK:
610 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
611 if (ret)
612 return size;
613
614 /* 10KHz -> MHz */
615 cur_value = cur_value / 100;
616
617 ret = smu_get_dpm_level_count(smu, clk_type, &count);
618 if (ret)
619 return size;
620
621 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
622 for (i = 0; i < count; i++) {
623 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
624 if (ret)
625 return size;
626
627 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
628 cur_value == value ? "*" : "");
629 }
630 } else {
631 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
632 if (ret)
633 return size;
634 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
635 if (ret)
636 return size;
637
638 freq_values[1] = cur_value;
639 mark_index = cur_value == freq_values[0] ? 0 :
640 cur_value == freq_values[2] ? 2 : 1;
641 if (mark_index != 1)
642 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
643
644 for (i = 0; i < 3; i++) {
645 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
646 i == mark_index ? "*" : "");
647 }
648
649 }
650 break;
b7d25b5f
LG		 651 case SMU_PCIE:
652 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
653 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
654 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
655 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
656 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
657 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
658 for (i = 0; i < NUM_LINK_LEVELS; i++)
659 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
660 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
661 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
662 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
663 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
664 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
665 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
666 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
667 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
668 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
669 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
670 pptable->LclkFreq[i],
671 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
672 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
673 "*" : "");
674 break;
b455159c
LG		 675 default:
676 break;
677 }
678
679 return size;
680}
681
682static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
683 enum smu_clk_type clk_type, uint32_t mask)
684{
685
686 int ret = 0, size = 0;
687 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
688
689 soft_min_level = mask ? (ffs(mask) - 1) : 0;
690 soft_max_level = mask ? (fls(mask) - 1) : 0;
691
692 switch (clk_type) {
693 case SMU_GFXCLK:
694 case SMU_SCLK:
695 case SMU_SOCCLK:
696 case SMU_MCLK:
697 case SMU_UCLK:
698 case SMU_DCEFCLK:
699 case SMU_FCLK:
9ad9c8ac
LG		 700 /* There is only 2 levels for fine grained DPM */
701 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
702 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
703 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
704 }
705
b455159c
LG		 706 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
707 if (ret)
708 return size;
709
710 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
711 if (ret)
712 return size;
713
714 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
715 if (ret)
716 return size;
717 break;
718 default:
719 break;
720 }
721
722 return size;
723}
724
725static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
726{
727 int ret = 0;
728 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
729
730 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
731 if (ret)
732 return ret;
733
734 smu->pstate_sclk = min_sclk_freq * 100;
735
736 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
737 if (ret)
738 return ret;
739
740 smu->pstate_mclk = min_mclk_freq * 100;
741
742 return ret;
743}
744
745static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
746 enum smu_clk_type clk_type,
747 struct pp_clock_levels_with_latency *clocks)
748{
749 int ret = 0, i = 0;
750 uint32_t level_count = 0, freq = 0;
751
752 switch (clk_type) {
753 case SMU_GFXCLK:
754 case SMU_DCEFCLK:
755 case SMU_SOCCLK:
756 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
757 if (ret)
758 return ret;
759
760 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
761 clocks->num_levels = level_count;
762
763 for (i = 0; i < level_count; i++) {
764 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
765 if (ret)
766 return ret;
767
768 clocks->data[i].clocks_in_khz = freq * 1000;
769 clocks->data[i].latency_in_us = 0;
770 }
771 break;
772 default:
773 break;
774 }
775
776 return ret;
777}
778
779static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
780{
781 int ret = 0;
782 uint32_t max_freq = 0;
783
784 /* Sienna_Cichlid do not support to change display num currently */
785 return 0;
786#if 0
787 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
788 if (ret)
789 return ret;
790#endif
791
792 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
793 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
794 if (ret)
795 return ret;
796 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
797 if (ret)
798 return ret;
799 }
800
801 return ret;
802}
803
804static int sienna_cichlid_display_config_changed(struct smu_context *smu)
805{
806 int ret = 0;
807
808 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
809 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
810 ret = smu_write_watermarks_table(smu);
811 if (ret)
812 return ret;
813
814 smu->watermarks_bitmap |= WATERMARKS_LOADED;
815 }
816
817 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
818 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
819 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
820 /* Sienna_Cichlid do not support to change display num currently */
821 ret = 0;
822#if 0
823 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
824 smu->display_config->num_display, NULL);
825#endif
826 if (ret)
827 return ret;
828 }
829
830 return ret;
831}
832
833static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
834{
835 int ret = 0, i = 0;
836 uint32_t min_freq, max_freq, force_freq;
837 enum smu_clk_type clk_type;
838
839 enum smu_clk_type clks[] = {
840 SMU_GFXCLK,
841 };
842
843 for (i = 0; i < ARRAY_SIZE(clks); i++) {
844 clk_type = clks[i];
845 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
846 if (ret)
847 return ret;
848
849 force_freq = highest ? max_freq : min_freq;
850 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
851 if (ret)
852 return ret;
853 }
854
855 return ret;
856}
857
858static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
859{
860 int ret = 0, i = 0;
861 uint32_t min_freq, max_freq;
862 enum smu_clk_type clk_type;
863
864 enum smu_clk_type clks[] = {
865 SMU_GFXCLK,
866 };
867
868 for (i = 0; i < ARRAY_SIZE(clks); i++) {
869 clk_type = clks[i];
870 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
871 if (ret)
872 return ret;
873
874 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
875 if (ret)
876 return ret;
877 }
878
879 return ret;
880}
881
882static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
883{
884 int ret = 0;
885 SmuMetrics_t metrics;
886
887 if (!value)
888 return -EINVAL;
889
890 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
891 if (ret)
892 return ret;
893
894 *value = metrics.AverageSocketPower << 8;
895
896 return 0;
897}
898
899static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
900 enum amd_pp_sensors sensor,
901 uint32_t *value)
902{
903 int ret = 0;
904 SmuMetrics_t metrics;
905
906 if (!value)
907 return -EINVAL;
908
909 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
910 if (ret)
911 return ret;
912
913 switch (sensor) {
914 case AMDGPU_PP_SENSOR_GPU_LOAD:
915 *value = metrics.AverageGfxActivity;
916 break;
917 case AMDGPU_PP_SENSOR_MEM_LOAD:
918 *value = metrics.AverageUclkActivity;
919 break;
920 default:
921 pr_err("Invalid sensor for retrieving clock activity\n");
922 return -EINVAL;
923 }
924
925 return 0;
926}
927
928static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
929{
930 int ret = 0;
931 uint32_t feature_mask[2];
932 unsigned long feature_enabled;
933 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
934 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
935 ((uint64_t)feature_mask[1] << 32));
936 return !!(feature_enabled & SMC_DPM_FEATURE);
937}
938
939static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
940 uint32_t *speed)
941{
942 SmuMetrics_t metrics;
943 int ret = 0;
944
945 if (!speed)
946 return -EINVAL;
947
948 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
949 if (ret)
950 return ret;
951
952 *speed = metrics.CurrFanSpeed;
953
954 return ret;
955}
956
957static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
958 uint32_t *speed)
959{
960 int ret = 0;
961 uint32_t percent = 0;
962 uint32_t current_rpm;
963 PPTable_t *pptable = smu->smu_table.driver_pptable;
964
965 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
966 if (ret)
967 return ret;
968
969 percent = current_rpm * 100 / pptable->FanMaximumRpm;
970 *speed = percent > 100 ? 100 : percent;
971
972 return ret;
973}
974
975static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
976{
977 DpmActivityMonitorCoeffInt_t activity_monitor;
978 uint32_t i, size = 0;
979 int16_t workload_type = 0;
980 static const char *profile_name[] = {
981 "BOOTUP_DEFAULT",
982 "3D_FULL_SCREEN",
983 "POWER_SAVING",
984 "VIDEO",
985 "VR",
986 "COMPUTE",
987 "CUSTOM"};
988 static const char *title[] = {
989 "PROFILE_INDEX(NAME)",
990 "CLOCK_TYPE(NAME)",
991 "FPS",
992 "MinFreqType",
993 "MinActiveFreqType",
994 "MinActiveFreq",
995 "BoosterFreqType",
996 "BoosterFreq",
997 "PD_Data_limit_c",
998 "PD_Data_error_coeff",
999 "PD_Data_error_rate_coeff"};
1000 int result = 0;
1001
1002 if (!buf)
1003 return -EINVAL;
1004
1005 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1006 title[0], title[1], title[2], title[3], title[4], title[5],
1007 title[6], title[7], title[8], title[9], title[10]);
1008
1009 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1010 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1011 workload_type = smu_workload_get_type(smu, i);
1012 if (workload_type < 0)
1013 return -EINVAL;
1014
1015 result = smu_update_table(smu,
1016 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1017 (void *)(&activity_monitor), false);
1018 if (result) {
1019 pr_err("[%s] Failed to get activity monitor!", __func__);
1020 return result;
1021 }
1022
1023 size += sprintf(buf + size, "%2d %14s%s:\n",
1024 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1025
1026 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1027 " ",
1028 0,
1029 "GFXCLK",
1030 activity_monitor.Gfx_FPS,
1031 activity_monitor.Gfx_MinFreqStep,
1032 activity_monitor.Gfx_MinActiveFreqType,
1033 activity_monitor.Gfx_MinActiveFreq,
1034 activity_monitor.Gfx_BoosterFreqType,
1035 activity_monitor.Gfx_BoosterFreq,
1036 activity_monitor.Gfx_PD_Data_limit_c,
1037 activity_monitor.Gfx_PD_Data_error_coeff,
1038 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1039
1040 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1041 " ",
1042 1,
1043 "SOCCLK",
1044 activity_monitor.Fclk_FPS,
1045 activity_monitor.Fclk_MinFreqStep,
1046 activity_monitor.Fclk_MinActiveFreqType,
1047 activity_monitor.Fclk_MinActiveFreq,
1048 activity_monitor.Fclk_BoosterFreqType,
1049 activity_monitor.Fclk_BoosterFreq,
1050 activity_monitor.Fclk_PD_Data_limit_c,
1051 activity_monitor.Fclk_PD_Data_error_coeff,
1052 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1053
1054 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1055 " ",
1056 2,
1057 "MEMLK",
1058 activity_monitor.Mem_FPS,
1059 activity_monitor.Mem_MinFreqStep,
1060 activity_monitor.Mem_MinActiveFreqType,
1061 activity_monitor.Mem_MinActiveFreq,
1062 activity_monitor.Mem_BoosterFreqType,
1063 activity_monitor.Mem_BoosterFreq,
1064 activity_monitor.Mem_PD_Data_limit_c,
1065 activity_monitor.Mem_PD_Data_error_coeff,
1066 activity_monitor.Mem_PD_Data_error_rate_coeff);
1067 }
1068
1069 return size;
1070}
1071
1072static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1073{
1074 DpmActivityMonitorCoeffInt_t activity_monitor;
1075 int workload_type, ret = 0;
1076
1077 smu->power_profile_mode = input[size];
1078
1079 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1080 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1081 return -EINVAL;
1082 }
1083
1084 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1085 if (size < 0)
1086 return -EINVAL;
1087
1088 ret = smu_update_table(smu,
1089 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1090 (void *)(&activity_monitor), false);
1091 if (ret) {
1092 pr_err("[%s] Failed to get activity monitor!", __func__);
1093 return ret;
1094 }
1095
1096 switch (input[0]) {
1097 case 0: /* Gfxclk */
1098 activity_monitor.Gfx_FPS = input[1];
1099 activity_monitor.Gfx_MinFreqStep = input[2];
1100 activity_monitor.Gfx_MinActiveFreqType = input[3];
1101 activity_monitor.Gfx_MinActiveFreq = input[4];
1102 activity_monitor.Gfx_BoosterFreqType = input[5];
1103 activity_monitor.Gfx_BoosterFreq = input[6];
1104 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1105 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1106 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1107 break;
1108 case 1: /* Socclk */
1109 activity_monitor.Fclk_FPS = input[1];
1110 activity_monitor.Fclk_MinFreqStep = input[2];
1111 activity_monitor.Fclk_MinActiveFreqType = input[3];
1112 activity_monitor.Fclk_MinActiveFreq = input[4];
1113 activity_monitor.Fclk_BoosterFreqType = input[5];
1114 activity_monitor.Fclk_BoosterFreq = input[6];
1115 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1116 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1117 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1118 break;
1119 case 2: /* Memlk */
1120 activity_monitor.Mem_FPS = input[1];
1121 activity_monitor.Mem_MinFreqStep = input[2];
1122 activity_monitor.Mem_MinActiveFreqType = input[3];
1123 activity_monitor.Mem_MinActiveFreq = input[4];
1124 activity_monitor.Mem_BoosterFreqType = input[5];
1125 activity_monitor.Mem_BoosterFreq = input[6];
1126 activity_monitor.Mem_PD_Data_limit_c = input[7];
1127 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1128 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1129 break;
1130 }
1131
1132 ret = smu_update_table(smu,
1133 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1134 (void *)(&activity_monitor), true);
1135 if (ret) {
1136 pr_err("[%s] Failed to set activity monitor!", __func__);
1137 return ret;
1138 }
1139 }
1140
1141 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1142 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1143 if (workload_type < 0)
1144 return -EINVAL;
1145 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1146 1 << workload_type, NULL);
1147
1148 return ret;
1149}
1150
1151static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1152 enum amd_dpm_forced_level level,
1153 uint32_t *sclk_mask,
1154 uint32_t *mclk_mask,
1155 uint32_t *soc_mask)
1156{
1157 int ret = 0;
1158 uint32_t level_count = 0;
1159
1160 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1161 if (sclk_mask)
1162 *sclk_mask = 0;
1163 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1164 if (mclk_mask)
1165 *mclk_mask = 0;
1166 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1167 if(sclk_mask) {
1168 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1169 if (ret)
1170 return ret;
1171 *sclk_mask = level_count - 1;
1172 }
1173
1174 if(mclk_mask) {
1175 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1176 if (ret)
1177 return ret;
1178 *mclk_mask = level_count - 1;
1179 }
1180
1181 if(soc_mask) {
1182 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1183 if (ret)
1184 return ret;
1185 *soc_mask = level_count - 1;
1186 }
1187 }
1188
1189 return ret;
1190}
1191
1192static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1193{
1194 struct smu_clocks min_clocks = {0};
1195 struct pp_display_clock_request clock_req;
1196 int ret = 0;
1197
1198 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1199 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1200 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1201
1202 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1203 clock_req.clock_type = amd_pp_dcef_clock;
1204 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1205
1206 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1207 if (!ret) {
1208 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1209 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1210 return ret;
1211 }
1212 } else {
1213 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1214 }
1215 }
1216
1217 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1218 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1219 if (ret) {
1220 pr_err("[%s] Set hard min uclk failed!", __func__);
1221 return ret;
1222 }
1223 }
1224
1225 return 0;
1226}
1227
1228static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1229 void *watermarks, struct
1230 dm_pp_wm_sets_with_clock_ranges_soc15
1231 *clock_ranges)
1232{
1233 int i;
1234 Watermarks_t *table = watermarks;
1235
1236 if (!table || !clock_ranges)
1237 return -EINVAL;
1238
1239 if (clock_ranges->num_wm_dmif_sets > 4 ||
1240 clock_ranges->num_wm_mcif_sets > 4)
1241 return -EINVAL;
1242
1243 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1244 table->WatermarkRow[1][i].MinClock =
1245 cpu_to_le16((uint16_t)
1246 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1247 1000));
1248 table->WatermarkRow[1][i].MaxClock =
1249 cpu_to_le16((uint16_t)
1250 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1251 1000));
1252 table->WatermarkRow[1][i].MinUclk =
1253 cpu_to_le16((uint16_t)
1254 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1255 1000));
1256 table->WatermarkRow[1][i].MaxUclk =
1257 cpu_to_le16((uint16_t)
1258 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1259 1000));
1260 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1261 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1262 }
1263
1264 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1265 table->WatermarkRow[0][i].MinClock =
1266 cpu_to_le16((uint16_t)
1267 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1268 1000));
1269 table->WatermarkRow[0][i].MaxClock =
1270 cpu_to_le16((uint16_t)
1271 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1272 1000));
1273 table->WatermarkRow[0][i].MinUclk =
1274 cpu_to_le16((uint16_t)
1275 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1276 1000));
1277 table->WatermarkRow[0][i].MaxUclk =
1278 cpu_to_le16((uint16_t)
1279 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1280 1000));
1281 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1282 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1283 }
1284
1285 return 0;
1286}
1287
1288static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1289 enum amd_pp_sensors sensor,
1290 uint32_t *value)
1291{
1292 SmuMetrics_t metrics;
1293 int ret = 0;
1294
1295 if (!value)
1296 return -EINVAL;
1297
1298 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1299 if (ret)
1300 return ret;
1301
1302 switch (sensor) {
1303 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1304 *value = metrics.TemperatureHotspot *
1305 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1306 break;
1307 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1308 *value = metrics.TemperatureEdge *
1309 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1310 break;
1311 case AMDGPU_PP_SENSOR_MEM_TEMP:
1312 *value = metrics.TemperatureMem *
1313 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1314 break;
1315 default:
1316 pr_err("Invalid sensor for retrieving temp\n");
1317 return -EINVAL;
1318 }
1319
1320 return 0;
1321}
1322
1323static int sienna_cichlid_read_sensor(struct smu_context *smu,
1324 enum amd_pp_sensors sensor,
1325 void *data, uint32_t *size)
1326{
1327 int ret = 0;
1328 struct smu_table_context *table_context = &smu->smu_table;
1329 PPTable_t *pptable = table_context->driver_pptable;
1330
1331 if(!data || !size)
1332 return -EINVAL;
1333
1334 mutex_lock(&smu->sensor_lock);
1335 switch (sensor) {
1336 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1337 *(uint32_t *)data = pptable->FanMaximumRpm;
1338 *size = 4;
1339 break;
1340 case AMDGPU_PP_SENSOR_MEM_LOAD:
1341 case AMDGPU_PP_SENSOR_GPU_LOAD:
1342 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1343 *size = 4;
1344 break;
1345 case AMDGPU_PP_SENSOR_GPU_POWER:
1346 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1347 *size = 4;
1348 break;
1349 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1350 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1351 case AMDGPU_PP_SENSOR_MEM_TEMP:
1352 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1353 *size = 4;
1354 break;
1355 default:
1356 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1357 }
1358 mutex_unlock(&smu->sensor_lock);
1359
1360 return ret;
1361}
1362
1363static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1364{
1365 uint32_t num_discrete_levels = 0;
1366 uint16_t *dpm_levels = NULL;
1367 uint16_t i = 0;
1368 struct smu_table_context *table_context = &smu->smu_table;
1369 PPTable_t *driver_ppt = NULL;
1370
1371 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1372 return -EINVAL;
1373
1374 driver_ppt = table_context->driver_pptable;
1375 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1376 dpm_levels = driver_ppt->FreqTableUclk;
1377
1378 if (num_discrete_levels == 0 || dpm_levels == NULL)
1379 return -EINVAL;
1380
1381 *num_states = num_discrete_levels;
1382 for (i = 0; i < num_discrete_levels; i++) {
1383 /* convert to khz */
1384 *clocks_in_khz = (*dpm_levels) * 1000;
1385 clocks_in_khz++;
1386 dpm_levels++;
1387 }
1388
1389 return 0;
1390}
1391
9ad9c8ac
LG		 1392static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1393 enum amd_dpm_forced_level level);
1394
1395static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1396{
1397 struct amdgpu_device *adev = smu->adev;
1398 int ret = 0;
1399 uint32_t sclk_freq = 0, uclk_freq = 0;
1400
1401 switch (adev->asic_type) {
1402 /* TODO: need to set specify clk value by asic type, not support yet*/
1403 default:
1404 /* by default, this is same as auto performance level */
1405 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1406 }
1407
1408 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1409 if (ret)
1410 return ret;
1411 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1412 if (ret)
1413 return ret;
1414
1415 return ret;
1416}
1417
1418static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1419{
1420 int ret = 0;
1421
1422 /* TODO: not support yet*/
1423 return ret;
1424}
1425
1426static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1427 enum amd_dpm_forced_level level)
1428{
1429 int ret = 0;
1430 uint32_t sclk_mask, mclk_mask, soc_mask;
1431
1432 switch (level) {
1433 case AMD_DPM_FORCED_LEVEL_HIGH:
1434 ret = smu_force_dpm_limit_value(smu, true);
1435 break;
1436 case AMD_DPM_FORCED_LEVEL_LOW:
1437 ret = smu_force_dpm_limit_value(smu, false);
1438 break;
1439 case AMD_DPM_FORCED_LEVEL_AUTO:
1440 ret = smu_unforce_dpm_levels(smu);
1441 break;
1442 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1443 ret = sienna_cichlid_set_standard_performance_level(smu);
1444 break;
1445 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1446 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1447 ret = smu_get_profiling_clk_mask(smu, level,
1448 &sclk_mask,
1449 &mclk_mask,
1450 &soc_mask);
1451 if (ret)
1452 return ret;
1453 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1454 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1455 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1456 break;
1457 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1458 ret = sienna_cichlid_set_peak_performance_level(smu);
1459 break;
1460 case AMD_DPM_FORCED_LEVEL_MANUAL:
1461 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1462 default:
1463 break;
1464 }
1465 return ret;
1466}
1467
b455159c
LG		 1468static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1469 struct smu_temperature_range *range)
1470{
1471 struct smu_table_context *table_context = &smu->smu_table;
1472 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1473
1474 if (!range || !powerplay_table)
1475 return -EINVAL;
1476
1477 range->max = powerplay_table->software_shutdown_temp *
1478 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1479
1480 return 0;
1481}
1482
1483static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1484 bool disable_memory_clock_switch)
1485{
1486 int ret = 0;
1487 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1488 (struct smu_11_0_max_sustainable_clocks *)
1489 smu->smu_table.max_sustainable_clocks;
1490 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1491 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1492
1493 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1494 return 0;
1495
1496 if(disable_memory_clock_switch)
1497 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1498 else
1499 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1500
1501 if(!ret)
1502 smu->disable_uclk_switch = disable_memory_clock_switch;
1503
1504 return ret;
1505}
1506
3059ec1c
LG		 1507static uint32_t sienna_cichlid_get_pptable_power_limit(struct smu_context *smu)
1508{
1509 PPTable_t *pptable = smu->smu_table.driver_pptable;
1510 return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1511}
1512
b455159c
LG		 1513static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1514 uint32_t *limit,
1515 bool cap)
1516{
1517 PPTable_t *pptable = smu->smu_table.driver_pptable;
1518 uint32_t asic_default_power_limit = 0;
1519 int ret = 0;
1520 int power_src;
1521
1522 if (!smu->power_limit) {
1523 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1524 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1525 if (power_src < 0)
1526 return -EINVAL;
1527
1528 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1529 power_src << 16, &asic_default_power_limit);
1530 if (ret) {
1531 pr_err("[%s] get PPT limit failed!", __func__);
1532 return ret;
1533 }
1534 } else {
1535 /* the last hope to figure out the ppt limit */
1536 if (!pptable) {
1537 pr_err("Cannot get PPT limit due to pptable missing!");
1538 return -EINVAL;
1539 }
1540 asic_default_power_limit =
1541 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1542 }
1543
1544 smu->power_limit = asic_default_power_limit;
1545 }
1546
1547 if (cap)
1548 *limit = smu_v11_0_get_max_power_limit(smu);
1549 else
1550 *limit = smu->power_limit;
1551
1552 return 0;
1553}
1554
08ccfe08
LG		 1555static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1556 uint32_t pcie_gen_cap,
1557 uint32_t pcie_width_cap)
1558{
1559 PPTable_t *pptable = smu->smu_table.driver_pptable;
1560 int ret, i;
1561 uint32_t smu_pcie_arg;
1562
1563 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1564 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1565
1566 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1567 smu_pcie_arg = (i << 16) |
1568 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1569 (pptable->PcieGenSpeed[i] << 8) :
1570 (pcie_gen_cap << 8)) |
1571 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1572 pptable->PcieLaneCount[i] :
1573 pcie_width_cap);
1574
1575 ret = smu_send_smc_msg_with_param(smu,
1576 SMU_MSG_OverridePcieParameters,
1577 smu_pcie_arg, NULL);
1578 if (ret)
1579 return ret;
1580
1581 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1582 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1583 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1584 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1585 }
1586
1587 return 0;
1588}
1589
b455159c
LG		 1590static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1591{
1592 struct smu_table_context *table_context = &smu->smu_table;
1593 PPTable_t *pptable = table_context->driver_pptable;
1594 int i;
1595
1596 pr_info("Dumped PPTable:\n");
1597
1598 pr_info("Version = 0x%08x\n", pptable->Version);
1599 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1600 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1601
1602 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1603 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1604 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1605 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1606 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1607 }
1608
1609 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1610 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1611 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1612 }
1613
1614 for (i = 0; i < TEMP_COUNT; i++) {
1615 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1616 }
1617
1618 pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1619 pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1620 pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1621 pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1622 pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1623
1624 pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1625 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1626 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1627 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1628 }
1629 pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1630 pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1631 pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1632 pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1633
1634 pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1635
1636 pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1637
1638 pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1639 pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1640 pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1641 pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1642
1643 pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1644 pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1645
1646 pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1647 pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1648 pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1649 pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1650
1651 pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1652 pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1653 pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1654 pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1655
1656 pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1657 pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1658
1659 pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1660 pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1661 pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1662 pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1663 pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1664 pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1665 pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1666 pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1667
1668 pr_info("[PPCLK_GFXCLK]\n"
1669 " .VoltageMode = 0x%02x\n"
1670 " .SnapToDiscrete = 0x%02x\n"
1671 " .NumDiscreteLevels = 0x%02x\n"
1672 " .padding = 0x%02x\n"
1673 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1674 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1675 " .SsFmin = 0x%04x\n"
1676 " .Padding_16 = 0x%04x\n",
1677 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1678 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1679 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1680 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1681 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1682 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1683 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1684 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1685 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1686 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1687 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1688
1689 pr_info("[PPCLK_SOCCLK]\n"
1690 " .VoltageMode = 0x%02x\n"
1691 " .SnapToDiscrete = 0x%02x\n"
1692 " .NumDiscreteLevels = 0x%02x\n"
1693 " .padding = 0x%02x\n"
1694 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1695 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1696 " .SsFmin = 0x%04x\n"
1697 " .Padding_16 = 0x%04x\n",
1698 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1699 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1700 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1701 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1702 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1703 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1704 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1705 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1706 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1707 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1708 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1709
1710 pr_info("[PPCLK_UCLK]\n"
1711 " .VoltageMode = 0x%02x\n"
1712 " .SnapToDiscrete = 0x%02x\n"
1713 " .NumDiscreteLevels = 0x%02x\n"
1714 " .padding = 0x%02x\n"
1715 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1716 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1717 " .SsFmin = 0x%04x\n"
1718 " .Padding_16 = 0x%04x\n",
1719 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1720 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1721 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1722 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1723 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1724 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1725 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1726 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1727 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1728 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1729 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1730
1731 pr_info("[PPCLK_FCLK]\n"
1732 " .VoltageMode = 0x%02x\n"
1733 " .SnapToDiscrete = 0x%02x\n"
1734 " .NumDiscreteLevels = 0x%02x\n"
1735 " .padding = 0x%02x\n"
1736 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1737 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1738 " .SsFmin = 0x%04x\n"
1739 " .Padding_16 = 0x%04x\n",
1740 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1741 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1742 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1743 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1744 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1745 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1746 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1747 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1748 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1749 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1750 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1751
1752 pr_info("[PPCLK_DCLK_0]\n"
1753 " .VoltageMode = 0x%02x\n"
1754 " .SnapToDiscrete = 0x%02x\n"
1755 " .NumDiscreteLevels = 0x%02x\n"
1756 " .padding = 0x%02x\n"
1757 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1758 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1759 " .SsFmin = 0x%04x\n"
1760 " .Padding_16 = 0x%04x\n",
1761 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1762 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1763 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1764 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1765 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1766 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1767 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1768 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1769 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1770 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1771 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1772
1773 pr_info("[PPCLK_VCLK_0]\n"
1774 " .VoltageMode = 0x%02x\n"
1775 " .SnapToDiscrete = 0x%02x\n"
1776 " .NumDiscreteLevels = 0x%02x\n"
1777 " .padding = 0x%02x\n"
1778 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1779 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1780 " .SsFmin = 0x%04x\n"
1781 " .Padding_16 = 0x%04x\n",
1782 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1783 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1784 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1785 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1786 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1787 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1788 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1789 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1790 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1791 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1792 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1793
1794 pr_info("[PPCLK_DCLK_1]\n"
1795 " .VoltageMode = 0x%02x\n"
1796 " .SnapToDiscrete = 0x%02x\n"
1797 " .NumDiscreteLevels = 0x%02x\n"
1798 " .padding = 0x%02x\n"
1799 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1800 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1801 " .SsFmin = 0x%04x\n"
1802 " .Padding_16 = 0x%04x\n",
1803 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1804 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1805 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1806 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1807 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1808 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1809 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1810 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1811 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1812 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1813 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1814
1815 pr_info("[PPCLK_VCLK_1]\n"
1816 " .VoltageMode = 0x%02x\n"
1817 " .SnapToDiscrete = 0x%02x\n"
1818 " .NumDiscreteLevels = 0x%02x\n"
1819 " .padding = 0x%02x\n"
1820 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1821 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1822 " .SsFmin = 0x%04x\n"
1823 " .Padding_16 = 0x%04x\n",
1824 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1825 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1826 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1827 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1828 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1829 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1830 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1831 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1832 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1833 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1834 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1835
1836 pr_info("FreqTableGfx\n");
1837 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1838 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1839
1840 pr_info("FreqTableVclk\n");
1841 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1842 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1843
1844 pr_info("FreqTableDclk\n");
1845 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1846 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1847
1848 pr_info("FreqTableSocclk\n");
1849 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1850 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1851
1852 pr_info("FreqTableUclk\n");
1853 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1854 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1855
1856 pr_info("FreqTableFclk\n");
1857 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1858 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1859
1860 pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
1861 pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
1862 pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
1863 pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
1864 pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
1865 pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
1866 pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
1867 pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
1868 pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
1869 pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
1870 pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1871 pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1872 pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1873 pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1874 pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1875 pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1876
1877 pr_info("DcModeMaxFreq\n");
1878 pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1879 pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1880 pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1881 pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1882 pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1883 pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1884 pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1885 pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1886
1887 pr_info("FreqTableUclkDiv\n");
1888 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1889 pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1890
1891 pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1892 pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1893
1894 pr_info("Mp0clkFreq\n");
1895 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1896 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1897
1898 pr_info("Mp0DpmVoltage\n");
1899 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1900 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1901
1902 pr_info("MemVddciVoltage\n");
1903 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1904 pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1905
1906 pr_info("MemMvddVoltage\n");
1907 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1908 pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1909
1910 pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1911 pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1912 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1913 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1914 pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1915
1916 pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1917
1918 pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1919 pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1920 pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1921 pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1922 pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1923 pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1924 pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1925 pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1926 pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1927 pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1928 pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1929
1930 pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1931 pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1932 pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1933 pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1934 pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1935 pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1936
1937 pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1938 pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1939 pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1940 pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1941 pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1942
1943 pr_info("FlopsPerByteTable\n");
1944 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1945 pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1946
1947 pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1948 pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1949 pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1950 pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1951
1952 pr_info("UclkDpmPstates\n");
1953 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1954 pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1955
1956 pr_info("UclkDpmSrcFreqRange\n");
1957 pr_info(" .Fmin = 0x%x\n",
1958 pptable->UclkDpmSrcFreqRange.Fmin);
1959 pr_info(" .Fmax = 0x%x\n",
1960 pptable->UclkDpmSrcFreqRange.Fmax);
1961 pr_info("UclkDpmTargFreqRange\n");
1962 pr_info(" .Fmin = 0x%x\n",
1963 pptable->UclkDpmTargFreqRange.Fmin);
1964 pr_info(" .Fmax = 0x%x\n",
1965 pptable->UclkDpmTargFreqRange.Fmax);
1966 pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1967 pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1968
1969 pr_info("PcieGenSpeed\n");
1970 for (i = 0; i < NUM_LINK_LEVELS; i++)
1971 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1972
1973 pr_info("PcieLaneCount\n");
1974 for (i = 0; i < NUM_LINK_LEVELS; i++)
1975 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1976
1977 pr_info("LclkFreq\n");
1978 for (i = 0; i < NUM_LINK_LEVELS; i++)
1979 pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1980
1981 pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1982 pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1983
1984 pr_info("FanGain\n");
1985 for (i = 0; i < TEMP_COUNT; i++)
1986 pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1987
1988 pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1989 pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1990 pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1991 pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1992 pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1993 pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1994 pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1995 pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1996 pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1997 pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1998 pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1999 pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2000
2001 pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2002 pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2003 pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2004 pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2005
2006 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2007 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2008 pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2009 pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2010
2011 pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2012 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2013 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2014 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2015 pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2016 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2017 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2018 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2019 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2020 pptable->dBtcGbGfxPll.a,
2021 pptable->dBtcGbGfxPll.b,
2022 pptable->dBtcGbGfxPll.c);
2023 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2024 pptable->dBtcGbGfxDfll.a,
2025 pptable->dBtcGbGfxDfll.b,
2026 pptable->dBtcGbGfxDfll.c);
2027 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2028 pptable->dBtcGbSoc.a,
2029 pptable->dBtcGbSoc.b,
2030 pptable->dBtcGbSoc.c);
2031 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2032 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2033 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2034 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2035 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2036 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2037
2038 pr_info("PiecewiseLinearDroopIntGfxDfll\n");
2039 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2040 pr_info(" Fset[%d] = 0x%x\n",
2041 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2042 pr_info(" Vdroop[%d] = 0x%x\n",
2043 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2044 }
2045
2046 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2047 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2048 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2049 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2050 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2051 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2052 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2053 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2054
2055 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2056 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2057
2058 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2059 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2060 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2061 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2062
2063 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2064 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2065 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2066 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2067
2068 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2069 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2070
2071 pr_info("XgmiDpmPstates\n");
2072 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2073 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2074 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2075 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2076
2077 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2078 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2079 pptable->ReservedEquation0.a,
2080 pptable->ReservedEquation0.b,
2081 pptable->ReservedEquation0.c);
2082 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2083 pptable->ReservedEquation1.a,
2084 pptable->ReservedEquation1.b,
2085 pptable->ReservedEquation1.c);
2086 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2087 pptable->ReservedEquation2.a,
2088 pptable->ReservedEquation2.b,
2089 pptable->ReservedEquation2.c);
2090 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2091 pptable->ReservedEquation3.a,
2092 pptable->ReservedEquation3.b,
2093 pptable->ReservedEquation3.c);
2094
2095 pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2096 pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2097 pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2098 pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2099 pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2100 pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2101 pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2102 pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2103 pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2104 pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2105 pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2106 pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2107 pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2108 pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2109 pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
2110
2111 pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2112 pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2113 pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2114 pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2115 pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2116 pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2117
2118 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2119 pr_info("I2cControllers[%d]:\n", i);
2120 pr_info(" .Enabled = 0x%x\n",
2121 pptable->I2cControllers[i].Enabled);
2122 pr_info(" .Speed = 0x%x\n",
2123 pptable->I2cControllers[i].Speed);
2124 pr_info(" .SlaveAddress = 0x%x\n",
2125 pptable->I2cControllers[i].SlaveAddress);
2126 pr_info(" .ControllerPort = 0x%x\n",
2127 pptable->I2cControllers[i].ControllerPort);
2128 pr_info(" .ControllerName = 0x%x\n",
2129 pptable->I2cControllers[i].ControllerName);
2130 pr_info(" .ThermalThrottler = 0x%x\n",
2131 pptable->I2cControllers[i].ThermalThrotter);
2132 pr_info(" .I2cProtocol = 0x%x\n",
2133 pptable->I2cControllers[i].I2cProtocol);
2134 pr_info(" .PaddingConfig = 0x%x\n",
2135 pptable->I2cControllers[i].PaddingConfig);
2136 }
2137
2138 pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
2139 pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
2140 pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2141 pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2142
2143 pr_info("Board Parameters:\n");
2144 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2145 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2146 pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2147 pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2148 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2149 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2150 pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2151 pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2152
2153 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2154 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
2155 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2156
2157 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2158 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
2159 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2160
2161 pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2162 pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2163 pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2164
2165 pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2166 pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2167 pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2168
2169 pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2170
2171 pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2172 pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2173 pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2174 pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2175 pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2176 pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2177 pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2178 pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2179 pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2180 pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2181 pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2182 pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2183 pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2184 pr_info("LedError = 0x%x\n", pptable->LedError);
2185 pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2186 pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2187
2188 pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2189 pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2190 pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2191
2192 pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2193 pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2194 pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2195
2196 pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2197 pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2198 pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2199
2200 pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2201 pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2202 pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2203
2204 pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2205 pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2206 pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2207 pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2208 pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2209
2210 pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2211 pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2212
2213 pr_info("XgmiLinkSpeed\n");
2214 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2215 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2216 pr_info("XgmiLinkWidth\n");
2217 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2218 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2219 pr_info("XgmiFclkFreq\n");
2220 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2221 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2222 pr_info("XgmiSocVoltage\n");
2223 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2224 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2225
2226 pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2227 pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2228 pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2229 pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2230
2231 pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2232 pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2233 pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2234 pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2235 pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2236 pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2237 pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2238 pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2239 pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2240 pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2241 pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2242 pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2243 pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2244 pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2245 pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2246
2247 pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2248 pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2249 pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2250 pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2251 pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2252 pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2253 pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2254 pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2255}
2256
2257static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2258 .tables_init = sienna_cichlid_tables_init,
2259 .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2260 .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2261 .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2262 .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2263 .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2264 .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2265 .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2266 .get_smu_table_index = sienna_cichlid_get_smu_table_index,
1d5ca713 2267 .get_smu_power_index = sienna_cichlid_get_pwr_src_index,
b455159c
LG		 2268 .get_workload_type = sienna_cichlid_get_workload_type,
2269 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2270 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2271 .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
6fb176a7 2272 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
b455159c
LG		 2273 .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2274 .print_clk_levels = sienna_cichlid_print_clk_levels,
2275 .force_clk_levels = sienna_cichlid_force_clk_levels,
2276 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2277 .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2278 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2279 .display_config_changed = sienna_cichlid_display_config_changed,
2280 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2281 .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2282 .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2283 .is_dpm_running = sienna_cichlid_is_dpm_running,
2284 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2285 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2286 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2287 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2288 .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2289 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2290 .read_sensor = sienna_cichlid_read_sensor,
2291 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
9ad9c8ac 2292 .set_performance_level = sienna_cichlid_set_performance_level,
b455159c
LG		 2293 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2294 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2295 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2296 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2297 .dump_pptable = sienna_cichlid_dump_pptable,
2298 .init_microcode = smu_v11_0_init_microcode,
2299 .load_microcode = smu_v11_0_load_microcode,
2300 .init_smc_tables = smu_v11_0_init_smc_tables,
2301 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2302 .init_power = smu_v11_0_init_power,
2303 .fini_power = smu_v11_0_fini_power,
2304 .check_fw_status = smu_v11_0_check_fw_status,
2305 .setup_pptable = smu_v11_0_setup_pptable,
2306 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2307 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2308 .check_pptable = smu_v11_0_check_pptable,
2309 .parse_pptable = smu_v11_0_parse_pptable,
2310 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2311 .check_fw_version = smu_v11_0_check_fw_version,
2312 .write_pptable = smu_v11_0_write_pptable,
2313 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2314 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2315 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2316 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2317 .system_features_control = smu_v11_0_system_features_control,
2318 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2319 .init_display_count = smu_v11_0_init_display_count,
2320 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2321 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2322 .notify_display_change = smu_v11_0_notify_display_change,
2323 .set_power_limit = smu_v11_0_set_power_limit,
2324 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2325 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2326 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2327 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2328 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2329 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2330 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2331 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2332 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2333 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2334 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2335 .gfx_off_control = smu_v11_0_gfx_off_control,
2336 .register_irq_handler = smu_v11_0_register_irq_handler,
2337 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2338 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2339 .baco_is_support= smu_v11_0_baco_is_support,
2340 .baco_get_state = smu_v11_0_baco_get_state,
2341 .baco_set_state = smu_v11_0_baco_set_state,
2342 .baco_enter = smu_v11_0_baco_enter,
2343 .baco_exit = smu_v11_0_baco_exit,
2344 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2345 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2346 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
3059ec1c 2347 .get_pptable_power_limit = sienna_cichlid_get_pptable_power_limit,
b455159c
LG		 2348};
2349
2350void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2351{
2352 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2353}
Linux 6.x block layer and io_uring tree(s)