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b455159c LG |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
b455159c LG |
24 | #include <linux/firmware.h> |
25 | #include <linux/pci.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_smu.h" | |
28 | #include "smu_internal.h" | |
29 | #include "atomfirmware.h" | |
30 | #include "amdgpu_atomfirmware.h" | |
31 | #include "smu_v11_0.h" | |
32 | #include "smu11_driver_if_sienna_cichlid.h" | |
33 | #include "soc15_common.h" | |
34 | #include "atom.h" | |
35 | #include "sienna_cichlid_ppt.h" | |
e05acd78 | 36 | #include "smu_v11_0_7_pptable.h" |
b455159c | 37 | #include "smu_v11_0_7_ppsmc.h" |
40d3b8db | 38 | #include "nbio/nbio_2_3_offset.h" |
b7d25b5f | 39 | #include "nbio/nbio_2_3_sh_mask.h" |
e05acd78 LG |
40 | #include "thm/thm_11_0_2_offset.h" |
41 | #include "thm/thm_11_0_2_sh_mask.h" | |
40d3b8db | 42 | |
b455159c LG |
43 | #include "asic_reg/mp/mp_11_0_sh_mask.h" |
44 | ||
55084d7f EQ |
45 | /* |
46 | * DO NOT use these for err/warn/info/debug messages. | |
47 | * Use dev_err, dev_warn, dev_info and dev_dbg instead. | |
48 | * They are more MGPU friendly. | |
49 | */ | |
50 | #undef pr_err | |
51 | #undef pr_warn | |
52 | #undef pr_info | |
53 | #undef pr_debug | |
54 | ||
b455159c LG |
55 | #define FEATURE_MASK(feature) (1ULL << feature) |
56 | #define SMC_DPM_FEATURE ( \ | |
57 | FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ | |
fea905d4 | 58 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ |
65297d50 | 59 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ |
5cb74353 | 60 | FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ |
4cd4f45b | 61 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ |
5f338f70 LG |
62 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ |
63 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) | |
b455159c LG |
64 | |
65 | #define MSG_MAP(msg, index) \ | |
66 | [SMU_MSG_##msg] = {1, (index)} | |
67 | ||
68 | static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { | |
69 | MSG_MAP(TestMessage, PPSMC_MSG_TestMessage), | |
70 | MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion), | |
71 | MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion), | |
72 | MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow), | |
73 | MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh), | |
74 | MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures), | |
75 | MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures), | |
76 | MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow), | |
77 | MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh), | |
78 | MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow), | |
79 | MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh), | |
80 | MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow), | |
81 | MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh), | |
82 | MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask), | |
83 | MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit), | |
84 | MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh), | |
85 | MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow), | |
86 | MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh), | |
87 | MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow), | |
88 | MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram), | |
89 | MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu), | |
90 | MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable), | |
91 | MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco), | |
92 | MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq), | |
93 | MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq), | |
94 | MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq), | |
95 | MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq), | |
96 | MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq), | |
97 | MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq), | |
98 | MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex), | |
99 | MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode), | |
100 | MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh), | |
101 | MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow), | |
102 | MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters), | |
103 | MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt), | |
104 | MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource), | |
105 | MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch), | |
106 | MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps), | |
107 | MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload), | |
108 | MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff), | |
109 | MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff), | |
110 | MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit), | |
111 | MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq), | |
112 | MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco), | |
113 | MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn), | |
114 | MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn), | |
115 | MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg), | |
116 | MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg), | |
117 | MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME), | |
3fc006f5 | 118 | MSG_MAP(ArmD3, PPSMC_MSG_ArmD3), |
b455159c LG |
119 | }; |
120 | ||
121 | static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { | |
122 | CLK_MAP(GFXCLK, PPCLK_GFXCLK), | |
123 | CLK_MAP(SCLK, PPCLK_GFXCLK), | |
124 | CLK_MAP(SOCCLK, PPCLK_SOCCLK), | |
125 | CLK_MAP(FCLK, PPCLK_FCLK), | |
126 | CLK_MAP(UCLK, PPCLK_UCLK), | |
127 | CLK_MAP(MCLK, PPCLK_UCLK), | |
128 | CLK_MAP(DCLK, PPCLK_DCLK_0), | |
129 | CLK_MAP(DCLK1, PPCLK_DCLK_0), | |
130 | CLK_MAP(VCLK, PPCLK_VCLK_1), | |
131 | CLK_MAP(VCLK1, PPCLK_VCLK_1), | |
132 | CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), | |
133 | CLK_MAP(DISPCLK, PPCLK_DISPCLK), | |
134 | CLK_MAP(PIXCLK, PPCLK_PIXCLK), | |
135 | CLK_MAP(PHYCLK, PPCLK_PHYCLK), | |
136 | }; | |
137 | ||
138 | static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { | |
139 | FEA_MAP(DPM_PREFETCHER), | |
140 | FEA_MAP(DPM_GFXCLK), | |
31cb0dd9 | 141 | FEA_MAP(DPM_GFX_GPO), |
b455159c LG |
142 | FEA_MAP(DPM_UCLK), |
143 | FEA_MAP(DPM_SOCCLK), | |
144 | FEA_MAP(DPM_MP0CLK), | |
145 | FEA_MAP(DPM_LINK), | |
146 | FEA_MAP(DPM_DCEFCLK), | |
147 | FEA_MAP(MEM_VDDCI_SCALING), | |
148 | FEA_MAP(MEM_MVDD_SCALING), | |
149 | FEA_MAP(DS_GFXCLK), | |
150 | FEA_MAP(DS_SOCCLK), | |
151 | FEA_MAP(DS_LCLK), | |
152 | FEA_MAP(DS_DCEFCLK), | |
153 | FEA_MAP(DS_UCLK), | |
154 | FEA_MAP(GFX_ULV), | |
155 | FEA_MAP(FW_DSTATE), | |
156 | FEA_MAP(GFXOFF), | |
157 | FEA_MAP(BACO), | |
6fb176a7 | 158 | FEA_MAP(MM_DPM_PG), |
b455159c LG |
159 | FEA_MAP(RSMU_SMN_CG), |
160 | FEA_MAP(PPT), | |
161 | FEA_MAP(TDC), | |
162 | FEA_MAP(APCC_PLUS), | |
163 | FEA_MAP(GTHR), | |
164 | FEA_MAP(ACDC), | |
165 | FEA_MAP(VR0HOT), | |
166 | FEA_MAP(VR1HOT), | |
167 | FEA_MAP(FW_CTF), | |
168 | FEA_MAP(FAN_CONTROL), | |
169 | FEA_MAP(THERMAL), | |
170 | FEA_MAP(GFX_DCS), | |
171 | FEA_MAP(RM), | |
172 | FEA_MAP(LED_DISPLAY), | |
173 | FEA_MAP(GFX_SS), | |
174 | FEA_MAP(OUT_OF_BAND_MONITOR), | |
175 | FEA_MAP(TEMP_DEPENDENT_VMIN), | |
176 | FEA_MAP(MMHUB_PG), | |
177 | FEA_MAP(ATHUB_PG), | |
cf06331f | 178 | FEA_MAP(APCC_DFLL), |
b455159c LG |
179 | }; |
180 | ||
181 | static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { | |
182 | TAB_MAP(PPTABLE), | |
183 | TAB_MAP(WATERMARKS), | |
184 | TAB_MAP(AVFS_PSM_DEBUG), | |
185 | TAB_MAP(AVFS_FUSE_OVERRIDE), | |
186 | TAB_MAP(PMSTATUSLOG), | |
187 | TAB_MAP(SMU_METRICS), | |
188 | TAB_MAP(DRIVER_SMU_CONFIG), | |
189 | TAB_MAP(ACTIVITY_MONITOR_COEFF), | |
190 | TAB_MAP(OVERDRIVE), | |
191 | TAB_MAP(I2C_COMMANDS), | |
192 | TAB_MAP(PACE), | |
193 | }; | |
194 | ||
1d5ca713 LG |
195 | static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { |
196 | PWR_MAP(AC), | |
197 | PWR_MAP(DC), | |
198 | }; | |
199 | ||
b455159c LG |
200 | static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { |
201 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), | |
202 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), | |
203 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), | |
204 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), | |
205 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), | |
206 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), | |
207 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), | |
208 | }; | |
209 | ||
210 | static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index) | |
211 | { | |
212 | struct smu_11_0_cmn2aisc_mapping mapping; | |
213 | ||
214 | if (index >= SMU_MSG_MAX_COUNT) | |
215 | return -EINVAL; | |
216 | ||
217 | mapping = sienna_cichlid_message_map[index]; | |
218 | if (!(mapping.valid_mapping)) { | |
219 | return -EINVAL; | |
220 | } | |
221 | ||
222 | return mapping.map_to; | |
223 | } | |
224 | ||
225 | static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index) | |
226 | { | |
227 | struct smu_11_0_cmn2aisc_mapping mapping; | |
228 | ||
229 | if (index >= SMU_CLK_COUNT) | |
230 | return -EINVAL; | |
231 | ||
232 | mapping = sienna_cichlid_clk_map[index]; | |
233 | if (!(mapping.valid_mapping)) { | |
234 | return -EINVAL; | |
235 | } | |
236 | ||
237 | return mapping.map_to; | |
238 | } | |
239 | ||
240 | static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index) | |
241 | { | |
242 | struct smu_11_0_cmn2aisc_mapping mapping; | |
243 | ||
244 | if (index >= SMU_FEATURE_COUNT) | |
245 | return -EINVAL; | |
246 | ||
247 | mapping = sienna_cichlid_feature_mask_map[index]; | |
248 | if (!(mapping.valid_mapping)) { | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | return mapping.map_to; | |
253 | } | |
254 | ||
255 | static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index) | |
256 | { | |
257 | struct smu_11_0_cmn2aisc_mapping mapping; | |
258 | ||
259 | if (index >= SMU_TABLE_COUNT) | |
260 | return -EINVAL; | |
261 | ||
262 | mapping = sienna_cichlid_table_map[index]; | |
263 | if (!(mapping.valid_mapping)) { | |
264 | return -EINVAL; | |
265 | } | |
266 | ||
267 | return mapping.map_to; | |
268 | } | |
269 | ||
1d5ca713 LG |
270 | static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index) |
271 | { | |
272 | struct smu_11_0_cmn2aisc_mapping mapping; | |
273 | ||
274 | if (index >= SMU_POWER_SOURCE_COUNT) | |
275 | return -EINVAL; | |
276 | ||
277 | mapping = sienna_cichlid_pwr_src_map[index]; | |
278 | if (!(mapping.valid_mapping)) { | |
279 | return -EINVAL; | |
280 | } | |
281 | ||
282 | return mapping.map_to; | |
283 | } | |
284 | ||
b455159c LG |
285 | static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile) |
286 | { | |
287 | struct smu_11_0_cmn2aisc_mapping mapping; | |
288 | ||
289 | if (profile > PP_SMC_POWER_PROFILE_CUSTOM) | |
290 | return -EINVAL; | |
291 | ||
292 | mapping = sienna_cichlid_workload_map[profile]; | |
293 | if (!(mapping.valid_mapping)) { | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | return mapping.map_to; | |
298 | } | |
299 | ||
300 | static int | |
301 | sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, | |
302 | uint32_t *feature_mask, uint32_t num) | |
303 | { | |
fea905d4 LG |
304 | struct amdgpu_device *adev = smu->adev; |
305 | ||
b455159c LG |
306 | if (num > 2) |
307 | return -EINVAL; | |
308 | ||
309 | memset(feature_mask, 0, sizeof(uint32_t) * num); | |
310 | ||
4cd4f45b | 311 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) |
15dbe18f | 312 | | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) |
094cdf15 | 313 | | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) |
5f338f70 | 314 | | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) |
86a9eb3f | 315 | | FEATURE_MASK(FEATURE_DS_FCLK_BIT) |
80c36f86 | 316 | | FEATURE_MASK(FEATURE_DS_UCLK_BIT) |
9aa60213 LG |
317 | | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) |
318 | | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) | |
d28f4aa1 | 319 | | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) |
20d71dcc | 320 | | FEATURE_MASK(FEATURE_GFX_SS_BIT) |
d0d71970 | 321 | | FEATURE_MASK(FEATURE_VR0HOT_BIT) |
886c8bc6 LG |
322 | | FEATURE_MASK(FEATURE_PPT_BIT) |
323 | | FEATURE_MASK(FEATURE_TDC_BIT) | |
3fc006f5 | 324 | | FEATURE_MASK(FEATURE_BACO_BIT) |
cf06331f | 325 | | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) |
35ed946c | 326 | | FEATURE_MASK(FEATURE_FW_CTF_BIT) |
1c58d429 | 327 | | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) |
b971df70 LG |
328 | | FEATURE_MASK(FEATURE_THERMAL_BIT) |
329 | | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); | |
fea905d4 | 330 | |
c96721eb | 331 | if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { |
fea905d4 | 332 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); |
c96721eb KF |
333 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); |
334 | } | |
fea905d4 | 335 | |
65297d50 | 336 | if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) |
fc17cd3f LG |
337 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) |
338 | | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) | |
339 | | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); | |
65297d50 | 340 | |
5cb74353 LG |
341 | if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) |
342 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); | |
343 | ||
5f338f70 LG |
344 | if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) |
345 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); | |
346 | ||
fea905d4 LG |
347 | if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) |
348 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); | |
b455159c | 349 | |
62c1ea6b LG |
350 | if (adev->pm.pp_feature & PP_ULV_MASK) |
351 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); | |
352 | ||
02bb391d LG |
353 | if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) |
354 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); | |
355 | ||
e0da123a LG |
356 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) |
357 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); | |
358 | ||
b794616d KF |
359 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) |
360 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); | |
361 | ||
846938c2 KF |
362 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) |
363 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); | |
364 | ||
6fb176a7 LG |
365 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || |
366 | smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) | |
367 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); | |
368 | ||
b455159c LG |
369 | return 0; |
370 | } | |
371 | ||
372 | static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) | |
373 | { | |
4a13b4ce | 374 | struct smu_table_context *table_context = &smu->smu_table; |
e05acd78 | 375 | struct smu_11_0_7_powerplay_table *powerplay_table = |
4a13b4ce EQ |
376 | table_context->power_play_table; |
377 | struct smu_baco_context *smu_baco = &smu->smu_baco; | |
378 | ||
379 | mutex_lock(&smu_baco->mutex); | |
e05acd78 LG |
380 | if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || |
381 | powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) | |
4a13b4ce EQ |
382 | smu_baco->platform_support = true; |
383 | mutex_unlock(&smu_baco->mutex); | |
384 | ||
385 | table_context->thermal_controller_type = | |
386 | powerplay_table->thermal_controller_type; | |
387 | ||
b455159c LG |
388 | return 0; |
389 | } | |
390 | ||
391 | static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) | |
392 | { | |
dccc7c21 LG |
393 | struct smu_table_context *table_context = &smu->smu_table; |
394 | PPTable_t *smc_pptable = table_context->driver_pptable; | |
395 | struct atom_smc_dpm_info_v4_9 *smc_dpm_table; | |
396 | int index, ret; | |
dccc7c21 LG |
397 | |
398 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, | |
399 | smc_dpm_info); | |
400 | ||
401 | ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL, | |
402 | (uint8_t **)&smc_dpm_table); | |
403 | if (ret) | |
404 | return ret; | |
405 | ||
406 | memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, | |
969c8d16 LG |
407 | sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); |
408 | ||
b455159c LG |
409 | return 0; |
410 | } | |
411 | ||
412 | static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) | |
413 | { | |
b455159c | 414 | struct smu_table_context *table_context = &smu->smu_table; |
e05acd78 | 415 | struct smu_11_0_7_powerplay_table *powerplay_table = |
4a13b4ce | 416 | table_context->power_play_table; |
b455159c LG |
417 | |
418 | memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, | |
419 | sizeof(PPTable_t)); | |
420 | ||
4a13b4ce EQ |
421 | return 0; |
422 | } | |
b455159c | 423 | |
4a13b4ce EQ |
424 | static int sienna_cichlid_setup_pptable(struct smu_context *smu) |
425 | { | |
426 | int ret = 0; | |
b455159c | 427 | |
4a13b4ce EQ |
428 | ret = smu_v11_0_setup_pptable(smu); |
429 | if (ret) | |
430 | return ret; | |
431 | ||
432 | ret = sienna_cichlid_store_powerplay_table(smu); | |
433 | if (ret) | |
434 | return ret; | |
435 | ||
436 | ret = sienna_cichlid_append_powerplay_table(smu); | |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | ret = sienna_cichlid_check_powerplay_table(smu); | |
441 | if (ret) | |
442 | return ret; | |
443 | ||
444 | return ret; | |
b455159c LG |
445 | } |
446 | ||
447 | static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables) | |
448 | { | |
449 | struct smu_table_context *smu_table = &smu->smu_table; | |
450 | ||
451 | SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), | |
452 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
453 | SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), | |
454 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
455 | SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), | |
456 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
457 | SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), | |
458 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
459 | SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, | |
460 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | |
461 | SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, | |
462 | sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, | |
463 | AMDGPU_GEM_DOMAIN_VRAM); | |
464 | ||
465 | smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); | |
466 | if (!smu_table->metrics_table) | |
467 | return -ENOMEM; | |
468 | smu_table->metrics_time = 0; | |
469 | ||
40d3b8db LG |
470 | smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); |
471 | if (!smu_table->watermarks_table) | |
472 | return -ENOMEM; | |
473 | ||
b455159c LG |
474 | return 0; |
475 | } | |
476 | ||
8c686254 EQ |
477 | static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, |
478 | MetricsMember_t member, | |
479 | uint32_t *value) | |
b455159c LG |
480 | { |
481 | struct smu_table_context *smu_table= &smu->smu_table; | |
8c686254 | 482 | SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; |
b455159c LG |
483 | int ret = 0; |
484 | ||
485 | mutex_lock(&smu->metrics_lock); | |
8c686254 | 486 | if (!smu_table->metrics_time || |
df06583d | 487 | time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) { |
8c686254 EQ |
488 | ret = smu_update_table(smu, |
489 | SMU_TABLE_SMU_METRICS, | |
490 | 0, | |
491 | smu_table->metrics_table, | |
492 | false); | |
b455159c | 493 | if (ret) { |
d9811cfc | 494 | dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n"); |
b455159c LG |
495 | mutex_unlock(&smu->metrics_lock); |
496 | return ret; | |
497 | } | |
498 | smu_table->metrics_time = jiffies; | |
499 | } | |
500 | ||
8c686254 EQ |
501 | switch (member) { |
502 | case METRICS_CURR_GFXCLK: | |
503 | *value = metrics->CurrClock[PPCLK_GFXCLK]; | |
504 | break; | |
505 | case METRICS_CURR_SOCCLK: | |
506 | *value = metrics->CurrClock[PPCLK_SOCCLK]; | |
507 | break; | |
508 | case METRICS_CURR_UCLK: | |
509 | *value = metrics->CurrClock[PPCLK_UCLK]; | |
510 | break; | |
511 | case METRICS_CURR_VCLK: | |
512 | *value = metrics->CurrClock[PPCLK_VCLK_0]; | |
513 | break; | |
514 | case METRICS_CURR_VCLK1: | |
515 | *value = metrics->CurrClock[PPCLK_VCLK_1]; | |
516 | break; | |
517 | case METRICS_CURR_DCLK: | |
518 | *value = metrics->CurrClock[PPCLK_DCLK_0]; | |
519 | break; | |
520 | case METRICS_CURR_DCLK1: | |
521 | *value = metrics->CurrClock[PPCLK_DCLK_1]; | |
522 | break; | |
9d09fa6f ND |
523 | case METRICS_CURR_DCEFCLK: |
524 | *value = metrics->CurrClock[PPCLK_DCEFCLK]; | |
525 | break; | |
8c686254 EQ |
526 | case METRICS_AVERAGE_GFXCLK: |
527 | *value = metrics->AverageGfxclkFrequency; | |
528 | break; | |
529 | case METRICS_AVERAGE_FCLK: | |
530 | *value = metrics->AverageFclkFrequency; | |
531 | break; | |
532 | case METRICS_AVERAGE_UCLK: | |
533 | *value = metrics->AverageUclkFrequency; | |
534 | break; | |
535 | case METRICS_AVERAGE_GFXACTIVITY: | |
536 | *value = metrics->AverageGfxActivity; | |
537 | break; | |
538 | case METRICS_AVERAGE_MEMACTIVITY: | |
539 | *value = metrics->AverageUclkActivity; | |
540 | break; | |
541 | case METRICS_AVERAGE_SOCKETPOWER: | |
542 | *value = metrics->AverageSocketPower << 8; | |
543 | break; | |
544 | case METRICS_TEMPERATURE_EDGE: | |
545 | *value = metrics->TemperatureEdge * | |
546 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
547 | break; | |
548 | case METRICS_TEMPERATURE_HOTSPOT: | |
549 | *value = metrics->TemperatureHotspot * | |
550 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
551 | break; | |
552 | case METRICS_TEMPERATURE_MEM: | |
553 | *value = metrics->TemperatureMem * | |
554 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
555 | break; | |
556 | case METRICS_TEMPERATURE_VRGFX: | |
557 | *value = metrics->TemperatureVrGfx * | |
558 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
559 | break; | |
560 | case METRICS_TEMPERATURE_VRSOC: | |
561 | *value = metrics->TemperatureVrSoc * | |
562 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
563 | break; | |
564 | case METRICS_THROTTLER_STATUS: | |
565 | *value = metrics->ThrottlerStatus; | |
566 | break; | |
567 | case METRICS_CURR_FANSPEED: | |
568 | *value = metrics->CurrFanSpeed; | |
569 | break; | |
570 | default: | |
571 | *value = UINT_MAX; | |
572 | break; | |
573 | } | |
574 | ||
b455159c LG |
575 | mutex_unlock(&smu->metrics_lock); |
576 | ||
577 | return ret; | |
8c686254 | 578 | |
b455159c LG |
579 | } |
580 | ||
581 | static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) | |
582 | { | |
583 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
584 | ||
585 | if (smu_dpm->dpm_context) | |
586 | return -EINVAL; | |
587 | ||
588 | smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), | |
589 | GFP_KERNEL); | |
590 | if (!smu_dpm->dpm_context) | |
591 | return -ENOMEM; | |
592 | ||
593 | smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) | |
599 | { | |
600 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
601 | struct smu_table_context *table_context = &smu->smu_table; | |
602 | struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; | |
603 | PPTable_t *driver_ppt = NULL; | |
08ccfe08 | 604 | int i; |
b455159c LG |
605 | |
606 | driver_ppt = table_context->driver_pptable; | |
607 | ||
608 | dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0]; | |
609 | dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1]; | |
610 | ||
611 | dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0]; | |
612 | dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1]; | |
613 | ||
614 | dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0]; | |
615 | dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1]; | |
616 | ||
617 | dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0]; | |
618 | dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1]; | |
619 | ||
620 | dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0]; | |
621 | dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1]; | |
622 | ||
623 | dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0]; | |
624 | dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1]; | |
625 | ||
626 | dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0]; | |
627 | dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1]; | |
628 | ||
629 | dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0]; | |
630 | dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1]; | |
631 | ||
632 | dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0]; | |
633 | dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1]; | |
634 | ||
08ccfe08 LG |
635 | for (i = 0; i < MAX_PCIE_CONF; i++) { |
636 | dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i]; | |
637 | dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i]; | |
638 | } | |
639 | ||
b455159c LG |
640 | return 0; |
641 | } | |
642 | ||
f6b4b4a1 | 643 | static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) |
b455159c LG |
644 | { |
645 | struct smu_power_context *smu_power = &smu->smu_power; | |
646 | struct smu_power_gate *power_gate = &smu_power->power_gate; | |
647 | int ret = 0; | |
648 | ||
649 | if (enable) { | |
650 | /* vcn dpm on is a prerequisite for vcn power gate messages */ | |
6fb176a7 LG |
651 | if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
652 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); | |
653 | if (ret) | |
654 | return ret; | |
655 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL); | |
b455159c LG |
656 | if (ret) |
657 | return ret; | |
658 | } | |
659 | power_gate->vcn_gated = false; | |
660 | } else { | |
6fb176a7 LG |
661 | if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { |
662 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); | |
663 | if (ret) | |
664 | return ret; | |
665 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL); | |
b455159c LG |
666 | if (ret) |
667 | return ret; | |
668 | } | |
669 | power_gate->vcn_gated = true; | |
670 | } | |
671 | ||
672 | return ret; | |
673 | } | |
674 | ||
6fb176a7 LG |
675 | static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) |
676 | { | |
677 | struct smu_power_context *smu_power = &smu->smu_power; | |
678 | struct smu_power_gate *power_gate = &smu_power->power_gate; | |
679 | int ret = 0; | |
680 | ||
681 | if (enable) { | |
682 | if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { | |
683 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); | |
684 | if (ret) | |
685 | return ret; | |
6fb176a7 LG |
686 | } |
687 | power_gate->jpeg_gated = false; | |
688 | } else { | |
689 | if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { | |
690 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); | |
691 | if (ret) | |
692 | return ret; | |
6fb176a7 LG |
693 | } |
694 | power_gate->jpeg_gated = true; | |
695 | } | |
696 | ||
697 | return ret; | |
698 | } | |
699 | ||
b455159c LG |
700 | static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, |
701 | enum smu_clk_type clk_type, | |
702 | uint32_t *value) | |
703 | { | |
8c686254 EQ |
704 | MetricsMember_t member_type; |
705 | int clk_id = 0; | |
b455159c LG |
706 | |
707 | clk_id = smu_clk_get_index(smu, clk_type); | |
708 | if (clk_id < 0) | |
709 | return clk_id; | |
710 | ||
8c686254 EQ |
711 | switch (clk_id) { |
712 | case PPCLK_GFXCLK: | |
713 | member_type = METRICS_CURR_GFXCLK; | |
714 | break; | |
715 | case PPCLK_UCLK: | |
716 | member_type = METRICS_CURR_UCLK; | |
717 | break; | |
718 | case PPCLK_SOCCLK: | |
719 | member_type = METRICS_CURR_SOCCLK; | |
720 | break; | |
721 | case PPCLK_FCLK: | |
722 | member_type = METRICS_CURR_FCLK; | |
723 | break; | |
724 | case PPCLK_VCLK_0: | |
725 | member_type = METRICS_CURR_VCLK; | |
726 | break; | |
727 | case PPCLK_VCLK_1: | |
728 | member_type = METRICS_CURR_VCLK1; | |
729 | break; | |
730 | case PPCLK_DCLK_0: | |
731 | member_type = METRICS_CURR_DCLK; | |
732 | break; | |
733 | case PPCLK_DCLK_1: | |
734 | member_type = METRICS_CURR_DCLK1; | |
735 | break; | |
736 | case PPCLK_DCEFCLK: | |
737 | member_type = METRICS_CURR_DCEFCLK; | |
738 | break; | |
739 | default: | |
740 | return -EINVAL; | |
741 | } | |
742 | ||
743 | return sienna_cichlid_get_smu_metrics_data(smu, | |
744 | member_type, | |
745 | value); | |
b455159c | 746 | |
b455159c LG |
747 | } |
748 | ||
749 | static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) | |
750 | { | |
751 | PPTable_t *pptable = smu->smu_table.driver_pptable; | |
752 | DpmDescriptor_t *dpm_desc = NULL; | |
753 | uint32_t clk_index = 0; | |
754 | ||
755 | clk_index = smu_clk_get_index(smu, clk_type); | |
756 | dpm_desc = &pptable->DpmDescriptor[clk_index]; | |
757 | ||
758 | /* 0 - Fine grained DPM, 1 - Discrete DPM */ | |
759 | return dpm_desc->SnapToDiscrete == 0 ? true : false; | |
760 | } | |
761 | ||
762 | static int sienna_cichlid_print_clk_levels(struct smu_context *smu, | |
763 | enum smu_clk_type clk_type, char *buf) | |
764 | { | |
b7d25b5f LG |
765 | struct amdgpu_device *adev = smu->adev; |
766 | struct smu_table_context *table_context = &smu->smu_table; | |
767 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
768 | struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; | |
769 | PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; | |
b455159c LG |
770 | int i, size = 0, ret = 0; |
771 | uint32_t cur_value = 0, value = 0, count = 0; | |
772 | uint32_t freq_values[3] = {0}; | |
773 | uint32_t mark_index = 0; | |
b7d25b5f | 774 | uint32_t gen_speed, lane_width; |
b455159c LG |
775 | |
776 | switch (clk_type) { | |
777 | case SMU_GFXCLK: | |
778 | case SMU_SCLK: | |
779 | case SMU_SOCCLK: | |
780 | case SMU_MCLK: | |
781 | case SMU_UCLK: | |
782 | case SMU_FCLK: | |
783 | case SMU_DCEFCLK: | |
5e6dc8fe | 784 | ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); |
b455159c | 785 | if (ret) |
258d290c | 786 | goto print_clk_out; |
b455159c | 787 | |
ba818620 KF |
788 | /* no need to disable gfxoff when retrieving the current gfxclk */ |
789 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) | |
790 | amdgpu_gfx_off_ctrl(adev, false); | |
791 | ||
b455159c LG |
792 | ret = smu_get_dpm_level_count(smu, clk_type, &count); |
793 | if (ret) | |
258d290c | 794 | goto print_clk_out; |
b455159c LG |
795 | |
796 | if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { | |
797 | for (i = 0; i < count; i++) { | |
798 | ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); | |
799 | if (ret) | |
258d290c | 800 | goto print_clk_out; |
b455159c LG |
801 | |
802 | size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, | |
803 | cur_value == value ? "*" : ""); | |
804 | } | |
805 | } else { | |
806 | ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); | |
807 | if (ret) | |
258d290c | 808 | goto print_clk_out; |
b455159c LG |
809 | ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); |
810 | if (ret) | |
258d290c | 811 | goto print_clk_out; |
b455159c LG |
812 | |
813 | freq_values[1] = cur_value; | |
814 | mark_index = cur_value == freq_values[0] ? 0 : | |
815 | cur_value == freq_values[2] ? 2 : 1; | |
816 | if (mark_index != 1) | |
817 | freq_values[1] = (freq_values[0] + freq_values[2]) / 2; | |
818 | ||
819 | for (i = 0; i < 3; i++) { | |
820 | size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], | |
821 | i == mark_index ? "*" : ""); | |
822 | } | |
823 | ||
824 | } | |
825 | break; | |
b7d25b5f LG |
826 | case SMU_PCIE: |
827 | gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & | |
828 | PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) | |
829 | >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; | |
830 | lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & | |
831 | PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) | |
832 | >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; | |
833 | for (i = 0; i < NUM_LINK_LEVELS; i++) | |
834 | size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, | |
835 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : | |
836 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : | |
837 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : | |
838 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", | |
839 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : | |
840 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : | |
841 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : | |
842 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : | |
843 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : | |
844 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", | |
845 | pptable->LclkFreq[i], | |
846 | (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && | |
847 | (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? | |
848 | "*" : ""); | |
849 | break; | |
b455159c LG |
850 | default: |
851 | break; | |
852 | } | |
853 | ||
258d290c LG |
854 | print_clk_out: |
855 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) | |
856 | amdgpu_gfx_off_ctrl(adev, true); | |
857 | ||
b455159c LG |
858 | return size; |
859 | } | |
860 | ||
861 | static int sienna_cichlid_force_clk_levels(struct smu_context *smu, | |
862 | enum smu_clk_type clk_type, uint32_t mask) | |
863 | { | |
258d290c | 864 | struct amdgpu_device *adev = smu->adev; |
b455159c LG |
865 | int ret = 0, size = 0; |
866 | uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; | |
867 | ||
868 | soft_min_level = mask ? (ffs(mask) - 1) : 0; | |
869 | soft_max_level = mask ? (fls(mask) - 1) : 0; | |
870 | ||
258d290c LG |
871 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) |
872 | amdgpu_gfx_off_ctrl(adev, false); | |
873 | ||
b455159c LG |
874 | switch (clk_type) { |
875 | case SMU_GFXCLK: | |
876 | case SMU_SCLK: | |
877 | case SMU_SOCCLK: | |
878 | case SMU_MCLK: | |
879 | case SMU_UCLK: | |
880 | case SMU_DCEFCLK: | |
881 | case SMU_FCLK: | |
9ad9c8ac LG |
882 | /* There is only 2 levels for fine grained DPM */ |
883 | if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { | |
884 | soft_max_level = (soft_max_level >= 1 ? 1 : 0); | |
885 | soft_min_level = (soft_min_level >= 1 ? 1 : 0); | |
886 | } | |
887 | ||
b455159c LG |
888 | ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); |
889 | if (ret) | |
258d290c | 890 | goto forec_level_out; |
b455159c LG |
891 | |
892 | ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); | |
893 | if (ret) | |
258d290c | 894 | goto forec_level_out; |
b455159c LG |
895 | |
896 | ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false); | |
897 | if (ret) | |
258d290c | 898 | goto forec_level_out; |
b455159c LG |
899 | break; |
900 | default: | |
901 | break; | |
902 | } | |
903 | ||
258d290c LG |
904 | forec_level_out: |
905 | if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) | |
906 | amdgpu_gfx_off_ctrl(adev, true); | |
907 | ||
b455159c LG |
908 | return size; |
909 | } | |
910 | ||
911 | static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) | |
912 | { | |
913 | int ret = 0; | |
914 | uint32_t min_sclk_freq = 0, min_mclk_freq = 0; | |
915 | ||
916 | ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false); | |
917 | if (ret) | |
918 | return ret; | |
919 | ||
920 | smu->pstate_sclk = min_sclk_freq * 100; | |
921 | ||
922 | ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false); | |
923 | if (ret) | |
924 | return ret; | |
925 | ||
926 | smu->pstate_mclk = min_mclk_freq * 100; | |
927 | ||
928 | return ret; | |
929 | } | |
930 | ||
b455159c LG |
931 | static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) |
932 | { | |
933 | int ret = 0; | |
934 | uint32_t max_freq = 0; | |
935 | ||
936 | /* Sienna_Cichlid do not support to change display num currently */ | |
937 | return 0; | |
938 | #if 0 | |
939 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); | |
940 | if (ret) | |
941 | return ret; | |
942 | #endif | |
943 | ||
944 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { | |
945 | ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false); | |
946 | if (ret) | |
947 | return ret; | |
948 | ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq); | |
949 | if (ret) | |
950 | return ret; | |
951 | } | |
952 | ||
953 | return ret; | |
954 | } | |
955 | ||
956 | static int sienna_cichlid_display_config_changed(struct smu_context *smu) | |
957 | { | |
958 | int ret = 0; | |
959 | ||
b455159c LG |
960 | if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && |
961 | smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && | |
962 | smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { | |
b455159c LG |
963 | #if 0 |
964 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, | |
40d3b8db LG |
965 | smu->display_config->num_display, |
966 | NULL); | |
b455159c LG |
967 | #endif |
968 | if (ret) | |
969 | return ret; | |
970 | } | |
971 | ||
972 | return ret; | |
973 | } | |
974 | ||
975 | static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest) | |
976 | { | |
977 | int ret = 0, i = 0; | |
978 | uint32_t min_freq, max_freq, force_freq; | |
979 | enum smu_clk_type clk_type; | |
980 | ||
981 | enum smu_clk_type clks[] = { | |
982 | SMU_GFXCLK, | |
9af9fe5b LG |
983 | SMU_MCLK, |
984 | SMU_SOCCLK, | |
b455159c LG |
985 | }; |
986 | ||
987 | for (i = 0; i < ARRAY_SIZE(clks); i++) { | |
988 | clk_type = clks[i]; | |
989 | ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false); | |
990 | if (ret) | |
991 | return ret; | |
992 | ||
993 | force_freq = highest ? max_freq : min_freq; | |
994 | ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false); | |
995 | if (ret) | |
996 | return ret; | |
997 | } | |
998 | ||
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu) | |
1003 | { | |
1004 | int ret = 0, i = 0; | |
1005 | uint32_t min_freq, max_freq; | |
1006 | enum smu_clk_type clk_type; | |
1007 | ||
1008 | enum smu_clk_type clks[] = { | |
1009 | SMU_GFXCLK, | |
9af9fe5b LG |
1010 | SMU_MCLK, |
1011 | SMU_SOCCLK, | |
b455159c LG |
1012 | }; |
1013 | ||
1014 | for (i = 0; i < ARRAY_SIZE(clks); i++) { | |
1015 | clk_type = clks[i]; | |
1016 | ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false); | |
1017 | if (ret) | |
1018 | return ret; | |
1019 | ||
1020 | ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false); | |
1021 | if (ret) | |
1022 | return ret; | |
1023 | } | |
1024 | ||
1025 | return ret; | |
1026 | } | |
1027 | ||
1028 | static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value) | |
1029 | { | |
b455159c LG |
1030 | if (!value) |
1031 | return -EINVAL; | |
1032 | ||
8c686254 EQ |
1033 | return sienna_cichlid_get_smu_metrics_data(smu, |
1034 | METRICS_AVERAGE_SOCKETPOWER, | |
1035 | value); | |
b455159c LG |
1036 | } |
1037 | ||
1038 | static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu, | |
1039 | enum amd_pp_sensors sensor, | |
1040 | uint32_t *value) | |
1041 | { | |
1042 | int ret = 0; | |
b455159c LG |
1043 | |
1044 | if (!value) | |
1045 | return -EINVAL; | |
1046 | ||
b455159c LG |
1047 | switch (sensor) { |
1048 | case AMDGPU_PP_SENSOR_GPU_LOAD: | |
8c686254 EQ |
1049 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1050 | METRICS_AVERAGE_GFXACTIVITY, | |
1051 | value); | |
b455159c LG |
1052 | break; |
1053 | case AMDGPU_PP_SENSOR_MEM_LOAD: | |
8c686254 EQ |
1054 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1055 | METRICS_AVERAGE_MEMACTIVITY, | |
1056 | value); | |
b455159c LG |
1057 | break; |
1058 | default: | |
d9811cfc | 1059 | dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); |
b455159c LG |
1060 | return -EINVAL; |
1061 | } | |
1062 | ||
8c686254 | 1063 | return ret; |
b455159c LG |
1064 | } |
1065 | ||
1066 | static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) | |
1067 | { | |
1068 | int ret = 0; | |
1069 | uint32_t feature_mask[2]; | |
1070 | unsigned long feature_enabled; | |
1071 | ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); | |
1072 | feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | | |
1073 | ((uint64_t)feature_mask[1] << 32)); | |
1074 | return !!(feature_enabled & SMC_DPM_FEATURE); | |
1075 | } | |
1076 | ||
1077 | static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, | |
1078 | uint32_t *speed) | |
1079 | { | |
b455159c LG |
1080 | if (!speed) |
1081 | return -EINVAL; | |
1082 | ||
8c686254 EQ |
1083 | return sienna_cichlid_get_smu_metrics_data(smu, |
1084 | METRICS_CURR_FANSPEED, | |
1085 | speed); | |
b455159c LG |
1086 | } |
1087 | ||
1088 | static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu, | |
1089 | uint32_t *speed) | |
1090 | { | |
1091 | int ret = 0; | |
1092 | uint32_t percent = 0; | |
1093 | uint32_t current_rpm; | |
1094 | PPTable_t *pptable = smu->smu_table.driver_pptable; | |
1095 | ||
1096 | ret = sienna_cichlid_get_fan_speed_rpm(smu, ¤t_rpm); | |
1097 | if (ret) | |
1098 | return ret; | |
1099 | ||
1100 | percent = current_rpm * 100 / pptable->FanMaximumRpm; | |
1101 | *speed = percent > 100 ? 100 : percent; | |
1102 | ||
1103 | return ret; | |
1104 | } | |
1105 | ||
1106 | static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) | |
1107 | { | |
1108 | DpmActivityMonitorCoeffInt_t activity_monitor; | |
1109 | uint32_t i, size = 0; | |
1110 | int16_t workload_type = 0; | |
1111 | static const char *profile_name[] = { | |
1112 | "BOOTUP_DEFAULT", | |
1113 | "3D_FULL_SCREEN", | |
1114 | "POWER_SAVING", | |
1115 | "VIDEO", | |
1116 | "VR", | |
1117 | "COMPUTE", | |
1118 | "CUSTOM"}; | |
1119 | static const char *title[] = { | |
1120 | "PROFILE_INDEX(NAME)", | |
1121 | "CLOCK_TYPE(NAME)", | |
1122 | "FPS", | |
1123 | "MinFreqType", | |
1124 | "MinActiveFreqType", | |
1125 | "MinActiveFreq", | |
1126 | "BoosterFreqType", | |
1127 | "BoosterFreq", | |
1128 | "PD_Data_limit_c", | |
1129 | "PD_Data_error_coeff", | |
1130 | "PD_Data_error_rate_coeff"}; | |
1131 | int result = 0; | |
1132 | ||
1133 | if (!buf) | |
1134 | return -EINVAL; | |
1135 | ||
1136 | size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", | |
1137 | title[0], title[1], title[2], title[3], title[4], title[5], | |
1138 | title[6], title[7], title[8], title[9], title[10]); | |
1139 | ||
1140 | for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { | |
1141 | /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ | |
1142 | workload_type = smu_workload_get_type(smu, i); | |
1143 | if (workload_type < 0) | |
1144 | return -EINVAL; | |
1145 | ||
1146 | result = smu_update_table(smu, | |
1147 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, | |
1148 | (void *)(&activity_monitor), false); | |
1149 | if (result) { | |
d9811cfc | 1150 | dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); |
b455159c LG |
1151 | return result; |
1152 | } | |
1153 | ||
1154 | size += sprintf(buf + size, "%2d %14s%s:\n", | |
1155 | i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); | |
1156 | ||
1157 | size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |
1158 | " ", | |
1159 | 0, | |
1160 | "GFXCLK", | |
1161 | activity_monitor.Gfx_FPS, | |
1162 | activity_monitor.Gfx_MinFreqStep, | |
1163 | activity_monitor.Gfx_MinActiveFreqType, | |
1164 | activity_monitor.Gfx_MinActiveFreq, | |
1165 | activity_monitor.Gfx_BoosterFreqType, | |
1166 | activity_monitor.Gfx_BoosterFreq, | |
1167 | activity_monitor.Gfx_PD_Data_limit_c, | |
1168 | activity_monitor.Gfx_PD_Data_error_coeff, | |
1169 | activity_monitor.Gfx_PD_Data_error_rate_coeff); | |
1170 | ||
1171 | size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |
1172 | " ", | |
1173 | 1, | |
1174 | "SOCCLK", | |
1175 | activity_monitor.Fclk_FPS, | |
1176 | activity_monitor.Fclk_MinFreqStep, | |
1177 | activity_monitor.Fclk_MinActiveFreqType, | |
1178 | activity_monitor.Fclk_MinActiveFreq, | |
1179 | activity_monitor.Fclk_BoosterFreqType, | |
1180 | activity_monitor.Fclk_BoosterFreq, | |
1181 | activity_monitor.Fclk_PD_Data_limit_c, | |
1182 | activity_monitor.Fclk_PD_Data_error_coeff, | |
1183 | activity_monitor.Fclk_PD_Data_error_rate_coeff); | |
1184 | ||
1185 | size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |
1186 | " ", | |
1187 | 2, | |
1188 | "MEMLK", | |
1189 | activity_monitor.Mem_FPS, | |
1190 | activity_monitor.Mem_MinFreqStep, | |
1191 | activity_monitor.Mem_MinActiveFreqType, | |
1192 | activity_monitor.Mem_MinActiveFreq, | |
1193 | activity_monitor.Mem_BoosterFreqType, | |
1194 | activity_monitor.Mem_BoosterFreq, | |
1195 | activity_monitor.Mem_PD_Data_limit_c, | |
1196 | activity_monitor.Mem_PD_Data_error_coeff, | |
1197 | activity_monitor.Mem_PD_Data_error_rate_coeff); | |
1198 | } | |
1199 | ||
1200 | return size; | |
1201 | } | |
1202 | ||
1203 | static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) | |
1204 | { | |
1205 | DpmActivityMonitorCoeffInt_t activity_monitor; | |
1206 | int workload_type, ret = 0; | |
1207 | ||
1208 | smu->power_profile_mode = input[size]; | |
1209 | ||
1210 | if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { | |
d9811cfc | 1211 | dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); |
b455159c LG |
1212 | return -EINVAL; |
1213 | } | |
1214 | ||
1215 | if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { | |
b455159c LG |
1216 | |
1217 | ret = smu_update_table(smu, | |
1218 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, | |
1219 | (void *)(&activity_monitor), false); | |
1220 | if (ret) { | |
d9811cfc | 1221 | dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); |
b455159c LG |
1222 | return ret; |
1223 | } | |
1224 | ||
1225 | switch (input[0]) { | |
1226 | case 0: /* Gfxclk */ | |
1227 | activity_monitor.Gfx_FPS = input[1]; | |
1228 | activity_monitor.Gfx_MinFreqStep = input[2]; | |
1229 | activity_monitor.Gfx_MinActiveFreqType = input[3]; | |
1230 | activity_monitor.Gfx_MinActiveFreq = input[4]; | |
1231 | activity_monitor.Gfx_BoosterFreqType = input[5]; | |
1232 | activity_monitor.Gfx_BoosterFreq = input[6]; | |
1233 | activity_monitor.Gfx_PD_Data_limit_c = input[7]; | |
1234 | activity_monitor.Gfx_PD_Data_error_coeff = input[8]; | |
1235 | activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; | |
1236 | break; | |
1237 | case 1: /* Socclk */ | |
1238 | activity_monitor.Fclk_FPS = input[1]; | |
1239 | activity_monitor.Fclk_MinFreqStep = input[2]; | |
1240 | activity_monitor.Fclk_MinActiveFreqType = input[3]; | |
1241 | activity_monitor.Fclk_MinActiveFreq = input[4]; | |
1242 | activity_monitor.Fclk_BoosterFreqType = input[5]; | |
1243 | activity_monitor.Fclk_BoosterFreq = input[6]; | |
1244 | activity_monitor.Fclk_PD_Data_limit_c = input[7]; | |
1245 | activity_monitor.Fclk_PD_Data_error_coeff = input[8]; | |
1246 | activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9]; | |
1247 | break; | |
1248 | case 2: /* Memlk */ | |
1249 | activity_monitor.Mem_FPS = input[1]; | |
1250 | activity_monitor.Mem_MinFreqStep = input[2]; | |
1251 | activity_monitor.Mem_MinActiveFreqType = input[3]; | |
1252 | activity_monitor.Mem_MinActiveFreq = input[4]; | |
1253 | activity_monitor.Mem_BoosterFreqType = input[5]; | |
1254 | activity_monitor.Mem_BoosterFreq = input[6]; | |
1255 | activity_monitor.Mem_PD_Data_limit_c = input[7]; | |
1256 | activity_monitor.Mem_PD_Data_error_coeff = input[8]; | |
1257 | activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; | |
1258 | break; | |
1259 | } | |
1260 | ||
1261 | ret = smu_update_table(smu, | |
1262 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, | |
1263 | (void *)(&activity_monitor), true); | |
1264 | if (ret) { | |
d9811cfc | 1265 | dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); |
b455159c LG |
1266 | return ret; |
1267 | } | |
1268 | } | |
1269 | ||
1270 | /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ | |
1271 | workload_type = smu_workload_get_type(smu, smu->power_profile_mode); | |
1272 | if (workload_type < 0) | |
1273 | return -EINVAL; | |
1274 | smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, | |
1275 | 1 << workload_type, NULL); | |
1276 | ||
1277 | return ret; | |
1278 | } | |
1279 | ||
1280 | static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu, | |
1281 | enum amd_dpm_forced_level level, | |
1282 | uint32_t *sclk_mask, | |
1283 | uint32_t *mclk_mask, | |
1284 | uint32_t *soc_mask) | |
1285 | { | |
258d290c | 1286 | struct amdgpu_device *adev = smu->adev; |
b455159c LG |
1287 | int ret = 0; |
1288 | uint32_t level_count = 0; | |
1289 | ||
1290 | if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { | |
1291 | if (sclk_mask) | |
1292 | *sclk_mask = 0; | |
1293 | } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { | |
1294 | if (mclk_mask) | |
1295 | *mclk_mask = 0; | |
1296 | } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { | |
1297 | if(sclk_mask) { | |
258d290c | 1298 | amdgpu_gfx_off_ctrl(adev, false); |
b455159c | 1299 | ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count); |
258d290c | 1300 | amdgpu_gfx_off_ctrl(adev, true); |
b455159c LG |
1301 | if (ret) |
1302 | return ret; | |
1303 | *sclk_mask = level_count - 1; | |
1304 | } | |
1305 | ||
1306 | if(mclk_mask) { | |
1307 | ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count); | |
1308 | if (ret) | |
1309 | return ret; | |
1310 | *mclk_mask = level_count - 1; | |
1311 | } | |
1312 | ||
1313 | if(soc_mask) { | |
1314 | ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count); | |
1315 | if (ret) | |
1316 | return ret; | |
1317 | *soc_mask = level_count - 1; | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | return ret; | |
1322 | } | |
1323 | ||
1324 | static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) | |
1325 | { | |
1326 | struct smu_clocks min_clocks = {0}; | |
1327 | struct pp_display_clock_request clock_req; | |
1328 | int ret = 0; | |
1329 | ||
1330 | min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; | |
1331 | min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; | |
1332 | min_clocks.memory_clock = smu->display_config->min_mem_set_clock; | |
1333 | ||
1334 | if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { | |
1335 | clock_req.clock_type = amd_pp_dcef_clock; | |
1336 | clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; | |
1337 | ||
1338 | ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); | |
1339 | if (!ret) { | |
1340 | if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { | |
40d3b8db LG |
1341 | ret = smu_send_smc_msg_with_param(smu, |
1342 | SMU_MSG_SetMinDeepSleepDcefclk, | |
1343 | min_clocks.dcef_clock_in_sr/100, | |
1344 | NULL); | |
1345 | if (ret) { | |
d9811cfc | 1346 | dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); |
40d3b8db LG |
1347 | return ret; |
1348 | } | |
b455159c LG |
1349 | } |
1350 | } else { | |
d9811cfc | 1351 | dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); |
b455159c LG |
1352 | } |
1353 | } | |
1354 | ||
1355 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { | |
1356 | ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); | |
1357 | if (ret) { | |
d9811cfc | 1358 | dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); |
b455159c LG |
1359 | return ret; |
1360 | } | |
1361 | } | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, | |
1367 | void *watermarks, struct | |
1368 | dm_pp_wm_sets_with_clock_ranges_soc15 | |
1369 | *clock_ranges) | |
1370 | { | |
1371 | int i; | |
40d3b8db | 1372 | int ret = 0; |
b455159c LG |
1373 | Watermarks_t *table = watermarks; |
1374 | ||
1375 | if (!table || !clock_ranges) | |
1376 | return -EINVAL; | |
1377 | ||
1378 | if (clock_ranges->num_wm_dmif_sets > 4 || | |
1379 | clock_ranges->num_wm_mcif_sets > 4) | |
1380 | return -EINVAL; | |
1381 | ||
1382 | for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { | |
1383 | table->WatermarkRow[1][i].MinClock = | |
1384 | cpu_to_le16((uint16_t) | |
1385 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / | |
1386 | 1000)); | |
1387 | table->WatermarkRow[1][i].MaxClock = | |
1388 | cpu_to_le16((uint16_t) | |
1389 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / | |
1390 | 1000)); | |
1391 | table->WatermarkRow[1][i].MinUclk = | |
1392 | cpu_to_le16((uint16_t) | |
1393 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / | |
1394 | 1000)); | |
1395 | table->WatermarkRow[1][i].MaxUclk = | |
1396 | cpu_to_le16((uint16_t) | |
1397 | (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / | |
1398 | 1000)); | |
1399 | table->WatermarkRow[1][i].WmSetting = (uint8_t) | |
1400 | clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; | |
1401 | } | |
1402 | ||
1403 | for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) { | |
1404 | table->WatermarkRow[0][i].MinClock = | |
1405 | cpu_to_le16((uint16_t) | |
1406 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / | |
1407 | 1000)); | |
1408 | table->WatermarkRow[0][i].MaxClock = | |
1409 | cpu_to_le16((uint16_t) | |
1410 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / | |
1411 | 1000)); | |
1412 | table->WatermarkRow[0][i].MinUclk = | |
1413 | cpu_to_le16((uint16_t) | |
1414 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz / | |
1415 | 1000)); | |
1416 | table->WatermarkRow[0][i].MaxUclk = | |
1417 | cpu_to_le16((uint16_t) | |
1418 | (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / | |
1419 | 1000)); | |
1420 | table->WatermarkRow[0][i].WmSetting = (uint8_t) | |
1421 | clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; | |
1422 | } | |
1423 | ||
40d3b8db LG |
1424 | smu->watermarks_bitmap |= WATERMARKS_EXIST; |
1425 | ||
1426 | if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) { | |
1427 | ret = smu_write_watermarks_table(smu); | |
1428 | if (ret) { | |
d9811cfc | 1429 | dev_err(smu->adev->dev, "Failed to update WMTABLE!"); |
40d3b8db LG |
1430 | return ret; |
1431 | } | |
1432 | smu->watermarks_bitmap |= WATERMARKS_LOADED; | |
1433 | } | |
1434 | ||
b455159c LG |
1435 | return 0; |
1436 | } | |
1437 | ||
1438 | static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu, | |
1439 | enum amd_pp_sensors sensor, | |
1440 | uint32_t *value) | |
1441 | { | |
b455159c LG |
1442 | int ret = 0; |
1443 | ||
1444 | if (!value) | |
1445 | return -EINVAL; | |
1446 | ||
b455159c LG |
1447 | switch (sensor) { |
1448 | case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: | |
8c686254 EQ |
1449 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1450 | METRICS_TEMPERATURE_HOTSPOT, | |
1451 | value); | |
b455159c LG |
1452 | break; |
1453 | case AMDGPU_PP_SENSOR_EDGE_TEMP: | |
8c686254 EQ |
1454 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1455 | METRICS_TEMPERATURE_EDGE, | |
1456 | value); | |
b455159c LG |
1457 | break; |
1458 | case AMDGPU_PP_SENSOR_MEM_TEMP: | |
8c686254 EQ |
1459 | ret = sienna_cichlid_get_smu_metrics_data(smu, |
1460 | METRICS_TEMPERATURE_MEM, | |
1461 | value); | |
b455159c LG |
1462 | break; |
1463 | default: | |
d9811cfc | 1464 | dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); |
b455159c LG |
1465 | return -EINVAL; |
1466 | } | |
1467 | ||
8c686254 | 1468 | return ret; |
b455159c LG |
1469 | } |
1470 | ||
1471 | static int sienna_cichlid_read_sensor(struct smu_context *smu, | |
1472 | enum amd_pp_sensors sensor, | |
1473 | void *data, uint32_t *size) | |
1474 | { | |
1475 | int ret = 0; | |
1476 | struct smu_table_context *table_context = &smu->smu_table; | |
1477 | PPTable_t *pptable = table_context->driver_pptable; | |
1478 | ||
1479 | if(!data || !size) | |
1480 | return -EINVAL; | |
1481 | ||
1482 | mutex_lock(&smu->sensor_lock); | |
1483 | switch (sensor) { | |
1484 | case AMDGPU_PP_SENSOR_MAX_FAN_RPM: | |
1485 | *(uint32_t *)data = pptable->FanMaximumRpm; | |
1486 | *size = 4; | |
1487 | break; | |
1488 | case AMDGPU_PP_SENSOR_MEM_LOAD: | |
1489 | case AMDGPU_PP_SENSOR_GPU_LOAD: | |
1490 | ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data); | |
1491 | *size = 4; | |
1492 | break; | |
1493 | case AMDGPU_PP_SENSOR_GPU_POWER: | |
1494 | ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data); | |
1495 | *size = 4; | |
1496 | break; | |
1497 | case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: | |
1498 | case AMDGPU_PP_SENSOR_EDGE_TEMP: | |
1499 | case AMDGPU_PP_SENSOR_MEM_TEMP: | |
1500 | ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data); | |
1501 | *size = 4; | |
1502 | break; | |
e0f9e936 EQ |
1503 | case AMDGPU_PP_SENSOR_GFX_MCLK: |
1504 | ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); | |
1505 | *(uint32_t *)data *= 100; | |
1506 | *size = 4; | |
1507 | break; | |
1508 | case AMDGPU_PP_SENSOR_GFX_SCLK: | |
1509 | ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); | |
1510 | *(uint32_t *)data *= 100; | |
1511 | *size = 4; | |
1512 | break; | |
b2febc99 EQ |
1513 | case AMDGPU_PP_SENSOR_VDDGFX: |
1514 | ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); | |
1515 | *size = 4; | |
1516 | break; | |
b455159c | 1517 | default: |
b2febc99 EQ |
1518 | ret = -EOPNOTSUPP; |
1519 | break; | |
b455159c LG |
1520 | } |
1521 | mutex_unlock(&smu->sensor_lock); | |
1522 | ||
1523 | return ret; | |
1524 | } | |
1525 | ||
1526 | static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) | |
1527 | { | |
1528 | uint32_t num_discrete_levels = 0; | |
1529 | uint16_t *dpm_levels = NULL; | |
1530 | uint16_t i = 0; | |
1531 | struct smu_table_context *table_context = &smu->smu_table; | |
1532 | PPTable_t *driver_ppt = NULL; | |
1533 | ||
1534 | if (!clocks_in_khz || !num_states || !table_context->driver_pptable) | |
1535 | return -EINVAL; | |
1536 | ||
1537 | driver_ppt = table_context->driver_pptable; | |
1538 | num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; | |
1539 | dpm_levels = driver_ppt->FreqTableUclk; | |
1540 | ||
1541 | if (num_discrete_levels == 0 || dpm_levels == NULL) | |
1542 | return -EINVAL; | |
1543 | ||
1544 | *num_states = num_discrete_levels; | |
1545 | for (i = 0; i < num_discrete_levels; i++) { | |
1546 | /* convert to khz */ | |
1547 | *clocks_in_khz = (*dpm_levels) * 1000; | |
1548 | clocks_in_khz++; | |
1549 | dpm_levels++; | |
1550 | } | |
1551 | ||
1552 | return 0; | |
1553 | } | |
1554 | ||
9ad9c8ac LG |
1555 | static int sienna_cichlid_set_performance_level(struct smu_context *smu, |
1556 | enum amd_dpm_forced_level level); | |
1557 | ||
1558 | static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu) | |
1559 | { | |
1560 | struct amdgpu_device *adev = smu->adev; | |
1561 | int ret = 0; | |
1562 | uint32_t sclk_freq = 0, uclk_freq = 0; | |
1563 | ||
1564 | switch (adev->asic_type) { | |
1565 | /* TODO: need to set specify clk value by asic type, not support yet*/ | |
1566 | default: | |
1567 | /* by default, this is same as auto performance level */ | |
1568 | return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO); | |
1569 | } | |
1570 | ||
1571 | ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false); | |
1572 | if (ret) | |
1573 | return ret; | |
1574 | ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false); | |
1575 | if (ret) | |
1576 | return ret; | |
1577 | ||
1578 | return ret; | |
1579 | } | |
1580 | ||
1581 | static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu) | |
1582 | { | |
1583 | int ret = 0; | |
1584 | ||
1585 | /* TODO: not support yet*/ | |
1586 | return ret; | |
1587 | } | |
1588 | ||
1589 | static int sienna_cichlid_set_performance_level(struct smu_context *smu, | |
1590 | enum amd_dpm_forced_level level) | |
1591 | { | |
1592 | int ret = 0; | |
1593 | uint32_t sclk_mask, mclk_mask, soc_mask; | |
1594 | ||
1595 | switch (level) { | |
1596 | case AMD_DPM_FORCED_LEVEL_HIGH: | |
1597 | ret = smu_force_dpm_limit_value(smu, true); | |
1598 | break; | |
1599 | case AMD_DPM_FORCED_LEVEL_LOW: | |
1600 | ret = smu_force_dpm_limit_value(smu, false); | |
1601 | break; | |
1602 | case AMD_DPM_FORCED_LEVEL_AUTO: | |
1603 | ret = smu_unforce_dpm_levels(smu); | |
1604 | break; | |
1605 | case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: | |
1606 | ret = sienna_cichlid_set_standard_performance_level(smu); | |
1607 | break; | |
1608 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: | |
1609 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: | |
1610 | ret = smu_get_profiling_clk_mask(smu, level, | |
1611 | &sclk_mask, | |
1612 | &mclk_mask, | |
1613 | &soc_mask); | |
1614 | if (ret) | |
1615 | return ret; | |
1616 | smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false); | |
1617 | smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false); | |
1618 | smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false); | |
1619 | break; | |
1620 | case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: | |
1621 | ret = sienna_cichlid_set_peak_performance_level(smu); | |
1622 | break; | |
1623 | case AMD_DPM_FORCED_LEVEL_MANUAL: | |
1624 | case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: | |
1625 | default: | |
1626 | break; | |
1627 | } | |
1628 | return ret; | |
1629 | } | |
1630 | ||
b455159c LG |
1631 | static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, |
1632 | struct smu_temperature_range *range) | |
1633 | { | |
1634 | struct smu_table_context *table_context = &smu->smu_table; | |
e05acd78 | 1635 | struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; |
b455159c LG |
1636 | |
1637 | if (!range || !powerplay_table) | |
1638 | return -EINVAL; | |
1639 | ||
1640 | range->max = powerplay_table->software_shutdown_temp * | |
1641 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | |
1642 | ||
1643 | return 0; | |
1644 | } | |
1645 | ||
1646 | static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, | |
1647 | bool disable_memory_clock_switch) | |
1648 | { | |
1649 | int ret = 0; | |
1650 | struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = | |
1651 | (struct smu_11_0_max_sustainable_clocks *) | |
1652 | smu->smu_table.max_sustainable_clocks; | |
1653 | uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; | |
1654 | uint32_t max_memory_clock = max_sustainable_clocks->uclock; | |
1655 | ||
1656 | if(smu->disable_uclk_switch == disable_memory_clock_switch) | |
1657 | return 0; | |
1658 | ||
1659 | if(disable_memory_clock_switch) | |
1660 | ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0); | |
1661 | else | |
1662 | ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0); | |
1663 | ||
1664 | if(!ret) | |
1665 | smu->disable_uclk_switch = disable_memory_clock_switch; | |
1666 | ||
1667 | return ret; | |
1668 | } | |
1669 | ||
a141b4e3 | 1670 | static int sienna_cichlid_get_power_limit(struct smu_context *smu) |
b455159c | 1671 | { |
1e239fdd EQ |
1672 | struct smu_11_0_7_powerplay_table *powerplay_table = |
1673 | (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; | |
b455159c | 1674 | PPTable_t *pptable = smu->smu_table.driver_pptable; |
1e239fdd EQ |
1675 | uint32_t power_limit, od_percent; |
1676 | ||
1677 | if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { | |
1678 | /* the last hope to figure out the ppt limit */ | |
1679 | if (!pptable) { | |
1680 | dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); | |
1681 | return -EINVAL; | |
b455159c | 1682 | } |
1e239fdd EQ |
1683 | power_limit = |
1684 | pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; | |
1685 | } | |
1686 | smu->current_power_limit = power_limit; | |
b455159c | 1687 | |
1e239fdd EQ |
1688 | if (smu->od_enabled) { |
1689 | od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); | |
1690 | ||
1691 | dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); | |
1692 | ||
1693 | power_limit *= (100 + od_percent); | |
1694 | power_limit /= 100; | |
b455159c | 1695 | } |
1e239fdd | 1696 | smu->max_power_limit = power_limit; |
b455159c | 1697 | |
b455159c LG |
1698 | return 0; |
1699 | } | |
1700 | ||
08ccfe08 LG |
1701 | static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, |
1702 | uint32_t pcie_gen_cap, | |
1703 | uint32_t pcie_width_cap) | |
1704 | { | |
1705 | PPTable_t *pptable = smu->smu_table.driver_pptable; | |
1706 | int ret, i; | |
1707 | uint32_t smu_pcie_arg; | |
1708 | ||
1709 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |
1710 | struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; | |
1711 | ||
1712 | for (i = 0; i < NUM_LINK_LEVELS; i++) { | |
1713 | smu_pcie_arg = (i << 16) | | |
1714 | ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? | |
1715 | (pptable->PcieGenSpeed[i] << 8) : | |
1716 | (pcie_gen_cap << 8)) | | |
1717 | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? | |
1718 | pptable->PcieLaneCount[i] : | |
1719 | pcie_width_cap); | |
1720 | ||
1721 | ret = smu_send_smc_msg_with_param(smu, | |
40d3b8db LG |
1722 | SMU_MSG_OverridePcieParameters, |
1723 | smu_pcie_arg, | |
1724 | NULL); | |
1725 | ||
08ccfe08 LG |
1726 | if (ret) |
1727 | return ret; | |
1728 | ||
1729 | if (pptable->PcieGenSpeed[i] > pcie_gen_cap) | |
1730 | dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; | |
1731 | if (pptable->PcieLaneCount[i] > pcie_width_cap) | |
1732 | dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; | |
1733 | } | |
1734 | ||
1735 | return 0; | |
1736 | } | |
1737 | ||
38ed7b09 | 1738 | static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, |
258d290c LG |
1739 | enum smu_clk_type clk_type, |
1740 | uint32_t *min, uint32_t *max) | |
1741 | { | |
1742 | struct amdgpu_device *adev = smu->adev; | |
1743 | int ret; | |
1744 | ||
1745 | if (clk_type == SMU_GFXCLK) | |
1746 | amdgpu_gfx_off_ctrl(adev, false); | |
1747 | ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); | |
1748 | if (clk_type == SMU_GFXCLK) | |
1749 | amdgpu_gfx_off_ctrl(adev, true); | |
1750 | ||
1751 | return ret; | |
1752 | } | |
1753 | ||
38ed7b09 | 1754 | static int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu, |
258d290c LG |
1755 | enum smu_clk_type clk_type, |
1756 | uint32_t min, uint32_t max) | |
1757 | { | |
1758 | struct amdgpu_device *adev = smu->adev; | |
1759 | int ret; | |
1760 | ||
1761 | if (clk_type == SMU_GFXCLK) | |
1762 | amdgpu_gfx_off_ctrl(adev, false); | |
1763 | ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max); | |
1764 | if (clk_type == SMU_GFXCLK) | |
1765 | amdgpu_gfx_off_ctrl(adev, true); | |
1766 | ||
1767 | return ret; | |
1768 | } | |
1769 | ||
40d3b8db LG |
1770 | static bool sienna_cichlid_is_baco_supported(struct smu_context *smu) |
1771 | { | |
1772 | struct amdgpu_device *adev = smu->adev; | |
1773 | uint32_t val; | |
1774 | ||
1775 | if (!smu_v11_0_baco_is_support(smu)) | |
1776 | return false; | |
1777 | ||
1778 | val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); | |
1779 | return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; | |
1780 | } | |
1781 | ||
e05acd78 LG |
1782 | static int sienna_cichlid_set_thermal_range(struct smu_context *smu, |
1783 | struct smu_temperature_range range) | |
1784 | { | |
1785 | struct amdgpu_device *adev = smu->adev; | |
1786 | int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; | |
1787 | int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; | |
1788 | uint32_t val; | |
1789 | struct smu_table_context *table_context = &smu->smu_table; | |
1790 | struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; | |
1791 | ||
1792 | low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, | |
1793 | range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); | |
1794 | high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); | |
1795 | ||
1796 | if (low > high) | |
1797 | return -EINVAL; | |
1798 | ||
1799 | val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); | |
1800 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); | |
1801 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); | |
1802 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); | |
1803 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); | |
1804 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); | |
1805 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); | |
1806 | val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); | |
1807 | ||
1808 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); | |
1809 | ||
1810 | return 0; | |
1811 | } | |
1812 | ||
b455159c LG |
1813 | static void sienna_cichlid_dump_pptable(struct smu_context *smu) |
1814 | { | |
1815 | struct smu_table_context *table_context = &smu->smu_table; | |
1816 | PPTable_t *pptable = table_context->driver_pptable; | |
1817 | int i; | |
1818 | ||
d9811cfc | 1819 | dev_info(smu->adev->dev, "Dumped PPTable:\n"); |
b455159c | 1820 | |
d9811cfc EQ |
1821 | dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); |
1822 | dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); | |
1823 | dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); | |
b455159c LG |
1824 | |
1825 | for (i = 0; i < PPT_THROTTLER_COUNT; i++) { | |
d9811cfc EQ |
1826 | dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); |
1827 | dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); | |
1828 | dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); | |
1829 | dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); | |
b455159c LG |
1830 | } |
1831 | ||
1832 | for (i = 0; i < TDC_THROTTLER_COUNT; i++) { | |
d9811cfc EQ |
1833 | dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); |
1834 | dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); | |
b455159c LG |
1835 | } |
1836 | ||
1837 | for (i = 0; i < TEMP_COUNT; i++) { | |
d9811cfc | 1838 | dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); |
b455159c LG |
1839 | } |
1840 | ||
d9811cfc EQ |
1841 | dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); |
1842 | dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); | |
1843 | dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); | |
1844 | dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); | |
1845 | dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); | |
b455159c | 1846 | |
d9811cfc | 1847 | dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); |
b455159c | 1848 | for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { |
d9811cfc EQ |
1849 | dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); |
1850 | dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); | |
b455159c | 1851 | } |
d9811cfc EQ |
1852 | dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]); |
1853 | dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]); | |
1854 | dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]); | |
1855 | dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]); | |
1856 | ||
1857 | dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); | |
1858 | ||
1859 | dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); | |
1860 | ||
1861 | dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); | |
1862 | dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); | |
1863 | dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); | |
1864 | dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); | |
1865 | ||
1866 | dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); | |
1867 | dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); | |
1868 | ||
1869 | dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); | |
1870 | dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); | |
1871 | dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); | |
1872 | dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); | |
1873 | ||
1874 | dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); | |
1875 | dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); | |
1876 | dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); | |
1877 | dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); | |
1878 | ||
1879 | dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); | |
1880 | dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); | |
1881 | ||
1882 | dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); | |
1883 | dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); | |
1884 | dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); | |
1885 | dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); | |
1886 | dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); | |
1887 | dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); | |
1888 | dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); | |
1889 | dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); | |
1890 | ||
1891 | dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" | |
b455159c LG |
1892 | " .VoltageMode = 0x%02x\n" |
1893 | " .SnapToDiscrete = 0x%02x\n" | |
1894 | " .NumDiscreteLevels = 0x%02x\n" | |
1895 | " .padding = 0x%02x\n" | |
1896 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1897 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1898 | " .SsFmin = 0x%04x\n" | |
1899 | " .Padding_16 = 0x%04x\n", | |
1900 | pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, | |
1901 | pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, | |
1902 | pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, | |
1903 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, | |
1904 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, | |
1905 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, | |
1906 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, | |
1907 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, | |
1908 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, | |
1909 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, | |
1910 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); | |
1911 | ||
d9811cfc | 1912 | dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" |
b455159c LG |
1913 | " .VoltageMode = 0x%02x\n" |
1914 | " .SnapToDiscrete = 0x%02x\n" | |
1915 | " .NumDiscreteLevels = 0x%02x\n" | |
1916 | " .padding = 0x%02x\n" | |
1917 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1918 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1919 | " .SsFmin = 0x%04x\n" | |
1920 | " .Padding_16 = 0x%04x\n", | |
1921 | pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, | |
1922 | pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, | |
1923 | pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, | |
1924 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, | |
1925 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, | |
1926 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, | |
1927 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, | |
1928 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, | |
1929 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, | |
1930 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, | |
1931 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); | |
1932 | ||
d9811cfc | 1933 | dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" |
b455159c LG |
1934 | " .VoltageMode = 0x%02x\n" |
1935 | " .SnapToDiscrete = 0x%02x\n" | |
1936 | " .NumDiscreteLevels = 0x%02x\n" | |
1937 | " .padding = 0x%02x\n" | |
1938 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1939 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1940 | " .SsFmin = 0x%04x\n" | |
1941 | " .Padding_16 = 0x%04x\n", | |
1942 | pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, | |
1943 | pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, | |
1944 | pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, | |
1945 | pptable->DpmDescriptor[PPCLK_UCLK].Padding, | |
1946 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, | |
1947 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, | |
1948 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, | |
1949 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, | |
1950 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, | |
1951 | pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, | |
1952 | pptable->DpmDescriptor[PPCLK_UCLK].Padding16); | |
1953 | ||
d9811cfc | 1954 | dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" |
b455159c LG |
1955 | " .VoltageMode = 0x%02x\n" |
1956 | " .SnapToDiscrete = 0x%02x\n" | |
1957 | " .NumDiscreteLevels = 0x%02x\n" | |
1958 | " .padding = 0x%02x\n" | |
1959 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1960 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1961 | " .SsFmin = 0x%04x\n" | |
1962 | " .Padding_16 = 0x%04x\n", | |
1963 | pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, | |
1964 | pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, | |
1965 | pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, | |
1966 | pptable->DpmDescriptor[PPCLK_FCLK].Padding, | |
1967 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, | |
1968 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, | |
1969 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, | |
1970 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, | |
1971 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, | |
1972 | pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, | |
1973 | pptable->DpmDescriptor[PPCLK_FCLK].Padding16); | |
1974 | ||
d9811cfc | 1975 | dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" |
b455159c LG |
1976 | " .VoltageMode = 0x%02x\n" |
1977 | " .SnapToDiscrete = 0x%02x\n" | |
1978 | " .NumDiscreteLevels = 0x%02x\n" | |
1979 | " .padding = 0x%02x\n" | |
1980 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
1981 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
1982 | " .SsFmin = 0x%04x\n" | |
1983 | " .Padding_16 = 0x%04x\n", | |
1984 | pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, | |
1985 | pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, | |
1986 | pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, | |
1987 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, | |
1988 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, | |
1989 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, | |
1990 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, | |
1991 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, | |
1992 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, | |
1993 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, | |
1994 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); | |
1995 | ||
d9811cfc | 1996 | dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" |
b455159c LG |
1997 | " .VoltageMode = 0x%02x\n" |
1998 | " .SnapToDiscrete = 0x%02x\n" | |
1999 | " .NumDiscreteLevels = 0x%02x\n" | |
2000 | " .padding = 0x%02x\n" | |
2001 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
2002 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
2003 | " .SsFmin = 0x%04x\n" | |
2004 | " .Padding_16 = 0x%04x\n", | |
2005 | pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, | |
2006 | pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, | |
2007 | pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, | |
2008 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, | |
2009 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, | |
2010 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, | |
2011 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, | |
2012 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, | |
2013 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, | |
2014 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, | |
2015 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); | |
2016 | ||
d9811cfc | 2017 | dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" |
b455159c LG |
2018 | " .VoltageMode = 0x%02x\n" |
2019 | " .SnapToDiscrete = 0x%02x\n" | |
2020 | " .NumDiscreteLevels = 0x%02x\n" | |
2021 | " .padding = 0x%02x\n" | |
2022 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
2023 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
2024 | " .SsFmin = 0x%04x\n" | |
2025 | " .Padding_16 = 0x%04x\n", | |
2026 | pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, | |
2027 | pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, | |
2028 | pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, | |
2029 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, | |
2030 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, | |
2031 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, | |
2032 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, | |
2033 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, | |
2034 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, | |
2035 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, | |
2036 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); | |
2037 | ||
d9811cfc | 2038 | dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" |
b455159c LG |
2039 | " .VoltageMode = 0x%02x\n" |
2040 | " .SnapToDiscrete = 0x%02x\n" | |
2041 | " .NumDiscreteLevels = 0x%02x\n" | |
2042 | " .padding = 0x%02x\n" | |
2043 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" | |
2044 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" | |
2045 | " .SsFmin = 0x%04x\n" | |
2046 | " .Padding_16 = 0x%04x\n", | |
2047 | pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, | |
2048 | pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, | |
2049 | pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, | |
2050 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, | |
2051 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, | |
2052 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, | |
2053 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, | |
2054 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, | |
2055 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, | |
2056 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, | |
2057 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); | |
2058 | ||
d9811cfc | 2059 | dev_info(smu->adev->dev, "FreqTableGfx\n"); |
b455159c | 2060 | for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) |
d9811cfc | 2061 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); |
b455159c | 2062 | |
d9811cfc | 2063 | dev_info(smu->adev->dev, "FreqTableVclk\n"); |
b455159c | 2064 | for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) |
d9811cfc | 2065 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); |
b455159c | 2066 | |
d9811cfc | 2067 | dev_info(smu->adev->dev, "FreqTableDclk\n"); |
b455159c | 2068 | for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) |
d9811cfc | 2069 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); |
b455159c | 2070 | |
d9811cfc | 2071 | dev_info(smu->adev->dev, "FreqTableSocclk\n"); |
b455159c | 2072 | for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) |
d9811cfc | 2073 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); |
b455159c | 2074 | |
d9811cfc | 2075 | dev_info(smu->adev->dev, "FreqTableUclk\n"); |
b455159c | 2076 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2077 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); |
b455159c | 2078 | |
d9811cfc | 2079 | dev_info(smu->adev->dev, "FreqTableFclk\n"); |
b455159c | 2080 | for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) |
d9811cfc EQ |
2081 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); |
2082 | ||
2083 | dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]); | |
2084 | dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]); | |
2085 | dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]); | |
2086 | dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]); | |
2087 | dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]); | |
2088 | dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]); | |
2089 | dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]); | |
2090 | dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]); | |
2091 | dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]); | |
2092 | dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]); | |
2093 | dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]); | |
2094 | dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]); | |
2095 | dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]); | |
2096 | dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]); | |
2097 | dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]); | |
2098 | dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]); | |
2099 | ||
2100 | dev_info(smu->adev->dev, "DcModeMaxFreq\n"); | |
2101 | dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); | |
2102 | dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); | |
2103 | dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); | |
2104 | dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); | |
2105 | dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); | |
2106 | dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); | |
2107 | dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); | |
2108 | dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); | |
2109 | ||
2110 | dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); | |
b455159c | 2111 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2112 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); |
b455159c | 2113 | |
d9811cfc EQ |
2114 | dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); |
2115 | dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); | |
b455159c | 2116 | |
d9811cfc | 2117 | dev_info(smu->adev->dev, "Mp0clkFreq\n"); |
b455159c | 2118 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) |
d9811cfc | 2119 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); |
b455159c | 2120 | |
d9811cfc | 2121 | dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); |
b455159c | 2122 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) |
d9811cfc | 2123 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); |
b455159c | 2124 | |
d9811cfc | 2125 | dev_info(smu->adev->dev, "MemVddciVoltage\n"); |
b455159c | 2126 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2127 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); |
b455159c | 2128 | |
d9811cfc | 2129 | dev_info(smu->adev->dev, "MemMvddVoltage\n"); |
b455159c | 2130 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc EQ |
2131 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); |
2132 | ||
2133 | dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); | |
2134 | dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); | |
2135 | dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); | |
2136 | dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); | |
2137 | dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); | |
2138 | ||
2139 | dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); | |
2140 | ||
2141 | dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); | |
2142 | dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); | |
2143 | dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); | |
2144 | dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); | |
2145 | dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); | |
2146 | dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); | |
2147 | dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); | |
2148 | dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); | |
2149 | dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); | |
2150 | dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); | |
2151 | dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); | |
2152 | ||
2153 | dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); | |
2154 | dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); | |
2155 | dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); | |
2156 | dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); | |
2157 | dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); | |
2158 | dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); | |
2159 | ||
2160 | dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); | |
2161 | dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); | |
2162 | dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); | |
2163 | dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); | |
2164 | dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); | |
2165 | ||
2166 | dev_info(smu->adev->dev, "FlopsPerByteTable\n"); | |
b455159c | 2167 | for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) |
d9811cfc | 2168 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); |
b455159c | 2169 | |
d9811cfc EQ |
2170 | dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); |
2171 | dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); | |
2172 | dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); | |
2173 | dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); | |
b455159c | 2174 | |
d9811cfc | 2175 | dev_info(smu->adev->dev, "UclkDpmPstates\n"); |
b455159c | 2176 | for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) |
d9811cfc | 2177 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); |
b455159c | 2178 | |
d9811cfc EQ |
2179 | dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); |
2180 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n", | |
b455159c | 2181 | pptable->UclkDpmSrcFreqRange.Fmin); |
d9811cfc | 2182 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n", |
b455159c | 2183 | pptable->UclkDpmSrcFreqRange.Fmax); |
d9811cfc EQ |
2184 | dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); |
2185 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n", | |
b455159c | 2186 | pptable->UclkDpmTargFreqRange.Fmin); |
d9811cfc | 2187 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n", |
b455159c | 2188 | pptable->UclkDpmTargFreqRange.Fmax); |
d9811cfc EQ |
2189 | dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); |
2190 | dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); | |
b455159c | 2191 | |
d9811cfc | 2192 | dev_info(smu->adev->dev, "PcieGenSpeed\n"); |
b455159c | 2193 | for (i = 0; i < NUM_LINK_LEVELS; i++) |
d9811cfc | 2194 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); |
b455159c | 2195 | |
d9811cfc | 2196 | dev_info(smu->adev->dev, "PcieLaneCount\n"); |
b455159c | 2197 | for (i = 0; i < NUM_LINK_LEVELS; i++) |
d9811cfc | 2198 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); |
b455159c | 2199 | |
d9811cfc | 2200 | dev_info(smu->adev->dev, "LclkFreq\n"); |
b455159c | 2201 | for (i = 0; i < NUM_LINK_LEVELS; i++) |
d9811cfc | 2202 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); |
b455159c | 2203 | |
d9811cfc EQ |
2204 | dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); |
2205 | dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); | |
b455159c | 2206 | |
d9811cfc | 2207 | dev_info(smu->adev->dev, "FanGain\n"); |
b455159c | 2208 | for (i = 0; i < TEMP_COUNT; i++) |
d9811cfc EQ |
2209 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); |
2210 | ||
2211 | dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); | |
2212 | dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); | |
2213 | dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); | |
2214 | dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); | |
2215 | dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); | |
2216 | dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); | |
2217 | dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); | |
2218 | dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); | |
2219 | dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); | |
2220 | dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); | |
2221 | dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); | |
2222 | dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); | |
2223 | ||
2224 | dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); | |
2225 | dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); | |
2226 | dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); | |
2227 | dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); | |
2228 | ||
2229 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); | |
2230 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); | |
2231 | dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); | |
2232 | dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); | |
2233 | ||
2234 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", | |
b455159c LG |
2235 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, |
2236 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, | |
2237 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); | |
d9811cfc | 2238 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2239 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, |
2240 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, | |
2241 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); | |
d9811cfc | 2242 | dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2243 | pptable->dBtcGbGfxPll.a, |
2244 | pptable->dBtcGbGfxPll.b, | |
2245 | pptable->dBtcGbGfxPll.c); | |
d9811cfc | 2246 | dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2247 | pptable->dBtcGbGfxDfll.a, |
2248 | pptable->dBtcGbGfxDfll.b, | |
2249 | pptable->dBtcGbGfxDfll.c); | |
d9811cfc | 2250 | dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2251 | pptable->dBtcGbSoc.a, |
2252 | pptable->dBtcGbSoc.b, | |
2253 | pptable->dBtcGbSoc.c); | |
d9811cfc | 2254 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", |
b455159c LG |
2255 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, |
2256 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); | |
d9811cfc | 2257 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", |
b455159c LG |
2258 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, |
2259 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); | |
2260 | ||
d9811cfc | 2261 | dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); |
b455159c | 2262 | for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { |
d9811cfc | 2263 | dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", |
b455159c | 2264 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); |
d9811cfc | 2265 | dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", |
b455159c LG |
2266 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); |
2267 | } | |
2268 | ||
d9811cfc | 2269 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2270 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, |
2271 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, | |
2272 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); | |
d9811cfc | 2273 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2274 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, |
2275 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, | |
2276 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); | |
2277 | ||
d9811cfc EQ |
2278 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); |
2279 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); | |
b455159c | 2280 | |
d9811cfc EQ |
2281 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); |
2282 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); | |
2283 | dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); | |
2284 | dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); | |
b455159c | 2285 | |
d9811cfc EQ |
2286 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); |
2287 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); | |
2288 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); | |
2289 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); | |
b455159c | 2290 | |
d9811cfc EQ |
2291 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); |
2292 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); | |
b455159c | 2293 | |
d9811cfc | 2294 | dev_info(smu->adev->dev, "XgmiDpmPstates\n"); |
b455159c | 2295 | for (i = 0; i < NUM_XGMI_LEVELS; i++) |
d9811cfc EQ |
2296 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); |
2297 | dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); | |
2298 | dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); | |
b455159c | 2299 | |
d9811cfc EQ |
2300 | dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); |
2301 | dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", | |
b455159c LG |
2302 | pptable->ReservedEquation0.a, |
2303 | pptable->ReservedEquation0.b, | |
2304 | pptable->ReservedEquation0.c); | |
d9811cfc | 2305 | dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2306 | pptable->ReservedEquation1.a, |
2307 | pptable->ReservedEquation1.b, | |
2308 | pptable->ReservedEquation1.c); | |
d9811cfc | 2309 | dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2310 | pptable->ReservedEquation2.a, |
2311 | pptable->ReservedEquation2.b, | |
2312 | pptable->ReservedEquation2.c); | |
d9811cfc | 2313 | dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", |
b455159c LG |
2314 | pptable->ReservedEquation3.a, |
2315 | pptable->ReservedEquation3.b, | |
2316 | pptable->ReservedEquation3.c); | |
2317 | ||
d9811cfc EQ |
2318 | dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); |
2319 | dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); | |
2320 | dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); | |
2321 | dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); | |
2322 | dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); | |
2323 | dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); | |
2324 | dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); | |
2325 | dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); | |
2326 | dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]); | |
2327 | dev_info(smu->adev->dev, "SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]); | |
2328 | dev_info(smu->adev->dev, "SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]); | |
2329 | dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]); | |
2330 | dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]); | |
2331 | dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]); | |
d9811cfc EQ |
2332 | |
2333 | dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); | |
2334 | dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); | |
2335 | dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); | |
2336 | dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); | |
2337 | dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); | |
2338 | dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); | |
b455159c LG |
2339 | |
2340 | for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { | |
d9811cfc EQ |
2341 | dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); |
2342 | dev_info(smu->adev->dev, " .Enabled = 0x%x\n", | |
b455159c | 2343 | pptable->I2cControllers[i].Enabled); |
d9811cfc | 2344 | dev_info(smu->adev->dev, " .Speed = 0x%x\n", |
b455159c | 2345 | pptable->I2cControllers[i].Speed); |
d9811cfc | 2346 | dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", |
b455159c | 2347 | pptable->I2cControllers[i].SlaveAddress); |
d9811cfc | 2348 | dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", |
b455159c | 2349 | pptable->I2cControllers[i].ControllerPort); |
d9811cfc | 2350 | dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", |
b455159c | 2351 | pptable->I2cControllers[i].ControllerName); |
d9811cfc | 2352 | dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", |
b455159c | 2353 | pptable->I2cControllers[i].ThermalThrotter); |
d9811cfc | 2354 | dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", |
b455159c | 2355 | pptable->I2cControllers[i].I2cProtocol); |
d9811cfc | 2356 | dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", |
b455159c LG |
2357 | pptable->I2cControllers[i].PaddingConfig); |
2358 | } | |
2359 | ||
d9811cfc EQ |
2360 | dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); |
2361 | dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); | |
2362 | dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); | |
2363 | dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); | |
2364 | ||
2365 | dev_info(smu->adev->dev, "Board Parameters:\n"); | |
2366 | dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); | |
2367 | dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); | |
2368 | dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); | |
2369 | dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); | |
2370 | dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); | |
2371 | dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); | |
2372 | dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); | |
2373 | dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); | |
2374 | ||
2375 | dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); | |
2376 | dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); | |
2377 | dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); | |
2378 | ||
2379 | dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); | |
2380 | dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); | |
2381 | dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); | |
2382 | ||
2383 | dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); | |
2384 | dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); | |
2385 | dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); | |
2386 | ||
2387 | dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); | |
2388 | dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); | |
2389 | dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); | |
2390 | ||
2391 | dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); | |
2392 | ||
2393 | dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); | |
2394 | dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); | |
2395 | dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); | |
2396 | dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); | |
2397 | dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); | |
2398 | dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); | |
2399 | dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); | |
2400 | dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); | |
2401 | dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); | |
2402 | dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); | |
2403 | dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); | |
2404 | dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); | |
2405 | dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); | |
2406 | dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); | |
2407 | dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); | |
2408 | dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); | |
2409 | ||
2410 | dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); | |
2411 | dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); | |
2412 | dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); | |
2413 | ||
2414 | dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); | |
2415 | dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); | |
2416 | dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); | |
2417 | ||
f0f3d68e | 2418 | dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); |
d9811cfc EQ |
2419 | dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); |
2420 | ||
2421 | dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); | |
2422 | dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); | |
2423 | dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); | |
2424 | ||
2425 | dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); | |
2426 | dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); | |
2427 | dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); | |
2428 | dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); | |
2429 | dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); | |
2430 | ||
2431 | dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); | |
2432 | dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); | |
2433 | ||
2434 | dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); | |
b455159c | 2435 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2436 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); |
2437 | dev_info(smu->adev->dev, "XgmiLinkWidth\n"); | |
b455159c | 2438 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2439 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); |
2440 | dev_info(smu->adev->dev, "XgmiFclkFreq\n"); | |
b455159c | 2441 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2442 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); |
2443 | dev_info(smu->adev->dev, "XgmiSocVoltage\n"); | |
b455159c | 2444 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) |
d9811cfc EQ |
2445 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); |
2446 | ||
2447 | dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); | |
2448 | dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); | |
2449 | dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); | |
2450 | dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); | |
2451 | ||
2452 | dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); | |
2453 | dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); | |
2454 | dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); | |
2455 | dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); | |
2456 | dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); | |
2457 | dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); | |
2458 | dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); | |
2459 | dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); | |
2460 | dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); | |
2461 | dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); | |
2462 | dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); | |
d9811cfc EQ |
2463 | |
2464 | dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); | |
2465 | dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); | |
2466 | dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); | |
2467 | dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); | |
2468 | dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); | |
2469 | dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); | |
2470 | dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); | |
2471 | dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); | |
b455159c LG |
2472 | } |
2473 | ||
2474 | static const struct pptable_funcs sienna_cichlid_ppt_funcs = { | |
2475 | .tables_init = sienna_cichlid_tables_init, | |
2476 | .alloc_dpm_context = sienna_cichlid_allocate_dpm_context, | |
b455159c LG |
2477 | .get_smu_msg_index = sienna_cichlid_get_smu_msg_index, |
2478 | .get_smu_clk_index = sienna_cichlid_get_smu_clk_index, | |
2479 | .get_smu_feature_index = sienna_cichlid_get_smu_feature_index, | |
2480 | .get_smu_table_index = sienna_cichlid_get_smu_table_index, | |
1d5ca713 | 2481 | .get_smu_power_index = sienna_cichlid_get_pwr_src_index, |
b455159c LG |
2482 | .get_workload_type = sienna_cichlid_get_workload_type, |
2483 | .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, | |
2484 | .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, | |
f6b4b4a1 | 2485 | .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, |
6fb176a7 | 2486 | .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, |
b455159c LG |
2487 | .print_clk_levels = sienna_cichlid_print_clk_levels, |
2488 | .force_clk_levels = sienna_cichlid_force_clk_levels, | |
2489 | .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, | |
b455159c LG |
2490 | .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, |
2491 | .display_config_changed = sienna_cichlid_display_config_changed, | |
2492 | .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, | |
2493 | .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value, | |
2494 | .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels, | |
2495 | .is_dpm_running = sienna_cichlid_is_dpm_running, | |
2496 | .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent, | |
2497 | .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, | |
2498 | .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, | |
2499 | .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, | |
2500 | .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask, | |
2501 | .set_watermarks_table = sienna_cichlid_set_watermarks_table, | |
2502 | .read_sensor = sienna_cichlid_read_sensor, | |
2503 | .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, | |
9ad9c8ac | 2504 | .set_performance_level = sienna_cichlid_set_performance_level, |
b455159c LG |
2505 | .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, |
2506 | .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, | |
2507 | .get_power_limit = sienna_cichlid_get_power_limit, | |
08ccfe08 | 2508 | .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, |
b455159c LG |
2509 | .dump_pptable = sienna_cichlid_dump_pptable, |
2510 | .init_microcode = smu_v11_0_init_microcode, | |
2511 | .load_microcode = smu_v11_0_load_microcode, | |
2512 | .init_smc_tables = smu_v11_0_init_smc_tables, | |
2513 | .fini_smc_tables = smu_v11_0_fini_smc_tables, | |
2514 | .init_power = smu_v11_0_init_power, | |
2515 | .fini_power = smu_v11_0_fini_power, | |
2516 | .check_fw_status = smu_v11_0_check_fw_status, | |
4a13b4ce | 2517 | .setup_pptable = sienna_cichlid_setup_pptable, |
b455159c | 2518 | .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, |
b455159c LG |
2519 | .check_fw_version = smu_v11_0_check_fw_version, |
2520 | .write_pptable = smu_v11_0_write_pptable, | |
b455159c LG |
2521 | .set_driver_table_location = smu_v11_0_set_driver_table_location, |
2522 | .set_tool_table_location = smu_v11_0_set_tool_table_location, | |
2523 | .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, | |
2524 | .system_features_control = smu_v11_0_system_features_control, | |
2525 | .send_smc_msg_with_param = smu_v11_0_send_msg_with_param, | |
31157341 | 2526 | .init_display_count = NULL, |
b455159c LG |
2527 | .set_allowed_mask = smu_v11_0_set_allowed_mask, |
2528 | .get_enabled_mask = smu_v11_0_get_enabled_mask, | |
31157341 | 2529 | .notify_display_change = NULL, |
b455159c | 2530 | .set_power_limit = smu_v11_0_set_power_limit, |
b455159c LG |
2531 | .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, |
2532 | .enable_thermal_alert = smu_v11_0_enable_thermal_alert, | |
2533 | .disable_thermal_alert = smu_v11_0_disable_thermal_alert, | |
ce63d8f8 | 2534 | .set_min_dcef_deep_sleep = NULL, |
b455159c LG |
2535 | .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, |
2536 | .get_fan_control_mode = smu_v11_0_get_fan_control_mode, | |
2537 | .set_fan_control_mode = smu_v11_0_set_fan_control_mode, | |
2538 | .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, | |
2539 | .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, | |
2540 | .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, | |
2541 | .gfx_off_control = smu_v11_0_gfx_off_control, | |
2542 | .register_irq_handler = smu_v11_0_register_irq_handler, | |
2543 | .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, | |
2544 | .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, | |
40d3b8db | 2545 | .baco_is_support= sienna_cichlid_is_baco_supported, |
b455159c LG |
2546 | .baco_get_state = smu_v11_0_baco_get_state, |
2547 | .baco_set_state = smu_v11_0_baco_set_state, | |
2548 | .baco_enter = smu_v11_0_baco_enter, | |
2549 | .baco_exit = smu_v11_0_baco_exit, | |
258d290c LG |
2550 | .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, |
2551 | .set_soft_freq_limited_range = sienna_cichlid_set_soft_freq_limited_range, | |
b455159c | 2552 | .override_pcie_parameters = smu_v11_0_override_pcie_parameters, |
e05acd78 | 2553 | .set_thermal_range = sienna_cichlid_set_thermal_range, |
b455159c LG |
2554 | }; |
2555 | ||
2556 | void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) | |
2557 | { | |
2558 | smu->ppt_funcs = &sienna_cichlid_ppt_funcs; | |
2559 | } |