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drm/amdkfd: sienna_cichlid virtual function support
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include <linux/pci.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "smu_internal.h"
30#include "atomfirmware.h"
31#include "amdgpu_atomfirmware.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_sienna_cichlid.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "sienna_cichlid_ppt.h"
37#include "smu_v11_0_pptable.h"
38#include "smu_v11_0_7_ppsmc.h"
39
b7d25b5f 40#include "nbio/nbio_2_3_sh_mask.h"
b455159c
LG		 41#include "asic_reg/mp/mp_11_0_sh_mask.h"
42
43#define FEATURE_MASK(feature) (1ULL << feature)
44#define SMC_DPM_FEATURE ( \
45 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 46 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 47 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 48 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 49 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70
LG		 50 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
51 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
b455159c
LG		 52
53#define MSG_MAP(msg, index) \
54 [SMU_MSG_##msg] = {1, (index)}
55
56static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
57 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
58 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
59 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
60 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
61 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
62 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
63 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
64 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
65 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
66 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
67 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
68 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
69 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
70 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
71 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
72 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
73 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
74 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
75 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
76 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
77 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
78 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
79 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
80 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
81 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
82 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
83 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
84 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
85 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
86 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
87 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
88 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
89 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
90 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
91 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
92 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
93 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
94 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
95 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
96 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
97 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
98 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
99 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
100 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
101 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
102 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
103 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
104 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
105 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
106};
107
108static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
109 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
110 CLK_MAP(SCLK, PPCLK_GFXCLK),
111 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
112 CLK_MAP(FCLK, PPCLK_FCLK),
113 CLK_MAP(UCLK, PPCLK_UCLK),
114 CLK_MAP(MCLK, PPCLK_UCLK),
115 CLK_MAP(DCLK, PPCLK_DCLK_0),
116 CLK_MAP(DCLK1, PPCLK_DCLK_0),
117 CLK_MAP(VCLK, PPCLK_VCLK_1),
118 CLK_MAP(VCLK1, PPCLK_VCLK_1),
119 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
120 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
121 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
122 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
123};
124
125static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
126 FEA_MAP(DPM_PREFETCHER),
127 FEA_MAP(DPM_GFXCLK),
128 FEA_MAP(DPM_UCLK),
129 FEA_MAP(DPM_SOCCLK),
130 FEA_MAP(DPM_MP0CLK),
131 FEA_MAP(DPM_LINK),
132 FEA_MAP(DPM_DCEFCLK),
133 FEA_MAP(MEM_VDDCI_SCALING),
134 FEA_MAP(MEM_MVDD_SCALING),
135 FEA_MAP(DS_GFXCLK),
136 FEA_MAP(DS_SOCCLK),
137 FEA_MAP(DS_LCLK),
138 FEA_MAP(DS_DCEFCLK),
139 FEA_MAP(DS_UCLK),
140 FEA_MAP(GFX_ULV),
141 FEA_MAP(FW_DSTATE),
142 FEA_MAP(GFXOFF),
143 FEA_MAP(BACO),
144 FEA_MAP(RSMU_SMN_CG),
145 FEA_MAP(PPT),
146 FEA_MAP(TDC),
147 FEA_MAP(APCC_PLUS),
148 FEA_MAP(GTHR),
149 FEA_MAP(ACDC),
150 FEA_MAP(VR0HOT),
151 FEA_MAP(VR1HOT),
152 FEA_MAP(FW_CTF),
153 FEA_MAP(FAN_CONTROL),
154 FEA_MAP(THERMAL),
155 FEA_MAP(GFX_DCS),
156 FEA_MAP(RM),
157 FEA_MAP(LED_DISPLAY),
158 FEA_MAP(GFX_SS),
159 FEA_MAP(OUT_OF_BAND_MONITOR),
160 FEA_MAP(TEMP_DEPENDENT_VMIN),
161 FEA_MAP(MMHUB_PG),
162 FEA_MAP(ATHUB_PG),
163};
164
165static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
166 TAB_MAP(PPTABLE),
167 TAB_MAP(WATERMARKS),
168 TAB_MAP(AVFS_PSM_DEBUG),
169 TAB_MAP(AVFS_FUSE_OVERRIDE),
170 TAB_MAP(PMSTATUSLOG),
171 TAB_MAP(SMU_METRICS),
172 TAB_MAP(DRIVER_SMU_CONFIG),
173 TAB_MAP(ACTIVITY_MONITOR_COEFF),
174 TAB_MAP(OVERDRIVE),
175 TAB_MAP(I2C_COMMANDS),
176 TAB_MAP(PACE),
177};
178
1d5ca713
LG		 179static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
180 PWR_MAP(AC),
181 PWR_MAP(DC),
182};
183
b455159c
LG		 184static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
185 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
191 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
192};
193
194static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
195{
196 struct smu_11_0_cmn2aisc_mapping mapping;
197
198 if (index >= SMU_MSG_MAX_COUNT)
199 return -EINVAL;
200
201 mapping = sienna_cichlid_message_map[index];
202 if (!(mapping.valid_mapping)) {
203 return -EINVAL;
204 }
205
206 return mapping.map_to;
207}
208
209static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
210{
211 struct smu_11_0_cmn2aisc_mapping mapping;
212
213 if (index >= SMU_CLK_COUNT)
214 return -EINVAL;
215
216 mapping = sienna_cichlid_clk_map[index];
217 if (!(mapping.valid_mapping)) {
218 return -EINVAL;
219 }
220
221 return mapping.map_to;
222}
223
224static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
225{
226 struct smu_11_0_cmn2aisc_mapping mapping;
227
228 if (index >= SMU_FEATURE_COUNT)
229 return -EINVAL;
230
231 mapping = sienna_cichlid_feature_mask_map[index];
232 if (!(mapping.valid_mapping)) {
233 return -EINVAL;
234 }
235
236 return mapping.map_to;
237}
238
239static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
240{
241 struct smu_11_0_cmn2aisc_mapping mapping;
242
243 if (index >= SMU_TABLE_COUNT)
244 return -EINVAL;
245
246 mapping = sienna_cichlid_table_map[index];
247 if (!(mapping.valid_mapping)) {
248 return -EINVAL;
249 }
250
251 return mapping.map_to;
252}
253
1d5ca713
LG		 254static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index)
255{
256 struct smu_11_0_cmn2aisc_mapping mapping;
257
258 if (index >= SMU_POWER_SOURCE_COUNT)
259 return -EINVAL;
260
261 mapping = sienna_cichlid_pwr_src_map[index];
262 if (!(mapping.valid_mapping)) {
263 return -EINVAL;
264 }
265
266 return mapping.map_to;
267}
268
b455159c
LG		 269static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
270{
271 struct smu_11_0_cmn2aisc_mapping mapping;
272
273 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
274 return -EINVAL;
275
276 mapping = sienna_cichlid_workload_map[profile];
277 if (!(mapping.valid_mapping)) {
278 return -EINVAL;
279 }
280
281 return mapping.map_to;
282}
283
284static int
285sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
286 uint32_t *feature_mask, uint32_t num)
287{
fea905d4
LG		 288 struct amdgpu_device *adev = smu->adev;
289
b455159c
LG		 290 if (num > 2)
291 return -EINVAL;
292
293 memset(feature_mask, 0, sizeof(uint32_t) * num);
294
4cd4f45b 295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 296 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
094cdf15 297 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 298 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
9aa60213
LG		 299 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
300 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
20d71dcc 301 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
886c8bc6
LG		 302 | FEATURE_MASK(FEATURE_PPT_BIT)
303 | FEATURE_MASK(FEATURE_TDC_BIT)
1c58d429 304 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
094cdf15 305 | FEATURE_MASK(FEATURE_THERMAL_BIT);
fea905d4
LG		 306
307 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
309
65297d50
LG		 310 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
312
5cb74353
LG		 313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
315
5f338f70
LG		 316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
318
fea905d4
LG		 319 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 321
62c1ea6b
LG		 322 if (adev->pm.pp_feature & PP_ULV_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
324
02bb391d
LG		 325 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
327
b455159c
LG		 328 return 0;
329}
330
331static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
332{
333 return 0;
334}
335
336static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
337{
338 return 0;
339}
340
341static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
342{
343 struct smu_11_0_powerplay_table *powerplay_table = NULL;
344 struct smu_table_context *table_context = &smu->smu_table;
345 struct smu_baco_context *smu_baco = &smu->smu_baco;
346
347 if (!table_context->power_play_table)
348 return -EINVAL;
349
350 powerplay_table = table_context->power_play_table;
351
352 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
353 sizeof(PPTable_t));
354
355 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
356
357 mutex_lock(&smu_baco->mutex);
358 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
359 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
360 smu_baco->platform_support = true;
361 mutex_unlock(&smu_baco->mutex);
362
363 return 0;
364}
365
366static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
367{
368 struct smu_table_context *smu_table = &smu->smu_table;
369
370 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
371 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
372 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
373 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
374 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
375 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
376 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
377 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
378 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
379 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
380 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
381 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
382 AMDGPU_GEM_DOMAIN_VRAM);
383
384 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
385 if (!smu_table->metrics_table)
386 return -ENOMEM;
387 smu_table->metrics_time = 0;
388
389 return 0;
390}
391
392static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
393 SmuMetrics_t *metrics_table)
394{
395 struct smu_table_context *smu_table= &smu->smu_table;
396 int ret = 0;
397
398 mutex_lock(&smu->metrics_lock);
399 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
400 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
401 (void *)smu_table->metrics_table, false);
402 if (ret) {
403 pr_info("Failed to export SMU metrics table!\n");
404 mutex_unlock(&smu->metrics_lock);
405 return ret;
406 }
407 smu_table->metrics_time = jiffies;
408 }
409
410 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
411 mutex_unlock(&smu->metrics_lock);
412
413 return ret;
414}
415
416static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
417{
418 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
419
420 if (smu_dpm->dpm_context)
421 return -EINVAL;
422
423 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
424 GFP_KERNEL);
425 if (!smu_dpm->dpm_context)
426 return -ENOMEM;
427
428 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
429
430 return 0;
431}
432
433static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
434{
435 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
436 struct smu_table_context *table_context = &smu->smu_table;
437 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
438 PPTable_t *driver_ppt = NULL;
08ccfe08 439 int i;
b455159c
LG		 440
441 driver_ppt = table_context->driver_pptable;
442
443 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
444 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
445
446 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
447 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
448
449 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
450 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
451
452 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
453 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
454
455 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
456 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
457
458 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
459 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
460
461 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
462 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
463
464 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
465 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
466
467 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
468 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
469
08ccfe08
LG		 470 for (i = 0; i < MAX_PCIE_CONF; i++) {
471 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
472 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
473 }
474
b455159c
LG		 475 return 0;
476}
477
478static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
479{
480 struct smu_power_context *smu_power = &smu->smu_power;
481 struct smu_power_gate *power_gate = &smu_power->power_gate;
482 int ret = 0;
483
484 if (enable) {
485 /* vcn dpm on is a prerequisite for vcn power gate messages */
486 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
487 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
488 if (ret)
489 return ret;
490 }
491 power_gate->vcn_gated = false;
492 } else {
493 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
494 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
495 if (ret)
496 return ret;
497 }
498 power_gate->vcn_gated = true;
499 }
500
501 return ret;
502}
503
504static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
505 enum smu_clk_type clk_type,
506 uint32_t *value)
507{
508 int ret = 0, clk_id = 0;
509 SmuMetrics_t metrics;
510
511 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
512 if (ret)
513 return ret;
514
515 clk_id = smu_clk_get_index(smu, clk_type);
516 if (clk_id < 0)
517 return clk_id;
518
519 *value = metrics.CurrClock[clk_id];
520
521 return ret;
522}
523
524static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
525{
526 PPTable_t *pptable = smu->smu_table.driver_pptable;
527 DpmDescriptor_t *dpm_desc = NULL;
528 uint32_t clk_index = 0;
529
530 clk_index = smu_clk_get_index(smu, clk_type);
531 dpm_desc = &pptable->DpmDescriptor[clk_index];
532
533 /* 0 - Fine grained DPM, 1 - Discrete DPM */
534 return dpm_desc->SnapToDiscrete == 0 ? true : false;
535}
536
537static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
538 enum smu_clk_type clk_type, char *buf)
539{
b7d25b5f
LG		 540 struct amdgpu_device *adev = smu->adev;
541 struct smu_table_context *table_context = &smu->smu_table;
542 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
543 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
544 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
b455159c
LG		 545 int i, size = 0, ret = 0;
546 uint32_t cur_value = 0, value = 0, count = 0;
547 uint32_t freq_values[3] = {0};
548 uint32_t mark_index = 0;
b7d25b5f 549 uint32_t gen_speed, lane_width;
b455159c
LG		 550
551 switch (clk_type) {
552 case SMU_GFXCLK:
553 case SMU_SCLK:
554 case SMU_SOCCLK:
555 case SMU_MCLK:
556 case SMU_UCLK:
557 case SMU_FCLK:
558 case SMU_DCEFCLK:
559 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
560 if (ret)
561 return size;
562
563 /* 10KHz -> MHz */
564 cur_value = cur_value / 100;
565
566 ret = smu_get_dpm_level_count(smu, clk_type, &count);
567 if (ret)
568 return size;
569
570 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
571 for (i = 0; i < count; i++) {
572 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
573 if (ret)
574 return size;
575
576 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
577 cur_value == value ? "*" : "");
578 }
579 } else {
580 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
581 if (ret)
582 return size;
583 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
584 if (ret)
585 return size;
586
587 freq_values[1] = cur_value;
588 mark_index = cur_value == freq_values[0] ? 0 :
589 cur_value == freq_values[2] ? 2 : 1;
590 if (mark_index != 1)
591 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
592
593 for (i = 0; i < 3; i++) {
594 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
595 i == mark_index ? "*" : "");
596 }
597
598 }
599 break;
b7d25b5f
LG		 600 case SMU_PCIE:
601 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
602 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
603 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
604 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
605 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
606 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
607 for (i = 0; i < NUM_LINK_LEVELS; i++)
608 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
609 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
610 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
611 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
612 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
613 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
614 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
615 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
616 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
617 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
618 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
619 pptable->LclkFreq[i],
620 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
621 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
622 "*" : "");
623 break;
b455159c
LG		 624 default:
625 break;
626 }
627
628 return size;
629}
630
631static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
632 enum smu_clk_type clk_type, uint32_t mask)
633{
634
635 int ret = 0, size = 0;
636 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
637
638 soft_min_level = mask ? (ffs(mask) - 1) : 0;
639 soft_max_level = mask ? (fls(mask) - 1) : 0;
640
641 switch (clk_type) {
642 case SMU_GFXCLK:
643 case SMU_SCLK:
644 case SMU_SOCCLK:
645 case SMU_MCLK:
646 case SMU_UCLK:
647 case SMU_DCEFCLK:
648 case SMU_FCLK:
9ad9c8ac
LG		 649 /* There is only 2 levels for fine grained DPM */
650 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
651 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
652 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
653 }
654
b455159c
LG		 655 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
656 if (ret)
657 return size;
658
659 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
660 if (ret)
661 return size;
662
663 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
664 if (ret)
665 return size;
666 break;
667 default:
668 break;
669 }
670
671 return size;
672}
673
674static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
675{
676 int ret = 0;
677 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
678
679 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
680 if (ret)
681 return ret;
682
683 smu->pstate_sclk = min_sclk_freq * 100;
684
685 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
686 if (ret)
687 return ret;
688
689 smu->pstate_mclk = min_mclk_freq * 100;
690
691 return ret;
692}
693
694static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
695 enum smu_clk_type clk_type,
696 struct pp_clock_levels_with_latency *clocks)
697{
698 int ret = 0, i = 0;
699 uint32_t level_count = 0, freq = 0;
700
701 switch (clk_type) {
702 case SMU_GFXCLK:
703 case SMU_DCEFCLK:
704 case SMU_SOCCLK:
705 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
706 if (ret)
707 return ret;
708
709 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
710 clocks->num_levels = level_count;
711
712 for (i = 0; i < level_count; i++) {
713 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
714 if (ret)
715 return ret;
716
717 clocks->data[i].clocks_in_khz = freq * 1000;
718 clocks->data[i].latency_in_us = 0;
719 }
720 break;
721 default:
722 break;
723 }
724
725 return ret;
726}
727
728static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
729{
730 int ret = 0;
731 uint32_t max_freq = 0;
732
733 /* Sienna_Cichlid do not support to change display num currently */
734 return 0;
735#if 0
736 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
737 if (ret)
738 return ret;
739#endif
740
741 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
742 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
743 if (ret)
744 return ret;
745 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
746 if (ret)
747 return ret;
748 }
749
750 return ret;
751}
752
753static int sienna_cichlid_display_config_changed(struct smu_context *smu)
754{
755 int ret = 0;
756
757 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
758 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
759 ret = smu_write_watermarks_table(smu);
760 if (ret)
761 return ret;
762
763 smu->watermarks_bitmap |= WATERMARKS_LOADED;
764 }
765
766 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
767 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
768 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
769 /* Sienna_Cichlid do not support to change display num currently */
770 ret = 0;
771#if 0
772 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
773 smu->display_config->num_display, NULL);
774#endif
775 if (ret)
776 return ret;
777 }
778
779 return ret;
780}
781
782static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
783{
784 int ret = 0, i = 0;
785 uint32_t min_freq, max_freq, force_freq;
786 enum smu_clk_type clk_type;
787
788 enum smu_clk_type clks[] = {
789 SMU_GFXCLK,
790 };
791
792 for (i = 0; i < ARRAY_SIZE(clks); i++) {
793 clk_type = clks[i];
794 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
795 if (ret)
796 return ret;
797
798 force_freq = highest ? max_freq : min_freq;
799 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
800 if (ret)
801 return ret;
802 }
803
804 return ret;
805}
806
807static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
808{
809 int ret = 0, i = 0;
810 uint32_t min_freq, max_freq;
811 enum smu_clk_type clk_type;
812
813 enum smu_clk_type clks[] = {
814 SMU_GFXCLK,
815 };
816
817 for (i = 0; i < ARRAY_SIZE(clks); i++) {
818 clk_type = clks[i];
819 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
820 if (ret)
821 return ret;
822
823 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
824 if (ret)
825 return ret;
826 }
827
828 return ret;
829}
830
831static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
832{
833 int ret = 0;
834 SmuMetrics_t metrics;
835
836 if (!value)
837 return -EINVAL;
838
839 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
840 if (ret)
841 return ret;
842
843 *value = metrics.AverageSocketPower << 8;
844
845 return 0;
846}
847
848static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
849 enum amd_pp_sensors sensor,
850 uint32_t *value)
851{
852 int ret = 0;
853 SmuMetrics_t metrics;
854
855 if (!value)
856 return -EINVAL;
857
858 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
859 if (ret)
860 return ret;
861
862 switch (sensor) {
863 case AMDGPU_PP_SENSOR_GPU_LOAD:
864 *value = metrics.AverageGfxActivity;
865 break;
866 case AMDGPU_PP_SENSOR_MEM_LOAD:
867 *value = metrics.AverageUclkActivity;
868 break;
869 default:
870 pr_err("Invalid sensor for retrieving clock activity\n");
871 return -EINVAL;
872 }
873
874 return 0;
875}
876
877static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
878{
879 int ret = 0;
880 uint32_t feature_mask[2];
881 unsigned long feature_enabled;
882 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
883 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
884 ((uint64_t)feature_mask[1] << 32));
885 return !!(feature_enabled & SMC_DPM_FEATURE);
886}
887
888static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
889 uint32_t *speed)
890{
891 SmuMetrics_t metrics;
892 int ret = 0;
893
894 if (!speed)
895 return -EINVAL;
896
897 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
898 if (ret)
899 return ret;
900
901 *speed = metrics.CurrFanSpeed;
902
903 return ret;
904}
905
906static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
907 uint32_t *speed)
908{
909 int ret = 0;
910 uint32_t percent = 0;
911 uint32_t current_rpm;
912 PPTable_t *pptable = smu->smu_table.driver_pptable;
913
914 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
915 if (ret)
916 return ret;
917
918 percent = current_rpm * 100 / pptable->FanMaximumRpm;
919 *speed = percent > 100 ? 100 : percent;
920
921 return ret;
922}
923
924static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
925{
926 DpmActivityMonitorCoeffInt_t activity_monitor;
927 uint32_t i, size = 0;
928 int16_t workload_type = 0;
929 static const char *profile_name[] = {
930 "BOOTUP_DEFAULT",
931 "3D_FULL_SCREEN",
932 "POWER_SAVING",
933 "VIDEO",
934 "VR",
935 "COMPUTE",
936 "CUSTOM"};
937 static const char *title[] = {
938 "PROFILE_INDEX(NAME)",
939 "CLOCK_TYPE(NAME)",
940 "FPS",
941 "MinFreqType",
942 "MinActiveFreqType",
943 "MinActiveFreq",
944 "BoosterFreqType",
945 "BoosterFreq",
946 "PD_Data_limit_c",
947 "PD_Data_error_coeff",
948 "PD_Data_error_rate_coeff"};
949 int result = 0;
950
951 if (!buf)
952 return -EINVAL;
953
954 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
955 title[0], title[1], title[2], title[3], title[4], title[5],
956 title[6], title[7], title[8], title[9], title[10]);
957
958 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
959 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
960 workload_type = smu_workload_get_type(smu, i);
961 if (workload_type < 0)
962 return -EINVAL;
963
964 result = smu_update_table(smu,
965 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
966 (void *)(&activity_monitor), false);
967 if (result) {
968 pr_err("[%s] Failed to get activity monitor!", __func__);
969 return result;
970 }
971
972 size += sprintf(buf + size, "%2d %14s%s:\n",
973 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
974
975 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
976 " ",
977 0,
978 "GFXCLK",
979 activity_monitor.Gfx_FPS,
980 activity_monitor.Gfx_MinFreqStep,
981 activity_monitor.Gfx_MinActiveFreqType,
982 activity_monitor.Gfx_MinActiveFreq,
983 activity_monitor.Gfx_BoosterFreqType,
984 activity_monitor.Gfx_BoosterFreq,
985 activity_monitor.Gfx_PD_Data_limit_c,
986 activity_monitor.Gfx_PD_Data_error_coeff,
987 activity_monitor.Gfx_PD_Data_error_rate_coeff);
988
989 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
990 " ",
991 1,
992 "SOCCLK",
993 activity_monitor.Fclk_FPS,
994 activity_monitor.Fclk_MinFreqStep,
995 activity_monitor.Fclk_MinActiveFreqType,
996 activity_monitor.Fclk_MinActiveFreq,
997 activity_monitor.Fclk_BoosterFreqType,
998 activity_monitor.Fclk_BoosterFreq,
999 activity_monitor.Fclk_PD_Data_limit_c,
1000 activity_monitor.Fclk_PD_Data_error_coeff,
1001 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1002
1003 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1004 " ",
1005 2,
1006 "MEMLK",
1007 activity_monitor.Mem_FPS,
1008 activity_monitor.Mem_MinFreqStep,
1009 activity_monitor.Mem_MinActiveFreqType,
1010 activity_monitor.Mem_MinActiveFreq,
1011 activity_monitor.Mem_BoosterFreqType,
1012 activity_monitor.Mem_BoosterFreq,
1013 activity_monitor.Mem_PD_Data_limit_c,
1014 activity_monitor.Mem_PD_Data_error_coeff,
1015 activity_monitor.Mem_PD_Data_error_rate_coeff);
1016 }
1017
1018 return size;
1019}
1020
1021static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1022{
1023 DpmActivityMonitorCoeffInt_t activity_monitor;
1024 int workload_type, ret = 0;
1025
1026 smu->power_profile_mode = input[size];
1027
1028 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1029 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1030 return -EINVAL;
1031 }
1032
1033 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1034 if (size < 0)
1035 return -EINVAL;
1036
1037 ret = smu_update_table(smu,
1038 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1039 (void *)(&activity_monitor), false);
1040 if (ret) {
1041 pr_err("[%s] Failed to get activity monitor!", __func__);
1042 return ret;
1043 }
1044
1045 switch (input[0]) {
1046 case 0: /* Gfxclk */
1047 activity_monitor.Gfx_FPS = input[1];
1048 activity_monitor.Gfx_MinFreqStep = input[2];
1049 activity_monitor.Gfx_MinActiveFreqType = input[3];
1050 activity_monitor.Gfx_MinActiveFreq = input[4];
1051 activity_monitor.Gfx_BoosterFreqType = input[5];
1052 activity_monitor.Gfx_BoosterFreq = input[6];
1053 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1054 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1055 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1056 break;
1057 case 1: /* Socclk */
1058 activity_monitor.Fclk_FPS = input[1];
1059 activity_monitor.Fclk_MinFreqStep = input[2];
1060 activity_monitor.Fclk_MinActiveFreqType = input[3];
1061 activity_monitor.Fclk_MinActiveFreq = input[4];
1062 activity_monitor.Fclk_BoosterFreqType = input[5];
1063 activity_monitor.Fclk_BoosterFreq = input[6];
1064 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1065 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1066 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1067 break;
1068 case 2: /* Memlk */
1069 activity_monitor.Mem_FPS = input[1];
1070 activity_monitor.Mem_MinFreqStep = input[2];
1071 activity_monitor.Mem_MinActiveFreqType = input[3];
1072 activity_monitor.Mem_MinActiveFreq = input[4];
1073 activity_monitor.Mem_BoosterFreqType = input[5];
1074 activity_monitor.Mem_BoosterFreq = input[6];
1075 activity_monitor.Mem_PD_Data_limit_c = input[7];
1076 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1077 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1078 break;
1079 }
1080
1081 ret = smu_update_table(smu,
1082 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1083 (void *)(&activity_monitor), true);
1084 if (ret) {
1085 pr_err("[%s] Failed to set activity monitor!", __func__);
1086 return ret;
1087 }
1088 }
1089
1090 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1091 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1092 if (workload_type < 0)
1093 return -EINVAL;
1094 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1095 1 << workload_type, NULL);
1096
1097 return ret;
1098}
1099
1100static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1101 enum amd_dpm_forced_level level,
1102 uint32_t *sclk_mask,
1103 uint32_t *mclk_mask,
1104 uint32_t *soc_mask)
1105{
1106 int ret = 0;
1107 uint32_t level_count = 0;
1108
1109 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1110 if (sclk_mask)
1111 *sclk_mask = 0;
1112 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1113 if (mclk_mask)
1114 *mclk_mask = 0;
1115 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1116 if(sclk_mask) {
1117 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1118 if (ret)
1119 return ret;
1120 *sclk_mask = level_count - 1;
1121 }
1122
1123 if(mclk_mask) {
1124 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1125 if (ret)
1126 return ret;
1127 *mclk_mask = level_count - 1;
1128 }
1129
1130 if(soc_mask) {
1131 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1132 if (ret)
1133 return ret;
1134 *soc_mask = level_count - 1;
1135 }
1136 }
1137
1138 return ret;
1139}
1140
1141static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1142{
1143 struct smu_clocks min_clocks = {0};
1144 struct pp_display_clock_request clock_req;
1145 int ret = 0;
1146
1147 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1148 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1149 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1150
1151 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1152 clock_req.clock_type = amd_pp_dcef_clock;
1153 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1154
1155 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1156 if (!ret) {
1157 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1158 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1159 return ret;
1160 }
1161 } else {
1162 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1163 }
1164 }
1165
1166 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1167 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1168 if (ret) {
1169 pr_err("[%s] Set hard min uclk failed!", __func__);
1170 return ret;
1171 }
1172 }
1173
1174 return 0;
1175}
1176
1177static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1178 void *watermarks, struct
1179 dm_pp_wm_sets_with_clock_ranges_soc15
1180 *clock_ranges)
1181{
1182 int i;
1183 Watermarks_t *table = watermarks;
1184
1185 if (!table || !clock_ranges)
1186 return -EINVAL;
1187
1188 if (clock_ranges->num_wm_dmif_sets > 4 ||
1189 clock_ranges->num_wm_mcif_sets > 4)
1190 return -EINVAL;
1191
1192 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1193 table->WatermarkRow[1][i].MinClock =
1194 cpu_to_le16((uint16_t)
1195 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1196 1000));
1197 table->WatermarkRow[1][i].MaxClock =
1198 cpu_to_le16((uint16_t)
1199 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1200 1000));
1201 table->WatermarkRow[1][i].MinUclk =
1202 cpu_to_le16((uint16_t)
1203 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1204 1000));
1205 table->WatermarkRow[1][i].MaxUclk =
1206 cpu_to_le16((uint16_t)
1207 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1208 1000));
1209 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1210 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1211 }
1212
1213 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1214 table->WatermarkRow[0][i].MinClock =
1215 cpu_to_le16((uint16_t)
1216 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1217 1000));
1218 table->WatermarkRow[0][i].MaxClock =
1219 cpu_to_le16((uint16_t)
1220 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1221 1000));
1222 table->WatermarkRow[0][i].MinUclk =
1223 cpu_to_le16((uint16_t)
1224 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1225 1000));
1226 table->WatermarkRow[0][i].MaxUclk =
1227 cpu_to_le16((uint16_t)
1228 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1229 1000));
1230 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1231 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1232 }
1233
1234 return 0;
1235}
1236
1237static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1238 enum amd_pp_sensors sensor,
1239 uint32_t *value)
1240{
1241 SmuMetrics_t metrics;
1242 int ret = 0;
1243
1244 if (!value)
1245 return -EINVAL;
1246
1247 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1248 if (ret)
1249 return ret;
1250
1251 switch (sensor) {
1252 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1253 *value = metrics.TemperatureHotspot *
1254 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1255 break;
1256 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1257 *value = metrics.TemperatureEdge *
1258 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1259 break;
1260 case AMDGPU_PP_SENSOR_MEM_TEMP:
1261 *value = metrics.TemperatureMem *
1262 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1263 break;
1264 default:
1265 pr_err("Invalid sensor for retrieving temp\n");
1266 return -EINVAL;
1267 }
1268
1269 return 0;
1270}
1271
1272static int sienna_cichlid_read_sensor(struct smu_context *smu,
1273 enum amd_pp_sensors sensor,
1274 void *data, uint32_t *size)
1275{
1276 int ret = 0;
1277 struct smu_table_context *table_context = &smu->smu_table;
1278 PPTable_t *pptable = table_context->driver_pptable;
1279
1280 if(!data || !size)
1281 return -EINVAL;
1282
1283 mutex_lock(&smu->sensor_lock);
1284 switch (sensor) {
1285 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1286 *(uint32_t *)data = pptable->FanMaximumRpm;
1287 *size = 4;
1288 break;
1289 case AMDGPU_PP_SENSOR_MEM_LOAD:
1290 case AMDGPU_PP_SENSOR_GPU_LOAD:
1291 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1292 *size = 4;
1293 break;
1294 case AMDGPU_PP_SENSOR_GPU_POWER:
1295 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1296 *size = 4;
1297 break;
1298 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1299 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1300 case AMDGPU_PP_SENSOR_MEM_TEMP:
1301 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1302 *size = 4;
1303 break;
1304 default:
1305 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1306 }
1307 mutex_unlock(&smu->sensor_lock);
1308
1309 return ret;
1310}
1311
1312static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1313{
1314 uint32_t num_discrete_levels = 0;
1315 uint16_t *dpm_levels = NULL;
1316 uint16_t i = 0;
1317 struct smu_table_context *table_context = &smu->smu_table;
1318 PPTable_t *driver_ppt = NULL;
1319
1320 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1321 return -EINVAL;
1322
1323 driver_ppt = table_context->driver_pptable;
1324 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1325 dpm_levels = driver_ppt->FreqTableUclk;
1326
1327 if (num_discrete_levels == 0 || dpm_levels == NULL)
1328 return -EINVAL;
1329
1330 *num_states = num_discrete_levels;
1331 for (i = 0; i < num_discrete_levels; i++) {
1332 /* convert to khz */
1333 *clocks_in_khz = (*dpm_levels) * 1000;
1334 clocks_in_khz++;
1335 dpm_levels++;
1336 }
1337
1338 return 0;
1339}
1340
9ad9c8ac
LG		 1341static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1342 enum amd_dpm_forced_level level);
1343
1344static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1345{
1346 struct amdgpu_device *adev = smu->adev;
1347 int ret = 0;
1348 uint32_t sclk_freq = 0, uclk_freq = 0;
1349
1350 switch (adev->asic_type) {
1351 /* TODO: need to set specify clk value by asic type, not support yet*/
1352 default:
1353 /* by default, this is same as auto performance level */
1354 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1355 }
1356
1357 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1358 if (ret)
1359 return ret;
1360 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1361 if (ret)
1362 return ret;
1363
1364 return ret;
1365}
1366
1367static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1368{
1369 int ret = 0;
1370
1371 /* TODO: not support yet*/
1372 return ret;
1373}
1374
1375static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1376 enum amd_dpm_forced_level level)
1377{
1378 int ret = 0;
1379 uint32_t sclk_mask, mclk_mask, soc_mask;
1380
1381 switch (level) {
1382 case AMD_DPM_FORCED_LEVEL_HIGH:
1383 ret = smu_force_dpm_limit_value(smu, true);
1384 break;
1385 case AMD_DPM_FORCED_LEVEL_LOW:
1386 ret = smu_force_dpm_limit_value(smu, false);
1387 break;
1388 case AMD_DPM_FORCED_LEVEL_AUTO:
1389 ret = smu_unforce_dpm_levels(smu);
1390 break;
1391 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1392 ret = sienna_cichlid_set_standard_performance_level(smu);
1393 break;
1394 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1395 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1396 ret = smu_get_profiling_clk_mask(smu, level,
1397 &sclk_mask,
1398 &mclk_mask,
1399 &soc_mask);
1400 if (ret)
1401 return ret;
1402 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1403 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1404 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1405 break;
1406 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1407 ret = sienna_cichlid_set_peak_performance_level(smu);
1408 break;
1409 case AMD_DPM_FORCED_LEVEL_MANUAL:
1410 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1411 default:
1412 break;
1413 }
1414 return ret;
1415}
1416
b455159c
LG		 1417static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1418 struct smu_temperature_range *range)
1419{
1420 struct smu_table_context *table_context = &smu->smu_table;
1421 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1422
1423 if (!range || !powerplay_table)
1424 return -EINVAL;
1425
1426 range->max = powerplay_table->software_shutdown_temp *
1427 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1428
1429 return 0;
1430}
1431
1432static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1433 bool disable_memory_clock_switch)
1434{
1435 int ret = 0;
1436 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1437 (struct smu_11_0_max_sustainable_clocks *)
1438 smu->smu_table.max_sustainable_clocks;
1439 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1440 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1441
1442 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1443 return 0;
1444
1445 if(disable_memory_clock_switch)
1446 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1447 else
1448 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1449
1450 if(!ret)
1451 smu->disable_uclk_switch = disable_memory_clock_switch;
1452
1453 return ret;
1454}
1455
1456static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1457 uint32_t *limit,
1458 bool cap)
1459{
1460 PPTable_t *pptable = smu->smu_table.driver_pptable;
1461 uint32_t asic_default_power_limit = 0;
1462 int ret = 0;
1463 int power_src;
1464
1465 if (!smu->power_limit) {
1466 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1467 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1468 if (power_src < 0)
1469 return -EINVAL;
1470
1471 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1472 power_src << 16, &asic_default_power_limit);
1473 if (ret) {
1474 pr_err("[%s] get PPT limit failed!", __func__);
1475 return ret;
1476 }
1477 } else {
1478 /* the last hope to figure out the ppt limit */
1479 if (!pptable) {
1480 pr_err("Cannot get PPT limit due to pptable missing!");
1481 return -EINVAL;
1482 }
1483 asic_default_power_limit =
1484 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1485 }
1486
1487 smu->power_limit = asic_default_power_limit;
1488 }
1489
1490 if (cap)
1491 *limit = smu_v11_0_get_max_power_limit(smu);
1492 else
1493 *limit = smu->power_limit;
1494
1495 return 0;
1496}
1497
08ccfe08
LG		 1498static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1499 uint32_t pcie_gen_cap,
1500 uint32_t pcie_width_cap)
1501{
1502 PPTable_t *pptable = smu->smu_table.driver_pptable;
1503 int ret, i;
1504 uint32_t smu_pcie_arg;
1505
1506 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1507 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1508
1509 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1510 smu_pcie_arg = (i << 16) |
1511 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1512 (pptable->PcieGenSpeed[i] << 8) :
1513 (pcie_gen_cap << 8)) |
1514 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1515 pptable->PcieLaneCount[i] :
1516 pcie_width_cap);
1517
1518 ret = smu_send_smc_msg_with_param(smu,
1519 SMU_MSG_OverridePcieParameters,
1520 smu_pcie_arg, NULL);
1521 if (ret)
1522 return ret;
1523
1524 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1525 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1526 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1527 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1528 }
1529
1530 return 0;
1531}
1532
b455159c
LG		 1533static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1534{
1535 struct smu_table_context *table_context = &smu->smu_table;
1536 PPTable_t *pptable = table_context->driver_pptable;
1537 int i;
1538
1539 pr_info("Dumped PPTable:\n");
1540
1541 pr_info("Version = 0x%08x\n", pptable->Version);
1542 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1543 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1544
1545 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1546 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1547 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1548 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1549 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1550 }
1551
1552 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1553 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1554 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1555 }
1556
1557 for (i = 0; i < TEMP_COUNT; i++) {
1558 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1559 }
1560
1561 pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1562 pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1563 pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1564 pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1565 pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1566
1567 pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1568 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1569 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1570 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1571 }
1572 pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1573 pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1574 pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1575 pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1576
1577 pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1578
1579 pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1580
1581 pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1582 pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1583 pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1584 pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1585
1586 pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1587 pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1588
1589 pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1590 pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1591 pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1592 pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1593
1594 pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1595 pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1596 pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1597 pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1598
1599 pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1600 pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1601
1602 pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1603 pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1604 pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1605 pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1606 pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1607 pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1608 pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1609 pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1610
1611 pr_info("[PPCLK_GFXCLK]\n"
1612 " .VoltageMode = 0x%02x\n"
1613 " .SnapToDiscrete = 0x%02x\n"
1614 " .NumDiscreteLevels = 0x%02x\n"
1615 " .padding = 0x%02x\n"
1616 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1617 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1618 " .SsFmin = 0x%04x\n"
1619 " .Padding_16 = 0x%04x\n",
1620 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1621 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1622 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1623 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1624 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1625 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1626 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1627 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1628 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1629 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1630 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1631
1632 pr_info("[PPCLK_SOCCLK]\n"
1633 " .VoltageMode = 0x%02x\n"
1634 " .SnapToDiscrete = 0x%02x\n"
1635 " .NumDiscreteLevels = 0x%02x\n"
1636 " .padding = 0x%02x\n"
1637 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1638 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1639 " .SsFmin = 0x%04x\n"
1640 " .Padding_16 = 0x%04x\n",
1641 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1642 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1643 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1644 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1645 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1646 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1647 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1648 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1649 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1650 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1651 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1652
1653 pr_info("[PPCLK_UCLK]\n"
1654 " .VoltageMode = 0x%02x\n"
1655 " .SnapToDiscrete = 0x%02x\n"
1656 " .NumDiscreteLevels = 0x%02x\n"
1657 " .padding = 0x%02x\n"
1658 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1659 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1660 " .SsFmin = 0x%04x\n"
1661 " .Padding_16 = 0x%04x\n",
1662 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1663 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1664 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1665 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1666 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1667 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1668 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1669 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1670 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1671 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1672 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1673
1674 pr_info("[PPCLK_FCLK]\n"
1675 " .VoltageMode = 0x%02x\n"
1676 " .SnapToDiscrete = 0x%02x\n"
1677 " .NumDiscreteLevels = 0x%02x\n"
1678 " .padding = 0x%02x\n"
1679 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1680 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1681 " .SsFmin = 0x%04x\n"
1682 " .Padding_16 = 0x%04x\n",
1683 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1684 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1685 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1686 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1687 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1688 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1689 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1690 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1691 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1692 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1693 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1694
1695 pr_info("[PPCLK_DCLK_0]\n"
1696 " .VoltageMode = 0x%02x\n"
1697 " .SnapToDiscrete = 0x%02x\n"
1698 " .NumDiscreteLevels = 0x%02x\n"
1699 " .padding = 0x%02x\n"
1700 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1701 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1702 " .SsFmin = 0x%04x\n"
1703 " .Padding_16 = 0x%04x\n",
1704 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1705 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1706 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1707 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1708 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1709 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1710 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1711 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1712 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1713 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1714 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1715
1716 pr_info("[PPCLK_VCLK_0]\n"
1717 " .VoltageMode = 0x%02x\n"
1718 " .SnapToDiscrete = 0x%02x\n"
1719 " .NumDiscreteLevels = 0x%02x\n"
1720 " .padding = 0x%02x\n"
1721 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1722 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1723 " .SsFmin = 0x%04x\n"
1724 " .Padding_16 = 0x%04x\n",
1725 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1726 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1727 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1728 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1729 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1730 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1731 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1732 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1733 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1734 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1735 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1736
1737 pr_info("[PPCLK_DCLK_1]\n"
1738 " .VoltageMode = 0x%02x\n"
1739 " .SnapToDiscrete = 0x%02x\n"
1740 " .NumDiscreteLevels = 0x%02x\n"
1741 " .padding = 0x%02x\n"
1742 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1743 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1744 " .SsFmin = 0x%04x\n"
1745 " .Padding_16 = 0x%04x\n",
1746 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1747 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1748 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1749 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1750 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1751 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1752 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1753 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1754 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1755 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1756 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1757
1758 pr_info("[PPCLK_VCLK_1]\n"
1759 " .VoltageMode = 0x%02x\n"
1760 " .SnapToDiscrete = 0x%02x\n"
1761 " .NumDiscreteLevels = 0x%02x\n"
1762 " .padding = 0x%02x\n"
1763 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1764 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1765 " .SsFmin = 0x%04x\n"
1766 " .Padding_16 = 0x%04x\n",
1767 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1768 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1769 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1770 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1771 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1772 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1773 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1774 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1775 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1776 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1777 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1778
1779 pr_info("FreqTableGfx\n");
1780 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1781 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1782
1783 pr_info("FreqTableVclk\n");
1784 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1785 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1786
1787 pr_info("FreqTableDclk\n");
1788 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1789 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1790
1791 pr_info("FreqTableSocclk\n");
1792 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1793 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1794
1795 pr_info("FreqTableUclk\n");
1796 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1797 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1798
1799 pr_info("FreqTableFclk\n");
1800 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1801 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1802
1803 pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
1804 pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
1805 pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
1806 pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
1807 pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
1808 pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
1809 pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
1810 pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
1811 pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
1812 pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
1813 pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1814 pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1815 pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1816 pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1817 pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1818 pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1819
1820 pr_info("DcModeMaxFreq\n");
1821 pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1822 pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1823 pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1824 pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1825 pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1826 pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1827 pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1828 pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1829
1830 pr_info("FreqTableUclkDiv\n");
1831 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1832 pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1833
1834 pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1835 pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1836
1837 pr_info("Mp0clkFreq\n");
1838 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1839 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1840
1841 pr_info("Mp0DpmVoltage\n");
1842 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1843 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1844
1845 pr_info("MemVddciVoltage\n");
1846 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1847 pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1848
1849 pr_info("MemMvddVoltage\n");
1850 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1851 pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1852
1853 pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1854 pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1855 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1856 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1857 pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1858
1859 pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1860
1861 pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1862 pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1863 pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1864 pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1865 pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1866 pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1867 pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1868 pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1869 pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1870 pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1871 pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1872
1873 pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1874 pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1875 pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1876 pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1877 pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1878 pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1879
1880 pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1881 pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1882 pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1883 pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1884 pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1885
1886 pr_info("FlopsPerByteTable\n");
1887 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1888 pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1889
1890 pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1891 pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1892 pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1893 pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1894
1895 pr_info("UclkDpmPstates\n");
1896 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1897 pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1898
1899 pr_info("UclkDpmSrcFreqRange\n");
1900 pr_info(" .Fmin = 0x%x\n",
1901 pptable->UclkDpmSrcFreqRange.Fmin);
1902 pr_info(" .Fmax = 0x%x\n",
1903 pptable->UclkDpmSrcFreqRange.Fmax);
1904 pr_info("UclkDpmTargFreqRange\n");
1905 pr_info(" .Fmin = 0x%x\n",
1906 pptable->UclkDpmTargFreqRange.Fmin);
1907 pr_info(" .Fmax = 0x%x\n",
1908 pptable->UclkDpmTargFreqRange.Fmax);
1909 pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1910 pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1911
1912 pr_info("PcieGenSpeed\n");
1913 for (i = 0; i < NUM_LINK_LEVELS; i++)
1914 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1915
1916 pr_info("PcieLaneCount\n");
1917 for (i = 0; i < NUM_LINK_LEVELS; i++)
1918 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1919
1920 pr_info("LclkFreq\n");
1921 for (i = 0; i < NUM_LINK_LEVELS; i++)
1922 pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1923
1924 pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1925 pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1926
1927 pr_info("FanGain\n");
1928 for (i = 0; i < TEMP_COUNT; i++)
1929 pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1930
1931 pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1932 pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1933 pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1934 pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1935 pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1936 pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1937 pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1938 pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1939 pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1940 pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1941 pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1942 pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1943
1944 pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1945 pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1946 pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1947 pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1948
1949 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1950 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1951 pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
1952 pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
1953
1954 pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1955 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
1956 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
1957 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
1958 pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1959 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
1960 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
1961 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
1962 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1963 pptable->dBtcGbGfxPll.a,
1964 pptable->dBtcGbGfxPll.b,
1965 pptable->dBtcGbGfxPll.c);
1966 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1967 pptable->dBtcGbGfxDfll.a,
1968 pptable->dBtcGbGfxDfll.b,
1969 pptable->dBtcGbGfxDfll.c);
1970 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1971 pptable->dBtcGbSoc.a,
1972 pptable->dBtcGbSoc.b,
1973 pptable->dBtcGbSoc.c);
1974 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1975 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1976 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1977 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1978 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1979 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1980
1981 pr_info("PiecewiseLinearDroopIntGfxDfll\n");
1982 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
1983 pr_info(" Fset[%d] = 0x%x\n",
1984 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
1985 pr_info(" Vdroop[%d] = 0x%x\n",
1986 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
1987 }
1988
1989 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1990 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1991 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1992 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1993 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1994 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1995 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1996 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1997
1998 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1999 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2000
2001 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2002 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2003 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2004 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2005
2006 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2007 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2008 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2009 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2010
2011 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2012 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2013
2014 pr_info("XgmiDpmPstates\n");
2015 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2016 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2017 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2018 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2019
2020 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2021 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2022 pptable->ReservedEquation0.a,
2023 pptable->ReservedEquation0.b,
2024 pptable->ReservedEquation0.c);
2025 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2026 pptable->ReservedEquation1.a,
2027 pptable->ReservedEquation1.b,
2028 pptable->ReservedEquation1.c);
2029 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2030 pptable->ReservedEquation2.a,
2031 pptable->ReservedEquation2.b,
2032 pptable->ReservedEquation2.c);
2033 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2034 pptable->ReservedEquation3.a,
2035 pptable->ReservedEquation3.b,
2036 pptable->ReservedEquation3.c);
2037
2038 pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2039 pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2040 pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2041 pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2042 pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2043 pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2044 pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2045 pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2046 pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2047 pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2048 pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2049 pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2050 pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2051 pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2052 pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
2053
2054 pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2055 pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2056 pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2057 pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2058 pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2059 pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2060
2061 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2062 pr_info("I2cControllers[%d]:\n", i);
2063 pr_info(" .Enabled = 0x%x\n",
2064 pptable->I2cControllers[i].Enabled);
2065 pr_info(" .Speed = 0x%x\n",
2066 pptable->I2cControllers[i].Speed);
2067 pr_info(" .SlaveAddress = 0x%x\n",
2068 pptable->I2cControllers[i].SlaveAddress);
2069 pr_info(" .ControllerPort = 0x%x\n",
2070 pptable->I2cControllers[i].ControllerPort);
2071 pr_info(" .ControllerName = 0x%x\n",
2072 pptable->I2cControllers[i].ControllerName);
2073 pr_info(" .ThermalThrottler = 0x%x\n",
2074 pptable->I2cControllers[i].ThermalThrotter);
2075 pr_info(" .I2cProtocol = 0x%x\n",
2076 pptable->I2cControllers[i].I2cProtocol);
2077 pr_info(" .PaddingConfig = 0x%x\n",
2078 pptable->I2cControllers[i].PaddingConfig);
2079 }
2080
2081 pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
2082 pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
2083 pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2084 pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2085
2086 pr_info("Board Parameters:\n");
2087 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2088 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2089 pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2090 pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2091 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2092 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2093 pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2094 pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2095
2096 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2097 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
2098 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2099
2100 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2101 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
2102 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2103
2104 pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2105 pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2106 pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2107
2108 pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2109 pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2110 pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2111
2112 pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2113
2114 pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2115 pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2116 pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2117 pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2118 pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2119 pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2120 pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2121 pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2122 pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2123 pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2124 pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2125 pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2126 pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2127 pr_info("LedError = 0x%x\n", pptable->LedError);
2128 pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2129 pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2130
2131 pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2132 pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2133 pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2134
2135 pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2136 pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2137 pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2138
2139 pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2140 pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2141 pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2142
2143 pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2144 pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2145 pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2146
2147 pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2148 pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2149 pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2150 pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2151 pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2152
2153 pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2154 pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2155
2156 pr_info("XgmiLinkSpeed\n");
2157 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2158 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2159 pr_info("XgmiLinkWidth\n");
2160 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2161 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2162 pr_info("XgmiFclkFreq\n");
2163 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2164 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2165 pr_info("XgmiSocVoltage\n");
2166 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2167 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2168
2169 pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2170 pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2171 pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2172 pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2173
2174 pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2175 pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2176 pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2177 pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2178 pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2179 pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2180 pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2181 pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2182 pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2183 pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2184 pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2185 pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2186 pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2187 pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2188 pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2189
2190 pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2191 pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2192 pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2193 pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2194 pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2195 pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2196 pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2197 pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2198}
2199
2200static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2201 .tables_init = sienna_cichlid_tables_init,
2202 .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2203 .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2204 .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2205 .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2206 .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2207 .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2208 .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2209 .get_smu_table_index = sienna_cichlid_get_smu_table_index,
1d5ca713 2210 .get_smu_power_index = sienna_cichlid_get_pwr_src_index,
b455159c
LG		 2211 .get_workload_type = sienna_cichlid_get_workload_type,
2212 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2213 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2214 .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2215 .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2216 .print_clk_levels = sienna_cichlid_print_clk_levels,
2217 .force_clk_levels = sienna_cichlid_force_clk_levels,
2218 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2219 .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2220 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2221 .display_config_changed = sienna_cichlid_display_config_changed,
2222 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2223 .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2224 .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2225 .is_dpm_running = sienna_cichlid_is_dpm_running,
2226 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2227 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2228 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2229 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2230 .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2231 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2232 .read_sensor = sienna_cichlid_read_sensor,
2233 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
9ad9c8ac 2234 .set_performance_level = sienna_cichlid_set_performance_level,
b455159c
LG		 2235 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2236 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2237 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2238 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2239 .dump_pptable = sienna_cichlid_dump_pptable,
2240 .init_microcode = smu_v11_0_init_microcode,
2241 .load_microcode = smu_v11_0_load_microcode,
2242 .init_smc_tables = smu_v11_0_init_smc_tables,
2243 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2244 .init_power = smu_v11_0_init_power,
2245 .fini_power = smu_v11_0_fini_power,
2246 .check_fw_status = smu_v11_0_check_fw_status,
2247 .setup_pptable = smu_v11_0_setup_pptable,
2248 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2249 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2250 .check_pptable = smu_v11_0_check_pptable,
2251 .parse_pptable = smu_v11_0_parse_pptable,
2252 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2253 .check_fw_version = smu_v11_0_check_fw_version,
2254 .write_pptable = smu_v11_0_write_pptable,
2255 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2256 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2257 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2258 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2259 .system_features_control = smu_v11_0_system_features_control,
2260 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2261 .init_display_count = smu_v11_0_init_display_count,
2262 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2263 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2264 .notify_display_change = smu_v11_0_notify_display_change,
2265 .set_power_limit = smu_v11_0_set_power_limit,
2266 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2267 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2268 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2269 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2270 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2271 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2272 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2273 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2274 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2275 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2276 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2277 .gfx_off_control = smu_v11_0_gfx_off_control,
2278 .register_irq_handler = smu_v11_0_register_irq_handler,
2279 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2280 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2281 .baco_is_support= smu_v11_0_baco_is_support,
2282 .baco_get_state = smu_v11_0_baco_get_state,
2283 .baco_set_state = smu_v11_0_baco_set_state,
2284 .baco_enter = smu_v11_0_baco_enter,
2285 .baco_exit = smu_v11_0_baco_exit,
2286 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2287 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2288 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2289};
2290
2291void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2292{
2293 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2294}
Linux 6.x block layer and io_uring tree(s)