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drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include <linux/pci.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "smu_internal.h"
30#include "atomfirmware.h"
31#include "amdgpu_atomfirmware.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_sienna_cichlid.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "sienna_cichlid_ppt.h"
37#include "smu_v11_0_pptable.h"
38#include "smu_v11_0_7_ppsmc.h"
39
40#include "asic_reg/mp/mp_11_0_sh_mask.h"
41
42#define FEATURE_MASK(feature) (1ULL << feature)
43#define SMC_DPM_FEATURE ( \
44 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 45 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 46 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
4cd4f45b
LG		 47 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
48 FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
b455159c
LG		 49
50#define MSG_MAP(msg, index) \
51 [SMU_MSG_##msg] = {1, (index)}
52
53static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
54 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
55 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
56 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
57 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
58 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
59 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
60 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
61 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
62 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
63 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
64 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
65 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
66 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
67 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
68 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
69 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
70 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
71 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
72 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
73 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
74 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
75 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
76 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
77 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
78 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
79 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
80 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
81 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
82 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
83 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
84 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
85 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
86 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
87 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
88 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
89 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
90 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
91 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
92 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
93 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
94 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
95 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
96 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
97 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
98 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
99 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
101 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
102 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
103};
104
105static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
106 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
107 CLK_MAP(SCLK, PPCLK_GFXCLK),
108 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
109 CLK_MAP(FCLK, PPCLK_FCLK),
110 CLK_MAP(UCLK, PPCLK_UCLK),
111 CLK_MAP(MCLK, PPCLK_UCLK),
112 CLK_MAP(DCLK, PPCLK_DCLK_0),
113 CLK_MAP(DCLK1, PPCLK_DCLK_0),
114 CLK_MAP(VCLK, PPCLK_VCLK_1),
115 CLK_MAP(VCLK1, PPCLK_VCLK_1),
116 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
117 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
118 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
119 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
120};
121
122static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
123 FEA_MAP(DPM_PREFETCHER),
124 FEA_MAP(DPM_GFXCLK),
125 FEA_MAP(DPM_UCLK),
126 FEA_MAP(DPM_SOCCLK),
127 FEA_MAP(DPM_MP0CLK),
128 FEA_MAP(DPM_LINK),
129 FEA_MAP(DPM_DCEFCLK),
130 FEA_MAP(MEM_VDDCI_SCALING),
131 FEA_MAP(MEM_MVDD_SCALING),
132 FEA_MAP(DS_GFXCLK),
133 FEA_MAP(DS_SOCCLK),
134 FEA_MAP(DS_LCLK),
135 FEA_MAP(DS_DCEFCLK),
136 FEA_MAP(DS_UCLK),
137 FEA_MAP(GFX_ULV),
138 FEA_MAP(FW_DSTATE),
139 FEA_MAP(GFXOFF),
140 FEA_MAP(BACO),
141 FEA_MAP(RSMU_SMN_CG),
142 FEA_MAP(PPT),
143 FEA_MAP(TDC),
144 FEA_MAP(APCC_PLUS),
145 FEA_MAP(GTHR),
146 FEA_MAP(ACDC),
147 FEA_MAP(VR0HOT),
148 FEA_MAP(VR1HOT),
149 FEA_MAP(FW_CTF),
150 FEA_MAP(FAN_CONTROL),
151 FEA_MAP(THERMAL),
152 FEA_MAP(GFX_DCS),
153 FEA_MAP(RM),
154 FEA_MAP(LED_DISPLAY),
155 FEA_MAP(GFX_SS),
156 FEA_MAP(OUT_OF_BAND_MONITOR),
157 FEA_MAP(TEMP_DEPENDENT_VMIN),
158 FEA_MAP(MMHUB_PG),
159 FEA_MAP(ATHUB_PG),
160};
161
162static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
163 TAB_MAP(PPTABLE),
164 TAB_MAP(WATERMARKS),
165 TAB_MAP(AVFS_PSM_DEBUG),
166 TAB_MAP(AVFS_FUSE_OVERRIDE),
167 TAB_MAP(PMSTATUSLOG),
168 TAB_MAP(SMU_METRICS),
169 TAB_MAP(DRIVER_SMU_CONFIG),
170 TAB_MAP(ACTIVITY_MONITOR_COEFF),
171 TAB_MAP(OVERDRIVE),
172 TAB_MAP(I2C_COMMANDS),
173 TAB_MAP(PACE),
174};
175
176static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
177 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
178 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
179 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
180 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
181 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
182 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
183 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
184};
185
186static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
187{
188 struct smu_11_0_cmn2aisc_mapping mapping;
189
190 if (index >= SMU_MSG_MAX_COUNT)
191 return -EINVAL;
192
193 mapping = sienna_cichlid_message_map[index];
194 if (!(mapping.valid_mapping)) {
195 return -EINVAL;
196 }
197
198 return mapping.map_to;
199}
200
201static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
202{
203 struct smu_11_0_cmn2aisc_mapping mapping;
204
205 if (index >= SMU_CLK_COUNT)
206 return -EINVAL;
207
208 mapping = sienna_cichlid_clk_map[index];
209 if (!(mapping.valid_mapping)) {
210 return -EINVAL;
211 }
212
213 return mapping.map_to;
214}
215
216static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
217{
218 struct smu_11_0_cmn2aisc_mapping mapping;
219
220 if (index >= SMU_FEATURE_COUNT)
221 return -EINVAL;
222
223 mapping = sienna_cichlid_feature_mask_map[index];
224 if (!(mapping.valid_mapping)) {
225 return -EINVAL;
226 }
227
228 return mapping.map_to;
229}
230
231static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
232{
233 struct smu_11_0_cmn2aisc_mapping mapping;
234
235 if (index >= SMU_TABLE_COUNT)
236 return -EINVAL;
237
238 mapping = sienna_cichlid_table_map[index];
239 if (!(mapping.valid_mapping)) {
240 return -EINVAL;
241 }
242
243 return mapping.map_to;
244}
245
246static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
247{
248 struct smu_11_0_cmn2aisc_mapping mapping;
249
250 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
251 return -EINVAL;
252
253 mapping = sienna_cichlid_workload_map[profile];
254 if (!(mapping.valid_mapping)) {
255 return -EINVAL;
256 }
257
258 return mapping.map_to;
259}
260
261static int
262sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
263 uint32_t *feature_mask, uint32_t num)
264{
fea905d4
LG		 265 struct amdgpu_device *adev = smu->adev;
266
b455159c
LG		 267 if (num > 2)
268 return -EINVAL;
269
270 memset(feature_mask, 0, sizeof(uint32_t) * num);
271
4cd4f45b 272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 273 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
094cdf15 274 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
9aa60213
LG		 275 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
276 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
094cdf15 277 | FEATURE_MASK(FEATURE_THERMAL_BIT);
fea905d4
LG		 278
279 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
281
65297d50
LG		 282 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
284
fea905d4
LG		 285 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 287
62c1ea6b
LG		 288 if (adev->pm.pp_feature & PP_ULV_MASK)
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
290
02bb391d
LG		 291 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
293
b455159c
LG		 294 return 0;
295}
296
297static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
298{
299 return 0;
300}
301
302static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
303{
304 return 0;
305}
306
307static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
308{
309 struct smu_11_0_powerplay_table *powerplay_table = NULL;
310 struct smu_table_context *table_context = &smu->smu_table;
311 struct smu_baco_context *smu_baco = &smu->smu_baco;
312
313 if (!table_context->power_play_table)
314 return -EINVAL;
315
316 powerplay_table = table_context->power_play_table;
317
318 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
319 sizeof(PPTable_t));
320
321 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
322
323 mutex_lock(&smu_baco->mutex);
324 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
325 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
326 smu_baco->platform_support = true;
327 mutex_unlock(&smu_baco->mutex);
328
329 return 0;
330}
331
332static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
333{
334 struct smu_table_context *smu_table = &smu->smu_table;
335
336 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
337 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
338 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
339 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
340 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
341 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
342 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
343 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
344 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
345 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
346 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
347 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
348 AMDGPU_GEM_DOMAIN_VRAM);
349
350 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
351 if (!smu_table->metrics_table)
352 return -ENOMEM;
353 smu_table->metrics_time = 0;
354
355 return 0;
356}
357
358static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
359 SmuMetrics_t *metrics_table)
360{
361 struct smu_table_context *smu_table= &smu->smu_table;
362 int ret = 0;
363
364 mutex_lock(&smu->metrics_lock);
365 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
366 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
367 (void *)smu_table->metrics_table, false);
368 if (ret) {
369 pr_info("Failed to export SMU metrics table!\n");
370 mutex_unlock(&smu->metrics_lock);
371 return ret;
372 }
373 smu_table->metrics_time = jiffies;
374 }
375
376 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
377 mutex_unlock(&smu->metrics_lock);
378
379 return ret;
380}
381
382static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
383{
384 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
385
386 if (smu_dpm->dpm_context)
387 return -EINVAL;
388
389 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
390 GFP_KERNEL);
391 if (!smu_dpm->dpm_context)
392 return -ENOMEM;
393
394 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
395
396 return 0;
397}
398
399static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
400{
401 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
402 struct smu_table_context *table_context = &smu->smu_table;
403 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
404 PPTable_t *driver_ppt = NULL;
405
406 driver_ppt = table_context->driver_pptable;
407
408 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
409 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
410
411 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
412 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
413
414 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
415 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
416
417 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
418 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
419
420 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
421 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
422
423 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
424 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
425
426 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
427 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
428
429 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
430 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
431
432 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
433 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
434
435 return 0;
436}
437
438static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
439{
440 struct smu_power_context *smu_power = &smu->smu_power;
441 struct smu_power_gate *power_gate = &smu_power->power_gate;
442 int ret = 0;
443
444 if (enable) {
445 /* vcn dpm on is a prerequisite for vcn power gate messages */
446 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
447 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
448 if (ret)
449 return ret;
450 }
451 power_gate->vcn_gated = false;
452 } else {
453 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
454 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
455 if (ret)
456 return ret;
457 }
458 power_gate->vcn_gated = true;
459 }
460
461 return ret;
462}
463
464static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
465 enum smu_clk_type clk_type,
466 uint32_t *value)
467{
468 int ret = 0, clk_id = 0;
469 SmuMetrics_t metrics;
470
471 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
472 if (ret)
473 return ret;
474
475 clk_id = smu_clk_get_index(smu, clk_type);
476 if (clk_id < 0)
477 return clk_id;
478
479 *value = metrics.CurrClock[clk_id];
480
481 return ret;
482}
483
484static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
485{
486 PPTable_t *pptable = smu->smu_table.driver_pptable;
487 DpmDescriptor_t *dpm_desc = NULL;
488 uint32_t clk_index = 0;
489
490 clk_index = smu_clk_get_index(smu, clk_type);
491 dpm_desc = &pptable->DpmDescriptor[clk_index];
492
493 /* 0 - Fine grained DPM, 1 - Discrete DPM */
494 return dpm_desc->SnapToDiscrete == 0 ? true : false;
495}
496
497static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
498 enum smu_clk_type clk_type, char *buf)
499{
500 int i, size = 0, ret = 0;
501 uint32_t cur_value = 0, value = 0, count = 0;
502 uint32_t freq_values[3] = {0};
503 uint32_t mark_index = 0;
504
505 switch (clk_type) {
506 case SMU_GFXCLK:
507 case SMU_SCLK:
508 case SMU_SOCCLK:
509 case SMU_MCLK:
510 case SMU_UCLK:
511 case SMU_FCLK:
512 case SMU_DCEFCLK:
513 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
514 if (ret)
515 return size;
516
517 /* 10KHz -> MHz */
518 cur_value = cur_value / 100;
519
520 ret = smu_get_dpm_level_count(smu, clk_type, &count);
521 if (ret)
522 return size;
523
524 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
525 for (i = 0; i < count; i++) {
526 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
527 if (ret)
528 return size;
529
530 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
531 cur_value == value ? "*" : "");
532 }
533 } else {
534 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
535 if (ret)
536 return size;
537 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
538 if (ret)
539 return size;
540
541 freq_values[1] = cur_value;
542 mark_index = cur_value == freq_values[0] ? 0 :
543 cur_value == freq_values[2] ? 2 : 1;
544 if (mark_index != 1)
545 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
546
547 for (i = 0; i < 3; i++) {
548 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
549 i == mark_index ? "*" : "");
550 }
551
552 }
553 break;
554 default:
555 break;
556 }
557
558 return size;
559}
560
561static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
562 enum smu_clk_type clk_type, uint32_t mask)
563{
564
565 int ret = 0, size = 0;
566 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
567
568 soft_min_level = mask ? (ffs(mask) - 1) : 0;
569 soft_max_level = mask ? (fls(mask) - 1) : 0;
570
571 switch (clk_type) {
572 case SMU_GFXCLK:
573 case SMU_SCLK:
574 case SMU_SOCCLK:
575 case SMU_MCLK:
576 case SMU_UCLK:
577 case SMU_DCEFCLK:
578 case SMU_FCLK:
9ad9c8ac
LG		 579 /* There is only 2 levels for fine grained DPM */
580 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
581 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
582 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
583 }
584
b455159c
LG		 585 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
586 if (ret)
587 return size;
588
589 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
590 if (ret)
591 return size;
592
593 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
594 if (ret)
595 return size;
596 break;
597 default:
598 break;
599 }
600
601 return size;
602}
603
604static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
605{
606 int ret = 0;
607 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
608
609 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
610 if (ret)
611 return ret;
612
613 smu->pstate_sclk = min_sclk_freq * 100;
614
615 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
616 if (ret)
617 return ret;
618
619 smu->pstate_mclk = min_mclk_freq * 100;
620
621 return ret;
622}
623
624static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
625 enum smu_clk_type clk_type,
626 struct pp_clock_levels_with_latency *clocks)
627{
628 int ret = 0, i = 0;
629 uint32_t level_count = 0, freq = 0;
630
631 switch (clk_type) {
632 case SMU_GFXCLK:
633 case SMU_DCEFCLK:
634 case SMU_SOCCLK:
635 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
636 if (ret)
637 return ret;
638
639 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
640 clocks->num_levels = level_count;
641
642 for (i = 0; i < level_count; i++) {
643 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
644 if (ret)
645 return ret;
646
647 clocks->data[i].clocks_in_khz = freq * 1000;
648 clocks->data[i].latency_in_us = 0;
649 }
650 break;
651 default:
652 break;
653 }
654
655 return ret;
656}
657
658static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
659{
660 int ret = 0;
661 uint32_t max_freq = 0;
662
663 /* Sienna_Cichlid do not support to change display num currently */
664 return 0;
665#if 0
666 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
667 if (ret)
668 return ret;
669#endif
670
671 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
672 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
673 if (ret)
674 return ret;
675 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
676 if (ret)
677 return ret;
678 }
679
680 return ret;
681}
682
683static int sienna_cichlid_display_config_changed(struct smu_context *smu)
684{
685 int ret = 0;
686
687 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
688 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
689 ret = smu_write_watermarks_table(smu);
690 if (ret)
691 return ret;
692
693 smu->watermarks_bitmap |= WATERMARKS_LOADED;
694 }
695
696 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
697 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
698 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
699 /* Sienna_Cichlid do not support to change display num currently */
700 ret = 0;
701#if 0
702 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
703 smu->display_config->num_display, NULL);
704#endif
705 if (ret)
706 return ret;
707 }
708
709 return ret;
710}
711
712static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
713{
714 int ret = 0, i = 0;
715 uint32_t min_freq, max_freq, force_freq;
716 enum smu_clk_type clk_type;
717
718 enum smu_clk_type clks[] = {
719 SMU_GFXCLK,
720 };
721
722 for (i = 0; i < ARRAY_SIZE(clks); i++) {
723 clk_type = clks[i];
724 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
725 if (ret)
726 return ret;
727
728 force_freq = highest ? max_freq : min_freq;
729 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
730 if (ret)
731 return ret;
732 }
733
734 return ret;
735}
736
737static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
738{
739 int ret = 0, i = 0;
740 uint32_t min_freq, max_freq;
741 enum smu_clk_type clk_type;
742
743 enum smu_clk_type clks[] = {
744 SMU_GFXCLK,
745 };
746
747 for (i = 0; i < ARRAY_SIZE(clks); i++) {
748 clk_type = clks[i];
749 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
750 if (ret)
751 return ret;
752
753 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
754 if (ret)
755 return ret;
756 }
757
758 return ret;
759}
760
761static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
762{
763 int ret = 0;
764 SmuMetrics_t metrics;
765
766 if (!value)
767 return -EINVAL;
768
769 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
770 if (ret)
771 return ret;
772
773 *value = metrics.AverageSocketPower << 8;
774
775 return 0;
776}
777
778static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
779 enum amd_pp_sensors sensor,
780 uint32_t *value)
781{
782 int ret = 0;
783 SmuMetrics_t metrics;
784
785 if (!value)
786 return -EINVAL;
787
788 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
789 if (ret)
790 return ret;
791
792 switch (sensor) {
793 case AMDGPU_PP_SENSOR_GPU_LOAD:
794 *value = metrics.AverageGfxActivity;
795 break;
796 case AMDGPU_PP_SENSOR_MEM_LOAD:
797 *value = metrics.AverageUclkActivity;
798 break;
799 default:
800 pr_err("Invalid sensor for retrieving clock activity\n");
801 return -EINVAL;
802 }
803
804 return 0;
805}
806
807static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
808{
809 int ret = 0;
810 uint32_t feature_mask[2];
811 unsigned long feature_enabled;
812 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
813 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
814 ((uint64_t)feature_mask[1] << 32));
815 return !!(feature_enabled & SMC_DPM_FEATURE);
816}
817
818static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
819 uint32_t *speed)
820{
821 SmuMetrics_t metrics;
822 int ret = 0;
823
824 if (!speed)
825 return -EINVAL;
826
827 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
828 if (ret)
829 return ret;
830
831 *speed = metrics.CurrFanSpeed;
832
833 return ret;
834}
835
836static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
837 uint32_t *speed)
838{
839 int ret = 0;
840 uint32_t percent = 0;
841 uint32_t current_rpm;
842 PPTable_t *pptable = smu->smu_table.driver_pptable;
843
844 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
845 if (ret)
846 return ret;
847
848 percent = current_rpm * 100 / pptable->FanMaximumRpm;
849 *speed = percent > 100 ? 100 : percent;
850
851 return ret;
852}
853
854static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
855{
856 DpmActivityMonitorCoeffInt_t activity_monitor;
857 uint32_t i, size = 0;
858 int16_t workload_type = 0;
859 static const char *profile_name[] = {
860 "BOOTUP_DEFAULT",
861 "3D_FULL_SCREEN",
862 "POWER_SAVING",
863 "VIDEO",
864 "VR",
865 "COMPUTE",
866 "CUSTOM"};
867 static const char *title[] = {
868 "PROFILE_INDEX(NAME)",
869 "CLOCK_TYPE(NAME)",
870 "FPS",
871 "MinFreqType",
872 "MinActiveFreqType",
873 "MinActiveFreq",
874 "BoosterFreqType",
875 "BoosterFreq",
876 "PD_Data_limit_c",
877 "PD_Data_error_coeff",
878 "PD_Data_error_rate_coeff"};
879 int result = 0;
880
881 if (!buf)
882 return -EINVAL;
883
884 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
885 title[0], title[1], title[2], title[3], title[4], title[5],
886 title[6], title[7], title[8], title[9], title[10]);
887
888 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
889 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
890 workload_type = smu_workload_get_type(smu, i);
891 if (workload_type < 0)
892 return -EINVAL;
893
894 result = smu_update_table(smu,
895 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
896 (void *)(&activity_monitor), false);
897 if (result) {
898 pr_err("[%s] Failed to get activity monitor!", __func__);
899 return result;
900 }
901
902 size += sprintf(buf + size, "%2d %14s%s:\n",
903 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
904
905 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
906 " ",
907 0,
908 "GFXCLK",
909 activity_monitor.Gfx_FPS,
910 activity_monitor.Gfx_MinFreqStep,
911 activity_monitor.Gfx_MinActiveFreqType,
912 activity_monitor.Gfx_MinActiveFreq,
913 activity_monitor.Gfx_BoosterFreqType,
914 activity_monitor.Gfx_BoosterFreq,
915 activity_monitor.Gfx_PD_Data_limit_c,
916 activity_monitor.Gfx_PD_Data_error_coeff,
917 activity_monitor.Gfx_PD_Data_error_rate_coeff);
918
919 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
920 " ",
921 1,
922 "SOCCLK",
923 activity_monitor.Fclk_FPS,
924 activity_monitor.Fclk_MinFreqStep,
925 activity_monitor.Fclk_MinActiveFreqType,
926 activity_monitor.Fclk_MinActiveFreq,
927 activity_monitor.Fclk_BoosterFreqType,
928 activity_monitor.Fclk_BoosterFreq,
929 activity_monitor.Fclk_PD_Data_limit_c,
930 activity_monitor.Fclk_PD_Data_error_coeff,
931 activity_monitor.Fclk_PD_Data_error_rate_coeff);
932
933 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
934 " ",
935 2,
936 "MEMLK",
937 activity_monitor.Mem_FPS,
938 activity_monitor.Mem_MinFreqStep,
939 activity_monitor.Mem_MinActiveFreqType,
940 activity_monitor.Mem_MinActiveFreq,
941 activity_monitor.Mem_BoosterFreqType,
942 activity_monitor.Mem_BoosterFreq,
943 activity_monitor.Mem_PD_Data_limit_c,
944 activity_monitor.Mem_PD_Data_error_coeff,
945 activity_monitor.Mem_PD_Data_error_rate_coeff);
946 }
947
948 return size;
949}
950
951static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
952{
953 DpmActivityMonitorCoeffInt_t activity_monitor;
954 int workload_type, ret = 0;
955
956 smu->power_profile_mode = input[size];
957
958 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
959 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
960 return -EINVAL;
961 }
962
963 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
964 if (size < 0)
965 return -EINVAL;
966
967 ret = smu_update_table(smu,
968 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
969 (void *)(&activity_monitor), false);
970 if (ret) {
971 pr_err("[%s] Failed to get activity monitor!", __func__);
972 return ret;
973 }
974
975 switch (input[0]) {
976 case 0: /* Gfxclk */
977 activity_monitor.Gfx_FPS = input[1];
978 activity_monitor.Gfx_MinFreqStep = input[2];
979 activity_monitor.Gfx_MinActiveFreqType = input[3];
980 activity_monitor.Gfx_MinActiveFreq = input[4];
981 activity_monitor.Gfx_BoosterFreqType = input[5];
982 activity_monitor.Gfx_BoosterFreq = input[6];
983 activity_monitor.Gfx_PD_Data_limit_c = input[7];
984 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
985 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
986 break;
987 case 1: /* Socclk */
988 activity_monitor.Fclk_FPS = input[1];
989 activity_monitor.Fclk_MinFreqStep = input[2];
990 activity_monitor.Fclk_MinActiveFreqType = input[3];
991 activity_monitor.Fclk_MinActiveFreq = input[4];
992 activity_monitor.Fclk_BoosterFreqType = input[5];
993 activity_monitor.Fclk_BoosterFreq = input[6];
994 activity_monitor.Fclk_PD_Data_limit_c = input[7];
995 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
996 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
997 break;
998 case 2: /* Memlk */
999 activity_monitor.Mem_FPS = input[1];
1000 activity_monitor.Mem_MinFreqStep = input[2];
1001 activity_monitor.Mem_MinActiveFreqType = input[3];
1002 activity_monitor.Mem_MinActiveFreq = input[4];
1003 activity_monitor.Mem_BoosterFreqType = input[5];
1004 activity_monitor.Mem_BoosterFreq = input[6];
1005 activity_monitor.Mem_PD_Data_limit_c = input[7];
1006 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1007 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1008 break;
1009 }
1010
1011 ret = smu_update_table(smu,
1012 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1013 (void *)(&activity_monitor), true);
1014 if (ret) {
1015 pr_err("[%s] Failed to set activity monitor!", __func__);
1016 return ret;
1017 }
1018 }
1019
1020 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1021 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1022 if (workload_type < 0)
1023 return -EINVAL;
1024 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1025 1 << workload_type, NULL);
1026
1027 return ret;
1028}
1029
1030static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1031 enum amd_dpm_forced_level level,
1032 uint32_t *sclk_mask,
1033 uint32_t *mclk_mask,
1034 uint32_t *soc_mask)
1035{
1036 int ret = 0;
1037 uint32_t level_count = 0;
1038
1039 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1040 if (sclk_mask)
1041 *sclk_mask = 0;
1042 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1043 if (mclk_mask)
1044 *mclk_mask = 0;
1045 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1046 if(sclk_mask) {
1047 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1048 if (ret)
1049 return ret;
1050 *sclk_mask = level_count - 1;
1051 }
1052
1053 if(mclk_mask) {
1054 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1055 if (ret)
1056 return ret;
1057 *mclk_mask = level_count - 1;
1058 }
1059
1060 if(soc_mask) {
1061 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1062 if (ret)
1063 return ret;
1064 *soc_mask = level_count - 1;
1065 }
1066 }
1067
1068 return ret;
1069}
1070
1071static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1072{
1073 struct smu_clocks min_clocks = {0};
1074 struct pp_display_clock_request clock_req;
1075 int ret = 0;
1076
1077 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1078 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1079 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1080
1081 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1082 clock_req.clock_type = amd_pp_dcef_clock;
1083 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1084
1085 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1086 if (!ret) {
1087 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1088 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1089 return ret;
1090 }
1091 } else {
1092 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1093 }
1094 }
1095
1096 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1097 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1098 if (ret) {
1099 pr_err("[%s] Set hard min uclk failed!", __func__);
1100 return ret;
1101 }
1102 }
1103
1104 return 0;
1105}
1106
1107static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1108 void *watermarks, struct
1109 dm_pp_wm_sets_with_clock_ranges_soc15
1110 *clock_ranges)
1111{
1112 int i;
1113 Watermarks_t *table = watermarks;
1114
1115 if (!table || !clock_ranges)
1116 return -EINVAL;
1117
1118 if (clock_ranges->num_wm_dmif_sets > 4 ||
1119 clock_ranges->num_wm_mcif_sets > 4)
1120 return -EINVAL;
1121
1122 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1123 table->WatermarkRow[1][i].MinClock =
1124 cpu_to_le16((uint16_t)
1125 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1126 1000));
1127 table->WatermarkRow[1][i].MaxClock =
1128 cpu_to_le16((uint16_t)
1129 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1130 1000));
1131 table->WatermarkRow[1][i].MinUclk =
1132 cpu_to_le16((uint16_t)
1133 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1134 1000));
1135 table->WatermarkRow[1][i].MaxUclk =
1136 cpu_to_le16((uint16_t)
1137 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1138 1000));
1139 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1140 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1141 }
1142
1143 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1144 table->WatermarkRow[0][i].MinClock =
1145 cpu_to_le16((uint16_t)
1146 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1147 1000));
1148 table->WatermarkRow[0][i].MaxClock =
1149 cpu_to_le16((uint16_t)
1150 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1151 1000));
1152 table->WatermarkRow[0][i].MinUclk =
1153 cpu_to_le16((uint16_t)
1154 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1155 1000));
1156 table->WatermarkRow[0][i].MaxUclk =
1157 cpu_to_le16((uint16_t)
1158 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1159 1000));
1160 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1161 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1162 }
1163
1164 return 0;
1165}
1166
1167static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1168 enum amd_pp_sensors sensor,
1169 uint32_t *value)
1170{
1171 SmuMetrics_t metrics;
1172 int ret = 0;
1173
1174 if (!value)
1175 return -EINVAL;
1176
1177 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1178 if (ret)
1179 return ret;
1180
1181 switch (sensor) {
1182 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1183 *value = metrics.TemperatureHotspot *
1184 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1185 break;
1186 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1187 *value = metrics.TemperatureEdge *
1188 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1189 break;
1190 case AMDGPU_PP_SENSOR_MEM_TEMP:
1191 *value = metrics.TemperatureMem *
1192 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1193 break;
1194 default:
1195 pr_err("Invalid sensor for retrieving temp\n");
1196 return -EINVAL;
1197 }
1198
1199 return 0;
1200}
1201
1202static int sienna_cichlid_read_sensor(struct smu_context *smu,
1203 enum amd_pp_sensors sensor,
1204 void *data, uint32_t *size)
1205{
1206 int ret = 0;
1207 struct smu_table_context *table_context = &smu->smu_table;
1208 PPTable_t *pptable = table_context->driver_pptable;
1209
1210 if(!data || !size)
1211 return -EINVAL;
1212
1213 mutex_lock(&smu->sensor_lock);
1214 switch (sensor) {
1215 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1216 *(uint32_t *)data = pptable->FanMaximumRpm;
1217 *size = 4;
1218 break;
1219 case AMDGPU_PP_SENSOR_MEM_LOAD:
1220 case AMDGPU_PP_SENSOR_GPU_LOAD:
1221 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1222 *size = 4;
1223 break;
1224 case AMDGPU_PP_SENSOR_GPU_POWER:
1225 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1226 *size = 4;
1227 break;
1228 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1229 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1230 case AMDGPU_PP_SENSOR_MEM_TEMP:
1231 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1232 *size = 4;
1233 break;
1234 default:
1235 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1236 }
1237 mutex_unlock(&smu->sensor_lock);
1238
1239 return ret;
1240}
1241
1242static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1243{
1244 uint32_t num_discrete_levels = 0;
1245 uint16_t *dpm_levels = NULL;
1246 uint16_t i = 0;
1247 struct smu_table_context *table_context = &smu->smu_table;
1248 PPTable_t *driver_ppt = NULL;
1249
1250 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1251 return -EINVAL;
1252
1253 driver_ppt = table_context->driver_pptable;
1254 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1255 dpm_levels = driver_ppt->FreqTableUclk;
1256
1257 if (num_discrete_levels == 0 || dpm_levels == NULL)
1258 return -EINVAL;
1259
1260 *num_states = num_discrete_levels;
1261 for (i = 0; i < num_discrete_levels; i++) {
1262 /* convert to khz */
1263 *clocks_in_khz = (*dpm_levels) * 1000;
1264 clocks_in_khz++;
1265 dpm_levels++;
1266 }
1267
1268 return 0;
1269}
1270
9ad9c8ac
LG		 1271static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1272 enum amd_dpm_forced_level level);
1273
1274static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1275{
1276 struct amdgpu_device *adev = smu->adev;
1277 int ret = 0;
1278 uint32_t sclk_freq = 0, uclk_freq = 0;
1279
1280 switch (adev->asic_type) {
1281 /* TODO: need to set specify clk value by asic type, not support yet*/
1282 default:
1283 /* by default, this is same as auto performance level */
1284 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1285 }
1286
1287 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1288 if (ret)
1289 return ret;
1290 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1291 if (ret)
1292 return ret;
1293
1294 return ret;
1295}
1296
1297static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1298{
1299 int ret = 0;
1300
1301 /* TODO: not support yet*/
1302 return ret;
1303}
1304
1305static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1306 enum amd_dpm_forced_level level)
1307{
1308 int ret = 0;
1309 uint32_t sclk_mask, mclk_mask, soc_mask;
1310
1311 switch (level) {
1312 case AMD_DPM_FORCED_LEVEL_HIGH:
1313 ret = smu_force_dpm_limit_value(smu, true);
1314 break;
1315 case AMD_DPM_FORCED_LEVEL_LOW:
1316 ret = smu_force_dpm_limit_value(smu, false);
1317 break;
1318 case AMD_DPM_FORCED_LEVEL_AUTO:
1319 ret = smu_unforce_dpm_levels(smu);
1320 break;
1321 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1322 ret = sienna_cichlid_set_standard_performance_level(smu);
1323 break;
1324 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1325 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1326 ret = smu_get_profiling_clk_mask(smu, level,
1327 &sclk_mask,
1328 &mclk_mask,
1329 &soc_mask);
1330 if (ret)
1331 return ret;
1332 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1333 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1334 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1335 break;
1336 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1337 ret = sienna_cichlid_set_peak_performance_level(smu);
1338 break;
1339 case AMD_DPM_FORCED_LEVEL_MANUAL:
1340 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1341 default:
1342 break;
1343 }
1344 return ret;
1345}
1346
b455159c
LG		 1347static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1348 struct smu_temperature_range *range)
1349{
1350 struct smu_table_context *table_context = &smu->smu_table;
1351 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1352
1353 if (!range || !powerplay_table)
1354 return -EINVAL;
1355
1356 range->max = powerplay_table->software_shutdown_temp *
1357 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1358
1359 return 0;
1360}
1361
1362static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1363 bool disable_memory_clock_switch)
1364{
1365 int ret = 0;
1366 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1367 (struct smu_11_0_max_sustainable_clocks *)
1368 smu->smu_table.max_sustainable_clocks;
1369 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1370 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1371
1372 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1373 return 0;
1374
1375 if(disable_memory_clock_switch)
1376 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1377 else
1378 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1379
1380 if(!ret)
1381 smu->disable_uclk_switch = disable_memory_clock_switch;
1382
1383 return ret;
1384}
1385
1386static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1387 uint32_t *limit,
1388 bool cap)
1389{
1390 PPTable_t *pptable = smu->smu_table.driver_pptable;
1391 uint32_t asic_default_power_limit = 0;
1392 int ret = 0;
1393 int power_src;
1394
1395 if (!smu->power_limit) {
1396 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1397 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1398 if (power_src < 0)
1399 return -EINVAL;
1400
1401 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1402 power_src << 16, &asic_default_power_limit);
1403 if (ret) {
1404 pr_err("[%s] get PPT limit failed!", __func__);
1405 return ret;
1406 }
1407 } else {
1408 /* the last hope to figure out the ppt limit */
1409 if (!pptable) {
1410 pr_err("Cannot get PPT limit due to pptable missing!");
1411 return -EINVAL;
1412 }
1413 asic_default_power_limit =
1414 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1415 }
1416
1417 smu->power_limit = asic_default_power_limit;
1418 }
1419
1420 if (cap)
1421 *limit = smu_v11_0_get_max_power_limit(smu);
1422 else
1423 *limit = smu->power_limit;
1424
1425 return 0;
1426}
1427
1428static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1429{
1430 struct smu_table_context *table_context = &smu->smu_table;
1431 PPTable_t *pptable = table_context->driver_pptable;
1432 int i;
1433
1434 pr_info("Dumped PPTable:\n");
1435
1436 pr_info("Version = 0x%08x\n", pptable->Version);
1437 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1438 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1439
1440 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1441 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1442 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1443 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1444 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1445 }
1446
1447 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1448 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1449 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1450 }
1451
1452 for (i = 0; i < TEMP_COUNT; i++) {
1453 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1454 }
1455
1456 pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1457 pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1458 pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1459 pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1460 pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1461
1462 pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1463 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1464 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1465 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1466 }
1467 pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1468 pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1469 pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1470 pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1471
1472 pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1473
1474 pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1475
1476 pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1477 pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1478 pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1479 pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1480
1481 pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1482 pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1483
1484 pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1485 pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1486 pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1487 pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1488
1489 pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1490 pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1491 pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1492 pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1493
1494 pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1495 pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1496
1497 pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1498 pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1499 pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1500 pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1501 pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1502 pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1503 pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1504 pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1505
1506 pr_info("[PPCLK_GFXCLK]\n"
1507 " .VoltageMode = 0x%02x\n"
1508 " .SnapToDiscrete = 0x%02x\n"
1509 " .NumDiscreteLevels = 0x%02x\n"
1510 " .padding = 0x%02x\n"
1511 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1512 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1513 " .SsFmin = 0x%04x\n"
1514 " .Padding_16 = 0x%04x\n",
1515 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1516 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1517 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1518 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1519 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1520 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1521 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1522 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1523 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1524 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1525 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1526
1527 pr_info("[PPCLK_SOCCLK]\n"
1528 " .VoltageMode = 0x%02x\n"
1529 " .SnapToDiscrete = 0x%02x\n"
1530 " .NumDiscreteLevels = 0x%02x\n"
1531 " .padding = 0x%02x\n"
1532 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1533 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1534 " .SsFmin = 0x%04x\n"
1535 " .Padding_16 = 0x%04x\n",
1536 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1537 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1538 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1539 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1540 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1541 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1542 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1543 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1544 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1545 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1546 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1547
1548 pr_info("[PPCLK_UCLK]\n"
1549 " .VoltageMode = 0x%02x\n"
1550 " .SnapToDiscrete = 0x%02x\n"
1551 " .NumDiscreteLevels = 0x%02x\n"
1552 " .padding = 0x%02x\n"
1553 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1554 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1555 " .SsFmin = 0x%04x\n"
1556 " .Padding_16 = 0x%04x\n",
1557 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1558 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1559 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1560 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1561 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1562 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1563 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1564 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1565 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1566 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1567 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1568
1569 pr_info("[PPCLK_FCLK]\n"
1570 " .VoltageMode = 0x%02x\n"
1571 " .SnapToDiscrete = 0x%02x\n"
1572 " .NumDiscreteLevels = 0x%02x\n"
1573 " .padding = 0x%02x\n"
1574 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1575 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1576 " .SsFmin = 0x%04x\n"
1577 " .Padding_16 = 0x%04x\n",
1578 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1579 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1580 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1581 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1582 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1583 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1584 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1585 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1586 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1587 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1588 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1589
1590 pr_info("[PPCLK_DCLK_0]\n"
1591 " .VoltageMode = 0x%02x\n"
1592 " .SnapToDiscrete = 0x%02x\n"
1593 " .NumDiscreteLevels = 0x%02x\n"
1594 " .padding = 0x%02x\n"
1595 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1596 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1597 " .SsFmin = 0x%04x\n"
1598 " .Padding_16 = 0x%04x\n",
1599 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1600 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1601 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1602 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1603 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1604 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1605 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1606 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1607 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1608 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1609 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1610
1611 pr_info("[PPCLK_VCLK_0]\n"
1612 " .VoltageMode = 0x%02x\n"
1613 " .SnapToDiscrete = 0x%02x\n"
1614 " .NumDiscreteLevels = 0x%02x\n"
1615 " .padding = 0x%02x\n"
1616 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1617 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1618 " .SsFmin = 0x%04x\n"
1619 " .Padding_16 = 0x%04x\n",
1620 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1621 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1622 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1623 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1624 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1625 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1626 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1627 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1628 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1629 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1630 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1631
1632 pr_info("[PPCLK_DCLK_1]\n"
1633 " .VoltageMode = 0x%02x\n"
1634 " .SnapToDiscrete = 0x%02x\n"
1635 " .NumDiscreteLevels = 0x%02x\n"
1636 " .padding = 0x%02x\n"
1637 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1638 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1639 " .SsFmin = 0x%04x\n"
1640 " .Padding_16 = 0x%04x\n",
1641 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1642 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1643 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1644 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1645 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1646 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1647 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1648 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1649 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1650 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1651 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1652
1653 pr_info("[PPCLK_VCLK_1]\n"
1654 " .VoltageMode = 0x%02x\n"
1655 " .SnapToDiscrete = 0x%02x\n"
1656 " .NumDiscreteLevels = 0x%02x\n"
1657 " .padding = 0x%02x\n"
1658 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1659 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1660 " .SsFmin = 0x%04x\n"
1661 " .Padding_16 = 0x%04x\n",
1662 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1663 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1664 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1665 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1666 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1667 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1668 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1669 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1670 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1671 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1672 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1673
1674 pr_info("FreqTableGfx\n");
1675 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1676 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1677
1678 pr_info("FreqTableVclk\n");
1679 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1680 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1681
1682 pr_info("FreqTableDclk\n");
1683 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1684 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1685
1686 pr_info("FreqTableSocclk\n");
1687 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1688 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1689
1690 pr_info("FreqTableUclk\n");
1691 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1692 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1693
1694 pr_info("FreqTableFclk\n");
1695 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1696 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1697
1698 pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
1699 pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
1700 pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
1701 pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
1702 pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
1703 pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
1704 pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
1705 pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
1706 pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
1707 pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
1708 pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1709 pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1710 pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1711 pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1712 pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1713 pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1714
1715 pr_info("DcModeMaxFreq\n");
1716 pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1717 pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1718 pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1719 pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1720 pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1721 pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1722 pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1723 pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1724
1725 pr_info("FreqTableUclkDiv\n");
1726 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1727 pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1728
1729 pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1730 pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1731
1732 pr_info("Mp0clkFreq\n");
1733 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1734 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1735
1736 pr_info("Mp0DpmVoltage\n");
1737 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1738 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1739
1740 pr_info("MemVddciVoltage\n");
1741 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1742 pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1743
1744 pr_info("MemMvddVoltage\n");
1745 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1746 pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1747
1748 pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1749 pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1750 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1751 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1752 pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1753
1754 pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1755
1756 pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1757 pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1758 pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1759 pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1760 pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1761 pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1762 pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1763 pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1764 pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1765 pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1766 pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1767
1768 pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1769 pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1770 pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1771 pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1772 pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1773 pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1774
1775 pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1776 pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1777 pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1778 pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1779 pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1780
1781 pr_info("FlopsPerByteTable\n");
1782 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1783 pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1784
1785 pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1786 pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1787 pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1788 pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1789
1790 pr_info("UclkDpmPstates\n");
1791 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1792 pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1793
1794 pr_info("UclkDpmSrcFreqRange\n");
1795 pr_info(" .Fmin = 0x%x\n",
1796 pptable->UclkDpmSrcFreqRange.Fmin);
1797 pr_info(" .Fmax = 0x%x\n",
1798 pptable->UclkDpmSrcFreqRange.Fmax);
1799 pr_info("UclkDpmTargFreqRange\n");
1800 pr_info(" .Fmin = 0x%x\n",
1801 pptable->UclkDpmTargFreqRange.Fmin);
1802 pr_info(" .Fmax = 0x%x\n",
1803 pptable->UclkDpmTargFreqRange.Fmax);
1804 pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1805 pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1806
1807 pr_info("PcieGenSpeed\n");
1808 for (i = 0; i < NUM_LINK_LEVELS; i++)
1809 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1810
1811 pr_info("PcieLaneCount\n");
1812 for (i = 0; i < NUM_LINK_LEVELS; i++)
1813 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1814
1815 pr_info("LclkFreq\n");
1816 for (i = 0; i < NUM_LINK_LEVELS; i++)
1817 pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1818
1819 pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1820 pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1821
1822 pr_info("FanGain\n");
1823 for (i = 0; i < TEMP_COUNT; i++)
1824 pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1825
1826 pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1827 pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1828 pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1829 pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1830 pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1831 pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1832 pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1833 pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1834 pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1835 pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1836 pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1837 pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1838
1839 pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1840 pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1841 pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1842 pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1843
1844 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1845 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1846 pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
1847 pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
1848
1849 pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1850 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
1851 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
1852 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
1853 pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1854 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
1855 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
1856 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
1857 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1858 pptable->dBtcGbGfxPll.a,
1859 pptable->dBtcGbGfxPll.b,
1860 pptable->dBtcGbGfxPll.c);
1861 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1862 pptable->dBtcGbGfxDfll.a,
1863 pptable->dBtcGbGfxDfll.b,
1864 pptable->dBtcGbGfxDfll.c);
1865 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1866 pptable->dBtcGbSoc.a,
1867 pptable->dBtcGbSoc.b,
1868 pptable->dBtcGbSoc.c);
1869 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1870 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1871 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1872 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1873 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1874 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1875
1876 pr_info("PiecewiseLinearDroopIntGfxDfll\n");
1877 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
1878 pr_info(" Fset[%d] = 0x%x\n",
1879 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
1880 pr_info(" Vdroop[%d] = 0x%x\n",
1881 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
1882 }
1883
1884 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1885 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1886 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1887 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1888 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1889 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1890 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1891 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1892
1893 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1894 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1895
1896 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1897 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1898 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1899 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1900
1901 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1902 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1903 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1904 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1905
1906 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1907 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1908
1909 pr_info("XgmiDpmPstates\n");
1910 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1911 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
1912 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1913 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1914
1915 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1916 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1917 pptable->ReservedEquation0.a,
1918 pptable->ReservedEquation0.b,
1919 pptable->ReservedEquation0.c);
1920 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1921 pptable->ReservedEquation1.a,
1922 pptable->ReservedEquation1.b,
1923 pptable->ReservedEquation1.c);
1924 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1925 pptable->ReservedEquation2.a,
1926 pptable->ReservedEquation2.b,
1927 pptable->ReservedEquation2.c);
1928 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1929 pptable->ReservedEquation3.a,
1930 pptable->ReservedEquation3.b,
1931 pptable->ReservedEquation3.c);
1932
1933 pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
1934 pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
1935 pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
1936 pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
1937 pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
1938 pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
1939 pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
1940 pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
1941 pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
1942 pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
1943 pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
1944 pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
1945 pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
1946 pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
1947 pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
1948
1949 pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
1950 pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
1951 pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
1952 pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
1953 pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
1954 pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
1955
1956 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1957 pr_info("I2cControllers[%d]:\n", i);
1958 pr_info(" .Enabled = 0x%x\n",
1959 pptable->I2cControllers[i].Enabled);
1960 pr_info(" .Speed = 0x%x\n",
1961 pptable->I2cControllers[i].Speed);
1962 pr_info(" .SlaveAddress = 0x%x\n",
1963 pptable->I2cControllers[i].SlaveAddress);
1964 pr_info(" .ControllerPort = 0x%x\n",
1965 pptable->I2cControllers[i].ControllerPort);
1966 pr_info(" .ControllerName = 0x%x\n",
1967 pptable->I2cControllers[i].ControllerName);
1968 pr_info(" .ThermalThrottler = 0x%x\n",
1969 pptable->I2cControllers[i].ThermalThrotter);
1970 pr_info(" .I2cProtocol = 0x%x\n",
1971 pptable->I2cControllers[i].I2cProtocol);
1972 pr_info(" .PaddingConfig = 0x%x\n",
1973 pptable->I2cControllers[i].PaddingConfig);
1974 }
1975
1976 pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
1977 pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
1978 pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
1979 pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
1980
1981 pr_info("Board Parameters:\n");
1982 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1983 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1984 pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
1985 pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
1986 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1987 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
1988 pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
1989 pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
1990
1991 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1992 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1993 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1994
1995 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1996 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1997 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1998
1999 pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2000 pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2001 pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2002
2003 pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2004 pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2005 pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2006
2007 pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2008
2009 pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2010 pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2011 pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2012 pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2013 pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2014 pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2015 pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2016 pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2017 pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2018 pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2019 pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2020 pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2021 pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2022 pr_info("LedError = 0x%x\n", pptable->LedError);
2023 pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2024 pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2025
2026 pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2027 pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2028 pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2029
2030 pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2031 pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2032 pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2033
2034 pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2035 pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2036 pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2037
2038 pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2039 pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2040 pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2041
2042 pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2043 pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2044 pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2045 pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2046 pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2047
2048 pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2049 pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2050
2051 pr_info("XgmiLinkSpeed\n");
2052 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2053 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2054 pr_info("XgmiLinkWidth\n");
2055 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2056 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2057 pr_info("XgmiFclkFreq\n");
2058 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2059 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2060 pr_info("XgmiSocVoltage\n");
2061 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2062 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2063
2064 pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2065 pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2066 pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2067 pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2068
2069 pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2070 pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2071 pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2072 pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2073 pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2074 pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2075 pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2076 pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2077 pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2078 pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2079 pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2080 pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2081 pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2082 pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2083 pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2084
2085 pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2086 pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2087 pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2088 pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2089 pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2090 pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2091 pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2092 pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2093}
2094
2095static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2096 .tables_init = sienna_cichlid_tables_init,
2097 .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2098 .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2099 .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2100 .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2101 .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2102 .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2103 .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2104 .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2105 .get_workload_type = sienna_cichlid_get_workload_type,
2106 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2107 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2108 .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2109 .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2110 .print_clk_levels = sienna_cichlid_print_clk_levels,
2111 .force_clk_levels = sienna_cichlid_force_clk_levels,
2112 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2113 .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2114 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2115 .display_config_changed = sienna_cichlid_display_config_changed,
2116 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2117 .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2118 .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2119 .is_dpm_running = sienna_cichlid_is_dpm_running,
2120 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2121 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2122 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2123 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2124 .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2125 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2126 .read_sensor = sienna_cichlid_read_sensor,
2127 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
9ad9c8ac 2128 .set_performance_level = sienna_cichlid_set_performance_level,
b455159c
LG		 2129 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2130 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2131 .get_power_limit = sienna_cichlid_get_power_limit,
2132 .dump_pptable = sienna_cichlid_dump_pptable,
2133 .init_microcode = smu_v11_0_init_microcode,
2134 .load_microcode = smu_v11_0_load_microcode,
2135 .init_smc_tables = smu_v11_0_init_smc_tables,
2136 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2137 .init_power = smu_v11_0_init_power,
2138 .fini_power = smu_v11_0_fini_power,
2139 .check_fw_status = smu_v11_0_check_fw_status,
2140 .setup_pptable = smu_v11_0_setup_pptable,
2141 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2142 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2143 .check_pptable = smu_v11_0_check_pptable,
2144 .parse_pptable = smu_v11_0_parse_pptable,
2145 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2146 .check_fw_version = smu_v11_0_check_fw_version,
2147 .write_pptable = smu_v11_0_write_pptable,
2148 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2149 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2150 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2151 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2152 .system_features_control = smu_v11_0_system_features_control,
2153 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2154 .init_display_count = smu_v11_0_init_display_count,
2155 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2156 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2157 .notify_display_change = smu_v11_0_notify_display_change,
2158 .set_power_limit = smu_v11_0_set_power_limit,
2159 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2160 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2161 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2162 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2163 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2164 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2165 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2166 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2167 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2168 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2169 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2170 .gfx_off_control = smu_v11_0_gfx_off_control,
2171 .register_irq_handler = smu_v11_0_register_irq_handler,
2172 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2173 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2174 .baco_is_support= smu_v11_0_baco_is_support,
2175 .baco_get_state = smu_v11_0_baco_get_state,
2176 .baco_set_state = smu_v11_0_baco_set_state,
2177 .baco_enter = smu_v11_0_baco_enter,
2178 .baco_exit = smu_v11_0_baco_exit,
2179 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2180 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2181 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2182};
2183
2184void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2185{
2186 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2187}
Linux 6.x block layer and io_uring tree(s)