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drm/amdgpu: add umc v8_7_0 IP headers
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37
EQ		 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
55084d7f
EQ		 51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
bc50ca29
AD		 61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70
LG		 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
b455159c 72
6c339f37
EQ		 73static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 77 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
78 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
79 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
80 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 81 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
82 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
83 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
84 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
85 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
86 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
87 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1
LG		 88 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
89 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
90 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
91 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
92 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
93 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
94 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
95 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
96 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
97 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
98 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
6c339f37 99 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 100 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 101 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
102 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
103 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 104 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
105 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
106 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
107 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
108 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
109 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
110 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
111 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 112 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 113 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
114 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
115 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 116 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 117 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
118 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
119 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
120 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
121 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
122 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
123 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
124 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
b455159c
LG		 125};
126
6c339f37 127static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 128 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
129 CLK_MAP(SCLK, PPCLK_GFXCLK),
130 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
131 CLK_MAP(FCLK, PPCLK_FCLK),
132 CLK_MAP(UCLK, PPCLK_UCLK),
133 CLK_MAP(MCLK, PPCLK_UCLK),
134 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 135 CLK_MAP(DCLK1, PPCLK_DCLK_1),
136 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 137 CLK_MAP(VCLK1, PPCLK_VCLK_1),
138 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
139 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
140 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
141 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
142};
143
6c339f37 144static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 145 FEA_MAP(DPM_PREFETCHER),
146 FEA_MAP(DPM_GFXCLK),
31cb0dd9 147 FEA_MAP(DPM_GFX_GPO),
b455159c
LG		 148 FEA_MAP(DPM_UCLK),
149 FEA_MAP(DPM_SOCCLK),
150 FEA_MAP(DPM_MP0CLK),
151 FEA_MAP(DPM_LINK),
152 FEA_MAP(DPM_DCEFCLK),
153 FEA_MAP(MEM_VDDCI_SCALING),
154 FEA_MAP(MEM_MVDD_SCALING),
155 FEA_MAP(DS_GFXCLK),
156 FEA_MAP(DS_SOCCLK),
157 FEA_MAP(DS_LCLK),
158 FEA_MAP(DS_DCEFCLK),
159 FEA_MAP(DS_UCLK),
160 FEA_MAP(GFX_ULV),
161 FEA_MAP(FW_DSTATE),
162 FEA_MAP(GFXOFF),
163 FEA_MAP(BACO),
6fb176a7 164 FEA_MAP(MM_DPM_PG),
b455159c
LG		 165 FEA_MAP(RSMU_SMN_CG),
166 FEA_MAP(PPT),
167 FEA_MAP(TDC),
168 FEA_MAP(APCC_PLUS),
169 FEA_MAP(GTHR),
170 FEA_MAP(ACDC),
171 FEA_MAP(VR0HOT),
172 FEA_MAP(VR1HOT),
173 FEA_MAP(FW_CTF),
174 FEA_MAP(FAN_CONTROL),
175 FEA_MAP(THERMAL),
176 FEA_MAP(GFX_DCS),
177 FEA_MAP(RM),
178 FEA_MAP(LED_DISPLAY),
179 FEA_MAP(GFX_SS),
180 FEA_MAP(OUT_OF_BAND_MONITOR),
181 FEA_MAP(TEMP_DEPENDENT_VMIN),
182 FEA_MAP(MMHUB_PG),
183 FEA_MAP(ATHUB_PG),
cf06331f 184 FEA_MAP(APCC_DFLL),
b455159c
LG		 185};
186
6c339f37 187static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 188 TAB_MAP(PPTABLE),
189 TAB_MAP(WATERMARKS),
190 TAB_MAP(AVFS_PSM_DEBUG),
191 TAB_MAP(AVFS_FUSE_OVERRIDE),
192 TAB_MAP(PMSTATUSLOG),
193 TAB_MAP(SMU_METRICS),
194 TAB_MAP(DRIVER_SMU_CONFIG),
195 TAB_MAP(ACTIVITY_MONITOR_COEFF),
196 TAB_MAP(OVERDRIVE),
197 TAB_MAP(I2C_COMMANDS),
198 TAB_MAP(PACE),
199};
200
6c339f37 201static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 202 PWR_MAP(AC),
203 PWR_MAP(DC),
204};
205
6c339f37 206static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
214};
215
b455159c
LG		 216static int
217sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
218 uint32_t *feature_mask, uint32_t num)
219{
fea905d4
LG		 220 struct amdgpu_device *adev = smu->adev;
221
b455159c
LG		 222 if (num > 2)
223 return -EINVAL;
224
225 memset(feature_mask, 0, sizeof(uint32_t) * num);
226
4cd4f45b 227 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 228 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
094cdf15 229 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 230 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 231 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 232 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 233 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
234 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 235 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 236 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 237 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 238 | FEATURE_MASK(FEATURE_PPT_BIT)
239 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 240 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 241 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 242 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 243 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 244 | FEATURE_MASK(FEATURE_THERMAL_BIT)
245 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 246
c96721eb 247 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 248 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 249 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
250 }
fea905d4 251
65297d50 252 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 253 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
254 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
255 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 256
5cb74353
LG		 257 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
259
5f338f70
LG		 260 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
261 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
262
fea905d4
LG		 263 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
264 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 265
62c1ea6b
LG		 266 if (adev->pm.pp_feature & PP_ULV_MASK)
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
268
02bb391d
LG		 269 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
271
e0da123a
LG		 272 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
274
b794616d
KF		 275 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
277
846938c2
KF		 278 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
280
6fb176a7
LG		 281 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
282 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
284
b455159c
LG		 285 return 0;
286}
287
288static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
289{
4a13b4ce 290 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 291 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 292 table_context->power_play_table;
293 struct smu_baco_context *smu_baco = &smu->smu_baco;
294
295 mutex_lock(&smu_baco->mutex);
e05acd78
LG		 296 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
297 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
4a13b4ce
EQ		 298 smu_baco->platform_support = true;
299 mutex_unlock(&smu_baco->mutex);
300
301 table_context->thermal_controller_type =
302 powerplay_table->thermal_controller_type;
303
b455159c
LG		 304 return 0;
305}
306
307static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
308{
dccc7c21
LG		 309 struct smu_table_context *table_context = &smu->smu_table;
310 PPTable_t *smc_pptable = table_context->driver_pptable;
311 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
312 int index, ret;
dccc7c21
LG		 313
314 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
315 smc_dpm_info);
316
22f2447c 317 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 318 (uint8_t **)&smc_dpm_table);
319 if (ret)
320 return ret;
321
322 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
969c8d16
LG		 323 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
324
b455159c
LG		 325 return 0;
326}
327
328static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
329{
b455159c 330 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 331 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 332 table_context->power_play_table;
b455159c
LG		 333
334 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
335 sizeof(PPTable_t));
336
4a13b4ce
EQ		 337 return 0;
338}
b455159c 339
4a13b4ce
EQ		 340static int sienna_cichlid_setup_pptable(struct smu_context *smu)
341{
342 int ret = 0;
b455159c 343
4a13b4ce
EQ		 344 ret = smu_v11_0_setup_pptable(smu);
345 if (ret)
346 return ret;
347
348 ret = sienna_cichlid_store_powerplay_table(smu);
349 if (ret)
350 return ret;
351
352 ret = sienna_cichlid_append_powerplay_table(smu);
353 if (ret)
354 return ret;
355
356 ret = sienna_cichlid_check_powerplay_table(smu);
357 if (ret)
358 return ret;
359
360 return ret;
b455159c
LG		 361}
362
c1b353b7 363static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 364{
365 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 366 struct smu_table *tables = smu_table->tables;
b455159c
LG		 367
368 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
369 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
370 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
371 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
372 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
373 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 374 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
375 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 376 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
377 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
378 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
379 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
380 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
381 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
382 AMDGPU_GEM_DOMAIN_VRAM);
383
384 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
385 if (!smu_table->metrics_table)
386 return -ENOMEM;
387 smu_table->metrics_time = 0;
388
40d3b8db
LG		 389 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
390 if (!smu_table->watermarks_table)
391 return -ENOMEM;
392
b455159c
LG		 393 return 0;
394}
395
8c686254
EQ		 396static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
397 MetricsMember_t member,
398 uint32_t *value)
b455159c
LG		 399{
400 struct smu_table_context *smu_table= &smu->smu_table;
8c686254 401 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
b455159c
LG		 402 int ret = 0;
403
404 mutex_lock(&smu->metrics_lock);
8c686254 405 if (!smu_table->metrics_time ||
df06583d 406 time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
caad2613 407 ret = smu_cmn_update_table(smu,
8c686254
EQ		 408 SMU_TABLE_SMU_METRICS,
409 0,
410 smu_table->metrics_table,
411 false);
b455159c 412 if (ret) {
d9811cfc 413 dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
b455159c
LG		 414 mutex_unlock(&smu->metrics_lock);
415 return ret;
416 }
417 smu_table->metrics_time = jiffies;
418 }
419
8c686254
EQ		 420 switch (member) {
421 case METRICS_CURR_GFXCLK:
422 *value = metrics->CurrClock[PPCLK_GFXCLK];
423 break;
424 case METRICS_CURR_SOCCLK:
425 *value = metrics->CurrClock[PPCLK_SOCCLK];
426 break;
427 case METRICS_CURR_UCLK:
428 *value = metrics->CurrClock[PPCLK_UCLK];
429 break;
430 case METRICS_CURR_VCLK:
431 *value = metrics->CurrClock[PPCLK_VCLK_0];
432 break;
433 case METRICS_CURR_VCLK1:
434 *value = metrics->CurrClock[PPCLK_VCLK_1];
435 break;
436 case METRICS_CURR_DCLK:
437 *value = metrics->CurrClock[PPCLK_DCLK_0];
438 break;
439 case METRICS_CURR_DCLK1:
440 *value = metrics->CurrClock[PPCLK_DCLK_1];
441 break;
9d09fa6f
ND		 442 case METRICS_CURR_DCEFCLK:
443 *value = metrics->CurrClock[PPCLK_DCEFCLK];
444 break;
8c686254
EQ		 445 case METRICS_AVERAGE_GFXCLK:
446 *value = metrics->AverageGfxclkFrequency;
447 break;
448 case METRICS_AVERAGE_FCLK:
449 *value = metrics->AverageFclkFrequency;
450 break;
451 case METRICS_AVERAGE_UCLK:
452 *value = metrics->AverageUclkFrequency;
453 break;
454 case METRICS_AVERAGE_GFXACTIVITY:
455 *value = metrics->AverageGfxActivity;
456 break;
457 case METRICS_AVERAGE_MEMACTIVITY:
458 *value = metrics->AverageUclkActivity;
459 break;
460 case METRICS_AVERAGE_SOCKETPOWER:
461 *value = metrics->AverageSocketPower << 8;
462 break;
463 case METRICS_TEMPERATURE_EDGE:
464 *value = metrics->TemperatureEdge *
465 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
466 break;
467 case METRICS_TEMPERATURE_HOTSPOT:
468 *value = metrics->TemperatureHotspot *
469 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
470 break;
471 case METRICS_TEMPERATURE_MEM:
472 *value = metrics->TemperatureMem *
473 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
474 break;
475 case METRICS_TEMPERATURE_VRGFX:
476 *value = metrics->TemperatureVrGfx *
477 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
478 break;
479 case METRICS_TEMPERATURE_VRSOC:
480 *value = metrics->TemperatureVrSoc *
481 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
482 break;
483 case METRICS_THROTTLER_STATUS:
484 *value = metrics->ThrottlerStatus;
485 break;
486 case METRICS_CURR_FANSPEED:
487 *value = metrics->CurrFanSpeed;
488 break;
489 default:
490 *value = UINT_MAX;
491 break;
492 }
493
b455159c
LG		 494 mutex_unlock(&smu->metrics_lock);
495
496 return ret;
8c686254 497
b455159c
LG		 498}
499
500static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
501{
502 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
503
b455159c
LG		 504 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
505 GFP_KERNEL);
506 if (!smu_dpm->dpm_context)
507 return -ENOMEM;
508
509 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
510
511 return 0;
512}
513
c1b353b7
EQ		 514static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
515{
516 int ret = 0;
517
518 ret = sienna_cichlid_tables_init(smu);
519 if (ret)
520 return ret;
521
522 ret = sienna_cichlid_allocate_dpm_context(smu);
523 if (ret)
524 return ret;
525
526 return smu_v11_0_init_smc_tables(smu);
527}
528
b455159c
LG		 529static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
530{
90a89c31
EQ		 531 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
532 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
533 struct smu_11_0_dpm_table *dpm_table;
85dec717 534 struct amdgpu_device *adev = smu->adev;
90a89c31 535 int ret = 0;
b455159c 536
90a89c31
EQ		 537 /* socclk dpm table setup */
538 dpm_table = &dpm_context->dpm_tables.soc_table;
b4bb3aaf 539 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 540 ret = smu_v11_0_set_single_dpm_table(smu,
541 SMU_SOCCLK,
542 dpm_table);
543 if (ret)
544 return ret;
545 dpm_table->is_fine_grained =
546 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
547 } else {
548 dpm_table->count = 1;
549 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
550 dpm_table->dpm_levels[0].enabled = true;
551 dpm_table->min = dpm_table->dpm_levels[0].value;
552 dpm_table->max = dpm_table->dpm_levels[0].value;
553 }
b455159c 554
90a89c31
EQ		 555 /* gfxclk dpm table setup */
556 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 557 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 558 ret = smu_v11_0_set_single_dpm_table(smu,
559 SMU_GFXCLK,
560 dpm_table);
561 if (ret)
562 return ret;
563 dpm_table->is_fine_grained =
564 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
565 } else {
566 dpm_table->count = 1;
567 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
568 dpm_table->dpm_levels[0].enabled = true;
569 dpm_table->min = dpm_table->dpm_levels[0].value;
570 dpm_table->max = dpm_table->dpm_levels[0].value;
571 }
b455159c 572
90a89c31
EQ		 573 /* uclk dpm table setup */
574 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 575 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 576 ret = smu_v11_0_set_single_dpm_table(smu,
577 SMU_UCLK,
578 dpm_table);
579 if (ret)
580 return ret;
581 dpm_table->is_fine_grained =
582 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
583 } else {
584 dpm_table->count = 1;
585 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
586 dpm_table->dpm_levels[0].enabled = true;
587 dpm_table->min = dpm_table->dpm_levels[0].value;
588 dpm_table->max = dpm_table->dpm_levels[0].value;
589 }
b455159c 590
90a89c31
EQ		 591 /* fclk dpm table setup */
592 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 593 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 594 ret = smu_v11_0_set_single_dpm_table(smu,
595 SMU_FCLK,
596 dpm_table);
597 if (ret)
598 return ret;
599 dpm_table->is_fine_grained =
600 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
601 } else {
602 dpm_table->count = 1;
603 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
604 dpm_table->dpm_levels[0].enabled = true;
605 dpm_table->min = dpm_table->dpm_levels[0].value;
606 dpm_table->max = dpm_table->dpm_levels[0].value;
607 }
b455159c 608
90a89c31
EQ		 609 /* vclk0 dpm table setup */
610 dpm_table = &dpm_context->dpm_tables.vclk_table;
b4bb3aaf 611 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 612 ret = smu_v11_0_set_single_dpm_table(smu,
613 SMU_VCLK,
614 dpm_table);
615 if (ret)
616 return ret;
617 dpm_table->is_fine_grained =
618 !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
619 } else {
620 dpm_table->count = 1;
621 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
622 dpm_table->dpm_levels[0].enabled = true;
623 dpm_table->min = dpm_table->dpm_levels[0].value;
624 dpm_table->max = dpm_table->dpm_levels[0].value;
625 }
b455159c 626
90a89c31 627 /* vclk1 dpm table setup */
85dec717
JC		 628 if (adev->vcn.num_vcn_inst > 1) {
629 dpm_table = &dpm_context->dpm_tables.vclk1_table;
630 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
631 ret = smu_v11_0_set_single_dpm_table(smu,
632 SMU_VCLK1,
633 dpm_table);
634 if (ret)
635 return ret;
636 dpm_table->is_fine_grained =
637 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
638 } else {
639 dpm_table->count = 1;
640 dpm_table->dpm_levels[0].value =
641 smu->smu_table.boot_values.vclk / 100;
642 dpm_table->dpm_levels[0].enabled = true;
643 dpm_table->min = dpm_table->dpm_levels[0].value;
644 dpm_table->max = dpm_table->dpm_levels[0].value;
645 }
90a89c31 646 }
b455159c 647
90a89c31
EQ		 648 /* dclk0 dpm table setup */
649 dpm_table = &dpm_context->dpm_tables.dclk_table;
b4bb3aaf 650 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 651 ret = smu_v11_0_set_single_dpm_table(smu,
652 SMU_DCLK,
653 dpm_table);
654 if (ret)
655 return ret;
656 dpm_table->is_fine_grained =
657 !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
658 } else {
659 dpm_table->count = 1;
660 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
661 dpm_table->dpm_levels[0].enabled = true;
662 dpm_table->min = dpm_table->dpm_levels[0].value;
663 dpm_table->max = dpm_table->dpm_levels[0].value;
664 }
665
666 /* dclk1 dpm table setup */
85dec717
JC		 667 if (adev->vcn.num_vcn_inst > 1) {
668 dpm_table = &dpm_context->dpm_tables.dclk1_table;
669 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
670 ret = smu_v11_0_set_single_dpm_table(smu,
671 SMU_DCLK1,
672 dpm_table);
673 if (ret)
674 return ret;
675 dpm_table->is_fine_grained =
676 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
677 } else {
678 dpm_table->count = 1;
679 dpm_table->dpm_levels[0].value =
680 smu->smu_table.boot_values.dclk / 100;
681 dpm_table->dpm_levels[0].enabled = true;
682 dpm_table->min = dpm_table->dpm_levels[0].value;
683 dpm_table->max = dpm_table->dpm_levels[0].value;
684 }
90a89c31
EQ		 685 }
686
687 /* dcefclk dpm table setup */
688 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 689 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 690 ret = smu_v11_0_set_single_dpm_table(smu,
691 SMU_DCEFCLK,
692 dpm_table);
693 if (ret)
694 return ret;
695 dpm_table->is_fine_grained =
696 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
697 } else {
698 dpm_table->count = 1;
699 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
700 dpm_table->dpm_levels[0].enabled = true;
701 dpm_table->min = dpm_table->dpm_levels[0].value;
702 dpm_table->max = dpm_table->dpm_levels[0].value;
703 }
b455159c 704
90a89c31
EQ		 705 /* pixelclk dpm table setup */
706 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 707 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 708 ret = smu_v11_0_set_single_dpm_table(smu,
709 SMU_PIXCLK,
710 dpm_table);
711 if (ret)
712 return ret;
713 dpm_table->is_fine_grained =
714 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
715 } else {
716 dpm_table->count = 1;
717 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
718 dpm_table->dpm_levels[0].enabled = true;
719 dpm_table->min = dpm_table->dpm_levels[0].value;
720 dpm_table->max = dpm_table->dpm_levels[0].value;
721 }
b455159c 722
90a89c31
EQ		 723 /* displayclk dpm table setup */
724 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 725 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 726 ret = smu_v11_0_set_single_dpm_table(smu,
727 SMU_DISPCLK,
728 dpm_table);
729 if (ret)
730 return ret;
731 dpm_table->is_fine_grained =
732 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
733 } else {
734 dpm_table->count = 1;
735 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
736 dpm_table->dpm_levels[0].enabled = true;
737 dpm_table->min = dpm_table->dpm_levels[0].value;
738 dpm_table->max = dpm_table->dpm_levels[0].value;
739 }
b455159c 740
90a89c31
EQ		 741 /* phyclk dpm table setup */
742 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 743 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 744 ret = smu_v11_0_set_single_dpm_table(smu,
745 SMU_PHYCLK,
746 dpm_table);
747 if (ret)
748 return ret;
749 dpm_table->is_fine_grained =
750 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
751 } else {
752 dpm_table->count = 1;
753 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
754 dpm_table->dpm_levels[0].enabled = true;
755 dpm_table->min = dpm_table->dpm_levels[0].value;
756 dpm_table->max = dpm_table->dpm_levels[0].value;
757 }
b455159c
LG		 758
759 return 0;
760}
761
f6b4b4a1 762static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c
LG		 763{
764 struct smu_power_context *smu_power = &smu->smu_power;
765 struct smu_power_gate *power_gate = &smu_power->power_gate;
d51dc613
JC		 766 struct amdgpu_device *adev = smu->adev;
767
b455159c
LG		 768 int ret = 0;
769
770 if (enable) {
771 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 772 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 773 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
6fb176a7
LG		 774 if (ret)
775 return ret;
d51dc613 776 if (adev->asic_type == CHIP_SIENNA_CICHLID) {
66c86828 777 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
d51dc613
JC		 778 0x10000, NULL);
779 if (ret)
780 return ret;
781 }
b455159c
LG		 782 }
783 power_gate->vcn_gated = false;
784 } else {
b4bb3aaf 785 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 786 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
6fb176a7
LG		 787 if (ret)
788 return ret;
d51dc613 789 if (adev->asic_type == CHIP_SIENNA_CICHLID) {
66c86828 790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
d51dc613
JC		 791 0x10000, NULL);
792 if (ret)
793 return ret;
794 }
b455159c
LG		 795 }
796 power_gate->vcn_gated = true;
797 }
798
799 return ret;
800}
801
6fb176a7
LG		 802static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
803{
804 struct smu_power_context *smu_power = &smu->smu_power;
805 struct smu_power_gate *power_gate = &smu_power->power_gate;
806 int ret = 0;
807
808 if (enable) {
b4bb3aaf 809 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 810 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 811 if (ret)
812 return ret;
6fb176a7
LG		 813 }
814 power_gate->jpeg_gated = false;
815 } else {
b4bb3aaf 816 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 817 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 818 if (ret)
819 return ret;
6fb176a7
LG		 820 }
821 power_gate->jpeg_gated = true;
822 }
823
824 return ret;
825}
826
b455159c
LG		 827static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
828 enum smu_clk_type clk_type,
829 uint32_t *value)
830{
8c686254
EQ		 831 MetricsMember_t member_type;
832 int clk_id = 0;
b455159c 833
6c339f37
EQ		 834 clk_id = smu_cmn_to_asic_specific_index(smu,
835 CMN2ASIC_MAPPING_CLK,
836 clk_type);
b455159c
LG		 837 if (clk_id < 0)
838 return clk_id;
839
8c686254
EQ		 840 switch (clk_id) {
841 case PPCLK_GFXCLK:
842 member_type = METRICS_CURR_GFXCLK;
843 break;
844 case PPCLK_UCLK:
845 member_type = METRICS_CURR_UCLK;
846 break;
847 case PPCLK_SOCCLK:
848 member_type = METRICS_CURR_SOCCLK;
849 break;
850 case PPCLK_FCLK:
851 member_type = METRICS_CURR_FCLK;
852 break;
853 case PPCLK_VCLK_0:
854 member_type = METRICS_CURR_VCLK;
855 break;
856 case PPCLK_VCLK_1:
857 member_type = METRICS_CURR_VCLK1;
858 break;
859 case PPCLK_DCLK_0:
860 member_type = METRICS_CURR_DCLK;
861 break;
862 case PPCLK_DCLK_1:
863 member_type = METRICS_CURR_DCLK1;
864 break;
865 case PPCLK_DCEFCLK:
866 member_type = METRICS_CURR_DCEFCLK;
867 break;
868 default:
869 return -EINVAL;
870 }
871
872 return sienna_cichlid_get_smu_metrics_data(smu,
873 member_type,
874 value);
b455159c 875
b455159c
LG		 876}
877
878static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
879{
880 PPTable_t *pptable = smu->smu_table.driver_pptable;
881 DpmDescriptor_t *dpm_desc = NULL;
882 uint32_t clk_index = 0;
883
6c339f37
EQ		 884 clk_index = smu_cmn_to_asic_specific_index(smu,
885 CMN2ASIC_MAPPING_CLK,
886 clk_type);
b455159c
LG		 887 dpm_desc = &pptable->DpmDescriptor[clk_index];
888
889 /* 0 - Fine grained DPM, 1 - Discrete DPM */
890 return dpm_desc->SnapToDiscrete == 0 ? true : false;
891}
892
893static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
894 enum smu_clk_type clk_type, char *buf)
895{
b7d25b5f
LG		 896 struct amdgpu_device *adev = smu->adev;
897 struct smu_table_context *table_context = &smu->smu_table;
898 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
899 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
900 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
b455159c
LG		 901 int i, size = 0, ret = 0;
902 uint32_t cur_value = 0, value = 0, count = 0;
903 uint32_t freq_values[3] = {0};
904 uint32_t mark_index = 0;
b7d25b5f 905 uint32_t gen_speed, lane_width;
b455159c
LG		 906
907 switch (clk_type) {
908 case SMU_GFXCLK:
909 case SMU_SCLK:
910 case SMU_SOCCLK:
911 case SMU_MCLK:
912 case SMU_UCLK:
913 case SMU_FCLK:
914 case SMU_DCEFCLK:
5e6dc8fe 915 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 916 if (ret)
258d290c 917 goto print_clk_out;
b455159c 918
ba818620
KF		 919 /* no need to disable gfxoff when retrieving the current gfxclk */
920 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
921 amdgpu_gfx_off_ctrl(adev, false);
922
d8d3493a 923 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 924 if (ret)
258d290c 925 goto print_clk_out;
b455159c
LG		 926
927 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
928 for (i = 0; i < count; i++) {
d8d3493a 929 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 930 if (ret)
258d290c 931 goto print_clk_out;
b455159c
LG		 932
933 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
934 cur_value == value ? "*" : "");
935 }
936 } else {
d8d3493a 937 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 938 if (ret)
258d290c 939 goto print_clk_out;
d8d3493a 940 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 941 if (ret)
258d290c 942 goto print_clk_out;
b455159c
LG		 943
944 freq_values[1] = cur_value;
945 mark_index = cur_value == freq_values[0] ? 0 :
946 cur_value == freq_values[2] ? 2 : 1;
947 if (mark_index != 1)
948 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
949
950 for (i = 0; i < 3; i++) {
951 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
952 i == mark_index ? "*" : "");
953 }
954
955 }
956 break;
b7d25b5f
LG		 957 case SMU_PCIE:
958 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
959 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
960 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
961 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
962 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
963 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
964 for (i = 0; i < NUM_LINK_LEVELS; i++)
965 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
966 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
967 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
968 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
969 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
970 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
971 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
972 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
973 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
974 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
975 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
976 pptable->LclkFreq[i],
977 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
978 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
979 "*" : "");
980 break;
b455159c
LG		 981 default:
982 break;
983 }
984
258d290c
LG		 985print_clk_out:
986 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
987 amdgpu_gfx_off_ctrl(adev, true);
988
b455159c
LG		 989 return size;
990}
991
992static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
993 enum smu_clk_type clk_type, uint32_t mask)
994{
258d290c 995 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 996 int ret = 0, size = 0;
997 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
998
999 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1000 soft_max_level = mask ? (fls(mask) - 1) : 0;
1001
258d290c
LG		 1002 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1003 amdgpu_gfx_off_ctrl(adev, false);
1004
b455159c
LG		 1005 switch (clk_type) {
1006 case SMU_GFXCLK:
1007 case SMU_SCLK:
1008 case SMU_SOCCLK:
1009 case SMU_MCLK:
1010 case SMU_UCLK:
1011 case SMU_DCEFCLK:
1012 case SMU_FCLK:
9ad9c8ac
LG		 1013 /* There is only 2 levels for fine grained DPM */
1014 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1015 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1016 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1017 }
1018
d8d3493a 1019 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1020 if (ret)
258d290c 1021 goto forec_level_out;
b455159c 1022
d8d3493a 1023 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1024 if (ret)
258d290c 1025 goto forec_level_out;
b455159c 1026
10e96d89 1027 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1028 if (ret)
258d290c 1029 goto forec_level_out;
b455159c
LG		 1030 break;
1031 default:
1032 break;
1033 }
1034
258d290c
LG		 1035forec_level_out:
1036 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1037 amdgpu_gfx_off_ctrl(adev, true);
1038
b455159c
LG		 1039 return size;
1040}
1041
1042static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1043{
62cc9dd1
EQ		 1044 struct smu_11_0_dpm_context *dpm_context =
1045 smu->smu_dpm.dpm_context;
1046 struct smu_11_0_dpm_table *gfx_table =
1047 &dpm_context->dpm_tables.gfx_table;
1048 struct smu_11_0_dpm_table *mem_table =
1049 &dpm_context->dpm_tables.uclk_table;
1050 struct smu_11_0_dpm_table *soc_table =
1051 &dpm_context->dpm_tables.soc_table;
1052 struct smu_umd_pstate_table *pstate_table =
1053 &smu->pstate_table;
1054
1055 pstate_table->gfxclk_pstate.min = gfx_table->min;
1056 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1057
1058 pstate_table->uclk_pstate.min = mem_table->min;
1059 pstate_table->uclk_pstate.peak = mem_table->max;
1060
1061 pstate_table->socclk_pstate.min = soc_table->min;
1062 pstate_table->socclk_pstate.peak = soc_table->max;
b455159c 1063
62cc9dd1 1064 return 0;
b455159c
LG		 1065}
1066
b455159c
LG		 1067static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1068{
1069 int ret = 0;
1070 uint32_t max_freq = 0;
1071
1072 /* Sienna_Cichlid do not support to change display num currently */
1073 return 0;
1074#if 0
66c86828 1075 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1076 if (ret)
1077 return ret;
1078#endif
1079
b4bb3aaf 1080 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1081 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1082 if (ret)
1083 return ret;
661b94f5 1084 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1085 if (ret)
1086 return ret;
1087 }
1088
1089 return ret;
1090}
1091
1092static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1093{
1094 int ret = 0;
1095
b455159c 1096 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1097 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1098 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1099#if 0
66c86828 1100 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1101 smu->display_config->num_display,
1102 NULL);
b455159c
LG		 1103#endif
1104 if (ret)
1105 return ret;
1106 }
1107
1108 return ret;
1109}
1110
b455159c
LG		 1111static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1112{
b455159c
LG		 1113 if (!value)
1114 return -EINVAL;
1115
8c686254
EQ		 1116 return sienna_cichlid_get_smu_metrics_data(smu,
1117 METRICS_AVERAGE_SOCKETPOWER,
1118 value);
b455159c
LG		 1119}
1120
1121static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1122 enum amd_pp_sensors sensor,
1123 uint32_t *value)
1124{
1125 int ret = 0;
b455159c
LG		 1126
1127 if (!value)
1128 return -EINVAL;
1129
b455159c
LG		 1130 switch (sensor) {
1131 case AMDGPU_PP_SENSOR_GPU_LOAD:
8c686254
EQ		 1132 ret = sienna_cichlid_get_smu_metrics_data(smu,
1133 METRICS_AVERAGE_GFXACTIVITY,
1134 value);
b455159c
LG		 1135 break;
1136 case AMDGPU_PP_SENSOR_MEM_LOAD:
8c686254
EQ		 1137 ret = sienna_cichlid_get_smu_metrics_data(smu,
1138 METRICS_AVERAGE_MEMACTIVITY,
1139 value);
b455159c
LG		 1140 break;
1141 default:
d9811cfc 1142 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
b455159c
LG		 1143 return -EINVAL;
1144 }
1145
8c686254 1146 return ret;
b455159c
LG		 1147}
1148
1149static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1150{
1151 int ret = 0;
1152 uint32_t feature_mask[2];
1153 unsigned long feature_enabled;
28251d72 1154 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
b455159c
LG		 1155 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1156 ((uint64_t)feature_mask[1] << 32));
1157 return !!(feature_enabled & SMC_DPM_FEATURE);
1158}
1159
1160static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1161 uint32_t *speed)
1162{
b455159c
LG		 1163 if (!speed)
1164 return -EINVAL;
1165
8c686254
EQ		 1166 return sienna_cichlid_get_smu_metrics_data(smu,
1167 METRICS_CURR_FANSPEED,
1168 speed);
b455159c
LG		 1169}
1170
1171static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1172 uint32_t *speed)
1173{
1174 int ret = 0;
1175 uint32_t percent = 0;
1176 uint32_t current_rpm;
1177 PPTable_t *pptable = smu->smu_table.driver_pptable;
1178
1179 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
1180 if (ret)
1181 return ret;
1182
1183 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1184 *speed = percent > 100 ? 100 : percent;
1185
1186 return ret;
1187}
1188
1189static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1190{
1191 DpmActivityMonitorCoeffInt_t activity_monitor;
1192 uint32_t i, size = 0;
1193 int16_t workload_type = 0;
1194 static const char *profile_name[] = {
1195 "BOOTUP_DEFAULT",
1196 "3D_FULL_SCREEN",
1197 "POWER_SAVING",
1198 "VIDEO",
1199 "VR",
1200 "COMPUTE",
1201 "CUSTOM"};
1202 static const char *title[] = {
1203 "PROFILE_INDEX(NAME)",
1204 "CLOCK_TYPE(NAME)",
1205 "FPS",
1206 "MinFreqType",
1207 "MinActiveFreqType",
1208 "MinActiveFreq",
1209 "BoosterFreqType",
1210 "BoosterFreq",
1211 "PD_Data_limit_c",
1212 "PD_Data_error_coeff",
1213 "PD_Data_error_rate_coeff"};
1214 int result = 0;
1215
1216 if (!buf)
1217 return -EINVAL;
1218
1219 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1220 title[0], title[1], title[2], title[3], title[4], title[5],
1221 title[6], title[7], title[8], title[9], title[10]);
1222
1223 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1224 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1225 workload_type = smu_cmn_to_asic_specific_index(smu,
1226 CMN2ASIC_MAPPING_WORKLOAD,
1227 i);
b455159c
LG		 1228 if (workload_type < 0)
1229 return -EINVAL;
1230
caad2613 1231 result = smu_cmn_update_table(smu,
b455159c
LG		 1232 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1233 (void *)(&activity_monitor), false);
1234 if (result) {
d9811cfc 1235 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1236 return result;
1237 }
1238
1239 size += sprintf(buf + size, "%2d %14s%s:\n",
1240 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1241
1242 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1243 " ",
1244 0,
1245 "GFXCLK",
1246 activity_monitor.Gfx_FPS,
1247 activity_monitor.Gfx_MinFreqStep,
1248 activity_monitor.Gfx_MinActiveFreqType,
1249 activity_monitor.Gfx_MinActiveFreq,
1250 activity_monitor.Gfx_BoosterFreqType,
1251 activity_monitor.Gfx_BoosterFreq,
1252 activity_monitor.Gfx_PD_Data_limit_c,
1253 activity_monitor.Gfx_PD_Data_error_coeff,
1254 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1255
1256 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1257 " ",
1258 1,
1259 "SOCCLK",
1260 activity_monitor.Fclk_FPS,
1261 activity_monitor.Fclk_MinFreqStep,
1262 activity_monitor.Fclk_MinActiveFreqType,
1263 activity_monitor.Fclk_MinActiveFreq,
1264 activity_monitor.Fclk_BoosterFreqType,
1265 activity_monitor.Fclk_BoosterFreq,
1266 activity_monitor.Fclk_PD_Data_limit_c,
1267 activity_monitor.Fclk_PD_Data_error_coeff,
1268 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1269
1270 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1271 " ",
1272 2,
1273 "MEMLK",
1274 activity_monitor.Mem_FPS,
1275 activity_monitor.Mem_MinFreqStep,
1276 activity_monitor.Mem_MinActiveFreqType,
1277 activity_monitor.Mem_MinActiveFreq,
1278 activity_monitor.Mem_BoosterFreqType,
1279 activity_monitor.Mem_BoosterFreq,
1280 activity_monitor.Mem_PD_Data_limit_c,
1281 activity_monitor.Mem_PD_Data_error_coeff,
1282 activity_monitor.Mem_PD_Data_error_rate_coeff);
1283 }
1284
1285 return size;
1286}
1287
1288static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1289{
1290 DpmActivityMonitorCoeffInt_t activity_monitor;
1291 int workload_type, ret = 0;
1292
1293 smu->power_profile_mode = input[size];
1294
1295 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1296 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1297 return -EINVAL;
1298 }
1299
1300 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1301
caad2613 1302 ret = smu_cmn_update_table(smu,
b455159c
LG		 1303 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1304 (void *)(&activity_monitor), false);
1305 if (ret) {
d9811cfc 1306 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1307 return ret;
1308 }
1309
1310 switch (input[0]) {
1311 case 0: /* Gfxclk */
1312 activity_monitor.Gfx_FPS = input[1];
1313 activity_monitor.Gfx_MinFreqStep = input[2];
1314 activity_monitor.Gfx_MinActiveFreqType = input[3];
1315 activity_monitor.Gfx_MinActiveFreq = input[4];
1316 activity_monitor.Gfx_BoosterFreqType = input[5];
1317 activity_monitor.Gfx_BoosterFreq = input[6];
1318 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1319 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1320 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1321 break;
1322 case 1: /* Socclk */
1323 activity_monitor.Fclk_FPS = input[1];
1324 activity_monitor.Fclk_MinFreqStep = input[2];
1325 activity_monitor.Fclk_MinActiveFreqType = input[3];
1326 activity_monitor.Fclk_MinActiveFreq = input[4];
1327 activity_monitor.Fclk_BoosterFreqType = input[5];
1328 activity_monitor.Fclk_BoosterFreq = input[6];
1329 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1330 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1331 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1332 break;
1333 case 2: /* Memlk */
1334 activity_monitor.Mem_FPS = input[1];
1335 activity_monitor.Mem_MinFreqStep = input[2];
1336 activity_monitor.Mem_MinActiveFreqType = input[3];
1337 activity_monitor.Mem_MinActiveFreq = input[4];
1338 activity_monitor.Mem_BoosterFreqType = input[5];
1339 activity_monitor.Mem_BoosterFreq = input[6];
1340 activity_monitor.Mem_PD_Data_limit_c = input[7];
1341 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1342 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1343 break;
1344 }
1345
caad2613 1346 ret = smu_cmn_update_table(smu,
b455159c
LG		 1347 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1348 (void *)(&activity_monitor), true);
1349 if (ret) {
d9811cfc 1350 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1351 return ret;
1352 }
1353 }
1354
1355 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1356 workload_type = smu_cmn_to_asic_specific_index(smu,
1357 CMN2ASIC_MAPPING_WORKLOAD,
1358 smu->power_profile_mode);
b455159c
LG		 1359 if (workload_type < 0)
1360 return -EINVAL;
66c86828 1361 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1362 1 << workload_type, NULL);
1363
1364 return ret;
1365}
1366
b455159c
LG		 1367static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1368{
1369 struct smu_clocks min_clocks = {0};
1370 struct pp_display_clock_request clock_req;
1371 int ret = 0;
1372
1373 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1374 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1375 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1376
4d942ae3 1377 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1378 clock_req.clock_type = amd_pp_dcef_clock;
1379 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1380
1381 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1382 if (!ret) {
4d942ae3 1383 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1384 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1385 SMU_MSG_SetMinDeepSleepDcefclk,
1386 min_clocks.dcef_clock_in_sr/100,
1387 NULL);
1388 if (ret) {
d9811cfc 1389 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1390 return ret;
1391 }
b455159c
LG		 1392 }
1393 } else {
d9811cfc 1394 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1395 }
1396 }
1397
b4bb3aaf 1398 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1399 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1400 if (ret) {
d9811cfc 1401 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1402 return ret;
1403 }
1404 }
1405
1406 return 0;
1407}
1408
1409static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
e7a95eea
EQ		 1410 struct dm_pp_wm_sets_with_clock_ranges_soc15
1411 *clock_ranges)
b455159c 1412{
e7a95eea 1413 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1414 int ret = 0;
e7a95eea 1415 int i;
b455159c 1416
e7a95eea
EQ		 1417 if (clock_ranges) {
1418 if (clock_ranges->num_wm_dmif_sets > 4 ||
1419 clock_ranges->num_wm_mcif_sets > 4)
1420 return -EINVAL;
1421
1422 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1423 table->WatermarkRow[1][i].MinClock =
1424 cpu_to_le16((uint16_t)
1425 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1426 1000));
1427 table->WatermarkRow[1][i].MaxClock =
1428 cpu_to_le16((uint16_t)
1429 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1430 1000));
1431 table->WatermarkRow[1][i].MinUclk =
1432 cpu_to_le16((uint16_t)
1433 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1434 1000));
1435 table->WatermarkRow[1][i].MaxUclk =
1436 cpu_to_le16((uint16_t)
1437 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1438 1000));
1439 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1440 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1441 }
b455159c 1442
e7a95eea
EQ		 1443 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1444 table->WatermarkRow[0][i].MinClock =
1445 cpu_to_le16((uint16_t)
1446 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1447 1000));
1448 table->WatermarkRow[0][i].MaxClock =
1449 cpu_to_le16((uint16_t)
1450 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1451 1000));
1452 table->WatermarkRow[0][i].MinUclk =
1453 cpu_to_le16((uint16_t)
1454 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1455 1000));
1456 table->WatermarkRow[0][i].MaxUclk =
1457 cpu_to_le16((uint16_t)
1458 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1459 1000));
1460 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1461 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1462 }
1463
1464 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1465 }
1466
1467 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1468 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1469 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1470 if (ret) {
d9811cfc 1471 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1472 return ret;
1473 }
1474 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1475 }
1476
b455159c
LG		 1477 return 0;
1478}
1479
1480static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1481 enum amd_pp_sensors sensor,
1482 uint32_t *value)
1483{
b455159c
LG		 1484 int ret = 0;
1485
1486 if (!value)
1487 return -EINVAL;
1488
b455159c
LG		 1489 switch (sensor) {
1490 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
8c686254
EQ		 1491 ret = sienna_cichlid_get_smu_metrics_data(smu,
1492 METRICS_TEMPERATURE_HOTSPOT,
1493 value);
b455159c
LG		 1494 break;
1495 case AMDGPU_PP_SENSOR_EDGE_TEMP:
8c686254
EQ		 1496 ret = sienna_cichlid_get_smu_metrics_data(smu,
1497 METRICS_TEMPERATURE_EDGE,
1498 value);
b455159c
LG		 1499 break;
1500 case AMDGPU_PP_SENSOR_MEM_TEMP:
8c686254
EQ		 1501 ret = sienna_cichlid_get_smu_metrics_data(smu,
1502 METRICS_TEMPERATURE_MEM,
1503 value);
b455159c
LG		 1504 break;
1505 default:
d9811cfc 1506 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
b455159c
LG		 1507 return -EINVAL;
1508 }
1509
8c686254 1510 return ret;
b455159c
LG		 1511}
1512
1513static int sienna_cichlid_read_sensor(struct smu_context *smu,
1514 enum amd_pp_sensors sensor,
1515 void *data, uint32_t *size)
1516{
1517 int ret = 0;
1518 struct smu_table_context *table_context = &smu->smu_table;
1519 PPTable_t *pptable = table_context->driver_pptable;
1520
1521 if(!data || !size)
1522 return -EINVAL;
1523
1524 mutex_lock(&smu->sensor_lock);
1525 switch (sensor) {
1526 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1527 *(uint32_t *)data = pptable->FanMaximumRpm;
1528 *size = 4;
1529 break;
1530 case AMDGPU_PP_SENSOR_MEM_LOAD:
1531 case AMDGPU_PP_SENSOR_GPU_LOAD:
1532 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1533 *size = 4;
1534 break;
1535 case AMDGPU_PP_SENSOR_GPU_POWER:
1536 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1537 *size = 4;
1538 break;
1539 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1540 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1541 case AMDGPU_PP_SENSOR_MEM_TEMP:
1542 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1543 *size = 4;
1544 break;
e0f9e936
EQ		 1545 case AMDGPU_PP_SENSOR_GFX_MCLK:
1546 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1547 *(uint32_t *)data *= 100;
1548 *size = 4;
1549 break;
1550 case AMDGPU_PP_SENSOR_GFX_SCLK:
1551 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1552 *(uint32_t *)data *= 100;
1553 *size = 4;
1554 break;
b2febc99
EQ		 1555 case AMDGPU_PP_SENSOR_VDDGFX:
1556 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1557 *size = 4;
1558 break;
b455159c 1559 default:
b2febc99
EQ		 1560 ret = -EOPNOTSUPP;
1561 break;
b455159c
LG		 1562 }
1563 mutex_unlock(&smu->sensor_lock);
1564
1565 return ret;
1566}
1567
1568static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1569{
1570 uint32_t num_discrete_levels = 0;
1571 uint16_t *dpm_levels = NULL;
1572 uint16_t i = 0;
1573 struct smu_table_context *table_context = &smu->smu_table;
1574 PPTable_t *driver_ppt = NULL;
1575
1576 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1577 return -EINVAL;
1578
1579 driver_ppt = table_context->driver_pptable;
1580 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1581 dpm_levels = driver_ppt->FreqTableUclk;
1582
1583 if (num_discrete_levels == 0 || dpm_levels == NULL)
1584 return -EINVAL;
1585
1586 *num_states = num_discrete_levels;
1587 for (i = 0; i < num_discrete_levels; i++) {
1588 /* convert to khz */
1589 *clocks_in_khz = (*dpm_levels) * 1000;
1590 clocks_in_khz++;
1591 dpm_levels++;
1592 }
1593
1594 return 0;
1595}
1596
1597static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1598 struct smu_temperature_range *range)
1599{
e02e4d51
EQ		 1600 struct smu_table_context *table_context = &smu->smu_table;
1601 struct smu_11_0_7_powerplay_table *powerplay_table =
1602 table_context->power_play_table;
2b1f12a2 1603 PPTable_t *pptable = smu->smu_table.driver_pptable;
b455159c 1604
2b1f12a2 1605 if (!range)
b455159c
LG		 1606 return -EINVAL;
1607
0540eced
EQ		 1608 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1609
2b1f12a2
EQ		 1610 range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1611 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1612 range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1613 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1614 range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1615 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1616 range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1617 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1618 range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1619 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1620 range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
b455159c 1621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
e02e4d51 1622 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1623
1624 return 0;
1625}
1626
1627static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1628 bool disable_memory_clock_switch)
1629{
1630 int ret = 0;
1631 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1632 (struct smu_11_0_max_sustainable_clocks *)
1633 smu->smu_table.max_sustainable_clocks;
1634 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1635 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1636
1637 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1638 return 0;
1639
1640 if(disable_memory_clock_switch)
661b94f5 1641 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1642 else
661b94f5 1643 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1644
1645 if(!ret)
1646 smu->disable_uclk_switch = disable_memory_clock_switch;
1647
1648 return ret;
1649}
1650
a141b4e3 1651static int sienna_cichlid_get_power_limit(struct smu_context *smu)
b455159c 1652{
1e239fdd
EQ		 1653 struct smu_11_0_7_powerplay_table *powerplay_table =
1654 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
b455159c 1655 PPTable_t *pptable = smu->smu_table.driver_pptable;
1e239fdd
EQ		 1656 uint32_t power_limit, od_percent;
1657
1658 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1659 /* the last hope to figure out the ppt limit */
1660 if (!pptable) {
1661 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1662 return -EINVAL;
b455159c 1663 }
1e239fdd
EQ		 1664 power_limit =
1665 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1666 }
1667 smu->current_power_limit = power_limit;
b455159c 1668
1e239fdd
EQ		 1669 if (smu->od_enabled) {
1670 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1671
1672 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1673
1674 power_limit *= (100 + od_percent);
1675 power_limit /= 100;
b455159c 1676 }
1e239fdd 1677 smu->max_power_limit = power_limit;
b455159c 1678
b455159c
LG		 1679 return 0;
1680}
1681
08ccfe08
LG		 1682static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1683 uint32_t pcie_gen_cap,
1684 uint32_t pcie_width_cap)
1685{
0b590970 1686 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
08ccfe08 1687 PPTable_t *pptable = smu->smu_table.driver_pptable;
08ccfe08 1688 uint32_t smu_pcie_arg;
0b590970 1689 int ret, i;
08ccfe08 1690
0b590970
EQ		 1691 /* lclk dpm table setup */
1692 for (i = 0; i < MAX_PCIE_CONF; i++) {
1693 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1694 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1695 }
08ccfe08
LG		 1696
1697 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1698 smu_pcie_arg = (i << 16) |
1699 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1700 (pptable->PcieGenSpeed[i] << 8) :
1701 (pcie_gen_cap << 8)) |
1702 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1703 pptable->PcieLaneCount[i] :
1704 pcie_width_cap);
1705
66c86828 1706 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1707 SMU_MSG_OverridePcieParameters,
1708 smu_pcie_arg,
1709 NULL);
1710
08ccfe08
LG		 1711 if (ret)
1712 return ret;
1713
1714 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1715 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1716 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1717 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1718 }
1719
1720 return 0;
1721}
1722
38ed7b09 1723static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1724 enum smu_clk_type clk_type,
1725 uint32_t *min, uint32_t *max)
1726{
1727 struct amdgpu_device *adev = smu->adev;
1728 int ret;
1729
1730 if (clk_type == SMU_GFXCLK)
1731 amdgpu_gfx_off_ctrl(adev, false);
1732 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1733 if (clk_type == SMU_GFXCLK)
1734 amdgpu_gfx_off_ctrl(adev, true);
1735
1736 return ret;
1737}
1738
40d3b8db
LG		 1739static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1740{
1741 struct amdgpu_device *adev = smu->adev;
1742 uint32_t val;
1743
311531f0 1744 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
40d3b8db
LG		 1745 return false;
1746
1747 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1748 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1749}
1750
ea8139d8
WS		 1751static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1752{
1753 struct amdgpu_device *adev = smu->adev;
1754 uint32_t val;
1755 u32 smu_version;
1756
1757 /**
1758 * SRIOV env will not support SMU mode1 reset
1759 * PM FW support mode1 reset from 58.26
1760 */
a7bae061 1761 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 1762 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1763 return false;
1764
1765 /**
1766 * mode1 reset relies on PSP, so we should check if
1767 * PSP is alive.
1768 */
1769 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1770 return val != 0x0;
1771}
1772
b455159c
LG		 1773static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1774{
1775 struct smu_table_context *table_context = &smu->smu_table;
1776 PPTable_t *pptable = table_context->driver_pptable;
1777 int i;
1778
d9811cfc 1779 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 1780
d9811cfc
EQ		 1781 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1782 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1783 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 1784
1785 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 1786 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1787 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1788 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1789 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 1790 }
1791
1792 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 1793 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1794 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 1795 }
1796
1797 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 1798 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 1799 }
1800
d9811cfc
EQ		 1801 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1802 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1803 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1804 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1805 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 1806
d9811cfc 1807 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 1808 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 1809 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1810 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 1811 }
d9811cfc
EQ		 1812 dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1813 dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1814 dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1815 dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1816
1817 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1818
1819 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1820
1821 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1822 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1823 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1824 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1825
1826 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1827 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1828
1829 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1830 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1831 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1832 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1833
1834 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1835 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1836 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1837 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1838
1839 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1840 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1841
1842 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1843 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1844 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1845 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1846 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1847 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1848 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1849 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1850
1851 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 1852 " .VoltageMode = 0x%02x\n"
1853 " .SnapToDiscrete = 0x%02x\n"
1854 " .NumDiscreteLevels = 0x%02x\n"
1855 " .padding = 0x%02x\n"
1856 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1857 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1858 " .SsFmin = 0x%04x\n"
1859 " .Padding_16 = 0x%04x\n",
1860 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1861 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1862 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1863 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1864 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1865 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1866 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1867 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1868 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1869 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1870 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1871
d9811cfc 1872 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 1873 " .VoltageMode = 0x%02x\n"
1874 " .SnapToDiscrete = 0x%02x\n"
1875 " .NumDiscreteLevels = 0x%02x\n"
1876 " .padding = 0x%02x\n"
1877 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1878 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1879 " .SsFmin = 0x%04x\n"
1880 " .Padding_16 = 0x%04x\n",
1881 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1882 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1883 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1884 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1885 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1886 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1887 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1888 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1889 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1890 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1891 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1892
d9811cfc 1893 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 1894 " .VoltageMode = 0x%02x\n"
1895 " .SnapToDiscrete = 0x%02x\n"
1896 " .NumDiscreteLevels = 0x%02x\n"
1897 " .padding = 0x%02x\n"
1898 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1899 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1900 " .SsFmin = 0x%04x\n"
1901 " .Padding_16 = 0x%04x\n",
1902 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1903 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1904 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1905 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1906 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1907 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1908 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1909 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1910 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1911 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1912 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1913
d9811cfc 1914 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 1915 " .VoltageMode = 0x%02x\n"
1916 " .SnapToDiscrete = 0x%02x\n"
1917 " .NumDiscreteLevels = 0x%02x\n"
1918 " .padding = 0x%02x\n"
1919 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1920 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1921 " .SsFmin = 0x%04x\n"
1922 " .Padding_16 = 0x%04x\n",
1923 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1924 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1925 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1926 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1927 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1928 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1929 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1930 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1931 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1932 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1933 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1934
d9811cfc 1935 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 1936 " .VoltageMode = 0x%02x\n"
1937 " .SnapToDiscrete = 0x%02x\n"
1938 " .NumDiscreteLevels = 0x%02x\n"
1939 " .padding = 0x%02x\n"
1940 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1941 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1942 " .SsFmin = 0x%04x\n"
1943 " .Padding_16 = 0x%04x\n",
1944 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1945 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1946 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1947 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1948 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1949 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1950 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1951 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1952 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1953 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1954 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1955
d9811cfc 1956 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 1957 " .VoltageMode = 0x%02x\n"
1958 " .SnapToDiscrete = 0x%02x\n"
1959 " .NumDiscreteLevels = 0x%02x\n"
1960 " .padding = 0x%02x\n"
1961 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1962 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1963 " .SsFmin = 0x%04x\n"
1964 " .Padding_16 = 0x%04x\n",
1965 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1966 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1967 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1968 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1969 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1970 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1971 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1972 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1973 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1974 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1975 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1976
d9811cfc 1977 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 1978 " .VoltageMode = 0x%02x\n"
1979 " .SnapToDiscrete = 0x%02x\n"
1980 " .NumDiscreteLevels = 0x%02x\n"
1981 " .padding = 0x%02x\n"
1982 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1983 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1984 " .SsFmin = 0x%04x\n"
1985 " .Padding_16 = 0x%04x\n",
1986 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1987 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1988 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1989 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1990 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1991 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1992 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1993 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1994 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1995 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1996 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1997
d9811cfc 1998 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 1999 " .VoltageMode = 0x%02x\n"
2000 " .SnapToDiscrete = 0x%02x\n"
2001 " .NumDiscreteLevels = 0x%02x\n"
2002 " .padding = 0x%02x\n"
2003 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2004 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2005 " .SsFmin = 0x%04x\n"
2006 " .Padding_16 = 0x%04x\n",
2007 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2008 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2009 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2010 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2011 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2012 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2013 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2014 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2015 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2016 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2017 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2018
d9811cfc 2019 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 2020 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 2021 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 2022
d9811cfc 2023 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 2024 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 2025 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 2026
d9811cfc 2027 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 2028 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 2029 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 2030
d9811cfc 2031 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 2032 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 2033 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 2034
d9811cfc 2035 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 2036 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2037 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 2038
d9811cfc 2039 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 2040 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 2041 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2042
2043 dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
2044 dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
2045 dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
2046 dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
2047 dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
2048 dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
2049 dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
2050 dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
2051 dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
2052 dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
2053 dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
2054 dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
2055 dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
2056 dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
2057 dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
2058 dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
2059
2060 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2061 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2062 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2063 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2064 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2065 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2066 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2067 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2068 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2069
2070 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 2071 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2072 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 2073
d9811cfc
EQ		 2074 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2075 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 2076
d9811cfc 2077 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 2078 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 2079 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 2080
d9811cfc 2081 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 2082 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 2083 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 2084
d9811cfc 2085 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 2086 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2087 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 2088
d9811cfc 2089 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 2090 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 2091 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2092
2093 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2094 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2095 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2096 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2097 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2098
2099 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2100
2101 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2102 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2103 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2104 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2105 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2106 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2107 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2108 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2109 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2110 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2111 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2112
2113 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2114 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2115 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2116 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2117 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2118 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2119
2120 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2121 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2122 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2123 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2124 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2125
2126 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 2127 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 2128 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 2129
d9811cfc
EQ		 2130 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2131 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2132 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2133 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 2134
d9811cfc 2135 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 2136 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2137 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 2138
d9811cfc
EQ		 2139 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2140 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 2141 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 2142 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 2143 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 2144 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2145 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 2146 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 2147 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 2148 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 2149 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2150 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 2151
d9811cfc 2152 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 2153 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2154 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 2155
d9811cfc 2156 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 2157 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2158 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 2159
d9811cfc 2160 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 2161 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2162 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 2163
d9811cfc
EQ		 2164 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2165 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 2166
d9811cfc 2167 dev_info(smu->adev->dev, "FanGain\n");
b455159c 2168 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 2169 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2170
2171 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2172 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2173 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2174 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2175 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2176 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2177 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2178 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2179 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2180 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2181 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2182 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2183
2184 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2185 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2186 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2187 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2188
2189 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2190 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2191 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2192 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2193
2194 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2195 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2196 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2197 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 2198 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2199 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2200 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2201 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 2202 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2203 pptable->dBtcGbGfxPll.a,
2204 pptable->dBtcGbGfxPll.b,
2205 pptable->dBtcGbGfxPll.c);
d9811cfc 2206 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2207 pptable->dBtcGbGfxDfll.a,
2208 pptable->dBtcGbGfxDfll.b,
2209 pptable->dBtcGbGfxDfll.c);
d9811cfc 2210 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2211 pptable->dBtcGbSoc.a,
2212 pptable->dBtcGbSoc.b,
2213 pptable->dBtcGbSoc.c);
d9811cfc 2214 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 2215 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2216 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 2217 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 2218 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2219 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2220
d9811cfc 2221 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 2222 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 2223 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 2224 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 2225 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 2226 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2227 }
2228
d9811cfc 2229 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2230 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2231 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2232 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 2233 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2234 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2235 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2236 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2237
d9811cfc
EQ		 2238 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2239 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 2240
d9811cfc
EQ		 2241 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2242 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2243 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2244 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 2245
d9811cfc
EQ		 2246 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2247 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2248 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2249 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 2250
d9811cfc
EQ		 2251 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2252 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 2253
d9811cfc 2254 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 2255 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 2256 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2257 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2258 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 2259
d9811cfc
EQ		 2260 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2261 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2262 pptable->ReservedEquation0.a,
2263 pptable->ReservedEquation0.b,
2264 pptable->ReservedEquation0.c);
d9811cfc 2265 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2266 pptable->ReservedEquation1.a,
2267 pptable->ReservedEquation1.b,
2268 pptable->ReservedEquation1.c);
d9811cfc 2269 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2270 pptable->ReservedEquation2.a,
2271 pptable->ReservedEquation2.b,
2272 pptable->ReservedEquation2.c);
d9811cfc 2273 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2274 pptable->ReservedEquation3.a,
2275 pptable->ReservedEquation3.b,
2276 pptable->ReservedEquation3.c);
2277
d9811cfc
EQ		 2278 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2279 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2280 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2281 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2282 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2283 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2284 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2285 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2286 dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2287 dev_info(smu->adev->dev, "SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2288 dev_info(smu->adev->dev, "SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2289 dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2290 dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2291 dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
d9811cfc
EQ		 2292
2293 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2294 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2295 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2296 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2297 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2298 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 2299
2300 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 2301 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2302 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 2303 pptable->I2cControllers[i].Enabled);
d9811cfc 2304 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 2305 pptable->I2cControllers[i].Speed);
d9811cfc 2306 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 2307 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 2308 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 2309 pptable->I2cControllers[i].ControllerPort);
d9811cfc 2310 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 2311 pptable->I2cControllers[i].ControllerName);
d9811cfc 2312 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 2313 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 2314 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 2315 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 2316 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 2317 pptable->I2cControllers[i].PaddingConfig);
2318 }
2319
d9811cfc
EQ		 2320 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2321 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2322 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2323 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2324
2325 dev_info(smu->adev->dev, "Board Parameters:\n");
2326 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2327 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2328 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2329 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2330 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2331 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2332 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2333 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2334
2335 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2336 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2337 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2338
2339 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2340 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2341 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2342
2343 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2344 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2345 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2346
2347 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2348 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2349 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2350
2351 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2352
2353 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2354 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2355 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2356 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2357 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2358 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2359 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2360 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2361 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2362 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2363 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2364 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2365 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2366 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2367 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2368 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2369
2370 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2371 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2372 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2373
2374 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2375 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2376 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2377
f0f3d68e 2378 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 2379 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2380
2381 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2382 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2383 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2384
2385 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2386 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2387 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2388 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2389 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2390
2391 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2392 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2393
2394 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 2395 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2396 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2397 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 2398 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2399 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2400 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 2401 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2402 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2403 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 2404 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2405 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2406
2407 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2408 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2409 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2410 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2411
2412 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2413 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2414 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2415 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2416 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2417 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2418 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2419 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2420 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2421 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2422 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 2423
2424 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2425 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2426 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2427 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2428 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2429 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2430 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2431 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 2432}
2433
bc50ca29
AD		 2434static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write,
2435 uint8_t address, uint32_t numbytes,
2436 uint8_t *data)
2437{
2438 int i;
2439
2440 BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
2441
2442 req->I2CcontrollerPort = 0;
2443 req->I2CSpeed = 2;
2444 req->SlaveAddress = address;
2445 req->NumCmds = numbytes;
2446
2447 for (i = 0; i < numbytes; i++) {
2448 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
2449
2450 /* First 2 bytes are always write for lower 2b EEPROM address */
2451 if (i < 2)
2452 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2453 else
2454 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2455
2456
2457 /* Add RESTART for read after address filled */
2458 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2459
2460 /* Add STOP in the end */
2461 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2462
2463 /* Fill with data regardless if read or write to simplify code */
2464 cmd->ReadWriteData = data[i];
2465 }
2466}
2467
2468static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2469 uint8_t address,
2470 uint8_t *data,
2471 uint32_t numbytes)
2472{
2473 uint32_t i, ret = 0;
2474 SwI2cRequest_t req;
2475 struct amdgpu_device *adev = to_amdgpu_device(control);
2476 struct smu_table_context *smu_table = &adev->smu.smu_table;
2477 struct smu_table *table = &smu_table->driver_table;
2478
2479 memset(&req, 0, sizeof(req));
2480 sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2481
2482 mutex_lock(&adev->smu.mutex);
2483 /* Now read data starting with that address */
2484 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2485 true);
2486 mutex_unlock(&adev->smu.mutex);
2487
2488 if (!ret) {
2489 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2490
2491 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
2492 for (i = 0; i < numbytes; i++)
2493 data[i] = res->SwI2cCmds[i].ReadWriteData;
2494
2495 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2496 (uint16_t)address, numbytes);
2497
2498 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2499 8, 1, data, numbytes, false);
2500 } else
2501 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2502
2503 return ret;
2504}
2505
2506static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2507 uint8_t address,
2508 uint8_t *data,
2509 uint32_t numbytes)
2510{
2511 uint32_t ret;
2512 SwI2cRequest_t req;
2513 struct amdgpu_device *adev = to_amdgpu_device(control);
2514
2515 memset(&req, 0, sizeof(req));
2516 sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2517
2518 mutex_lock(&adev->smu.mutex);
2519 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2520 mutex_unlock(&adev->smu.mutex);
2521
2522 if (!ret) {
2523 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2524 (uint16_t)address, numbytes);
2525
2526 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2527 8, 1, data, numbytes, false);
2528 /*
2529 * According to EEPROM spec there is a MAX of 10 ms required for
2530 * EEPROM to flush internal RX buffer after STOP was issued at the
2531 * end of write transaction. During this time the EEPROM will not be
2532 * responsive to any more commands - so wait a bit more.
2533 */
2534 msleep(10);
2535
2536 } else
2537 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2538
2539 return ret;
2540}
2541
2542static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2543 struct i2c_msg *msgs, int num)
2544{
2545 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2546 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2547
2548 for (i = 0; i < num; i++) {
2549 /*
2550 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2551 * once and hence the data needs to be spliced into chunks and sent each
2552 * chunk separately
2553 */
2554 data_size = msgs[i].len - 2;
2555 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2556 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2557 data_ptr = msgs[i].buf + 2;
2558
2559 for (j = 0; j < data_size / data_chunk_size; j++) {
2560 /* Insert the EEPROM dest addess, bits 0-15 */
2561 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2562 data_chunk[1] = (next_eeprom_addr & 0xff);
2563
2564 if (msgs[i].flags & I2C_M_RD) {
2565 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2566 (uint8_t)msgs[i].addr,
2567 data_chunk, MAX_SW_I2C_COMMANDS);
2568
2569 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2570 } else {
2571
2572 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2573
2574 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2575 (uint8_t)msgs[i].addr,
2576 data_chunk, MAX_SW_I2C_COMMANDS);
2577 }
2578
2579 if (ret) {
2580 num = -EIO;
2581 goto fail;
2582 }
2583
2584 next_eeprom_addr += data_chunk_size;
2585 data_ptr += data_chunk_size;
2586 }
2587
2588 if (data_size % data_chunk_size) {
2589 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2590 data_chunk[1] = (next_eeprom_addr & 0xff);
2591
2592 if (msgs[i].flags & I2C_M_RD) {
2593 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2594 (uint8_t)msgs[i].addr,
2595 data_chunk, (data_size % data_chunk_size) + 2);
2596
2597 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2598 } else {
2599 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2600
2601 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2602 (uint8_t)msgs[i].addr,
2603 data_chunk, (data_size % data_chunk_size) + 2);
2604 }
2605
2606 if (ret) {
2607 num = -EIO;
2608 goto fail;
2609 }
2610 }
2611 }
2612
2613fail:
2614 return num;
2615}
2616
2617static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2618{
2619 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2620}
2621
2622
2623static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2624 .master_xfer = sienna_cichlid_i2c_xfer,
2625 .functionality = sienna_cichlid_i2c_func,
2626};
2627
2628static bool sienna_cichlid_i2c_adapter_is_added(struct i2c_adapter *control)
2629{
2630 struct amdgpu_device *adev = to_amdgpu_device(control);
2631
2632 return control->dev.parent == &adev->pdev->dev;
2633}
2634
2635static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2636{
2637 struct amdgpu_device *adev = to_amdgpu_device(control);
2638 int res;
2639
2640 /* smu_i2c_eeprom_init may be called twice in sriov */
2641 if (sienna_cichlid_i2c_adapter_is_added(control))
2642 return 0;
2643
2644 control->owner = THIS_MODULE;
2645 control->class = I2C_CLASS_SPD;
2646 control->dev.parent = &adev->pdev->dev;
2647 control->algo = &sienna_cichlid_i2c_algo;
2648 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2649
2650 res = i2c_add_adapter(control);
2651 if (res)
2652 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2653
2654 return res;
2655}
2656
2657static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2658{
2659 if (!sienna_cichlid_i2c_adapter_is_added(control))
2660 return;
2661
2662 i2c_del_adapter(control);
2663}
2664
2665
b455159c 2666static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 2667 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2668 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 2669 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 2670 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 2671 .i2c_init = sienna_cichlid_i2c_control_init,
2672 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 2673 .print_clk_levels = sienna_cichlid_print_clk_levels,
2674 .force_clk_levels = sienna_cichlid_force_clk_levels,
2675 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 2676 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2677 .display_config_changed = sienna_cichlid_display_config_changed,
2678 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c
LG		 2679 .is_dpm_running = sienna_cichlid_is_dpm_running,
2680 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2681 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2682 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2683 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 2684 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2685 .read_sensor = sienna_cichlid_read_sensor,
2686 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 2687 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 2688 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2689 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2690 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2691 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2692 .dump_pptable = sienna_cichlid_dump_pptable,
2693 .init_microcode = smu_v11_0_init_microcode,
2694 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 2695 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 2696 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2697 .init_power = smu_v11_0_init_power,
2698 .fini_power = smu_v11_0_fini_power,
2699 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 2700 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 2701 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 2702 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 2703 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 2704 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2705 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2706 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2707 .system_features_control = smu_v11_0_system_features_control,
66c86828
EQ		 2708 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2709 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 2710 .init_display_count = NULL,
b455159c 2711 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 2712 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 2713 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 2714 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 2715 .notify_display_change = NULL,
b455159c 2716 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 2717 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2718 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2719 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 2720 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 2721 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2722 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2723 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2724 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2725 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2726 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2727 .gfx_off_control = smu_v11_0_gfx_off_control,
2728 .register_irq_handler = smu_v11_0_register_irq_handler,
2729 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2730 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
40d3b8db 2731 .baco_is_support= sienna_cichlid_is_baco_supported,
b455159c
LG		 2732 .baco_get_state = smu_v11_0_baco_get_state,
2733 .baco_set_state = smu_v11_0_baco_set_state,
2734 .baco_enter = smu_v11_0_baco_enter,
2735 .baco_exit = smu_v11_0_baco_exit,
ea8139d8
WS		 2736 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2737 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 2738 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 2739 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
7dbf7805
EQ		 2740 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2741 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
b455159c
LG		 2742};
2743
2744void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2745{
2746 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 2747 smu->message_map = sienna_cichlid_message_map;
2748 smu->clock_map = sienna_cichlid_clk_map;
2749 smu->feature_map = sienna_cichlid_feature_mask_map;
2750 smu->table_map = sienna_cichlid_table_map;
2751 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2752 smu->workload_map = sienna_cichlid_workload_map;
b455159c 2753}
Linux 6.x block layer and io_uring tree(s)