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drm/amd/powerplay: enable LCLK DPM for sienna_cichlid
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include <linux/pci.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "smu_internal.h"
30#include "atomfirmware.h"
31#include "amdgpu_atomfirmware.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_sienna_cichlid.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "sienna_cichlid_ppt.h"
37#include "smu_v11_0_pptable.h"
38#include "smu_v11_0_7_ppsmc.h"
39
b7d25b5f 40#include "nbio/nbio_2_3_sh_mask.h"
b455159c
LG		 41#include "asic_reg/mp/mp_11_0_sh_mask.h"
42
43#define FEATURE_MASK(feature) (1ULL << feature)
44#define SMC_DPM_FEATURE ( \
45 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 46 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 47 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 48 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 49 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70
LG		 50 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
51 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
b455159c
LG		 52
53#define MSG_MAP(msg, index) \
54 [SMU_MSG_##msg] = {1, (index)}
55
56static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
57 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
58 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
59 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
60 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
61 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
62 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
63 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
64 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
65 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
66 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
67 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
68 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
69 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
70 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
71 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
72 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
73 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
74 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
75 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
76 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
77 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
78 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
79 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
80 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
81 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
82 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
83 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
84 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
85 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
86 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
87 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
88 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
89 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
90 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
91 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
92 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
93 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
94 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
95 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
96 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
97 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
98 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
99 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
100 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
101 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
102 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
103 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
104 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
105 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
106};
107
108static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
109 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
110 CLK_MAP(SCLK, PPCLK_GFXCLK),
111 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
112 CLK_MAP(FCLK, PPCLK_FCLK),
113 CLK_MAP(UCLK, PPCLK_UCLK),
114 CLK_MAP(MCLK, PPCLK_UCLK),
115 CLK_MAP(DCLK, PPCLK_DCLK_0),
116 CLK_MAP(DCLK1, PPCLK_DCLK_0),
117 CLK_MAP(VCLK, PPCLK_VCLK_1),
118 CLK_MAP(VCLK1, PPCLK_VCLK_1),
119 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
120 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
121 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
122 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
123};
124
125static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
126 FEA_MAP(DPM_PREFETCHER),
127 FEA_MAP(DPM_GFXCLK),
128 FEA_MAP(DPM_UCLK),
129 FEA_MAP(DPM_SOCCLK),
130 FEA_MAP(DPM_MP0CLK),
131 FEA_MAP(DPM_LINK),
132 FEA_MAP(DPM_DCEFCLK),
133 FEA_MAP(MEM_VDDCI_SCALING),
134 FEA_MAP(MEM_MVDD_SCALING),
135 FEA_MAP(DS_GFXCLK),
136 FEA_MAP(DS_SOCCLK),
137 FEA_MAP(DS_LCLK),
138 FEA_MAP(DS_DCEFCLK),
139 FEA_MAP(DS_UCLK),
140 FEA_MAP(GFX_ULV),
141 FEA_MAP(FW_DSTATE),
142 FEA_MAP(GFXOFF),
143 FEA_MAP(BACO),
144 FEA_MAP(RSMU_SMN_CG),
145 FEA_MAP(PPT),
146 FEA_MAP(TDC),
147 FEA_MAP(APCC_PLUS),
148 FEA_MAP(GTHR),
149 FEA_MAP(ACDC),
150 FEA_MAP(VR0HOT),
151 FEA_MAP(VR1HOT),
152 FEA_MAP(FW_CTF),
153 FEA_MAP(FAN_CONTROL),
154 FEA_MAP(THERMAL),
155 FEA_MAP(GFX_DCS),
156 FEA_MAP(RM),
157 FEA_MAP(LED_DISPLAY),
158 FEA_MAP(GFX_SS),
159 FEA_MAP(OUT_OF_BAND_MONITOR),
160 FEA_MAP(TEMP_DEPENDENT_VMIN),
161 FEA_MAP(MMHUB_PG),
162 FEA_MAP(ATHUB_PG),
163};
164
165static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
166 TAB_MAP(PPTABLE),
167 TAB_MAP(WATERMARKS),
168 TAB_MAP(AVFS_PSM_DEBUG),
169 TAB_MAP(AVFS_FUSE_OVERRIDE),
170 TAB_MAP(PMSTATUSLOG),
171 TAB_MAP(SMU_METRICS),
172 TAB_MAP(DRIVER_SMU_CONFIG),
173 TAB_MAP(ACTIVITY_MONITOR_COEFF),
174 TAB_MAP(OVERDRIVE),
175 TAB_MAP(I2C_COMMANDS),
176 TAB_MAP(PACE),
177};
178
179static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
180 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
181 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
182 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
183 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
184 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
185 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
187};
188
189static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
190{
191 struct smu_11_0_cmn2aisc_mapping mapping;
192
193 if (index >= SMU_MSG_MAX_COUNT)
194 return -EINVAL;
195
196 mapping = sienna_cichlid_message_map[index];
197 if (!(mapping.valid_mapping)) {
198 return -EINVAL;
199 }
200
201 return mapping.map_to;
202}
203
204static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
205{
206 struct smu_11_0_cmn2aisc_mapping mapping;
207
208 if (index >= SMU_CLK_COUNT)
209 return -EINVAL;
210
211 mapping = sienna_cichlid_clk_map[index];
212 if (!(mapping.valid_mapping)) {
213 return -EINVAL;
214 }
215
216 return mapping.map_to;
217}
218
219static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
220{
221 struct smu_11_0_cmn2aisc_mapping mapping;
222
223 if (index >= SMU_FEATURE_COUNT)
224 return -EINVAL;
225
226 mapping = sienna_cichlid_feature_mask_map[index];
227 if (!(mapping.valid_mapping)) {
228 return -EINVAL;
229 }
230
231 return mapping.map_to;
232}
233
234static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
235{
236 struct smu_11_0_cmn2aisc_mapping mapping;
237
238 if (index >= SMU_TABLE_COUNT)
239 return -EINVAL;
240
241 mapping = sienna_cichlid_table_map[index];
242 if (!(mapping.valid_mapping)) {
243 return -EINVAL;
244 }
245
246 return mapping.map_to;
247}
248
249static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
250{
251 struct smu_11_0_cmn2aisc_mapping mapping;
252
253 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
254 return -EINVAL;
255
256 mapping = sienna_cichlid_workload_map[profile];
257 if (!(mapping.valid_mapping)) {
258 return -EINVAL;
259 }
260
261 return mapping.map_to;
262}
263
264static int
265sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
266 uint32_t *feature_mask, uint32_t num)
267{
fea905d4
LG		 268 struct amdgpu_device *adev = smu->adev;
269
b455159c
LG		 270 if (num > 2)
271 return -EINVAL;
272
273 memset(feature_mask, 0, sizeof(uint32_t) * num);
274
4cd4f45b 275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 276 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
094cdf15 277 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
9aa60213
LG		 279 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
280 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
094cdf15 281 | FEATURE_MASK(FEATURE_THERMAL_BIT);
fea905d4
LG		 282
283 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
285
65297d50
LG		 286 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
288
5cb74353
LG		 289 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
291
5f338f70
LG		 292 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
294
fea905d4
LG		 295 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 297
62c1ea6b
LG		 298 if (adev->pm.pp_feature & PP_ULV_MASK)
299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
300
02bb391d
LG		 301 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
303
b455159c
LG		 304 return 0;
305}
306
307static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
308{
309 return 0;
310}
311
312static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
313{
314 return 0;
315}
316
317static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
318{
319 struct smu_11_0_powerplay_table *powerplay_table = NULL;
320 struct smu_table_context *table_context = &smu->smu_table;
321 struct smu_baco_context *smu_baco = &smu->smu_baco;
322
323 if (!table_context->power_play_table)
324 return -EINVAL;
325
326 powerplay_table = table_context->power_play_table;
327
328 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
329 sizeof(PPTable_t));
330
331 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
332
333 mutex_lock(&smu_baco->mutex);
334 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
335 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
336 smu_baco->platform_support = true;
337 mutex_unlock(&smu_baco->mutex);
338
339 return 0;
340}
341
342static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
343{
344 struct smu_table_context *smu_table = &smu->smu_table;
345
346 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
347 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
348 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
349 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
350 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
351 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
352 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
353 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
354 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
355 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
356 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
357 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
358 AMDGPU_GEM_DOMAIN_VRAM);
359
360 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
361 if (!smu_table->metrics_table)
362 return -ENOMEM;
363 smu_table->metrics_time = 0;
364
365 return 0;
366}
367
368static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
369 SmuMetrics_t *metrics_table)
370{
371 struct smu_table_context *smu_table= &smu->smu_table;
372 int ret = 0;
373
374 mutex_lock(&smu->metrics_lock);
375 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
376 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
377 (void *)smu_table->metrics_table, false);
378 if (ret) {
379 pr_info("Failed to export SMU metrics table!\n");
380 mutex_unlock(&smu->metrics_lock);
381 return ret;
382 }
383 smu_table->metrics_time = jiffies;
384 }
385
386 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
387 mutex_unlock(&smu->metrics_lock);
388
389 return ret;
390}
391
392static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
393{
394 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
395
396 if (smu_dpm->dpm_context)
397 return -EINVAL;
398
399 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
400 GFP_KERNEL);
401 if (!smu_dpm->dpm_context)
402 return -ENOMEM;
403
404 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
405
406 return 0;
407}
408
409static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
410{
411 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
412 struct smu_table_context *table_context = &smu->smu_table;
413 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
414 PPTable_t *driver_ppt = NULL;
08ccfe08 415 int i;
b455159c
LG		 416
417 driver_ppt = table_context->driver_pptable;
418
419 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
420 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
421
422 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
423 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
424
425 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
426 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
427
428 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
429 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
430
431 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
432 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
433
434 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
435 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
436
437 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
438 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
439
440 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
441 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
442
443 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
444 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
445
08ccfe08
LG		 446 for (i = 0; i < MAX_PCIE_CONF; i++) {
447 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
448 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
449 }
450
b455159c
LG		 451 return 0;
452}
453
454static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
455{
456 struct smu_power_context *smu_power = &smu->smu_power;
457 struct smu_power_gate *power_gate = &smu_power->power_gate;
458 int ret = 0;
459
460 if (enable) {
461 /* vcn dpm on is a prerequisite for vcn power gate messages */
462 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
463 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
464 if (ret)
465 return ret;
466 }
467 power_gate->vcn_gated = false;
468 } else {
469 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
470 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
471 if (ret)
472 return ret;
473 }
474 power_gate->vcn_gated = true;
475 }
476
477 return ret;
478}
479
480static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
481 enum smu_clk_type clk_type,
482 uint32_t *value)
483{
484 int ret = 0, clk_id = 0;
485 SmuMetrics_t metrics;
486
487 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
488 if (ret)
489 return ret;
490
491 clk_id = smu_clk_get_index(smu, clk_type);
492 if (clk_id < 0)
493 return clk_id;
494
495 *value = metrics.CurrClock[clk_id];
496
497 return ret;
498}
499
500static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
501{
502 PPTable_t *pptable = smu->smu_table.driver_pptable;
503 DpmDescriptor_t *dpm_desc = NULL;
504 uint32_t clk_index = 0;
505
506 clk_index = smu_clk_get_index(smu, clk_type);
507 dpm_desc = &pptable->DpmDescriptor[clk_index];
508
509 /* 0 - Fine grained DPM, 1 - Discrete DPM */
510 return dpm_desc->SnapToDiscrete == 0 ? true : false;
511}
512
513static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
514 enum smu_clk_type clk_type, char *buf)
515{
b7d25b5f
LG		 516 struct amdgpu_device *adev = smu->adev;
517 struct smu_table_context *table_context = &smu->smu_table;
518 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
519 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
520 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
b455159c
LG		 521 int i, size = 0, ret = 0;
522 uint32_t cur_value = 0, value = 0, count = 0;
523 uint32_t freq_values[3] = {0};
524 uint32_t mark_index = 0;
b7d25b5f 525 uint32_t gen_speed, lane_width;
b455159c
LG		 526
527 switch (clk_type) {
528 case SMU_GFXCLK:
529 case SMU_SCLK:
530 case SMU_SOCCLK:
531 case SMU_MCLK:
532 case SMU_UCLK:
533 case SMU_FCLK:
534 case SMU_DCEFCLK:
535 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
536 if (ret)
537 return size;
538
539 /* 10KHz -> MHz */
540 cur_value = cur_value / 100;
541
542 ret = smu_get_dpm_level_count(smu, clk_type, &count);
543 if (ret)
544 return size;
545
546 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
547 for (i = 0; i < count; i++) {
548 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
549 if (ret)
550 return size;
551
552 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
553 cur_value == value ? "*" : "");
554 }
555 } else {
556 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
557 if (ret)
558 return size;
559 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
560 if (ret)
561 return size;
562
563 freq_values[1] = cur_value;
564 mark_index = cur_value == freq_values[0] ? 0 :
565 cur_value == freq_values[2] ? 2 : 1;
566 if (mark_index != 1)
567 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
568
569 for (i = 0; i < 3; i++) {
570 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
571 i == mark_index ? "*" : "");
572 }
573
574 }
575 break;
b7d25b5f
LG		 576 case SMU_PCIE:
577 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
578 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
579 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
580 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
581 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
582 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
583 for (i = 0; i < NUM_LINK_LEVELS; i++)
584 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
585 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
586 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
587 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
588 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
589 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
590 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
591 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
592 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
593 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
594 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
595 pptable->LclkFreq[i],
596 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
597 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
598 "*" : "");
599 break;
b455159c
LG		 600 default:
601 break;
602 }
603
604 return size;
605}
606
607static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
608 enum smu_clk_type clk_type, uint32_t mask)
609{
610
611 int ret = 0, size = 0;
612 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
613
614 soft_min_level = mask ? (ffs(mask) - 1) : 0;
615 soft_max_level = mask ? (fls(mask) - 1) : 0;
616
617 switch (clk_type) {
618 case SMU_GFXCLK:
619 case SMU_SCLK:
620 case SMU_SOCCLK:
621 case SMU_MCLK:
622 case SMU_UCLK:
623 case SMU_DCEFCLK:
624 case SMU_FCLK:
9ad9c8ac
LG		 625 /* There is only 2 levels for fine grained DPM */
626 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
627 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
628 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
629 }
630
b455159c
LG		 631 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
632 if (ret)
633 return size;
634
635 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
636 if (ret)
637 return size;
638
639 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
640 if (ret)
641 return size;
642 break;
643 default:
644 break;
645 }
646
647 return size;
648}
649
650static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
651{
652 int ret = 0;
653 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
654
655 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
656 if (ret)
657 return ret;
658
659 smu->pstate_sclk = min_sclk_freq * 100;
660
661 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
662 if (ret)
663 return ret;
664
665 smu->pstate_mclk = min_mclk_freq * 100;
666
667 return ret;
668}
669
670static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
671 enum smu_clk_type clk_type,
672 struct pp_clock_levels_with_latency *clocks)
673{
674 int ret = 0, i = 0;
675 uint32_t level_count = 0, freq = 0;
676
677 switch (clk_type) {
678 case SMU_GFXCLK:
679 case SMU_DCEFCLK:
680 case SMU_SOCCLK:
681 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
682 if (ret)
683 return ret;
684
685 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
686 clocks->num_levels = level_count;
687
688 for (i = 0; i < level_count; i++) {
689 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
690 if (ret)
691 return ret;
692
693 clocks->data[i].clocks_in_khz = freq * 1000;
694 clocks->data[i].latency_in_us = 0;
695 }
696 break;
697 default:
698 break;
699 }
700
701 return ret;
702}
703
704static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
705{
706 int ret = 0;
707 uint32_t max_freq = 0;
708
709 /* Sienna_Cichlid do not support to change display num currently */
710 return 0;
711#if 0
712 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
713 if (ret)
714 return ret;
715#endif
716
717 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
718 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
719 if (ret)
720 return ret;
721 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
722 if (ret)
723 return ret;
724 }
725
726 return ret;
727}
728
729static int sienna_cichlid_display_config_changed(struct smu_context *smu)
730{
731 int ret = 0;
732
733 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
734 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
735 ret = smu_write_watermarks_table(smu);
736 if (ret)
737 return ret;
738
739 smu->watermarks_bitmap |= WATERMARKS_LOADED;
740 }
741
742 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
743 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
744 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
745 /* Sienna_Cichlid do not support to change display num currently */
746 ret = 0;
747#if 0
748 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
749 smu->display_config->num_display, NULL);
750#endif
751 if (ret)
752 return ret;
753 }
754
755 return ret;
756}
757
758static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
759{
760 int ret = 0, i = 0;
761 uint32_t min_freq, max_freq, force_freq;
762 enum smu_clk_type clk_type;
763
764 enum smu_clk_type clks[] = {
765 SMU_GFXCLK,
766 };
767
768 for (i = 0; i < ARRAY_SIZE(clks); i++) {
769 clk_type = clks[i];
770 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
771 if (ret)
772 return ret;
773
774 force_freq = highest ? max_freq : min_freq;
775 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
776 if (ret)
777 return ret;
778 }
779
780 return ret;
781}
782
783static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
784{
785 int ret = 0, i = 0;
786 uint32_t min_freq, max_freq;
787 enum smu_clk_type clk_type;
788
789 enum smu_clk_type clks[] = {
790 SMU_GFXCLK,
791 };
792
793 for (i = 0; i < ARRAY_SIZE(clks); i++) {
794 clk_type = clks[i];
795 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
796 if (ret)
797 return ret;
798
799 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
800 if (ret)
801 return ret;
802 }
803
804 return ret;
805}
806
807static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
808{
809 int ret = 0;
810 SmuMetrics_t metrics;
811
812 if (!value)
813 return -EINVAL;
814
815 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
816 if (ret)
817 return ret;
818
819 *value = metrics.AverageSocketPower << 8;
820
821 return 0;
822}
823
824static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
825 enum amd_pp_sensors sensor,
826 uint32_t *value)
827{
828 int ret = 0;
829 SmuMetrics_t metrics;
830
831 if (!value)
832 return -EINVAL;
833
834 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
835 if (ret)
836 return ret;
837
838 switch (sensor) {
839 case AMDGPU_PP_SENSOR_GPU_LOAD:
840 *value = metrics.AverageGfxActivity;
841 break;
842 case AMDGPU_PP_SENSOR_MEM_LOAD:
843 *value = metrics.AverageUclkActivity;
844 break;
845 default:
846 pr_err("Invalid sensor for retrieving clock activity\n");
847 return -EINVAL;
848 }
849
850 return 0;
851}
852
853static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
854{
855 int ret = 0;
856 uint32_t feature_mask[2];
857 unsigned long feature_enabled;
858 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
859 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
860 ((uint64_t)feature_mask[1] << 32));
861 return !!(feature_enabled & SMC_DPM_FEATURE);
862}
863
864static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
865 uint32_t *speed)
866{
867 SmuMetrics_t metrics;
868 int ret = 0;
869
870 if (!speed)
871 return -EINVAL;
872
873 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
874 if (ret)
875 return ret;
876
877 *speed = metrics.CurrFanSpeed;
878
879 return ret;
880}
881
882static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
883 uint32_t *speed)
884{
885 int ret = 0;
886 uint32_t percent = 0;
887 uint32_t current_rpm;
888 PPTable_t *pptable = smu->smu_table.driver_pptable;
889
890 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
891 if (ret)
892 return ret;
893
894 percent = current_rpm * 100 / pptable->FanMaximumRpm;
895 *speed = percent > 100 ? 100 : percent;
896
897 return ret;
898}
899
900static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
901{
902 DpmActivityMonitorCoeffInt_t activity_monitor;
903 uint32_t i, size = 0;
904 int16_t workload_type = 0;
905 static const char *profile_name[] = {
906 "BOOTUP_DEFAULT",
907 "3D_FULL_SCREEN",
908 "POWER_SAVING",
909 "VIDEO",
910 "VR",
911 "COMPUTE",
912 "CUSTOM"};
913 static const char *title[] = {
914 "PROFILE_INDEX(NAME)",
915 "CLOCK_TYPE(NAME)",
916 "FPS",
917 "MinFreqType",
918 "MinActiveFreqType",
919 "MinActiveFreq",
920 "BoosterFreqType",
921 "BoosterFreq",
922 "PD_Data_limit_c",
923 "PD_Data_error_coeff",
924 "PD_Data_error_rate_coeff"};
925 int result = 0;
926
927 if (!buf)
928 return -EINVAL;
929
930 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
931 title[0], title[1], title[2], title[3], title[4], title[5],
932 title[6], title[7], title[8], title[9], title[10]);
933
934 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
935 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
936 workload_type = smu_workload_get_type(smu, i);
937 if (workload_type < 0)
938 return -EINVAL;
939
940 result = smu_update_table(smu,
941 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
942 (void *)(&activity_monitor), false);
943 if (result) {
944 pr_err("[%s] Failed to get activity monitor!", __func__);
945 return result;
946 }
947
948 size += sprintf(buf + size, "%2d %14s%s:\n",
949 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
950
951 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
952 " ",
953 0,
954 "GFXCLK",
955 activity_monitor.Gfx_FPS,
956 activity_monitor.Gfx_MinFreqStep,
957 activity_monitor.Gfx_MinActiveFreqType,
958 activity_monitor.Gfx_MinActiveFreq,
959 activity_monitor.Gfx_BoosterFreqType,
960 activity_monitor.Gfx_BoosterFreq,
961 activity_monitor.Gfx_PD_Data_limit_c,
962 activity_monitor.Gfx_PD_Data_error_coeff,
963 activity_monitor.Gfx_PD_Data_error_rate_coeff);
964
965 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
966 " ",
967 1,
968 "SOCCLK",
969 activity_monitor.Fclk_FPS,
970 activity_monitor.Fclk_MinFreqStep,
971 activity_monitor.Fclk_MinActiveFreqType,
972 activity_monitor.Fclk_MinActiveFreq,
973 activity_monitor.Fclk_BoosterFreqType,
974 activity_monitor.Fclk_BoosterFreq,
975 activity_monitor.Fclk_PD_Data_limit_c,
976 activity_monitor.Fclk_PD_Data_error_coeff,
977 activity_monitor.Fclk_PD_Data_error_rate_coeff);
978
979 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
980 " ",
981 2,
982 "MEMLK",
983 activity_monitor.Mem_FPS,
984 activity_monitor.Mem_MinFreqStep,
985 activity_monitor.Mem_MinActiveFreqType,
986 activity_monitor.Mem_MinActiveFreq,
987 activity_monitor.Mem_BoosterFreqType,
988 activity_monitor.Mem_BoosterFreq,
989 activity_monitor.Mem_PD_Data_limit_c,
990 activity_monitor.Mem_PD_Data_error_coeff,
991 activity_monitor.Mem_PD_Data_error_rate_coeff);
992 }
993
994 return size;
995}
996
997static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
998{
999 DpmActivityMonitorCoeffInt_t activity_monitor;
1000 int workload_type, ret = 0;
1001
1002 smu->power_profile_mode = input[size];
1003
1004 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1005 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1006 return -EINVAL;
1007 }
1008
1009 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1010 if (size < 0)
1011 return -EINVAL;
1012
1013 ret = smu_update_table(smu,
1014 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1015 (void *)(&activity_monitor), false);
1016 if (ret) {
1017 pr_err("[%s] Failed to get activity monitor!", __func__);
1018 return ret;
1019 }
1020
1021 switch (input[0]) {
1022 case 0: /* Gfxclk */
1023 activity_monitor.Gfx_FPS = input[1];
1024 activity_monitor.Gfx_MinFreqStep = input[2];
1025 activity_monitor.Gfx_MinActiveFreqType = input[3];
1026 activity_monitor.Gfx_MinActiveFreq = input[4];
1027 activity_monitor.Gfx_BoosterFreqType = input[5];
1028 activity_monitor.Gfx_BoosterFreq = input[6];
1029 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1030 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1031 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1032 break;
1033 case 1: /* Socclk */
1034 activity_monitor.Fclk_FPS = input[1];
1035 activity_monitor.Fclk_MinFreqStep = input[2];
1036 activity_monitor.Fclk_MinActiveFreqType = input[3];
1037 activity_monitor.Fclk_MinActiveFreq = input[4];
1038 activity_monitor.Fclk_BoosterFreqType = input[5];
1039 activity_monitor.Fclk_BoosterFreq = input[6];
1040 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1041 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1042 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1043 break;
1044 case 2: /* Memlk */
1045 activity_monitor.Mem_FPS = input[1];
1046 activity_monitor.Mem_MinFreqStep = input[2];
1047 activity_monitor.Mem_MinActiveFreqType = input[3];
1048 activity_monitor.Mem_MinActiveFreq = input[4];
1049 activity_monitor.Mem_BoosterFreqType = input[5];
1050 activity_monitor.Mem_BoosterFreq = input[6];
1051 activity_monitor.Mem_PD_Data_limit_c = input[7];
1052 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1053 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1054 break;
1055 }
1056
1057 ret = smu_update_table(smu,
1058 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1059 (void *)(&activity_monitor), true);
1060 if (ret) {
1061 pr_err("[%s] Failed to set activity monitor!", __func__);
1062 return ret;
1063 }
1064 }
1065
1066 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1067 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1068 if (workload_type < 0)
1069 return -EINVAL;
1070 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1071 1 << workload_type, NULL);
1072
1073 return ret;
1074}
1075
1076static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1077 enum amd_dpm_forced_level level,
1078 uint32_t *sclk_mask,
1079 uint32_t *mclk_mask,
1080 uint32_t *soc_mask)
1081{
1082 int ret = 0;
1083 uint32_t level_count = 0;
1084
1085 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1086 if (sclk_mask)
1087 *sclk_mask = 0;
1088 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1089 if (mclk_mask)
1090 *mclk_mask = 0;
1091 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1092 if(sclk_mask) {
1093 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1094 if (ret)
1095 return ret;
1096 *sclk_mask = level_count - 1;
1097 }
1098
1099 if(mclk_mask) {
1100 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1101 if (ret)
1102 return ret;
1103 *mclk_mask = level_count - 1;
1104 }
1105
1106 if(soc_mask) {
1107 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1108 if (ret)
1109 return ret;
1110 *soc_mask = level_count - 1;
1111 }
1112 }
1113
1114 return ret;
1115}
1116
1117static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1118{
1119 struct smu_clocks min_clocks = {0};
1120 struct pp_display_clock_request clock_req;
1121 int ret = 0;
1122
1123 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1124 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1125 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1126
1127 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1128 clock_req.clock_type = amd_pp_dcef_clock;
1129 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1130
1131 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1132 if (!ret) {
1133 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1134 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1135 return ret;
1136 }
1137 } else {
1138 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1139 }
1140 }
1141
1142 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1143 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1144 if (ret) {
1145 pr_err("[%s] Set hard min uclk failed!", __func__);
1146 return ret;
1147 }
1148 }
1149
1150 return 0;
1151}
1152
1153static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1154 void *watermarks, struct
1155 dm_pp_wm_sets_with_clock_ranges_soc15
1156 *clock_ranges)
1157{
1158 int i;
1159 Watermarks_t *table = watermarks;
1160
1161 if (!table || !clock_ranges)
1162 return -EINVAL;
1163
1164 if (clock_ranges->num_wm_dmif_sets > 4 ||
1165 clock_ranges->num_wm_mcif_sets > 4)
1166 return -EINVAL;
1167
1168 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1169 table->WatermarkRow[1][i].MinClock =
1170 cpu_to_le16((uint16_t)
1171 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1172 1000));
1173 table->WatermarkRow[1][i].MaxClock =
1174 cpu_to_le16((uint16_t)
1175 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1176 1000));
1177 table->WatermarkRow[1][i].MinUclk =
1178 cpu_to_le16((uint16_t)
1179 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1180 1000));
1181 table->WatermarkRow[1][i].MaxUclk =
1182 cpu_to_le16((uint16_t)
1183 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1184 1000));
1185 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1186 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1187 }
1188
1189 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1190 table->WatermarkRow[0][i].MinClock =
1191 cpu_to_le16((uint16_t)
1192 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1193 1000));
1194 table->WatermarkRow[0][i].MaxClock =
1195 cpu_to_le16((uint16_t)
1196 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1197 1000));
1198 table->WatermarkRow[0][i].MinUclk =
1199 cpu_to_le16((uint16_t)
1200 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1201 1000));
1202 table->WatermarkRow[0][i].MaxUclk =
1203 cpu_to_le16((uint16_t)
1204 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1205 1000));
1206 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1207 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1208 }
1209
1210 return 0;
1211}
1212
1213static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1214 enum amd_pp_sensors sensor,
1215 uint32_t *value)
1216{
1217 SmuMetrics_t metrics;
1218 int ret = 0;
1219
1220 if (!value)
1221 return -EINVAL;
1222
1223 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1224 if (ret)
1225 return ret;
1226
1227 switch (sensor) {
1228 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1229 *value = metrics.TemperatureHotspot *
1230 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1231 break;
1232 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1233 *value = metrics.TemperatureEdge *
1234 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1235 break;
1236 case AMDGPU_PP_SENSOR_MEM_TEMP:
1237 *value = metrics.TemperatureMem *
1238 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1239 break;
1240 default:
1241 pr_err("Invalid sensor for retrieving temp\n");
1242 return -EINVAL;
1243 }
1244
1245 return 0;
1246}
1247
1248static int sienna_cichlid_read_sensor(struct smu_context *smu,
1249 enum amd_pp_sensors sensor,
1250 void *data, uint32_t *size)
1251{
1252 int ret = 0;
1253 struct smu_table_context *table_context = &smu->smu_table;
1254 PPTable_t *pptable = table_context->driver_pptable;
1255
1256 if(!data || !size)
1257 return -EINVAL;
1258
1259 mutex_lock(&smu->sensor_lock);
1260 switch (sensor) {
1261 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1262 *(uint32_t *)data = pptable->FanMaximumRpm;
1263 *size = 4;
1264 break;
1265 case AMDGPU_PP_SENSOR_MEM_LOAD:
1266 case AMDGPU_PP_SENSOR_GPU_LOAD:
1267 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1268 *size = 4;
1269 break;
1270 case AMDGPU_PP_SENSOR_GPU_POWER:
1271 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1272 *size = 4;
1273 break;
1274 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1275 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1276 case AMDGPU_PP_SENSOR_MEM_TEMP:
1277 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1278 *size = 4;
1279 break;
1280 default:
1281 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1282 }
1283 mutex_unlock(&smu->sensor_lock);
1284
1285 return ret;
1286}
1287
1288static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1289{
1290 uint32_t num_discrete_levels = 0;
1291 uint16_t *dpm_levels = NULL;
1292 uint16_t i = 0;
1293 struct smu_table_context *table_context = &smu->smu_table;
1294 PPTable_t *driver_ppt = NULL;
1295
1296 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1297 return -EINVAL;
1298
1299 driver_ppt = table_context->driver_pptable;
1300 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1301 dpm_levels = driver_ppt->FreqTableUclk;
1302
1303 if (num_discrete_levels == 0 || dpm_levels == NULL)
1304 return -EINVAL;
1305
1306 *num_states = num_discrete_levels;
1307 for (i = 0; i < num_discrete_levels; i++) {
1308 /* convert to khz */
1309 *clocks_in_khz = (*dpm_levels) * 1000;
1310 clocks_in_khz++;
1311 dpm_levels++;
1312 }
1313
1314 return 0;
1315}
1316
9ad9c8ac
LG		 1317static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1318 enum amd_dpm_forced_level level);
1319
1320static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1321{
1322 struct amdgpu_device *adev = smu->adev;
1323 int ret = 0;
1324 uint32_t sclk_freq = 0, uclk_freq = 0;
1325
1326 switch (adev->asic_type) {
1327 /* TODO: need to set specify clk value by asic type, not support yet*/
1328 default:
1329 /* by default, this is same as auto performance level */
1330 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1331 }
1332
1333 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1334 if (ret)
1335 return ret;
1336 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1337 if (ret)
1338 return ret;
1339
1340 return ret;
1341}
1342
1343static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1344{
1345 int ret = 0;
1346
1347 /* TODO: not support yet*/
1348 return ret;
1349}
1350
1351static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1352 enum amd_dpm_forced_level level)
1353{
1354 int ret = 0;
1355 uint32_t sclk_mask, mclk_mask, soc_mask;
1356
1357 switch (level) {
1358 case AMD_DPM_FORCED_LEVEL_HIGH:
1359 ret = smu_force_dpm_limit_value(smu, true);
1360 break;
1361 case AMD_DPM_FORCED_LEVEL_LOW:
1362 ret = smu_force_dpm_limit_value(smu, false);
1363 break;
1364 case AMD_DPM_FORCED_LEVEL_AUTO:
1365 ret = smu_unforce_dpm_levels(smu);
1366 break;
1367 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1368 ret = sienna_cichlid_set_standard_performance_level(smu);
1369 break;
1370 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1371 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1372 ret = smu_get_profiling_clk_mask(smu, level,
1373 &sclk_mask,
1374 &mclk_mask,
1375 &soc_mask);
1376 if (ret)
1377 return ret;
1378 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1379 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1380 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1381 break;
1382 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1383 ret = sienna_cichlid_set_peak_performance_level(smu);
1384 break;
1385 case AMD_DPM_FORCED_LEVEL_MANUAL:
1386 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1387 default:
1388 break;
1389 }
1390 return ret;
1391}
1392
b455159c
LG		 1393static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1394 struct smu_temperature_range *range)
1395{
1396 struct smu_table_context *table_context = &smu->smu_table;
1397 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1398
1399 if (!range || !powerplay_table)
1400 return -EINVAL;
1401
1402 range->max = powerplay_table->software_shutdown_temp *
1403 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1404
1405 return 0;
1406}
1407
1408static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1409 bool disable_memory_clock_switch)
1410{
1411 int ret = 0;
1412 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1413 (struct smu_11_0_max_sustainable_clocks *)
1414 smu->smu_table.max_sustainable_clocks;
1415 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1416 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1417
1418 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1419 return 0;
1420
1421 if(disable_memory_clock_switch)
1422 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1423 else
1424 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1425
1426 if(!ret)
1427 smu->disable_uclk_switch = disable_memory_clock_switch;
1428
1429 return ret;
1430}
1431
1432static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1433 uint32_t *limit,
1434 bool cap)
1435{
1436 PPTable_t *pptable = smu->smu_table.driver_pptable;
1437 uint32_t asic_default_power_limit = 0;
1438 int ret = 0;
1439 int power_src;
1440
1441 if (!smu->power_limit) {
1442 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1443 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1444 if (power_src < 0)
1445 return -EINVAL;
1446
1447 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1448 power_src << 16, &asic_default_power_limit);
1449 if (ret) {
1450 pr_err("[%s] get PPT limit failed!", __func__);
1451 return ret;
1452 }
1453 } else {
1454 /* the last hope to figure out the ppt limit */
1455 if (!pptable) {
1456 pr_err("Cannot get PPT limit due to pptable missing!");
1457 return -EINVAL;
1458 }
1459 asic_default_power_limit =
1460 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1461 }
1462
1463 smu->power_limit = asic_default_power_limit;
1464 }
1465
1466 if (cap)
1467 *limit = smu_v11_0_get_max_power_limit(smu);
1468 else
1469 *limit = smu->power_limit;
1470
1471 return 0;
1472}
1473
08ccfe08
LG		 1474static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1475 uint32_t pcie_gen_cap,
1476 uint32_t pcie_width_cap)
1477{
1478 PPTable_t *pptable = smu->smu_table.driver_pptable;
1479 int ret, i;
1480 uint32_t smu_pcie_arg;
1481
1482 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1483 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1484
1485 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1486 smu_pcie_arg = (i << 16) |
1487 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1488 (pptable->PcieGenSpeed[i] << 8) :
1489 (pcie_gen_cap << 8)) |
1490 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1491 pptable->PcieLaneCount[i] :
1492 pcie_width_cap);
1493
1494 ret = smu_send_smc_msg_with_param(smu,
1495 SMU_MSG_OverridePcieParameters,
1496 smu_pcie_arg, NULL);
1497 if (ret)
1498 return ret;
1499
1500 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1501 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1502 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1503 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1504 }
1505
1506 return 0;
1507}
1508
b455159c
LG		 1509static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1510{
1511 struct smu_table_context *table_context = &smu->smu_table;
1512 PPTable_t *pptable = table_context->driver_pptable;
1513 int i;
1514
1515 pr_info("Dumped PPTable:\n");
1516
1517 pr_info("Version = 0x%08x\n", pptable->Version);
1518 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1519 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1520
1521 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1522 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1523 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1524 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1525 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1526 }
1527
1528 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1529 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1530 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1531 }
1532
1533 for (i = 0; i < TEMP_COUNT; i++) {
1534 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1535 }
1536
1537 pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1538 pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1539 pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1540 pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1541 pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1542
1543 pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1544 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1545 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1546 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1547 }
1548 pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1549 pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1550 pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1551 pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1552
1553 pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1554
1555 pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1556
1557 pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1558 pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1559 pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1560 pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1561
1562 pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1563 pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1564
1565 pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1566 pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1567 pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1568 pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1569
1570 pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1571 pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1572 pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1573 pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1574
1575 pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1576 pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1577
1578 pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1579 pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1580 pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1581 pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1582 pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1583 pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1584 pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1585 pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1586
1587 pr_info("[PPCLK_GFXCLK]\n"
1588 " .VoltageMode = 0x%02x\n"
1589 " .SnapToDiscrete = 0x%02x\n"
1590 " .NumDiscreteLevels = 0x%02x\n"
1591 " .padding = 0x%02x\n"
1592 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1593 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1594 " .SsFmin = 0x%04x\n"
1595 " .Padding_16 = 0x%04x\n",
1596 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1597 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1598 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1599 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1600 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1601 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1602 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1603 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1604 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1605 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1606 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1607
1608 pr_info("[PPCLK_SOCCLK]\n"
1609 " .VoltageMode = 0x%02x\n"
1610 " .SnapToDiscrete = 0x%02x\n"
1611 " .NumDiscreteLevels = 0x%02x\n"
1612 " .padding = 0x%02x\n"
1613 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1614 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1615 " .SsFmin = 0x%04x\n"
1616 " .Padding_16 = 0x%04x\n",
1617 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1618 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1619 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1620 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1621 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1622 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1623 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1624 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1625 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1626 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1627 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1628
1629 pr_info("[PPCLK_UCLK]\n"
1630 " .VoltageMode = 0x%02x\n"
1631 " .SnapToDiscrete = 0x%02x\n"
1632 " .NumDiscreteLevels = 0x%02x\n"
1633 " .padding = 0x%02x\n"
1634 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1635 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1636 " .SsFmin = 0x%04x\n"
1637 " .Padding_16 = 0x%04x\n",
1638 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1639 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1640 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1641 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1642 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1643 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1644 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1645 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1646 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1647 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1648 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1649
1650 pr_info("[PPCLK_FCLK]\n"
1651 " .VoltageMode = 0x%02x\n"
1652 " .SnapToDiscrete = 0x%02x\n"
1653 " .NumDiscreteLevels = 0x%02x\n"
1654 " .padding = 0x%02x\n"
1655 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1656 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1657 " .SsFmin = 0x%04x\n"
1658 " .Padding_16 = 0x%04x\n",
1659 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1660 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1661 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1662 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1663 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1664 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1665 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1666 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1667 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1668 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1669 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1670
1671 pr_info("[PPCLK_DCLK_0]\n"
1672 " .VoltageMode = 0x%02x\n"
1673 " .SnapToDiscrete = 0x%02x\n"
1674 " .NumDiscreteLevels = 0x%02x\n"
1675 " .padding = 0x%02x\n"
1676 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1677 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1678 " .SsFmin = 0x%04x\n"
1679 " .Padding_16 = 0x%04x\n",
1680 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1681 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1682 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1683 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1684 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1685 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1686 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1687 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1688 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1689 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1690 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1691
1692 pr_info("[PPCLK_VCLK_0]\n"
1693 " .VoltageMode = 0x%02x\n"
1694 " .SnapToDiscrete = 0x%02x\n"
1695 " .NumDiscreteLevels = 0x%02x\n"
1696 " .padding = 0x%02x\n"
1697 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1698 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1699 " .SsFmin = 0x%04x\n"
1700 " .Padding_16 = 0x%04x\n",
1701 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1702 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1703 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1704 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1705 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1706 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1707 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1708 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1709 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1710 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1711 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1712
1713 pr_info("[PPCLK_DCLK_1]\n"
1714 " .VoltageMode = 0x%02x\n"
1715 " .SnapToDiscrete = 0x%02x\n"
1716 " .NumDiscreteLevels = 0x%02x\n"
1717 " .padding = 0x%02x\n"
1718 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1719 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1720 " .SsFmin = 0x%04x\n"
1721 " .Padding_16 = 0x%04x\n",
1722 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1723 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1724 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1725 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1726 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1727 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1728 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1729 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1730 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1731 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1732 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1733
1734 pr_info("[PPCLK_VCLK_1]\n"
1735 " .VoltageMode = 0x%02x\n"
1736 " .SnapToDiscrete = 0x%02x\n"
1737 " .NumDiscreteLevels = 0x%02x\n"
1738 " .padding = 0x%02x\n"
1739 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1740 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1741 " .SsFmin = 0x%04x\n"
1742 " .Padding_16 = 0x%04x\n",
1743 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1744 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1745 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1746 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1747 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1748 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1749 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1750 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1751 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1752 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1753 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1754
1755 pr_info("FreqTableGfx\n");
1756 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1757 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1758
1759 pr_info("FreqTableVclk\n");
1760 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1761 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1762
1763 pr_info("FreqTableDclk\n");
1764 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1765 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1766
1767 pr_info("FreqTableSocclk\n");
1768 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1769 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1770
1771 pr_info("FreqTableUclk\n");
1772 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1773 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1774
1775 pr_info("FreqTableFclk\n");
1776 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1777 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1778
1779 pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
1780 pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
1781 pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
1782 pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
1783 pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
1784 pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
1785 pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
1786 pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
1787 pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
1788 pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
1789 pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1790 pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1791 pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1792 pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1793 pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1794 pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1795
1796 pr_info("DcModeMaxFreq\n");
1797 pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1798 pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1799 pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1800 pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1801 pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1802 pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1803 pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1804 pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1805
1806 pr_info("FreqTableUclkDiv\n");
1807 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1808 pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1809
1810 pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1811 pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1812
1813 pr_info("Mp0clkFreq\n");
1814 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1815 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1816
1817 pr_info("Mp0DpmVoltage\n");
1818 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1819 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1820
1821 pr_info("MemVddciVoltage\n");
1822 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1823 pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1824
1825 pr_info("MemMvddVoltage\n");
1826 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1827 pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1828
1829 pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1830 pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1831 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1832 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1833 pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1834
1835 pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1836
1837 pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1838 pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1839 pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1840 pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1841 pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1842 pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1843 pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1844 pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1845 pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1846 pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1847 pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1848
1849 pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1850 pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1851 pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1852 pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1853 pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1854 pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1855
1856 pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1857 pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1858 pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1859 pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1860 pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1861
1862 pr_info("FlopsPerByteTable\n");
1863 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1864 pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1865
1866 pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1867 pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1868 pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1869 pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1870
1871 pr_info("UclkDpmPstates\n");
1872 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1873 pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1874
1875 pr_info("UclkDpmSrcFreqRange\n");
1876 pr_info(" .Fmin = 0x%x\n",
1877 pptable->UclkDpmSrcFreqRange.Fmin);
1878 pr_info(" .Fmax = 0x%x\n",
1879 pptable->UclkDpmSrcFreqRange.Fmax);
1880 pr_info("UclkDpmTargFreqRange\n");
1881 pr_info(" .Fmin = 0x%x\n",
1882 pptable->UclkDpmTargFreqRange.Fmin);
1883 pr_info(" .Fmax = 0x%x\n",
1884 pptable->UclkDpmTargFreqRange.Fmax);
1885 pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1886 pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1887
1888 pr_info("PcieGenSpeed\n");
1889 for (i = 0; i < NUM_LINK_LEVELS; i++)
1890 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1891
1892 pr_info("PcieLaneCount\n");
1893 for (i = 0; i < NUM_LINK_LEVELS; i++)
1894 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1895
1896 pr_info("LclkFreq\n");
1897 for (i = 0; i < NUM_LINK_LEVELS; i++)
1898 pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1899
1900 pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1901 pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1902
1903 pr_info("FanGain\n");
1904 for (i = 0; i < TEMP_COUNT; i++)
1905 pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1906
1907 pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1908 pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1909 pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1910 pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1911 pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1912 pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1913 pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1914 pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1915 pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1916 pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1917 pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1918 pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1919
1920 pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1921 pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1922 pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1923 pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1924
1925 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1926 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1927 pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
1928 pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
1929
1930 pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1931 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
1932 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
1933 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
1934 pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1935 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
1936 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
1937 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
1938 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1939 pptable->dBtcGbGfxPll.a,
1940 pptable->dBtcGbGfxPll.b,
1941 pptable->dBtcGbGfxPll.c);
1942 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1943 pptable->dBtcGbGfxDfll.a,
1944 pptable->dBtcGbGfxDfll.b,
1945 pptable->dBtcGbGfxDfll.c);
1946 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1947 pptable->dBtcGbSoc.a,
1948 pptable->dBtcGbSoc.b,
1949 pptable->dBtcGbSoc.c);
1950 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1951 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1952 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1953 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1954 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1955 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1956
1957 pr_info("PiecewiseLinearDroopIntGfxDfll\n");
1958 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
1959 pr_info(" Fset[%d] = 0x%x\n",
1960 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
1961 pr_info(" Vdroop[%d] = 0x%x\n",
1962 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
1963 }
1964
1965 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1966 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1967 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1968 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1969 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1970 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1971 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1972 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1973
1974 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1975 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1976
1977 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1978 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1979 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1980 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1981
1982 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1983 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1984 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1985 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1986
1987 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1988 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1989
1990 pr_info("XgmiDpmPstates\n");
1991 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1992 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
1993 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1994 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1995
1996 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1997 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1998 pptable->ReservedEquation0.a,
1999 pptable->ReservedEquation0.b,
2000 pptable->ReservedEquation0.c);
2001 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2002 pptable->ReservedEquation1.a,
2003 pptable->ReservedEquation1.b,
2004 pptable->ReservedEquation1.c);
2005 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2006 pptable->ReservedEquation2.a,
2007 pptable->ReservedEquation2.b,
2008 pptable->ReservedEquation2.c);
2009 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2010 pptable->ReservedEquation3.a,
2011 pptable->ReservedEquation3.b,
2012 pptable->ReservedEquation3.c);
2013
2014 pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2015 pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2016 pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2017 pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2018 pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2019 pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2020 pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2021 pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2022 pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2023 pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2024 pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2025 pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2026 pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2027 pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2028 pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
2029
2030 pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2031 pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2032 pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2033 pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2034 pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2035 pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2036
2037 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2038 pr_info("I2cControllers[%d]:\n", i);
2039 pr_info(" .Enabled = 0x%x\n",
2040 pptable->I2cControllers[i].Enabled);
2041 pr_info(" .Speed = 0x%x\n",
2042 pptable->I2cControllers[i].Speed);
2043 pr_info(" .SlaveAddress = 0x%x\n",
2044 pptable->I2cControllers[i].SlaveAddress);
2045 pr_info(" .ControllerPort = 0x%x\n",
2046 pptable->I2cControllers[i].ControllerPort);
2047 pr_info(" .ControllerName = 0x%x\n",
2048 pptable->I2cControllers[i].ControllerName);
2049 pr_info(" .ThermalThrottler = 0x%x\n",
2050 pptable->I2cControllers[i].ThermalThrotter);
2051 pr_info(" .I2cProtocol = 0x%x\n",
2052 pptable->I2cControllers[i].I2cProtocol);
2053 pr_info(" .PaddingConfig = 0x%x\n",
2054 pptable->I2cControllers[i].PaddingConfig);
2055 }
2056
2057 pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
2058 pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
2059 pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2060 pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2061
2062 pr_info("Board Parameters:\n");
2063 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2064 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2065 pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2066 pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2067 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2068 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2069 pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2070 pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2071
2072 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2073 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
2074 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2075
2076 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2077 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
2078 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2079
2080 pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2081 pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2082 pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2083
2084 pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2085 pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2086 pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2087
2088 pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2089
2090 pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2091 pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2092 pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2093 pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2094 pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2095 pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2096 pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2097 pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2098 pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2099 pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2100 pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2101 pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2102 pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2103 pr_info("LedError = 0x%x\n", pptable->LedError);
2104 pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2105 pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2106
2107 pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2108 pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2109 pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2110
2111 pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2112 pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2113 pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2114
2115 pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2116 pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2117 pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2118
2119 pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2120 pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2121 pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2122
2123 pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2124 pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2125 pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2126 pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2127 pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2128
2129 pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2130 pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2131
2132 pr_info("XgmiLinkSpeed\n");
2133 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2134 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2135 pr_info("XgmiLinkWidth\n");
2136 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2137 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2138 pr_info("XgmiFclkFreq\n");
2139 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2140 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2141 pr_info("XgmiSocVoltage\n");
2142 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2143 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2144
2145 pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2146 pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2147 pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2148 pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2149
2150 pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2151 pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2152 pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2153 pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2154 pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2155 pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2156 pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2157 pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2158 pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2159 pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2160 pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2161 pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2162 pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2163 pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2164 pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2165
2166 pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2167 pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2168 pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2169 pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2170 pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2171 pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2172 pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2173 pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2174}
2175
2176static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2177 .tables_init = sienna_cichlid_tables_init,
2178 .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2179 .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2180 .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2181 .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2182 .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2183 .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2184 .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2185 .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2186 .get_workload_type = sienna_cichlid_get_workload_type,
2187 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2188 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2189 .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2190 .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2191 .print_clk_levels = sienna_cichlid_print_clk_levels,
2192 .force_clk_levels = sienna_cichlid_force_clk_levels,
2193 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2194 .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2195 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2196 .display_config_changed = sienna_cichlid_display_config_changed,
2197 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2198 .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2199 .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2200 .is_dpm_running = sienna_cichlid_is_dpm_running,
2201 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2202 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2203 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2204 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2205 .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2206 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2207 .read_sensor = sienna_cichlid_read_sensor,
2208 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
9ad9c8ac 2209 .set_performance_level = sienna_cichlid_set_performance_level,
b455159c
LG		 2210 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2211 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2212 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2213 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2214 .dump_pptable = sienna_cichlid_dump_pptable,
2215 .init_microcode = smu_v11_0_init_microcode,
2216 .load_microcode = smu_v11_0_load_microcode,
2217 .init_smc_tables = smu_v11_0_init_smc_tables,
2218 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2219 .init_power = smu_v11_0_init_power,
2220 .fini_power = smu_v11_0_fini_power,
2221 .check_fw_status = smu_v11_0_check_fw_status,
2222 .setup_pptable = smu_v11_0_setup_pptable,
2223 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2224 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2225 .check_pptable = smu_v11_0_check_pptable,
2226 .parse_pptable = smu_v11_0_parse_pptable,
2227 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2228 .check_fw_version = smu_v11_0_check_fw_version,
2229 .write_pptable = smu_v11_0_write_pptable,
2230 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2231 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2232 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2233 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2234 .system_features_control = smu_v11_0_system_features_control,
2235 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2236 .init_display_count = smu_v11_0_init_display_count,
2237 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2238 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2239 .notify_display_change = smu_v11_0_notify_display_change,
2240 .set_power_limit = smu_v11_0_set_power_limit,
2241 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2242 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2243 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2244 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2245 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2246 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2247 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2248 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2249 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2250 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2251 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2252 .gfx_off_control = smu_v11_0_gfx_off_control,
2253 .register_irq_handler = smu_v11_0_register_irq_handler,
2254 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2255 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2256 .baco_is_support= smu_v11_0_baco_is_support,
2257 .baco_get_state = smu_v11_0_baco_get_state,
2258 .baco_set_state = smu_v11_0_baco_set_state,
2259 .baco_enter = smu_v11_0_baco_enter,
2260 .baco_exit = smu_v11_0_baco_exit,
2261 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2262 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2263 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2264};
2265
2266void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2267{
2268 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2269}
Linux 6.x block layer and io_uring tree(s)