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drm/amdgpu/powerplay: set Thermal control for sienna_cichlid
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include <linux/pci.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "smu_internal.h"
30#include "atomfirmware.h"
31#include "amdgpu_atomfirmware.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_sienna_cichlid.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "sienna_cichlid_ppt.h"
37#include "smu_v11_0_pptable.h"
38#include "smu_v11_0_7_ppsmc.h"
39
40#include "asic_reg/mp/mp_11_0_sh_mask.h"
41
42#define FEATURE_MASK(feature) (1ULL << feature)
43#define SMC_DPM_FEATURE ( \
44 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 45 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
4cd4f45b
LG		 46 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
47 FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
b455159c
LG		 48
49#define MSG_MAP(msg, index) \
50 [SMU_MSG_##msg] = {1, (index)}
51
52static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
53 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
54 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
55 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
56 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
57 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
58 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
59 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
60 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
61 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
62 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
63 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
64 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
65 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
66 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
67 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
70 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
71 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
72 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
73 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
74 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
75 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
76 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
77 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
78 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
79 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
80 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
81 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
82 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
83 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
84 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
85 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
86 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
87 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
88 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
89 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
90 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
91 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
92 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
93 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
94 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
95 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
96 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
97 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
98 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
99 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
100 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
101 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
102};
103
104static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
105 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
106 CLK_MAP(SCLK, PPCLK_GFXCLK),
107 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
108 CLK_MAP(FCLK, PPCLK_FCLK),
109 CLK_MAP(UCLK, PPCLK_UCLK),
110 CLK_MAP(MCLK, PPCLK_UCLK),
111 CLK_MAP(DCLK, PPCLK_DCLK_0),
112 CLK_MAP(DCLK1, PPCLK_DCLK_0),
113 CLK_MAP(VCLK, PPCLK_VCLK_1),
114 CLK_MAP(VCLK1, PPCLK_VCLK_1),
115 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
116 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
117 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
118 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
119};
120
121static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
122 FEA_MAP(DPM_PREFETCHER),
123 FEA_MAP(DPM_GFXCLK),
124 FEA_MAP(DPM_UCLK),
125 FEA_MAP(DPM_SOCCLK),
126 FEA_MAP(DPM_MP0CLK),
127 FEA_MAP(DPM_LINK),
128 FEA_MAP(DPM_DCEFCLK),
129 FEA_MAP(MEM_VDDCI_SCALING),
130 FEA_MAP(MEM_MVDD_SCALING),
131 FEA_MAP(DS_GFXCLK),
132 FEA_MAP(DS_SOCCLK),
133 FEA_MAP(DS_LCLK),
134 FEA_MAP(DS_DCEFCLK),
135 FEA_MAP(DS_UCLK),
136 FEA_MAP(GFX_ULV),
137 FEA_MAP(FW_DSTATE),
138 FEA_MAP(GFXOFF),
139 FEA_MAP(BACO),
140 FEA_MAP(RSMU_SMN_CG),
141 FEA_MAP(PPT),
142 FEA_MAP(TDC),
143 FEA_MAP(APCC_PLUS),
144 FEA_MAP(GTHR),
145 FEA_MAP(ACDC),
146 FEA_MAP(VR0HOT),
147 FEA_MAP(VR1HOT),
148 FEA_MAP(FW_CTF),
149 FEA_MAP(FAN_CONTROL),
150 FEA_MAP(THERMAL),
151 FEA_MAP(GFX_DCS),
152 FEA_MAP(RM),
153 FEA_MAP(LED_DISPLAY),
154 FEA_MAP(GFX_SS),
155 FEA_MAP(OUT_OF_BAND_MONITOR),
156 FEA_MAP(TEMP_DEPENDENT_VMIN),
157 FEA_MAP(MMHUB_PG),
158 FEA_MAP(ATHUB_PG),
159};
160
161static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
162 TAB_MAP(PPTABLE),
163 TAB_MAP(WATERMARKS),
164 TAB_MAP(AVFS_PSM_DEBUG),
165 TAB_MAP(AVFS_FUSE_OVERRIDE),
166 TAB_MAP(PMSTATUSLOG),
167 TAB_MAP(SMU_METRICS),
168 TAB_MAP(DRIVER_SMU_CONFIG),
169 TAB_MAP(ACTIVITY_MONITOR_COEFF),
170 TAB_MAP(OVERDRIVE),
171 TAB_MAP(I2C_COMMANDS),
172 TAB_MAP(PACE),
173};
174
175static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
176 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
177 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
178 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
179 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
180 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
181 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
182 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
183};
184
185static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
186{
187 struct smu_11_0_cmn2aisc_mapping mapping;
188
189 if (index >= SMU_MSG_MAX_COUNT)
190 return -EINVAL;
191
192 mapping = sienna_cichlid_message_map[index];
193 if (!(mapping.valid_mapping)) {
194 return -EINVAL;
195 }
196
197 return mapping.map_to;
198}
199
200static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
201{
202 struct smu_11_0_cmn2aisc_mapping mapping;
203
204 if (index >= SMU_CLK_COUNT)
205 return -EINVAL;
206
207 mapping = sienna_cichlid_clk_map[index];
208 if (!(mapping.valid_mapping)) {
209 return -EINVAL;
210 }
211
212 return mapping.map_to;
213}
214
215static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
216{
217 struct smu_11_0_cmn2aisc_mapping mapping;
218
219 if (index >= SMU_FEATURE_COUNT)
220 return -EINVAL;
221
222 mapping = sienna_cichlid_feature_mask_map[index];
223 if (!(mapping.valid_mapping)) {
224 return -EINVAL;
225 }
226
227 return mapping.map_to;
228}
229
230static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
231{
232 struct smu_11_0_cmn2aisc_mapping mapping;
233
234 if (index >= SMU_TABLE_COUNT)
235 return -EINVAL;
236
237 mapping = sienna_cichlid_table_map[index];
238 if (!(mapping.valid_mapping)) {
239 return -EINVAL;
240 }
241
242 return mapping.map_to;
243}
244
245static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
246{
247 struct smu_11_0_cmn2aisc_mapping mapping;
248
249 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
250 return -EINVAL;
251
252 mapping = sienna_cichlid_workload_map[profile];
253 if (!(mapping.valid_mapping)) {
254 return -EINVAL;
255 }
256
257 return mapping.map_to;
258}
259
260static int
261sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
262 uint32_t *feature_mask, uint32_t num)
263{
fea905d4
LG		 264 struct amdgpu_device *adev = smu->adev;
265
b455159c
LG		 266 if (num > 2)
267 return -EINVAL;
268
269 memset(feature_mask, 0, sizeof(uint32_t) * num);
270
4cd4f45b 271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 272 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
983ab9f2 273 | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
094cdf15
LG		 274 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
275 | FEATURE_MASK(FEATURE_THERMAL_BIT);
fea905d4
LG		 276
277 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
279
280 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 282
62c1ea6b
LG		 283 if (adev->pm.pp_feature & PP_ULV_MASK)
284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
285
b455159c
LG		 286 return 0;
287}
288
289static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
290{
291 return 0;
292}
293
294static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
295{
296 return 0;
297}
298
299static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
300{
301 struct smu_11_0_powerplay_table *powerplay_table = NULL;
302 struct smu_table_context *table_context = &smu->smu_table;
303 struct smu_baco_context *smu_baco = &smu->smu_baco;
304
305 if (!table_context->power_play_table)
306 return -EINVAL;
307
308 powerplay_table = table_context->power_play_table;
309
310 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
311 sizeof(PPTable_t));
312
313 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
314
315 mutex_lock(&smu_baco->mutex);
316 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
317 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
318 smu_baco->platform_support = true;
319 mutex_unlock(&smu_baco->mutex);
320
321 return 0;
322}
323
324static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
325{
326 struct smu_table_context *smu_table = &smu->smu_table;
327
328 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
329 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
330 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
331 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
332 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
333 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
334 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
335 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
336 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
337 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
338 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
339 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
340 AMDGPU_GEM_DOMAIN_VRAM);
341
342 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
343 if (!smu_table->metrics_table)
344 return -ENOMEM;
345 smu_table->metrics_time = 0;
346
347 return 0;
348}
349
350static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
351 SmuMetrics_t *metrics_table)
352{
353 struct smu_table_context *smu_table= &smu->smu_table;
354 int ret = 0;
355
356 mutex_lock(&smu->metrics_lock);
357 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
358 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
359 (void *)smu_table->metrics_table, false);
360 if (ret) {
361 pr_info("Failed to export SMU metrics table!\n");
362 mutex_unlock(&smu->metrics_lock);
363 return ret;
364 }
365 smu_table->metrics_time = jiffies;
366 }
367
368 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
369 mutex_unlock(&smu->metrics_lock);
370
371 return ret;
372}
373
374static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
375{
376 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
377
378 if (smu_dpm->dpm_context)
379 return -EINVAL;
380
381 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
382 GFP_KERNEL);
383 if (!smu_dpm->dpm_context)
384 return -ENOMEM;
385
386 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
387
388 return 0;
389}
390
391static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
392{
393 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
394 struct smu_table_context *table_context = &smu->smu_table;
395 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
396 PPTable_t *driver_ppt = NULL;
397
398 driver_ppt = table_context->driver_pptable;
399
400 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
401 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
402
403 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
404 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
405
406 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
407 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
408
409 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
410 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
411
412 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
413 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
414
415 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
416 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
417
418 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
419 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
420
421 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
422 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
423
424 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
425 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
426
427 return 0;
428}
429
430static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
431{
432 struct smu_power_context *smu_power = &smu->smu_power;
433 struct smu_power_gate *power_gate = &smu_power->power_gate;
434 int ret = 0;
435
436 if (enable) {
437 /* vcn dpm on is a prerequisite for vcn power gate messages */
438 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
439 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
440 if (ret)
441 return ret;
442 }
443 power_gate->vcn_gated = false;
444 } else {
445 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
446 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
447 if (ret)
448 return ret;
449 }
450 power_gate->vcn_gated = true;
451 }
452
453 return ret;
454}
455
456static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
457 enum smu_clk_type clk_type,
458 uint32_t *value)
459{
460 int ret = 0, clk_id = 0;
461 SmuMetrics_t metrics;
462
463 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
464 if (ret)
465 return ret;
466
467 clk_id = smu_clk_get_index(smu, clk_type);
468 if (clk_id < 0)
469 return clk_id;
470
471 *value = metrics.CurrClock[clk_id];
472
473 return ret;
474}
475
476static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
477{
478 PPTable_t *pptable = smu->smu_table.driver_pptable;
479 DpmDescriptor_t *dpm_desc = NULL;
480 uint32_t clk_index = 0;
481
482 clk_index = smu_clk_get_index(smu, clk_type);
483 dpm_desc = &pptable->DpmDescriptor[clk_index];
484
485 /* 0 - Fine grained DPM, 1 - Discrete DPM */
486 return dpm_desc->SnapToDiscrete == 0 ? true : false;
487}
488
489static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
490 enum smu_clk_type clk_type, char *buf)
491{
492 int i, size = 0, ret = 0;
493 uint32_t cur_value = 0, value = 0, count = 0;
494 uint32_t freq_values[3] = {0};
495 uint32_t mark_index = 0;
496
497 switch (clk_type) {
498 case SMU_GFXCLK:
499 case SMU_SCLK:
500 case SMU_SOCCLK:
501 case SMU_MCLK:
502 case SMU_UCLK:
503 case SMU_FCLK:
504 case SMU_DCEFCLK:
505 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
506 if (ret)
507 return size;
508
509 /* 10KHz -> MHz */
510 cur_value = cur_value / 100;
511
512 ret = smu_get_dpm_level_count(smu, clk_type, &count);
513 if (ret)
514 return size;
515
516 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
517 for (i = 0; i < count; i++) {
518 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
519 if (ret)
520 return size;
521
522 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
523 cur_value == value ? "*" : "");
524 }
525 } else {
526 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
527 if (ret)
528 return size;
529 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
530 if (ret)
531 return size;
532
533 freq_values[1] = cur_value;
534 mark_index = cur_value == freq_values[0] ? 0 :
535 cur_value == freq_values[2] ? 2 : 1;
536 if (mark_index != 1)
537 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
538
539 for (i = 0; i < 3; i++) {
540 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
541 i == mark_index ? "*" : "");
542 }
543
544 }
545 break;
546 default:
547 break;
548 }
549
550 return size;
551}
552
553static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
554 enum smu_clk_type clk_type, uint32_t mask)
555{
556
557 int ret = 0, size = 0;
558 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
559
560 soft_min_level = mask ? (ffs(mask) - 1) : 0;
561 soft_max_level = mask ? (fls(mask) - 1) : 0;
562
563 switch (clk_type) {
564 case SMU_GFXCLK:
565 case SMU_SCLK:
566 case SMU_SOCCLK:
567 case SMU_MCLK:
568 case SMU_UCLK:
569 case SMU_DCEFCLK:
570 case SMU_FCLK:
9ad9c8ac
LG		 571 /* There is only 2 levels for fine grained DPM */
572 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
573 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
574 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
575 }
576
b455159c
LG		 577 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
578 if (ret)
579 return size;
580
581 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
582 if (ret)
583 return size;
584
585 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
586 if (ret)
587 return size;
588 break;
589 default:
590 break;
591 }
592
593 return size;
594}
595
596static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
597{
598 int ret = 0;
599 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
600
601 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
602 if (ret)
603 return ret;
604
605 smu->pstate_sclk = min_sclk_freq * 100;
606
607 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
608 if (ret)
609 return ret;
610
611 smu->pstate_mclk = min_mclk_freq * 100;
612
613 return ret;
614}
615
616static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
617 enum smu_clk_type clk_type,
618 struct pp_clock_levels_with_latency *clocks)
619{
620 int ret = 0, i = 0;
621 uint32_t level_count = 0, freq = 0;
622
623 switch (clk_type) {
624 case SMU_GFXCLK:
625 case SMU_DCEFCLK:
626 case SMU_SOCCLK:
627 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
628 if (ret)
629 return ret;
630
631 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
632 clocks->num_levels = level_count;
633
634 for (i = 0; i < level_count; i++) {
635 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
636 if (ret)
637 return ret;
638
639 clocks->data[i].clocks_in_khz = freq * 1000;
640 clocks->data[i].latency_in_us = 0;
641 }
642 break;
643 default:
644 break;
645 }
646
647 return ret;
648}
649
650static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
651{
652 int ret = 0;
653 uint32_t max_freq = 0;
654
655 /* Sienna_Cichlid do not support to change display num currently */
656 return 0;
657#if 0
658 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
659 if (ret)
660 return ret;
661#endif
662
663 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
664 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
665 if (ret)
666 return ret;
667 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
668 if (ret)
669 return ret;
670 }
671
672 return ret;
673}
674
675static int sienna_cichlid_display_config_changed(struct smu_context *smu)
676{
677 int ret = 0;
678
679 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
680 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
681 ret = smu_write_watermarks_table(smu);
682 if (ret)
683 return ret;
684
685 smu->watermarks_bitmap |= WATERMARKS_LOADED;
686 }
687
688 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
689 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
690 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
691 /* Sienna_Cichlid do not support to change display num currently */
692 ret = 0;
693#if 0
694 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
695 smu->display_config->num_display, NULL);
696#endif
697 if (ret)
698 return ret;
699 }
700
701 return ret;
702}
703
704static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
705{
706 int ret = 0, i = 0;
707 uint32_t min_freq, max_freq, force_freq;
708 enum smu_clk_type clk_type;
709
710 enum smu_clk_type clks[] = {
711 SMU_GFXCLK,
712 };
713
714 for (i = 0; i < ARRAY_SIZE(clks); i++) {
715 clk_type = clks[i];
716 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
717 if (ret)
718 return ret;
719
720 force_freq = highest ? max_freq : min_freq;
721 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
722 if (ret)
723 return ret;
724 }
725
726 return ret;
727}
728
729static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
730{
731 int ret = 0, i = 0;
732 uint32_t min_freq, max_freq;
733 enum smu_clk_type clk_type;
734
735 enum smu_clk_type clks[] = {
736 SMU_GFXCLK,
737 };
738
739 for (i = 0; i < ARRAY_SIZE(clks); i++) {
740 clk_type = clks[i];
741 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
742 if (ret)
743 return ret;
744
745 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
746 if (ret)
747 return ret;
748 }
749
750 return ret;
751}
752
753static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
754{
755 int ret = 0;
756 SmuMetrics_t metrics;
757
758 if (!value)
759 return -EINVAL;
760
761 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
762 if (ret)
763 return ret;
764
765 *value = metrics.AverageSocketPower << 8;
766
767 return 0;
768}
769
770static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
771 enum amd_pp_sensors sensor,
772 uint32_t *value)
773{
774 int ret = 0;
775 SmuMetrics_t metrics;
776
777 if (!value)
778 return -EINVAL;
779
780 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
781 if (ret)
782 return ret;
783
784 switch (sensor) {
785 case AMDGPU_PP_SENSOR_GPU_LOAD:
786 *value = metrics.AverageGfxActivity;
787 break;
788 case AMDGPU_PP_SENSOR_MEM_LOAD:
789 *value = metrics.AverageUclkActivity;
790 break;
791 default:
792 pr_err("Invalid sensor for retrieving clock activity\n");
793 return -EINVAL;
794 }
795
796 return 0;
797}
798
799static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
800{
801 int ret = 0;
802 uint32_t feature_mask[2];
803 unsigned long feature_enabled;
804 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
805 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
806 ((uint64_t)feature_mask[1] << 32));
807 return !!(feature_enabled & SMC_DPM_FEATURE);
808}
809
810static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
811 uint32_t *speed)
812{
813 SmuMetrics_t metrics;
814 int ret = 0;
815
816 if (!speed)
817 return -EINVAL;
818
819 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
820 if (ret)
821 return ret;
822
823 *speed = metrics.CurrFanSpeed;
824
825 return ret;
826}
827
828static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
829 uint32_t *speed)
830{
831 int ret = 0;
832 uint32_t percent = 0;
833 uint32_t current_rpm;
834 PPTable_t *pptable = smu->smu_table.driver_pptable;
835
836 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
837 if (ret)
838 return ret;
839
840 percent = current_rpm * 100 / pptable->FanMaximumRpm;
841 *speed = percent > 100 ? 100 : percent;
842
843 return ret;
844}
845
846static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
847{
848 DpmActivityMonitorCoeffInt_t activity_monitor;
849 uint32_t i, size = 0;
850 int16_t workload_type = 0;
851 static const char *profile_name[] = {
852 "BOOTUP_DEFAULT",
853 "3D_FULL_SCREEN",
854 "POWER_SAVING",
855 "VIDEO",
856 "VR",
857 "COMPUTE",
858 "CUSTOM"};
859 static const char *title[] = {
860 "PROFILE_INDEX(NAME)",
861 "CLOCK_TYPE(NAME)",
862 "FPS",
863 "MinFreqType",
864 "MinActiveFreqType",
865 "MinActiveFreq",
866 "BoosterFreqType",
867 "BoosterFreq",
868 "PD_Data_limit_c",
869 "PD_Data_error_coeff",
870 "PD_Data_error_rate_coeff"};
871 int result = 0;
872
873 if (!buf)
874 return -EINVAL;
875
876 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
877 title[0], title[1], title[2], title[3], title[4], title[5],
878 title[6], title[7], title[8], title[9], title[10]);
879
880 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
881 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
882 workload_type = smu_workload_get_type(smu, i);
883 if (workload_type < 0)
884 return -EINVAL;
885
886 result = smu_update_table(smu,
887 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
888 (void *)(&activity_monitor), false);
889 if (result) {
890 pr_err("[%s] Failed to get activity monitor!", __func__);
891 return result;
892 }
893
894 size += sprintf(buf + size, "%2d %14s%s:\n",
895 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
896
897 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
898 " ",
899 0,
900 "GFXCLK",
901 activity_monitor.Gfx_FPS,
902 activity_monitor.Gfx_MinFreqStep,
903 activity_monitor.Gfx_MinActiveFreqType,
904 activity_monitor.Gfx_MinActiveFreq,
905 activity_monitor.Gfx_BoosterFreqType,
906 activity_monitor.Gfx_BoosterFreq,
907 activity_monitor.Gfx_PD_Data_limit_c,
908 activity_monitor.Gfx_PD_Data_error_coeff,
909 activity_monitor.Gfx_PD_Data_error_rate_coeff);
910
911 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
912 " ",
913 1,
914 "SOCCLK",
915 activity_monitor.Fclk_FPS,
916 activity_monitor.Fclk_MinFreqStep,
917 activity_monitor.Fclk_MinActiveFreqType,
918 activity_monitor.Fclk_MinActiveFreq,
919 activity_monitor.Fclk_BoosterFreqType,
920 activity_monitor.Fclk_BoosterFreq,
921 activity_monitor.Fclk_PD_Data_limit_c,
922 activity_monitor.Fclk_PD_Data_error_coeff,
923 activity_monitor.Fclk_PD_Data_error_rate_coeff);
924
925 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
926 " ",
927 2,
928 "MEMLK",
929 activity_monitor.Mem_FPS,
930 activity_monitor.Mem_MinFreqStep,
931 activity_monitor.Mem_MinActiveFreqType,
932 activity_monitor.Mem_MinActiveFreq,
933 activity_monitor.Mem_BoosterFreqType,
934 activity_monitor.Mem_BoosterFreq,
935 activity_monitor.Mem_PD_Data_limit_c,
936 activity_monitor.Mem_PD_Data_error_coeff,
937 activity_monitor.Mem_PD_Data_error_rate_coeff);
938 }
939
940 return size;
941}
942
943static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
944{
945 DpmActivityMonitorCoeffInt_t activity_monitor;
946 int workload_type, ret = 0;
947
948 smu->power_profile_mode = input[size];
949
950 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
951 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
952 return -EINVAL;
953 }
954
955 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
956 if (size < 0)
957 return -EINVAL;
958
959 ret = smu_update_table(smu,
960 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
961 (void *)(&activity_monitor), false);
962 if (ret) {
963 pr_err("[%s] Failed to get activity monitor!", __func__);
964 return ret;
965 }
966
967 switch (input[0]) {
968 case 0: /* Gfxclk */
969 activity_monitor.Gfx_FPS = input[1];
970 activity_monitor.Gfx_MinFreqStep = input[2];
971 activity_monitor.Gfx_MinActiveFreqType = input[3];
972 activity_monitor.Gfx_MinActiveFreq = input[4];
973 activity_monitor.Gfx_BoosterFreqType = input[5];
974 activity_monitor.Gfx_BoosterFreq = input[6];
975 activity_monitor.Gfx_PD_Data_limit_c = input[7];
976 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
977 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
978 break;
979 case 1: /* Socclk */
980 activity_monitor.Fclk_FPS = input[1];
981 activity_monitor.Fclk_MinFreqStep = input[2];
982 activity_monitor.Fclk_MinActiveFreqType = input[3];
983 activity_monitor.Fclk_MinActiveFreq = input[4];
984 activity_monitor.Fclk_BoosterFreqType = input[5];
985 activity_monitor.Fclk_BoosterFreq = input[6];
986 activity_monitor.Fclk_PD_Data_limit_c = input[7];
987 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
988 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
989 break;
990 case 2: /* Memlk */
991 activity_monitor.Mem_FPS = input[1];
992 activity_monitor.Mem_MinFreqStep = input[2];
993 activity_monitor.Mem_MinActiveFreqType = input[3];
994 activity_monitor.Mem_MinActiveFreq = input[4];
995 activity_monitor.Mem_BoosterFreqType = input[5];
996 activity_monitor.Mem_BoosterFreq = input[6];
997 activity_monitor.Mem_PD_Data_limit_c = input[7];
998 activity_monitor.Mem_PD_Data_error_coeff = input[8];
999 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1000 break;
1001 }
1002
1003 ret = smu_update_table(smu,
1004 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1005 (void *)(&activity_monitor), true);
1006 if (ret) {
1007 pr_err("[%s] Failed to set activity monitor!", __func__);
1008 return ret;
1009 }
1010 }
1011
1012 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1013 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1014 if (workload_type < 0)
1015 return -EINVAL;
1016 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1017 1 << workload_type, NULL);
1018
1019 return ret;
1020}
1021
1022static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1023 enum amd_dpm_forced_level level,
1024 uint32_t *sclk_mask,
1025 uint32_t *mclk_mask,
1026 uint32_t *soc_mask)
1027{
1028 int ret = 0;
1029 uint32_t level_count = 0;
1030
1031 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1032 if (sclk_mask)
1033 *sclk_mask = 0;
1034 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1035 if (mclk_mask)
1036 *mclk_mask = 0;
1037 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1038 if(sclk_mask) {
1039 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1040 if (ret)
1041 return ret;
1042 *sclk_mask = level_count - 1;
1043 }
1044
1045 if(mclk_mask) {
1046 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1047 if (ret)
1048 return ret;
1049 *mclk_mask = level_count - 1;
1050 }
1051
1052 if(soc_mask) {
1053 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1054 if (ret)
1055 return ret;
1056 *soc_mask = level_count - 1;
1057 }
1058 }
1059
1060 return ret;
1061}
1062
1063static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1064{
1065 struct smu_clocks min_clocks = {0};
1066 struct pp_display_clock_request clock_req;
1067 int ret = 0;
1068
1069 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1070 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1071 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1072
1073 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1074 clock_req.clock_type = amd_pp_dcef_clock;
1075 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1076
1077 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1078 if (!ret) {
1079 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1080 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1081 return ret;
1082 }
1083 } else {
1084 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1085 }
1086 }
1087
1088 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1089 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1090 if (ret) {
1091 pr_err("[%s] Set hard min uclk failed!", __func__);
1092 return ret;
1093 }
1094 }
1095
1096 return 0;
1097}
1098
1099static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1100 void *watermarks, struct
1101 dm_pp_wm_sets_with_clock_ranges_soc15
1102 *clock_ranges)
1103{
1104 int i;
1105 Watermarks_t *table = watermarks;
1106
1107 if (!table || !clock_ranges)
1108 return -EINVAL;
1109
1110 if (clock_ranges->num_wm_dmif_sets > 4 ||
1111 clock_ranges->num_wm_mcif_sets > 4)
1112 return -EINVAL;
1113
1114 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1115 table->WatermarkRow[1][i].MinClock =
1116 cpu_to_le16((uint16_t)
1117 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1118 1000));
1119 table->WatermarkRow[1][i].MaxClock =
1120 cpu_to_le16((uint16_t)
1121 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1122 1000));
1123 table->WatermarkRow[1][i].MinUclk =
1124 cpu_to_le16((uint16_t)
1125 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1126 1000));
1127 table->WatermarkRow[1][i].MaxUclk =
1128 cpu_to_le16((uint16_t)
1129 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1130 1000));
1131 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1132 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1133 }
1134
1135 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1136 table->WatermarkRow[0][i].MinClock =
1137 cpu_to_le16((uint16_t)
1138 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1139 1000));
1140 table->WatermarkRow[0][i].MaxClock =
1141 cpu_to_le16((uint16_t)
1142 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1143 1000));
1144 table->WatermarkRow[0][i].MinUclk =
1145 cpu_to_le16((uint16_t)
1146 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1147 1000));
1148 table->WatermarkRow[0][i].MaxUclk =
1149 cpu_to_le16((uint16_t)
1150 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1151 1000));
1152 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1153 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1154 }
1155
1156 return 0;
1157}
1158
1159static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1160 enum amd_pp_sensors sensor,
1161 uint32_t *value)
1162{
1163 SmuMetrics_t metrics;
1164 int ret = 0;
1165
1166 if (!value)
1167 return -EINVAL;
1168
1169 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1170 if (ret)
1171 return ret;
1172
1173 switch (sensor) {
1174 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1175 *value = metrics.TemperatureHotspot *
1176 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1177 break;
1178 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1179 *value = metrics.TemperatureEdge *
1180 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1181 break;
1182 case AMDGPU_PP_SENSOR_MEM_TEMP:
1183 *value = metrics.TemperatureMem *
1184 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1185 break;
1186 default:
1187 pr_err("Invalid sensor for retrieving temp\n");
1188 return -EINVAL;
1189 }
1190
1191 return 0;
1192}
1193
1194static int sienna_cichlid_read_sensor(struct smu_context *smu,
1195 enum amd_pp_sensors sensor,
1196 void *data, uint32_t *size)
1197{
1198 int ret = 0;
1199 struct smu_table_context *table_context = &smu->smu_table;
1200 PPTable_t *pptable = table_context->driver_pptable;
1201
1202 if(!data || !size)
1203 return -EINVAL;
1204
1205 mutex_lock(&smu->sensor_lock);
1206 switch (sensor) {
1207 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1208 *(uint32_t *)data = pptable->FanMaximumRpm;
1209 *size = 4;
1210 break;
1211 case AMDGPU_PP_SENSOR_MEM_LOAD:
1212 case AMDGPU_PP_SENSOR_GPU_LOAD:
1213 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1214 *size = 4;
1215 break;
1216 case AMDGPU_PP_SENSOR_GPU_POWER:
1217 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1218 *size = 4;
1219 break;
1220 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1221 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1222 case AMDGPU_PP_SENSOR_MEM_TEMP:
1223 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1224 *size = 4;
1225 break;
1226 default:
1227 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1228 }
1229 mutex_unlock(&smu->sensor_lock);
1230
1231 return ret;
1232}
1233
1234static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1235{
1236 uint32_t num_discrete_levels = 0;
1237 uint16_t *dpm_levels = NULL;
1238 uint16_t i = 0;
1239 struct smu_table_context *table_context = &smu->smu_table;
1240 PPTable_t *driver_ppt = NULL;
1241
1242 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1243 return -EINVAL;
1244
1245 driver_ppt = table_context->driver_pptable;
1246 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1247 dpm_levels = driver_ppt->FreqTableUclk;
1248
1249 if (num_discrete_levels == 0 || dpm_levels == NULL)
1250 return -EINVAL;
1251
1252 *num_states = num_discrete_levels;
1253 for (i = 0; i < num_discrete_levels; i++) {
1254 /* convert to khz */
1255 *clocks_in_khz = (*dpm_levels) * 1000;
1256 clocks_in_khz++;
1257 dpm_levels++;
1258 }
1259
1260 return 0;
1261}
1262
9ad9c8ac
LG		 1263static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1264 enum amd_dpm_forced_level level);
1265
1266static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1267{
1268 struct amdgpu_device *adev = smu->adev;
1269 int ret = 0;
1270 uint32_t sclk_freq = 0, uclk_freq = 0;
1271
1272 switch (adev->asic_type) {
1273 /* TODO: need to set specify clk value by asic type, not support yet*/
1274 default:
1275 /* by default, this is same as auto performance level */
1276 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1277 }
1278
1279 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1280 if (ret)
1281 return ret;
1282 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1283 if (ret)
1284 return ret;
1285
1286 return ret;
1287}
1288
1289static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1290{
1291 int ret = 0;
1292
1293 /* TODO: not support yet*/
1294 return ret;
1295}
1296
1297static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1298 enum amd_dpm_forced_level level)
1299{
1300 int ret = 0;
1301 uint32_t sclk_mask, mclk_mask, soc_mask;
1302
1303 switch (level) {
1304 case AMD_DPM_FORCED_LEVEL_HIGH:
1305 ret = smu_force_dpm_limit_value(smu, true);
1306 break;
1307 case AMD_DPM_FORCED_LEVEL_LOW:
1308 ret = smu_force_dpm_limit_value(smu, false);
1309 break;
1310 case AMD_DPM_FORCED_LEVEL_AUTO:
1311 ret = smu_unforce_dpm_levels(smu);
1312 break;
1313 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1314 ret = sienna_cichlid_set_standard_performance_level(smu);
1315 break;
1316 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1317 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1318 ret = smu_get_profiling_clk_mask(smu, level,
1319 &sclk_mask,
1320 &mclk_mask,
1321 &soc_mask);
1322 if (ret)
1323 return ret;
1324 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1325 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1326 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1327 break;
1328 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1329 ret = sienna_cichlid_set_peak_performance_level(smu);
1330 break;
1331 case AMD_DPM_FORCED_LEVEL_MANUAL:
1332 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1333 default:
1334 break;
1335 }
1336 return ret;
1337}
1338
b455159c
LG		 1339static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1340 struct smu_temperature_range *range)
1341{
1342 struct smu_table_context *table_context = &smu->smu_table;
1343 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1344
1345 if (!range || !powerplay_table)
1346 return -EINVAL;
1347
1348 range->max = powerplay_table->software_shutdown_temp *
1349 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1350
1351 return 0;
1352}
1353
1354static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1355 bool disable_memory_clock_switch)
1356{
1357 int ret = 0;
1358 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1359 (struct smu_11_0_max_sustainable_clocks *)
1360 smu->smu_table.max_sustainable_clocks;
1361 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1362 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1363
1364 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1365 return 0;
1366
1367 if(disable_memory_clock_switch)
1368 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1369 else
1370 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1371
1372 if(!ret)
1373 smu->disable_uclk_switch = disable_memory_clock_switch;
1374
1375 return ret;
1376}
1377
1378static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1379 uint32_t *limit,
1380 bool cap)
1381{
1382 PPTable_t *pptable = smu->smu_table.driver_pptable;
1383 uint32_t asic_default_power_limit = 0;
1384 int ret = 0;
1385 int power_src;
1386
1387 if (!smu->power_limit) {
1388 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1389 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1390 if (power_src < 0)
1391 return -EINVAL;
1392
1393 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1394 power_src << 16, &asic_default_power_limit);
1395 if (ret) {
1396 pr_err("[%s] get PPT limit failed!", __func__);
1397 return ret;
1398 }
1399 } else {
1400 /* the last hope to figure out the ppt limit */
1401 if (!pptable) {
1402 pr_err("Cannot get PPT limit due to pptable missing!");
1403 return -EINVAL;
1404 }
1405 asic_default_power_limit =
1406 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1407 }
1408
1409 smu->power_limit = asic_default_power_limit;
1410 }
1411
1412 if (cap)
1413 *limit = smu_v11_0_get_max_power_limit(smu);
1414 else
1415 *limit = smu->power_limit;
1416
1417 return 0;
1418}
1419
1420static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1421{
1422 struct smu_table_context *table_context = &smu->smu_table;
1423 PPTable_t *pptable = table_context->driver_pptable;
1424 int i;
1425
1426 pr_info("Dumped PPTable:\n");
1427
1428 pr_info("Version = 0x%08x\n", pptable->Version);
1429 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1430 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1431
1432 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1433 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1434 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1435 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1436 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1437 }
1438
1439 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1440 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1441 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1442 }
1443
1444 for (i = 0; i < TEMP_COUNT; i++) {
1445 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1446 }
1447
1448 pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1449 pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1450 pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1451 pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1452 pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1453
1454 pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1455 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1456 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1457 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1458 }
1459 pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1460 pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1461 pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1462 pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1463
1464 pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1465
1466 pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1467
1468 pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1469 pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1470 pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1471 pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1472
1473 pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1474 pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1475
1476 pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1477 pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1478 pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1479 pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1480
1481 pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1482 pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1483 pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1484 pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1485
1486 pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1487 pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1488
1489 pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1490 pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1491 pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1492 pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1493 pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1494 pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1495 pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1496 pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1497
1498 pr_info("[PPCLK_GFXCLK]\n"
1499 " .VoltageMode = 0x%02x\n"
1500 " .SnapToDiscrete = 0x%02x\n"
1501 " .NumDiscreteLevels = 0x%02x\n"
1502 " .padding = 0x%02x\n"
1503 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1504 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1505 " .SsFmin = 0x%04x\n"
1506 " .Padding_16 = 0x%04x\n",
1507 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1508 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1509 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1510 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1511 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1512 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1513 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1514 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1515 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1516 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1517 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1518
1519 pr_info("[PPCLK_SOCCLK]\n"
1520 " .VoltageMode = 0x%02x\n"
1521 " .SnapToDiscrete = 0x%02x\n"
1522 " .NumDiscreteLevels = 0x%02x\n"
1523 " .padding = 0x%02x\n"
1524 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1525 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1526 " .SsFmin = 0x%04x\n"
1527 " .Padding_16 = 0x%04x\n",
1528 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1529 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1530 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1531 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1532 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1533 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1534 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1535 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1536 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1537 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1538 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1539
1540 pr_info("[PPCLK_UCLK]\n"
1541 " .VoltageMode = 0x%02x\n"
1542 " .SnapToDiscrete = 0x%02x\n"
1543 " .NumDiscreteLevels = 0x%02x\n"
1544 " .padding = 0x%02x\n"
1545 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1546 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1547 " .SsFmin = 0x%04x\n"
1548 " .Padding_16 = 0x%04x\n",
1549 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1550 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1551 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1552 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1553 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1554 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1555 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1556 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1557 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1558 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1559 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1560
1561 pr_info("[PPCLK_FCLK]\n"
1562 " .VoltageMode = 0x%02x\n"
1563 " .SnapToDiscrete = 0x%02x\n"
1564 " .NumDiscreteLevels = 0x%02x\n"
1565 " .padding = 0x%02x\n"
1566 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1567 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1568 " .SsFmin = 0x%04x\n"
1569 " .Padding_16 = 0x%04x\n",
1570 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1571 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1572 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1573 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1574 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1575 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1576 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1577 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1578 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1579 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1580 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1581
1582 pr_info("[PPCLK_DCLK_0]\n"
1583 " .VoltageMode = 0x%02x\n"
1584 " .SnapToDiscrete = 0x%02x\n"
1585 " .NumDiscreteLevels = 0x%02x\n"
1586 " .padding = 0x%02x\n"
1587 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1588 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1589 " .SsFmin = 0x%04x\n"
1590 " .Padding_16 = 0x%04x\n",
1591 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1592 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1593 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1594 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1595 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1596 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1597 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1598 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1599 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1600 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1601 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1602
1603 pr_info("[PPCLK_VCLK_0]\n"
1604 " .VoltageMode = 0x%02x\n"
1605 " .SnapToDiscrete = 0x%02x\n"
1606 " .NumDiscreteLevels = 0x%02x\n"
1607 " .padding = 0x%02x\n"
1608 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1609 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1610 " .SsFmin = 0x%04x\n"
1611 " .Padding_16 = 0x%04x\n",
1612 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1613 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1614 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1615 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1616 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1617 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1618 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1619 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1620 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1621 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1622 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1623
1624 pr_info("[PPCLK_DCLK_1]\n"
1625 " .VoltageMode = 0x%02x\n"
1626 " .SnapToDiscrete = 0x%02x\n"
1627 " .NumDiscreteLevels = 0x%02x\n"
1628 " .padding = 0x%02x\n"
1629 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1630 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1631 " .SsFmin = 0x%04x\n"
1632 " .Padding_16 = 0x%04x\n",
1633 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1634 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1635 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1636 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1637 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1638 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1639 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1640 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1641 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1642 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1643 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1644
1645 pr_info("[PPCLK_VCLK_1]\n"
1646 " .VoltageMode = 0x%02x\n"
1647 " .SnapToDiscrete = 0x%02x\n"
1648 " .NumDiscreteLevels = 0x%02x\n"
1649 " .padding = 0x%02x\n"
1650 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1651 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1652 " .SsFmin = 0x%04x\n"
1653 " .Padding_16 = 0x%04x\n",
1654 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1655 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1656 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1657 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1658 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1659 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1660 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1661 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1662 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1663 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1664 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1665
1666 pr_info("FreqTableGfx\n");
1667 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1668 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1669
1670 pr_info("FreqTableVclk\n");
1671 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1672 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1673
1674 pr_info("FreqTableDclk\n");
1675 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1676 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1677
1678 pr_info("FreqTableSocclk\n");
1679 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1680 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1681
1682 pr_info("FreqTableUclk\n");
1683 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1684 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1685
1686 pr_info("FreqTableFclk\n");
1687 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1688 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1689
1690 pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
1691 pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
1692 pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
1693 pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
1694 pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
1695 pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
1696 pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
1697 pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
1698 pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
1699 pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
1700 pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1701 pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1702 pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1703 pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1704 pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1705 pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1706
1707 pr_info("DcModeMaxFreq\n");
1708 pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1709 pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1710 pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1711 pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1712 pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1713 pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1714 pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1715 pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1716
1717 pr_info("FreqTableUclkDiv\n");
1718 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1719 pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1720
1721 pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1722 pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1723
1724 pr_info("Mp0clkFreq\n");
1725 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1726 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1727
1728 pr_info("Mp0DpmVoltage\n");
1729 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1730 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1731
1732 pr_info("MemVddciVoltage\n");
1733 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1734 pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1735
1736 pr_info("MemMvddVoltage\n");
1737 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1738 pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1739
1740 pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1741 pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1742 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1743 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1744 pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1745
1746 pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1747
1748 pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1749 pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1750 pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1751 pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1752 pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1753 pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1754 pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1755 pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1756 pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1757 pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1758 pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1759
1760 pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1761 pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1762 pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1763 pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1764 pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1765 pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1766
1767 pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1768 pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1769 pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1770 pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1771 pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1772
1773 pr_info("FlopsPerByteTable\n");
1774 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1775 pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1776
1777 pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1778 pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1779 pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1780 pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1781
1782 pr_info("UclkDpmPstates\n");
1783 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1784 pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1785
1786 pr_info("UclkDpmSrcFreqRange\n");
1787 pr_info(" .Fmin = 0x%x\n",
1788 pptable->UclkDpmSrcFreqRange.Fmin);
1789 pr_info(" .Fmax = 0x%x\n",
1790 pptable->UclkDpmSrcFreqRange.Fmax);
1791 pr_info("UclkDpmTargFreqRange\n");
1792 pr_info(" .Fmin = 0x%x\n",
1793 pptable->UclkDpmTargFreqRange.Fmin);
1794 pr_info(" .Fmax = 0x%x\n",
1795 pptable->UclkDpmTargFreqRange.Fmax);
1796 pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1797 pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1798
1799 pr_info("PcieGenSpeed\n");
1800 for (i = 0; i < NUM_LINK_LEVELS; i++)
1801 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1802
1803 pr_info("PcieLaneCount\n");
1804 for (i = 0; i < NUM_LINK_LEVELS; i++)
1805 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1806
1807 pr_info("LclkFreq\n");
1808 for (i = 0; i < NUM_LINK_LEVELS; i++)
1809 pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1810
1811 pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1812 pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1813
1814 pr_info("FanGain\n");
1815 for (i = 0; i < TEMP_COUNT; i++)
1816 pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1817
1818 pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1819 pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1820 pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1821 pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1822 pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1823 pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1824 pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1825 pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1826 pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1827 pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1828 pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1829 pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1830
1831 pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1832 pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1833 pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1834 pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1835
1836 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1837 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1838 pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
1839 pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
1840
1841 pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1842 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
1843 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
1844 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
1845 pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1846 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
1847 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
1848 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
1849 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1850 pptable->dBtcGbGfxPll.a,
1851 pptable->dBtcGbGfxPll.b,
1852 pptable->dBtcGbGfxPll.c);
1853 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1854 pptable->dBtcGbGfxDfll.a,
1855 pptable->dBtcGbGfxDfll.b,
1856 pptable->dBtcGbGfxDfll.c);
1857 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1858 pptable->dBtcGbSoc.a,
1859 pptable->dBtcGbSoc.b,
1860 pptable->dBtcGbSoc.c);
1861 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1862 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1863 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1864 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1865 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1866 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1867
1868 pr_info("PiecewiseLinearDroopIntGfxDfll\n");
1869 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
1870 pr_info(" Fset[%d] = 0x%x\n",
1871 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
1872 pr_info(" Vdroop[%d] = 0x%x\n",
1873 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
1874 }
1875
1876 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1877 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1878 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1879 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1880 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1881 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1882 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1883 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1884
1885 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1886 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1887
1888 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1889 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1890 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1891 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1892
1893 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1894 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1895 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1896 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1897
1898 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1899 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1900
1901 pr_info("XgmiDpmPstates\n");
1902 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1903 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
1904 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1905 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1906
1907 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1908 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1909 pptable->ReservedEquation0.a,
1910 pptable->ReservedEquation0.b,
1911 pptable->ReservedEquation0.c);
1912 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1913 pptable->ReservedEquation1.a,
1914 pptable->ReservedEquation1.b,
1915 pptable->ReservedEquation1.c);
1916 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1917 pptable->ReservedEquation2.a,
1918 pptable->ReservedEquation2.b,
1919 pptable->ReservedEquation2.c);
1920 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1921 pptable->ReservedEquation3.a,
1922 pptable->ReservedEquation3.b,
1923 pptable->ReservedEquation3.c);
1924
1925 pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
1926 pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
1927 pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
1928 pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
1929 pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
1930 pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
1931 pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
1932 pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
1933 pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
1934 pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
1935 pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
1936 pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
1937 pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
1938 pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
1939 pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
1940
1941 pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
1942 pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
1943 pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
1944 pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
1945 pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
1946 pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
1947
1948 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1949 pr_info("I2cControllers[%d]:\n", i);
1950 pr_info(" .Enabled = 0x%x\n",
1951 pptable->I2cControllers[i].Enabled);
1952 pr_info(" .Speed = 0x%x\n",
1953 pptable->I2cControllers[i].Speed);
1954 pr_info(" .SlaveAddress = 0x%x\n",
1955 pptable->I2cControllers[i].SlaveAddress);
1956 pr_info(" .ControllerPort = 0x%x\n",
1957 pptable->I2cControllers[i].ControllerPort);
1958 pr_info(" .ControllerName = 0x%x\n",
1959 pptable->I2cControllers[i].ControllerName);
1960 pr_info(" .ThermalThrottler = 0x%x\n",
1961 pptable->I2cControllers[i].ThermalThrotter);
1962 pr_info(" .I2cProtocol = 0x%x\n",
1963 pptable->I2cControllers[i].I2cProtocol);
1964 pr_info(" .PaddingConfig = 0x%x\n",
1965 pptable->I2cControllers[i].PaddingConfig);
1966 }
1967
1968 pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
1969 pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
1970 pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
1971 pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
1972
1973 pr_info("Board Parameters:\n");
1974 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1975 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1976 pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
1977 pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
1978 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1979 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
1980 pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
1981 pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
1982
1983 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1984 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1985 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1986
1987 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1988 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1989 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1990
1991 pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
1992 pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
1993 pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
1994
1995 pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
1996 pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
1997 pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
1998
1999 pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2000
2001 pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2002 pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2003 pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2004 pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2005 pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2006 pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2007 pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2008 pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2009 pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2010 pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2011 pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2012 pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2013 pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2014 pr_info("LedError = 0x%x\n", pptable->LedError);
2015 pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2016 pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2017
2018 pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2019 pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2020 pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2021
2022 pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2023 pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2024 pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2025
2026 pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2027 pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2028 pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2029
2030 pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2031 pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2032 pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2033
2034 pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2035 pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2036 pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2037 pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2038 pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2039
2040 pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2041 pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2042
2043 pr_info("XgmiLinkSpeed\n");
2044 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2045 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2046 pr_info("XgmiLinkWidth\n");
2047 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2048 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2049 pr_info("XgmiFclkFreq\n");
2050 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2051 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2052 pr_info("XgmiSocVoltage\n");
2053 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2054 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2055
2056 pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2057 pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2058 pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2059 pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2060
2061 pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2062 pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2063 pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2064 pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2065 pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2066 pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2067 pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2068 pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2069 pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2070 pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2071 pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2072 pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2073 pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2074 pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2075 pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2076
2077 pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2078 pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2079 pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2080 pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2081 pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2082 pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2083 pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2084 pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2085}
2086
2087static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2088 .tables_init = sienna_cichlid_tables_init,
2089 .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2090 .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2091 .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2092 .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2093 .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2094 .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2095 .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2096 .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2097 .get_workload_type = sienna_cichlid_get_workload_type,
2098 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2099 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2100 .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2101 .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2102 .print_clk_levels = sienna_cichlid_print_clk_levels,
2103 .force_clk_levels = sienna_cichlid_force_clk_levels,
2104 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2105 .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2106 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2107 .display_config_changed = sienna_cichlid_display_config_changed,
2108 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2109 .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2110 .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2111 .is_dpm_running = sienna_cichlid_is_dpm_running,
2112 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2113 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2114 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2115 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2116 .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2117 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2118 .read_sensor = sienna_cichlid_read_sensor,
2119 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
9ad9c8ac 2120 .set_performance_level = sienna_cichlid_set_performance_level,
b455159c
LG		 2121 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2122 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2123 .get_power_limit = sienna_cichlid_get_power_limit,
2124 .dump_pptable = sienna_cichlid_dump_pptable,
2125 .init_microcode = smu_v11_0_init_microcode,
2126 .load_microcode = smu_v11_0_load_microcode,
2127 .init_smc_tables = smu_v11_0_init_smc_tables,
2128 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2129 .init_power = smu_v11_0_init_power,
2130 .fini_power = smu_v11_0_fini_power,
2131 .check_fw_status = smu_v11_0_check_fw_status,
2132 .setup_pptable = smu_v11_0_setup_pptable,
2133 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2134 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2135 .check_pptable = smu_v11_0_check_pptable,
2136 .parse_pptable = smu_v11_0_parse_pptable,
2137 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2138 .check_fw_version = smu_v11_0_check_fw_version,
2139 .write_pptable = smu_v11_0_write_pptable,
2140 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2141 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2142 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2143 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2144 .system_features_control = smu_v11_0_system_features_control,
2145 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2146 .init_display_count = smu_v11_0_init_display_count,
2147 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2148 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2149 .notify_display_change = smu_v11_0_notify_display_change,
2150 .set_power_limit = smu_v11_0_set_power_limit,
2151 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2152 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2153 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2154 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2155 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2156 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2157 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2158 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2159 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2160 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2161 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2162 .gfx_off_control = smu_v11_0_gfx_off_control,
2163 .register_irq_handler = smu_v11_0_register_irq_handler,
2164 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2165 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2166 .baco_is_support= smu_v11_0_baco_is_support,
2167 .baco_get_state = smu_v11_0_baco_get_state,
2168 .baco_set_state = smu_v11_0_baco_set_state,
2169 .baco_enter = smu_v11_0_baco_enter,
2170 .baco_exit = smu_v11_0_baco_exit,
2171 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2172 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2173 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2174};
2175
2176void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2177{
2178 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2179}
Linux 6.x block layer and io_uring tree(s)