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drm/amd/powerplay: support pcie value set and update for sienna_cichlid
[linux-block.git] / drivers / gpu / drm / amd / powerplay / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include <linux/pci.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "smu_internal.h"
30#include "atomfirmware.h"
31#include "amdgpu_atomfirmware.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_sienna_cichlid.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "sienna_cichlid_ppt.h"
37#include "smu_v11_0_pptable.h"
38#include "smu_v11_0_7_ppsmc.h"
39
40#include "asic_reg/mp/mp_11_0_sh_mask.h"
41
42#define FEATURE_MASK(feature) (1ULL << feature)
43#define SMC_DPM_FEATURE ( \
44 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 45 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 46 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
4cd4f45b 47 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70
LG		 48 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
49 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
b455159c
LG		 50
51#define MSG_MAP(msg, index) \
52 [SMU_MSG_##msg] = {1, (index)}
53
54static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
55 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
56 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
57 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
58 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
59 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
60 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
61 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
62 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
63 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
64 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
65 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
66 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
67 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
68 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
69 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
70 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
71 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
72 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
73 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
74 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
75 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
76 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
77 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
78 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
79 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
80 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
81 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
82 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
83 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
84 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
85 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
86 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
87 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
88 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
89 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
90 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
91 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
92 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
93 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
94 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
95 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
96 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
97 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
98 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
99 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
100 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
101 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
102 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
103 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
104};
105
106static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
107 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
108 CLK_MAP(SCLK, PPCLK_GFXCLK),
109 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
110 CLK_MAP(FCLK, PPCLK_FCLK),
111 CLK_MAP(UCLK, PPCLK_UCLK),
112 CLK_MAP(MCLK, PPCLK_UCLK),
113 CLK_MAP(DCLK, PPCLK_DCLK_0),
114 CLK_MAP(DCLK1, PPCLK_DCLK_0),
115 CLK_MAP(VCLK, PPCLK_VCLK_1),
116 CLK_MAP(VCLK1, PPCLK_VCLK_1),
117 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
118 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
119 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
120 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
121};
122
123static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
124 FEA_MAP(DPM_PREFETCHER),
125 FEA_MAP(DPM_GFXCLK),
126 FEA_MAP(DPM_UCLK),
127 FEA_MAP(DPM_SOCCLK),
128 FEA_MAP(DPM_MP0CLK),
129 FEA_MAP(DPM_LINK),
130 FEA_MAP(DPM_DCEFCLK),
131 FEA_MAP(MEM_VDDCI_SCALING),
132 FEA_MAP(MEM_MVDD_SCALING),
133 FEA_MAP(DS_GFXCLK),
134 FEA_MAP(DS_SOCCLK),
135 FEA_MAP(DS_LCLK),
136 FEA_MAP(DS_DCEFCLK),
137 FEA_MAP(DS_UCLK),
138 FEA_MAP(GFX_ULV),
139 FEA_MAP(FW_DSTATE),
140 FEA_MAP(GFXOFF),
141 FEA_MAP(BACO),
142 FEA_MAP(RSMU_SMN_CG),
143 FEA_MAP(PPT),
144 FEA_MAP(TDC),
145 FEA_MAP(APCC_PLUS),
146 FEA_MAP(GTHR),
147 FEA_MAP(ACDC),
148 FEA_MAP(VR0HOT),
149 FEA_MAP(VR1HOT),
150 FEA_MAP(FW_CTF),
151 FEA_MAP(FAN_CONTROL),
152 FEA_MAP(THERMAL),
153 FEA_MAP(GFX_DCS),
154 FEA_MAP(RM),
155 FEA_MAP(LED_DISPLAY),
156 FEA_MAP(GFX_SS),
157 FEA_MAP(OUT_OF_BAND_MONITOR),
158 FEA_MAP(TEMP_DEPENDENT_VMIN),
159 FEA_MAP(MMHUB_PG),
160 FEA_MAP(ATHUB_PG),
161};
162
163static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
164 TAB_MAP(PPTABLE),
165 TAB_MAP(WATERMARKS),
166 TAB_MAP(AVFS_PSM_DEBUG),
167 TAB_MAP(AVFS_FUSE_OVERRIDE),
168 TAB_MAP(PMSTATUSLOG),
169 TAB_MAP(SMU_METRICS),
170 TAB_MAP(DRIVER_SMU_CONFIG),
171 TAB_MAP(ACTIVITY_MONITOR_COEFF),
172 TAB_MAP(OVERDRIVE),
173 TAB_MAP(I2C_COMMANDS),
174 TAB_MAP(PACE),
175};
176
177static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
178 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
179 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
180 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
181 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
182 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
183 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
184 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
185};
186
187static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
188{
189 struct smu_11_0_cmn2aisc_mapping mapping;
190
191 if (index >= SMU_MSG_MAX_COUNT)
192 return -EINVAL;
193
194 mapping = sienna_cichlid_message_map[index];
195 if (!(mapping.valid_mapping)) {
196 return -EINVAL;
197 }
198
199 return mapping.map_to;
200}
201
202static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
203{
204 struct smu_11_0_cmn2aisc_mapping mapping;
205
206 if (index >= SMU_CLK_COUNT)
207 return -EINVAL;
208
209 mapping = sienna_cichlid_clk_map[index];
210 if (!(mapping.valid_mapping)) {
211 return -EINVAL;
212 }
213
214 return mapping.map_to;
215}
216
217static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
218{
219 struct smu_11_0_cmn2aisc_mapping mapping;
220
221 if (index >= SMU_FEATURE_COUNT)
222 return -EINVAL;
223
224 mapping = sienna_cichlid_feature_mask_map[index];
225 if (!(mapping.valid_mapping)) {
226 return -EINVAL;
227 }
228
229 return mapping.map_to;
230}
231
232static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
233{
234 struct smu_11_0_cmn2aisc_mapping mapping;
235
236 if (index >= SMU_TABLE_COUNT)
237 return -EINVAL;
238
239 mapping = sienna_cichlid_table_map[index];
240 if (!(mapping.valid_mapping)) {
241 return -EINVAL;
242 }
243
244 return mapping.map_to;
245}
246
247static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
248{
249 struct smu_11_0_cmn2aisc_mapping mapping;
250
251 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
252 return -EINVAL;
253
254 mapping = sienna_cichlid_workload_map[profile];
255 if (!(mapping.valid_mapping)) {
256 return -EINVAL;
257 }
258
259 return mapping.map_to;
260}
261
262static int
263sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
264 uint32_t *feature_mask, uint32_t num)
265{
fea905d4
LG		 266 struct amdgpu_device *adev = smu->adev;
267
b455159c
LG		 268 if (num > 2)
269 return -EINVAL;
270
271 memset(feature_mask, 0, sizeof(uint32_t) * num);
272
4cd4f45b 273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 274 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
094cdf15 275 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 276 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
9aa60213
LG		 277 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
278 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
094cdf15 279 | FEATURE_MASK(FEATURE_THERMAL_BIT);
fea905d4
LG		 280
281 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
283
65297d50
LG		 284 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
286
5f338f70
LG		 287 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
289
fea905d4
LG		 290 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 292
62c1ea6b
LG		 293 if (adev->pm.pp_feature & PP_ULV_MASK)
294 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
295
02bb391d
LG		 296 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
298
b455159c
LG		 299 return 0;
300}
301
302static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
303{
304 return 0;
305}
306
307static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
308{
309 return 0;
310}
311
312static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
313{
314 struct smu_11_0_powerplay_table *powerplay_table = NULL;
315 struct smu_table_context *table_context = &smu->smu_table;
316 struct smu_baco_context *smu_baco = &smu->smu_baco;
317
318 if (!table_context->power_play_table)
319 return -EINVAL;
320
321 powerplay_table = table_context->power_play_table;
322
323 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
324 sizeof(PPTable_t));
325
326 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
327
328 mutex_lock(&smu_baco->mutex);
329 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
330 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
331 smu_baco->platform_support = true;
332 mutex_unlock(&smu_baco->mutex);
333
334 return 0;
335}
336
337static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
338{
339 struct smu_table_context *smu_table = &smu->smu_table;
340
341 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
342 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
343 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
344 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
345 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
346 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
347 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
348 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
349 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
350 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
351 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
352 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
353 AMDGPU_GEM_DOMAIN_VRAM);
354
355 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
356 if (!smu_table->metrics_table)
357 return -ENOMEM;
358 smu_table->metrics_time = 0;
359
360 return 0;
361}
362
363static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
364 SmuMetrics_t *metrics_table)
365{
366 struct smu_table_context *smu_table= &smu->smu_table;
367 int ret = 0;
368
369 mutex_lock(&smu->metrics_lock);
370 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
371 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
372 (void *)smu_table->metrics_table, false);
373 if (ret) {
374 pr_info("Failed to export SMU metrics table!\n");
375 mutex_unlock(&smu->metrics_lock);
376 return ret;
377 }
378 smu_table->metrics_time = jiffies;
379 }
380
381 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
382 mutex_unlock(&smu->metrics_lock);
383
384 return ret;
385}
386
387static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
388{
389 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
390
391 if (smu_dpm->dpm_context)
392 return -EINVAL;
393
394 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
395 GFP_KERNEL);
396 if (!smu_dpm->dpm_context)
397 return -ENOMEM;
398
399 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
400
401 return 0;
402}
403
404static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
405{
406 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
407 struct smu_table_context *table_context = &smu->smu_table;
408 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
409 PPTable_t *driver_ppt = NULL;
08ccfe08 410 int i;
b455159c
LG		 411
412 driver_ppt = table_context->driver_pptable;
413
414 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
415 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
416
417 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
418 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
419
420 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
421 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
422
423 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
424 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
425
426 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
427 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
428
429 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
430 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
431
432 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
433 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
434
435 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
436 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
437
438 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
439 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
440
08ccfe08
LG		 441 for (i = 0; i < MAX_PCIE_CONF; i++) {
442 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
443 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
444 }
445
b455159c
LG		 446 return 0;
447}
448
449static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
450{
451 struct smu_power_context *smu_power = &smu->smu_power;
452 struct smu_power_gate *power_gate = &smu_power->power_gate;
453 int ret = 0;
454
455 if (enable) {
456 /* vcn dpm on is a prerequisite for vcn power gate messages */
457 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
458 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
459 if (ret)
460 return ret;
461 }
462 power_gate->vcn_gated = false;
463 } else {
464 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
465 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
466 if (ret)
467 return ret;
468 }
469 power_gate->vcn_gated = true;
470 }
471
472 return ret;
473}
474
475static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
476 enum smu_clk_type clk_type,
477 uint32_t *value)
478{
479 int ret = 0, clk_id = 0;
480 SmuMetrics_t metrics;
481
482 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
483 if (ret)
484 return ret;
485
486 clk_id = smu_clk_get_index(smu, clk_type);
487 if (clk_id < 0)
488 return clk_id;
489
490 *value = metrics.CurrClock[clk_id];
491
492 return ret;
493}
494
495static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
496{
497 PPTable_t *pptable = smu->smu_table.driver_pptable;
498 DpmDescriptor_t *dpm_desc = NULL;
499 uint32_t clk_index = 0;
500
501 clk_index = smu_clk_get_index(smu, clk_type);
502 dpm_desc = &pptable->DpmDescriptor[clk_index];
503
504 /* 0 - Fine grained DPM, 1 - Discrete DPM */
505 return dpm_desc->SnapToDiscrete == 0 ? true : false;
506}
507
508static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
509 enum smu_clk_type clk_type, char *buf)
510{
511 int i, size = 0, ret = 0;
512 uint32_t cur_value = 0, value = 0, count = 0;
513 uint32_t freq_values[3] = {0};
514 uint32_t mark_index = 0;
515
516 switch (clk_type) {
517 case SMU_GFXCLK:
518 case SMU_SCLK:
519 case SMU_SOCCLK:
520 case SMU_MCLK:
521 case SMU_UCLK:
522 case SMU_FCLK:
523 case SMU_DCEFCLK:
524 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
525 if (ret)
526 return size;
527
528 /* 10KHz -> MHz */
529 cur_value = cur_value / 100;
530
531 ret = smu_get_dpm_level_count(smu, clk_type, &count);
532 if (ret)
533 return size;
534
535 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
536 for (i = 0; i < count; i++) {
537 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
538 if (ret)
539 return size;
540
541 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
542 cur_value == value ? "*" : "");
543 }
544 } else {
545 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
546 if (ret)
547 return size;
548 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
549 if (ret)
550 return size;
551
552 freq_values[1] = cur_value;
553 mark_index = cur_value == freq_values[0] ? 0 :
554 cur_value == freq_values[2] ? 2 : 1;
555 if (mark_index != 1)
556 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
557
558 for (i = 0; i < 3; i++) {
559 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
560 i == mark_index ? "*" : "");
561 }
562
563 }
564 break;
565 default:
566 break;
567 }
568
569 return size;
570}
571
572static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
573 enum smu_clk_type clk_type, uint32_t mask)
574{
575
576 int ret = 0, size = 0;
577 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
578
579 soft_min_level = mask ? (ffs(mask) - 1) : 0;
580 soft_max_level = mask ? (fls(mask) - 1) : 0;
581
582 switch (clk_type) {
583 case SMU_GFXCLK:
584 case SMU_SCLK:
585 case SMU_SOCCLK:
586 case SMU_MCLK:
587 case SMU_UCLK:
588 case SMU_DCEFCLK:
589 case SMU_FCLK:
9ad9c8ac
LG		 590 /* There is only 2 levels for fine grained DPM */
591 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
592 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
593 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
594 }
595
b455159c
LG		 596 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
597 if (ret)
598 return size;
599
600 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
601 if (ret)
602 return size;
603
604 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
605 if (ret)
606 return size;
607 break;
608 default:
609 break;
610 }
611
612 return size;
613}
614
615static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
616{
617 int ret = 0;
618 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
619
620 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
621 if (ret)
622 return ret;
623
624 smu->pstate_sclk = min_sclk_freq * 100;
625
626 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
627 if (ret)
628 return ret;
629
630 smu->pstate_mclk = min_mclk_freq * 100;
631
632 return ret;
633}
634
635static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
636 enum smu_clk_type clk_type,
637 struct pp_clock_levels_with_latency *clocks)
638{
639 int ret = 0, i = 0;
640 uint32_t level_count = 0, freq = 0;
641
642 switch (clk_type) {
643 case SMU_GFXCLK:
644 case SMU_DCEFCLK:
645 case SMU_SOCCLK:
646 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
647 if (ret)
648 return ret;
649
650 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
651 clocks->num_levels = level_count;
652
653 for (i = 0; i < level_count; i++) {
654 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
655 if (ret)
656 return ret;
657
658 clocks->data[i].clocks_in_khz = freq * 1000;
659 clocks->data[i].latency_in_us = 0;
660 }
661 break;
662 default:
663 break;
664 }
665
666 return ret;
667}
668
669static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
670{
671 int ret = 0;
672 uint32_t max_freq = 0;
673
674 /* Sienna_Cichlid do not support to change display num currently */
675 return 0;
676#if 0
677 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
678 if (ret)
679 return ret;
680#endif
681
682 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
683 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
684 if (ret)
685 return ret;
686 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
687 if (ret)
688 return ret;
689 }
690
691 return ret;
692}
693
694static int sienna_cichlid_display_config_changed(struct smu_context *smu)
695{
696 int ret = 0;
697
698 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
699 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
700 ret = smu_write_watermarks_table(smu);
701 if (ret)
702 return ret;
703
704 smu->watermarks_bitmap |= WATERMARKS_LOADED;
705 }
706
707 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
708 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
709 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
710 /* Sienna_Cichlid do not support to change display num currently */
711 ret = 0;
712#if 0
713 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
714 smu->display_config->num_display, NULL);
715#endif
716 if (ret)
717 return ret;
718 }
719
720 return ret;
721}
722
723static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
724{
725 int ret = 0, i = 0;
726 uint32_t min_freq, max_freq, force_freq;
727 enum smu_clk_type clk_type;
728
729 enum smu_clk_type clks[] = {
730 SMU_GFXCLK,
731 };
732
733 for (i = 0; i < ARRAY_SIZE(clks); i++) {
734 clk_type = clks[i];
735 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
736 if (ret)
737 return ret;
738
739 force_freq = highest ? max_freq : min_freq;
740 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
741 if (ret)
742 return ret;
743 }
744
745 return ret;
746}
747
748static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
749{
750 int ret = 0, i = 0;
751 uint32_t min_freq, max_freq;
752 enum smu_clk_type clk_type;
753
754 enum smu_clk_type clks[] = {
755 SMU_GFXCLK,
756 };
757
758 for (i = 0; i < ARRAY_SIZE(clks); i++) {
759 clk_type = clks[i];
760 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
761 if (ret)
762 return ret;
763
764 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
765 if (ret)
766 return ret;
767 }
768
769 return ret;
770}
771
772static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
773{
774 int ret = 0;
775 SmuMetrics_t metrics;
776
777 if (!value)
778 return -EINVAL;
779
780 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
781 if (ret)
782 return ret;
783
784 *value = metrics.AverageSocketPower << 8;
785
786 return 0;
787}
788
789static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
790 enum amd_pp_sensors sensor,
791 uint32_t *value)
792{
793 int ret = 0;
794 SmuMetrics_t metrics;
795
796 if (!value)
797 return -EINVAL;
798
799 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
800 if (ret)
801 return ret;
802
803 switch (sensor) {
804 case AMDGPU_PP_SENSOR_GPU_LOAD:
805 *value = metrics.AverageGfxActivity;
806 break;
807 case AMDGPU_PP_SENSOR_MEM_LOAD:
808 *value = metrics.AverageUclkActivity;
809 break;
810 default:
811 pr_err("Invalid sensor for retrieving clock activity\n");
812 return -EINVAL;
813 }
814
815 return 0;
816}
817
818static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
819{
820 int ret = 0;
821 uint32_t feature_mask[2];
822 unsigned long feature_enabled;
823 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
824 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
825 ((uint64_t)feature_mask[1] << 32));
826 return !!(feature_enabled & SMC_DPM_FEATURE);
827}
828
829static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
830 uint32_t *speed)
831{
832 SmuMetrics_t metrics;
833 int ret = 0;
834
835 if (!speed)
836 return -EINVAL;
837
838 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
839 if (ret)
840 return ret;
841
842 *speed = metrics.CurrFanSpeed;
843
844 return ret;
845}
846
847static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
848 uint32_t *speed)
849{
850 int ret = 0;
851 uint32_t percent = 0;
852 uint32_t current_rpm;
853 PPTable_t *pptable = smu->smu_table.driver_pptable;
854
855 ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
856 if (ret)
857 return ret;
858
859 percent = current_rpm * 100 / pptable->FanMaximumRpm;
860 *speed = percent > 100 ? 100 : percent;
861
862 return ret;
863}
864
865static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
866{
867 DpmActivityMonitorCoeffInt_t activity_monitor;
868 uint32_t i, size = 0;
869 int16_t workload_type = 0;
870 static const char *profile_name[] = {
871 "BOOTUP_DEFAULT",
872 "3D_FULL_SCREEN",
873 "POWER_SAVING",
874 "VIDEO",
875 "VR",
876 "COMPUTE",
877 "CUSTOM"};
878 static const char *title[] = {
879 "PROFILE_INDEX(NAME)",
880 "CLOCK_TYPE(NAME)",
881 "FPS",
882 "MinFreqType",
883 "MinActiveFreqType",
884 "MinActiveFreq",
885 "BoosterFreqType",
886 "BoosterFreq",
887 "PD_Data_limit_c",
888 "PD_Data_error_coeff",
889 "PD_Data_error_rate_coeff"};
890 int result = 0;
891
892 if (!buf)
893 return -EINVAL;
894
895 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
896 title[0], title[1], title[2], title[3], title[4], title[5],
897 title[6], title[7], title[8], title[9], title[10]);
898
899 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
900 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
901 workload_type = smu_workload_get_type(smu, i);
902 if (workload_type < 0)
903 return -EINVAL;
904
905 result = smu_update_table(smu,
906 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
907 (void *)(&activity_monitor), false);
908 if (result) {
909 pr_err("[%s] Failed to get activity monitor!", __func__);
910 return result;
911 }
912
913 size += sprintf(buf + size, "%2d %14s%s:\n",
914 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
915
916 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
917 " ",
918 0,
919 "GFXCLK",
920 activity_monitor.Gfx_FPS,
921 activity_monitor.Gfx_MinFreqStep,
922 activity_monitor.Gfx_MinActiveFreqType,
923 activity_monitor.Gfx_MinActiveFreq,
924 activity_monitor.Gfx_BoosterFreqType,
925 activity_monitor.Gfx_BoosterFreq,
926 activity_monitor.Gfx_PD_Data_limit_c,
927 activity_monitor.Gfx_PD_Data_error_coeff,
928 activity_monitor.Gfx_PD_Data_error_rate_coeff);
929
930 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
931 " ",
932 1,
933 "SOCCLK",
934 activity_monitor.Fclk_FPS,
935 activity_monitor.Fclk_MinFreqStep,
936 activity_monitor.Fclk_MinActiveFreqType,
937 activity_monitor.Fclk_MinActiveFreq,
938 activity_monitor.Fclk_BoosterFreqType,
939 activity_monitor.Fclk_BoosterFreq,
940 activity_monitor.Fclk_PD_Data_limit_c,
941 activity_monitor.Fclk_PD_Data_error_coeff,
942 activity_monitor.Fclk_PD_Data_error_rate_coeff);
943
944 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
945 " ",
946 2,
947 "MEMLK",
948 activity_monitor.Mem_FPS,
949 activity_monitor.Mem_MinFreqStep,
950 activity_monitor.Mem_MinActiveFreqType,
951 activity_monitor.Mem_MinActiveFreq,
952 activity_monitor.Mem_BoosterFreqType,
953 activity_monitor.Mem_BoosterFreq,
954 activity_monitor.Mem_PD_Data_limit_c,
955 activity_monitor.Mem_PD_Data_error_coeff,
956 activity_monitor.Mem_PD_Data_error_rate_coeff);
957 }
958
959 return size;
960}
961
962static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
963{
964 DpmActivityMonitorCoeffInt_t activity_monitor;
965 int workload_type, ret = 0;
966
967 smu->power_profile_mode = input[size];
968
969 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
970 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
971 return -EINVAL;
972 }
973
974 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
975 if (size < 0)
976 return -EINVAL;
977
978 ret = smu_update_table(smu,
979 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
980 (void *)(&activity_monitor), false);
981 if (ret) {
982 pr_err("[%s] Failed to get activity monitor!", __func__);
983 return ret;
984 }
985
986 switch (input[0]) {
987 case 0: /* Gfxclk */
988 activity_monitor.Gfx_FPS = input[1];
989 activity_monitor.Gfx_MinFreqStep = input[2];
990 activity_monitor.Gfx_MinActiveFreqType = input[3];
991 activity_monitor.Gfx_MinActiveFreq = input[4];
992 activity_monitor.Gfx_BoosterFreqType = input[5];
993 activity_monitor.Gfx_BoosterFreq = input[6];
994 activity_monitor.Gfx_PD_Data_limit_c = input[7];
995 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
996 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
997 break;
998 case 1: /* Socclk */
999 activity_monitor.Fclk_FPS = input[1];
1000 activity_monitor.Fclk_MinFreqStep = input[2];
1001 activity_monitor.Fclk_MinActiveFreqType = input[3];
1002 activity_monitor.Fclk_MinActiveFreq = input[4];
1003 activity_monitor.Fclk_BoosterFreqType = input[5];
1004 activity_monitor.Fclk_BoosterFreq = input[6];
1005 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1006 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1007 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1008 break;
1009 case 2: /* Memlk */
1010 activity_monitor.Mem_FPS = input[1];
1011 activity_monitor.Mem_MinFreqStep = input[2];
1012 activity_monitor.Mem_MinActiveFreqType = input[3];
1013 activity_monitor.Mem_MinActiveFreq = input[4];
1014 activity_monitor.Mem_BoosterFreqType = input[5];
1015 activity_monitor.Mem_BoosterFreq = input[6];
1016 activity_monitor.Mem_PD_Data_limit_c = input[7];
1017 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1018 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1019 break;
1020 }
1021
1022 ret = smu_update_table(smu,
1023 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1024 (void *)(&activity_monitor), true);
1025 if (ret) {
1026 pr_err("[%s] Failed to set activity monitor!", __func__);
1027 return ret;
1028 }
1029 }
1030
1031 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1032 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1033 if (workload_type < 0)
1034 return -EINVAL;
1035 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1036 1 << workload_type, NULL);
1037
1038 return ret;
1039}
1040
1041static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1042 enum amd_dpm_forced_level level,
1043 uint32_t *sclk_mask,
1044 uint32_t *mclk_mask,
1045 uint32_t *soc_mask)
1046{
1047 int ret = 0;
1048 uint32_t level_count = 0;
1049
1050 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1051 if (sclk_mask)
1052 *sclk_mask = 0;
1053 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1054 if (mclk_mask)
1055 *mclk_mask = 0;
1056 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1057 if(sclk_mask) {
1058 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1059 if (ret)
1060 return ret;
1061 *sclk_mask = level_count - 1;
1062 }
1063
1064 if(mclk_mask) {
1065 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1066 if (ret)
1067 return ret;
1068 *mclk_mask = level_count - 1;
1069 }
1070
1071 if(soc_mask) {
1072 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1073 if (ret)
1074 return ret;
1075 *soc_mask = level_count - 1;
1076 }
1077 }
1078
1079 return ret;
1080}
1081
1082static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1083{
1084 struct smu_clocks min_clocks = {0};
1085 struct pp_display_clock_request clock_req;
1086 int ret = 0;
1087
1088 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1089 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1090 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1091
1092 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1093 clock_req.clock_type = amd_pp_dcef_clock;
1094 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1095
1096 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1097 if (!ret) {
1098 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1099 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1100 return ret;
1101 }
1102 } else {
1103 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1104 }
1105 }
1106
1107 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1108 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1109 if (ret) {
1110 pr_err("[%s] Set hard min uclk failed!", __func__);
1111 return ret;
1112 }
1113 }
1114
1115 return 0;
1116}
1117
1118static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1119 void *watermarks, struct
1120 dm_pp_wm_sets_with_clock_ranges_soc15
1121 *clock_ranges)
1122{
1123 int i;
1124 Watermarks_t *table = watermarks;
1125
1126 if (!table || !clock_ranges)
1127 return -EINVAL;
1128
1129 if (clock_ranges->num_wm_dmif_sets > 4 ||
1130 clock_ranges->num_wm_mcif_sets > 4)
1131 return -EINVAL;
1132
1133 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1134 table->WatermarkRow[1][i].MinClock =
1135 cpu_to_le16((uint16_t)
1136 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1137 1000));
1138 table->WatermarkRow[1][i].MaxClock =
1139 cpu_to_le16((uint16_t)
1140 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1141 1000));
1142 table->WatermarkRow[1][i].MinUclk =
1143 cpu_to_le16((uint16_t)
1144 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1145 1000));
1146 table->WatermarkRow[1][i].MaxUclk =
1147 cpu_to_le16((uint16_t)
1148 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1149 1000));
1150 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1151 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1152 }
1153
1154 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1155 table->WatermarkRow[0][i].MinClock =
1156 cpu_to_le16((uint16_t)
1157 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1158 1000));
1159 table->WatermarkRow[0][i].MaxClock =
1160 cpu_to_le16((uint16_t)
1161 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1162 1000));
1163 table->WatermarkRow[0][i].MinUclk =
1164 cpu_to_le16((uint16_t)
1165 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1166 1000));
1167 table->WatermarkRow[0][i].MaxUclk =
1168 cpu_to_le16((uint16_t)
1169 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1170 1000));
1171 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1172 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1173 }
1174
1175 return 0;
1176}
1177
1178static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1179 enum amd_pp_sensors sensor,
1180 uint32_t *value)
1181{
1182 SmuMetrics_t metrics;
1183 int ret = 0;
1184
1185 if (!value)
1186 return -EINVAL;
1187
1188 ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1189 if (ret)
1190 return ret;
1191
1192 switch (sensor) {
1193 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1194 *value = metrics.TemperatureHotspot *
1195 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1196 break;
1197 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1198 *value = metrics.TemperatureEdge *
1199 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1200 break;
1201 case AMDGPU_PP_SENSOR_MEM_TEMP:
1202 *value = metrics.TemperatureMem *
1203 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1204 break;
1205 default:
1206 pr_err("Invalid sensor for retrieving temp\n");
1207 return -EINVAL;
1208 }
1209
1210 return 0;
1211}
1212
1213static int sienna_cichlid_read_sensor(struct smu_context *smu,
1214 enum amd_pp_sensors sensor,
1215 void *data, uint32_t *size)
1216{
1217 int ret = 0;
1218 struct smu_table_context *table_context = &smu->smu_table;
1219 PPTable_t *pptable = table_context->driver_pptable;
1220
1221 if(!data || !size)
1222 return -EINVAL;
1223
1224 mutex_lock(&smu->sensor_lock);
1225 switch (sensor) {
1226 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1227 *(uint32_t *)data = pptable->FanMaximumRpm;
1228 *size = 4;
1229 break;
1230 case AMDGPU_PP_SENSOR_MEM_LOAD:
1231 case AMDGPU_PP_SENSOR_GPU_LOAD:
1232 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1233 *size = 4;
1234 break;
1235 case AMDGPU_PP_SENSOR_GPU_POWER:
1236 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1237 *size = 4;
1238 break;
1239 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1240 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1241 case AMDGPU_PP_SENSOR_MEM_TEMP:
1242 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1243 *size = 4;
1244 break;
1245 default:
1246 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1247 }
1248 mutex_unlock(&smu->sensor_lock);
1249
1250 return ret;
1251}
1252
1253static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1254{
1255 uint32_t num_discrete_levels = 0;
1256 uint16_t *dpm_levels = NULL;
1257 uint16_t i = 0;
1258 struct smu_table_context *table_context = &smu->smu_table;
1259 PPTable_t *driver_ppt = NULL;
1260
1261 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1262 return -EINVAL;
1263
1264 driver_ppt = table_context->driver_pptable;
1265 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1266 dpm_levels = driver_ppt->FreqTableUclk;
1267
1268 if (num_discrete_levels == 0 || dpm_levels == NULL)
1269 return -EINVAL;
1270
1271 *num_states = num_discrete_levels;
1272 for (i = 0; i < num_discrete_levels; i++) {
1273 /* convert to khz */
1274 *clocks_in_khz = (*dpm_levels) * 1000;
1275 clocks_in_khz++;
1276 dpm_levels++;
1277 }
1278
1279 return 0;
1280}
1281
9ad9c8ac
LG		 1282static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1283 enum amd_dpm_forced_level level);
1284
1285static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1286{
1287 struct amdgpu_device *adev = smu->adev;
1288 int ret = 0;
1289 uint32_t sclk_freq = 0, uclk_freq = 0;
1290
1291 switch (adev->asic_type) {
1292 /* TODO: need to set specify clk value by asic type, not support yet*/
1293 default:
1294 /* by default, this is same as auto performance level */
1295 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1296 }
1297
1298 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1299 if (ret)
1300 return ret;
1301 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1302 if (ret)
1303 return ret;
1304
1305 return ret;
1306}
1307
1308static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1309{
1310 int ret = 0;
1311
1312 /* TODO: not support yet*/
1313 return ret;
1314}
1315
1316static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1317 enum amd_dpm_forced_level level)
1318{
1319 int ret = 0;
1320 uint32_t sclk_mask, mclk_mask, soc_mask;
1321
1322 switch (level) {
1323 case AMD_DPM_FORCED_LEVEL_HIGH:
1324 ret = smu_force_dpm_limit_value(smu, true);
1325 break;
1326 case AMD_DPM_FORCED_LEVEL_LOW:
1327 ret = smu_force_dpm_limit_value(smu, false);
1328 break;
1329 case AMD_DPM_FORCED_LEVEL_AUTO:
1330 ret = smu_unforce_dpm_levels(smu);
1331 break;
1332 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1333 ret = sienna_cichlid_set_standard_performance_level(smu);
1334 break;
1335 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1336 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1337 ret = smu_get_profiling_clk_mask(smu, level,
1338 &sclk_mask,
1339 &mclk_mask,
1340 &soc_mask);
1341 if (ret)
1342 return ret;
1343 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1344 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1345 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1346 break;
1347 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1348 ret = sienna_cichlid_set_peak_performance_level(smu);
1349 break;
1350 case AMD_DPM_FORCED_LEVEL_MANUAL:
1351 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1352 default:
1353 break;
1354 }
1355 return ret;
1356}
1357
b455159c
LG		 1358static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1359 struct smu_temperature_range *range)
1360{
1361 struct smu_table_context *table_context = &smu->smu_table;
1362 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1363
1364 if (!range || !powerplay_table)
1365 return -EINVAL;
1366
1367 range->max = powerplay_table->software_shutdown_temp *
1368 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1369
1370 return 0;
1371}
1372
1373static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1374 bool disable_memory_clock_switch)
1375{
1376 int ret = 0;
1377 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1378 (struct smu_11_0_max_sustainable_clocks *)
1379 smu->smu_table.max_sustainable_clocks;
1380 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1381 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1382
1383 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1384 return 0;
1385
1386 if(disable_memory_clock_switch)
1387 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1388 else
1389 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1390
1391 if(!ret)
1392 smu->disable_uclk_switch = disable_memory_clock_switch;
1393
1394 return ret;
1395}
1396
1397static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1398 uint32_t *limit,
1399 bool cap)
1400{
1401 PPTable_t *pptable = smu->smu_table.driver_pptable;
1402 uint32_t asic_default_power_limit = 0;
1403 int ret = 0;
1404 int power_src;
1405
1406 if (!smu->power_limit) {
1407 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1408 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1409 if (power_src < 0)
1410 return -EINVAL;
1411
1412 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1413 power_src << 16, &asic_default_power_limit);
1414 if (ret) {
1415 pr_err("[%s] get PPT limit failed!", __func__);
1416 return ret;
1417 }
1418 } else {
1419 /* the last hope to figure out the ppt limit */
1420 if (!pptable) {
1421 pr_err("Cannot get PPT limit due to pptable missing!");
1422 return -EINVAL;
1423 }
1424 asic_default_power_limit =
1425 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1426 }
1427
1428 smu->power_limit = asic_default_power_limit;
1429 }
1430
1431 if (cap)
1432 *limit = smu_v11_0_get_max_power_limit(smu);
1433 else
1434 *limit = smu->power_limit;
1435
1436 return 0;
1437}
1438
08ccfe08
LG		 1439static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1440 uint32_t pcie_gen_cap,
1441 uint32_t pcie_width_cap)
1442{
1443 PPTable_t *pptable = smu->smu_table.driver_pptable;
1444 int ret, i;
1445 uint32_t smu_pcie_arg;
1446
1447 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1448 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1449
1450 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1451 smu_pcie_arg = (i << 16) |
1452 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1453 (pptable->PcieGenSpeed[i] << 8) :
1454 (pcie_gen_cap << 8)) |
1455 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1456 pptable->PcieLaneCount[i] :
1457 pcie_width_cap);
1458
1459 ret = smu_send_smc_msg_with_param(smu,
1460 SMU_MSG_OverridePcieParameters,
1461 smu_pcie_arg, NULL);
1462 if (ret)
1463 return ret;
1464
1465 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1466 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1467 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1468 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1469 }
1470
1471 return 0;
1472}
1473
b455159c
LG		 1474static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1475{
1476 struct smu_table_context *table_context = &smu->smu_table;
1477 PPTable_t *pptable = table_context->driver_pptable;
1478 int i;
1479
1480 pr_info("Dumped PPTable:\n");
1481
1482 pr_info("Version = 0x%08x\n", pptable->Version);
1483 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1484 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1485
1486 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1487 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1488 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1489 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1490 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1491 }
1492
1493 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1494 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1495 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1496 }
1497
1498 for (i = 0; i < TEMP_COUNT; i++) {
1499 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1500 }
1501
1502 pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1503 pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1504 pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1505 pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1506 pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1507
1508 pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1509 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1510 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1511 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1512 }
1513 pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1514 pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1515 pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1516 pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1517
1518 pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1519
1520 pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1521
1522 pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1523 pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1524 pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1525 pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1526
1527 pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1528 pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1529
1530 pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1531 pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1532 pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1533 pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1534
1535 pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1536 pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1537 pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1538 pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1539
1540 pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1541 pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1542
1543 pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1544 pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1545 pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1546 pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1547 pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1548 pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1549 pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1550 pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1551
1552 pr_info("[PPCLK_GFXCLK]\n"
1553 " .VoltageMode = 0x%02x\n"
1554 " .SnapToDiscrete = 0x%02x\n"
1555 " .NumDiscreteLevels = 0x%02x\n"
1556 " .padding = 0x%02x\n"
1557 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1558 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1559 " .SsFmin = 0x%04x\n"
1560 " .Padding_16 = 0x%04x\n",
1561 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1562 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1563 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1564 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1565 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1566 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1567 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1568 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1569 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1570 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1571 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1572
1573 pr_info("[PPCLK_SOCCLK]\n"
1574 " .VoltageMode = 0x%02x\n"
1575 " .SnapToDiscrete = 0x%02x\n"
1576 " .NumDiscreteLevels = 0x%02x\n"
1577 " .padding = 0x%02x\n"
1578 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1579 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1580 " .SsFmin = 0x%04x\n"
1581 " .Padding_16 = 0x%04x\n",
1582 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1583 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1584 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1585 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1586 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1587 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1588 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1589 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1590 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1591 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1592 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1593
1594 pr_info("[PPCLK_UCLK]\n"
1595 " .VoltageMode = 0x%02x\n"
1596 " .SnapToDiscrete = 0x%02x\n"
1597 " .NumDiscreteLevels = 0x%02x\n"
1598 " .padding = 0x%02x\n"
1599 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1600 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1601 " .SsFmin = 0x%04x\n"
1602 " .Padding_16 = 0x%04x\n",
1603 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1604 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1605 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1606 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1607 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1608 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1609 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1610 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1611 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1612 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1613 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1614
1615 pr_info("[PPCLK_FCLK]\n"
1616 " .VoltageMode = 0x%02x\n"
1617 " .SnapToDiscrete = 0x%02x\n"
1618 " .NumDiscreteLevels = 0x%02x\n"
1619 " .padding = 0x%02x\n"
1620 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1621 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1622 " .SsFmin = 0x%04x\n"
1623 " .Padding_16 = 0x%04x\n",
1624 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1625 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1626 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1627 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1628 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1629 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1630 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1631 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1632 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1633 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1634 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1635
1636 pr_info("[PPCLK_DCLK_0]\n"
1637 " .VoltageMode = 0x%02x\n"
1638 " .SnapToDiscrete = 0x%02x\n"
1639 " .NumDiscreteLevels = 0x%02x\n"
1640 " .padding = 0x%02x\n"
1641 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1642 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1643 " .SsFmin = 0x%04x\n"
1644 " .Padding_16 = 0x%04x\n",
1645 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1646 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1647 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1648 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1649 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1650 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1651 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1652 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1653 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1654 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1655 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1656
1657 pr_info("[PPCLK_VCLK_0]\n"
1658 " .VoltageMode = 0x%02x\n"
1659 " .SnapToDiscrete = 0x%02x\n"
1660 " .NumDiscreteLevels = 0x%02x\n"
1661 " .padding = 0x%02x\n"
1662 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1663 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1664 " .SsFmin = 0x%04x\n"
1665 " .Padding_16 = 0x%04x\n",
1666 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1667 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1668 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1669 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1670 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1671 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1672 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1673 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1674 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1675 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1676 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1677
1678 pr_info("[PPCLK_DCLK_1]\n"
1679 " .VoltageMode = 0x%02x\n"
1680 " .SnapToDiscrete = 0x%02x\n"
1681 " .NumDiscreteLevels = 0x%02x\n"
1682 " .padding = 0x%02x\n"
1683 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1684 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1685 " .SsFmin = 0x%04x\n"
1686 " .Padding_16 = 0x%04x\n",
1687 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1688 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1689 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1690 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1691 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1692 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1693 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1694 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1695 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1696 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1697 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1698
1699 pr_info("[PPCLK_VCLK_1]\n"
1700 " .VoltageMode = 0x%02x\n"
1701 " .SnapToDiscrete = 0x%02x\n"
1702 " .NumDiscreteLevels = 0x%02x\n"
1703 " .padding = 0x%02x\n"
1704 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1705 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1706 " .SsFmin = 0x%04x\n"
1707 " .Padding_16 = 0x%04x\n",
1708 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1709 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1710 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1711 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1712 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1713 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1714 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1715 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1716 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1717 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1718 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1719
1720 pr_info("FreqTableGfx\n");
1721 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1722 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1723
1724 pr_info("FreqTableVclk\n");
1725 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1726 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1727
1728 pr_info("FreqTableDclk\n");
1729 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1730 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1731
1732 pr_info("FreqTableSocclk\n");
1733 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1734 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1735
1736 pr_info("FreqTableUclk\n");
1737 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1738 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1739
1740 pr_info("FreqTableFclk\n");
1741 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1742 pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1743
1744 pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
1745 pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
1746 pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
1747 pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
1748 pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
1749 pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
1750 pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
1751 pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
1752 pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
1753 pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
1754 pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1755 pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1756 pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1757 pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1758 pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1759 pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1760
1761 pr_info("DcModeMaxFreq\n");
1762 pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1763 pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1764 pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1765 pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1766 pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1767 pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1768 pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1769 pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1770
1771 pr_info("FreqTableUclkDiv\n");
1772 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1773 pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1774
1775 pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1776 pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1777
1778 pr_info("Mp0clkFreq\n");
1779 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1780 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1781
1782 pr_info("Mp0DpmVoltage\n");
1783 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1784 pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1785
1786 pr_info("MemVddciVoltage\n");
1787 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1788 pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1789
1790 pr_info("MemMvddVoltage\n");
1791 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1792 pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1793
1794 pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1795 pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1796 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1797 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1798 pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1799
1800 pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1801
1802 pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1803 pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1804 pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1805 pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1806 pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1807 pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1808 pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1809 pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1810 pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1811 pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1812 pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1813
1814 pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1815 pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1816 pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1817 pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1818 pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1819 pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1820
1821 pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1822 pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1823 pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1824 pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1825 pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1826
1827 pr_info("FlopsPerByteTable\n");
1828 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1829 pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1830
1831 pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1832 pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1833 pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1834 pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1835
1836 pr_info("UclkDpmPstates\n");
1837 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1838 pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1839
1840 pr_info("UclkDpmSrcFreqRange\n");
1841 pr_info(" .Fmin = 0x%x\n",
1842 pptable->UclkDpmSrcFreqRange.Fmin);
1843 pr_info(" .Fmax = 0x%x\n",
1844 pptable->UclkDpmSrcFreqRange.Fmax);
1845 pr_info("UclkDpmTargFreqRange\n");
1846 pr_info(" .Fmin = 0x%x\n",
1847 pptable->UclkDpmTargFreqRange.Fmin);
1848 pr_info(" .Fmax = 0x%x\n",
1849 pptable->UclkDpmTargFreqRange.Fmax);
1850 pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1851 pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1852
1853 pr_info("PcieGenSpeed\n");
1854 for (i = 0; i < NUM_LINK_LEVELS; i++)
1855 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1856
1857 pr_info("PcieLaneCount\n");
1858 for (i = 0; i < NUM_LINK_LEVELS; i++)
1859 pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1860
1861 pr_info("LclkFreq\n");
1862 for (i = 0; i < NUM_LINK_LEVELS; i++)
1863 pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1864
1865 pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1866 pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1867
1868 pr_info("FanGain\n");
1869 for (i = 0; i < TEMP_COUNT; i++)
1870 pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1871
1872 pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1873 pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1874 pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1875 pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1876 pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1877 pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1878 pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1879 pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1880 pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1881 pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1882 pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1883 pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1884
1885 pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1886 pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1887 pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1888 pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1889
1890 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1891 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1892 pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
1893 pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
1894
1895 pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1896 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
1897 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
1898 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
1899 pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1900 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
1901 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
1902 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
1903 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1904 pptable->dBtcGbGfxPll.a,
1905 pptable->dBtcGbGfxPll.b,
1906 pptable->dBtcGbGfxPll.c);
1907 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1908 pptable->dBtcGbGfxDfll.a,
1909 pptable->dBtcGbGfxDfll.b,
1910 pptable->dBtcGbGfxDfll.c);
1911 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1912 pptable->dBtcGbSoc.a,
1913 pptable->dBtcGbSoc.b,
1914 pptable->dBtcGbSoc.c);
1915 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1916 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1917 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1918 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1919 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1920 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1921
1922 pr_info("PiecewiseLinearDroopIntGfxDfll\n");
1923 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
1924 pr_info(" Fset[%d] = 0x%x\n",
1925 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
1926 pr_info(" Vdroop[%d] = 0x%x\n",
1927 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
1928 }
1929
1930 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1931 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1932 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1933 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1934 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1935 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1936 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1937 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1938
1939 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1940 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1941
1942 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1943 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1944 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1945 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1946
1947 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1948 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1949 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1950 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1951
1952 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1953 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1954
1955 pr_info("XgmiDpmPstates\n");
1956 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1957 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
1958 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1959 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1960
1961 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1962 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1963 pptable->ReservedEquation0.a,
1964 pptable->ReservedEquation0.b,
1965 pptable->ReservedEquation0.c);
1966 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1967 pptable->ReservedEquation1.a,
1968 pptable->ReservedEquation1.b,
1969 pptable->ReservedEquation1.c);
1970 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1971 pptable->ReservedEquation2.a,
1972 pptable->ReservedEquation2.b,
1973 pptable->ReservedEquation2.c);
1974 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1975 pptable->ReservedEquation3.a,
1976 pptable->ReservedEquation3.b,
1977 pptable->ReservedEquation3.c);
1978
1979 pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
1980 pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
1981 pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
1982 pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
1983 pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
1984 pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
1985 pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
1986 pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
1987 pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
1988 pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
1989 pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
1990 pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
1991 pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
1992 pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
1993 pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
1994
1995 pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
1996 pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
1997 pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
1998 pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
1999 pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2000 pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2001
2002 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2003 pr_info("I2cControllers[%d]:\n", i);
2004 pr_info(" .Enabled = 0x%x\n",
2005 pptable->I2cControllers[i].Enabled);
2006 pr_info(" .Speed = 0x%x\n",
2007 pptable->I2cControllers[i].Speed);
2008 pr_info(" .SlaveAddress = 0x%x\n",
2009 pptable->I2cControllers[i].SlaveAddress);
2010 pr_info(" .ControllerPort = 0x%x\n",
2011 pptable->I2cControllers[i].ControllerPort);
2012 pr_info(" .ControllerName = 0x%x\n",
2013 pptable->I2cControllers[i].ControllerName);
2014 pr_info(" .ThermalThrottler = 0x%x\n",
2015 pptable->I2cControllers[i].ThermalThrotter);
2016 pr_info(" .I2cProtocol = 0x%x\n",
2017 pptable->I2cControllers[i].I2cProtocol);
2018 pr_info(" .PaddingConfig = 0x%x\n",
2019 pptable->I2cControllers[i].PaddingConfig);
2020 }
2021
2022 pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
2023 pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
2024 pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2025 pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2026
2027 pr_info("Board Parameters:\n");
2028 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2029 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2030 pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2031 pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2032 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2033 pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2034 pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2035 pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2036
2037 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2038 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
2039 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2040
2041 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2042 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
2043 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2044
2045 pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2046 pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2047 pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2048
2049 pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2050 pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2051 pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2052
2053 pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2054
2055 pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2056 pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2057 pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2058 pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2059 pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2060 pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2061 pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2062 pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2063 pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2064 pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2065 pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2066 pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2067 pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2068 pr_info("LedError = 0x%x\n", pptable->LedError);
2069 pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2070 pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2071
2072 pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2073 pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2074 pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2075
2076 pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2077 pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2078 pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2079
2080 pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2081 pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2082 pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2083
2084 pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2085 pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2086 pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2087
2088 pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2089 pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2090 pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2091 pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2092 pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2093
2094 pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2095 pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2096
2097 pr_info("XgmiLinkSpeed\n");
2098 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2099 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2100 pr_info("XgmiLinkWidth\n");
2101 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2102 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2103 pr_info("XgmiFclkFreq\n");
2104 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2105 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2106 pr_info("XgmiSocVoltage\n");
2107 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2108 pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2109
2110 pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2111 pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2112 pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2113 pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2114
2115 pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2116 pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2117 pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2118 pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2119 pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2120 pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2121 pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2122 pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2123 pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2124 pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2125 pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2126 pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2127 pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2128 pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2129 pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2130
2131 pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2132 pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2133 pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2134 pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2135 pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2136 pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2137 pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2138 pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2139}
2140
2141static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2142 .tables_init = sienna_cichlid_tables_init,
2143 .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2144 .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2145 .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2146 .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2147 .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2148 .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2149 .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2150 .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2151 .get_workload_type = sienna_cichlid_get_workload_type,
2152 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2153 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2154 .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2155 .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2156 .print_clk_levels = sienna_cichlid_print_clk_levels,
2157 .force_clk_levels = sienna_cichlid_force_clk_levels,
2158 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2159 .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2160 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2161 .display_config_changed = sienna_cichlid_display_config_changed,
2162 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2163 .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2164 .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2165 .is_dpm_running = sienna_cichlid_is_dpm_running,
2166 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2167 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2168 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2169 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2170 .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2171 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2172 .read_sensor = sienna_cichlid_read_sensor,
2173 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
9ad9c8ac 2174 .set_performance_level = sienna_cichlid_set_performance_level,
b455159c
LG		 2175 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2176 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2177 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2178 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2179 .dump_pptable = sienna_cichlid_dump_pptable,
2180 .init_microcode = smu_v11_0_init_microcode,
2181 .load_microcode = smu_v11_0_load_microcode,
2182 .init_smc_tables = smu_v11_0_init_smc_tables,
2183 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2184 .init_power = smu_v11_0_init_power,
2185 .fini_power = smu_v11_0_fini_power,
2186 .check_fw_status = smu_v11_0_check_fw_status,
2187 .setup_pptable = smu_v11_0_setup_pptable,
2188 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2189 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2190 .check_pptable = smu_v11_0_check_pptable,
2191 .parse_pptable = smu_v11_0_parse_pptable,
2192 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2193 .check_fw_version = smu_v11_0_check_fw_version,
2194 .write_pptable = smu_v11_0_write_pptable,
2195 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2196 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2197 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2198 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2199 .system_features_control = smu_v11_0_system_features_control,
2200 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2201 .init_display_count = smu_v11_0_init_display_count,
2202 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2203 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2204 .notify_display_change = smu_v11_0_notify_display_change,
2205 .set_power_limit = smu_v11_0_set_power_limit,
2206 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2207 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2208 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2209 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2210 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2211 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2212 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2213 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2214 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2215 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2216 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2217 .gfx_off_control = smu_v11_0_gfx_off_control,
2218 .register_irq_handler = smu_v11_0_register_irq_handler,
2219 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2220 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2221 .baco_is_support= smu_v11_0_baco_is_support,
2222 .baco_get_state = smu_v11_0_baco_get_state,
2223 .baco_set_state = smu_v11_0_baco_set_state,
2224 .baco_enter = smu_v11_0_baco_enter,
2225 .baco_exit = smu_v11_0_baco_exit,
2226 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2227 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2228 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2229};
2230
2231void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2232{
2233 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2234}
Linux 6.x block layer and io_uring tree(s)