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3bace359 JZ |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #ifndef _HARDWARE_MANAGER_H_ | |
24 | #define _HARDWARE_MANAGER_H_ | |
25 | ||
28a18bab RZ |
26 | |
27 | ||
3bace359 | 28 | struct pp_hwmgr; |
28a18bab RZ |
29 | struct pp_hw_power_state; |
30 | struct pp_power_state; | |
31 | enum amd_dpm_forced_level; | |
fba4eef5 RZ |
32 | struct PP_TemperatureRange; |
33 | ||
34 | struct phm_fan_speed_info { | |
35 | uint32_t min_percent; | |
36 | uint32_t max_percent; | |
37 | uint32_t min_rpm; | |
38 | uint32_t max_rpm; | |
39 | bool supports_percent_read; | |
40 | bool supports_percent_write; | |
41 | bool supports_rpm_read; | |
42 | bool supports_rpm_write; | |
43 | }; | |
3bace359 JZ |
44 | |
45 | /* Automatic Power State Throttling */ | |
46 | enum PHM_AutoThrottleSource | |
47 | { | |
48 | PHM_AutoThrottleSource_Thermal, | |
49 | PHM_AutoThrottleSource_External | |
50 | }; | |
51 | ||
52 | typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource; | |
53 | ||
54 | enum phm_platform_caps { | |
55 | PHM_PlatformCaps_AtomBiosPpV1 = 0, | |
56 | PHM_PlatformCaps_PowerPlaySupport, | |
57 | PHM_PlatformCaps_ACOverdriveSupport, | |
58 | PHM_PlatformCaps_BacklightSupport, | |
59 | PHM_PlatformCaps_ThermalController, | |
60 | PHM_PlatformCaps_BiosPowerSourceControl, | |
61 | PHM_PlatformCaps_DisableVoltageTransition, | |
62 | PHM_PlatformCaps_DisableEngineTransition, | |
63 | PHM_PlatformCaps_DisableMemoryTransition, | |
64 | PHM_PlatformCaps_DynamicPowerManagement, | |
65 | PHM_PlatformCaps_EnableASPML0s, | |
66 | PHM_PlatformCaps_EnableASPML1, | |
67 | PHM_PlatformCaps_OD5inACSupport, | |
68 | PHM_PlatformCaps_OD5inDCSupport, | |
69 | PHM_PlatformCaps_SoftStateOD5, | |
70 | PHM_PlatformCaps_NoOD5Support, | |
71 | PHM_PlatformCaps_ContinuousHardwarePerformanceRange, | |
72 | PHM_PlatformCaps_ActivityReporting, | |
73 | PHM_PlatformCaps_EnableBackbias, | |
74 | PHM_PlatformCaps_OverdriveDisabledByPowerBudget, | |
75 | PHM_PlatformCaps_ShowPowerBudgetWarning, | |
76 | PHM_PlatformCaps_PowerBudgetWaiverAvailable, | |
77 | PHM_PlatformCaps_GFXClockGatingSupport, | |
78 | PHM_PlatformCaps_MMClockGatingSupport, | |
79 | PHM_PlatformCaps_AutomaticDCTransition, | |
80 | PHM_PlatformCaps_GeminiPrimary, | |
81 | PHM_PlatformCaps_MemorySpreadSpectrumSupport, | |
82 | PHM_PlatformCaps_EngineSpreadSpectrumSupport, | |
83 | PHM_PlatformCaps_StepVddc, | |
84 | PHM_PlatformCaps_DynamicPCIEGen2Support, | |
85 | PHM_PlatformCaps_SMC, | |
86 | PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */ | |
87 | PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */ | |
88 | PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */ | |
89 | PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */ | |
90 | PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */ | |
91 | PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overrided/automated mode. */ | |
92 | PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */ | |
93 | PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */ | |
94 | PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */ | |
95 | PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */ | |
96 | PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */ | |
97 | PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */ | |
98 | PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */ | |
99 | PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */ | |
100 | PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */ | |
101 | PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */ | |
102 | PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */ | |
103 | PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */ | |
104 | PHM_PlatformCaps_ABM, /* ABM support.*/ | |
105 | PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */ | |
106 | PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */ | |
107 | PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */ | |
108 | PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */ | |
109 | PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */ | |
110 | PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */ | |
111 | PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */ | |
112 | PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */ | |
113 | PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */ | |
114 | PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */ | |
115 | PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */ | |
116 | PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */ | |
117 | PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */ | |
118 | PHM_PlatformCaps_AdjustUVDPriorityForSP, | |
119 | PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */ | |
120 | PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */ | |
121 | PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */ | |
122 | PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */ | |
123 | PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */ | |
124 | PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */ | |
125 | PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */ | |
126 | PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */ | |
127 | PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */ | |
128 | PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */ | |
129 | PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */ | |
130 | PHM_PlatformCaps_BLControlledByGPU, /* support varibright */ | |
131 | PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */ | |
132 | PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */ | |
133 | PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */ | |
134 | PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */ | |
135 | PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */ | |
136 | PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */ | |
137 | PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */ | |
138 | PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */ | |
139 | PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */ | |
140 | PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */ | |
141 | PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */ | |
142 | PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */ | |
143 | PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */ | |
144 | PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */ | |
145 | PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */ | |
146 | PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/ | |
147 | PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */ | |
148 | PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */ | |
149 | PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */ | |
150 | PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */ | |
151 | PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */ | |
152 | PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */ | |
153 | PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */ | |
154 | PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */ | |
155 | PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */ | |
156 | PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */ | |
157 | PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */ | |
158 | PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */ | |
159 | PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */ | |
160 | PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */ | |
161 | PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */ | |
162 | PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */ | |
163 | PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */ | |
164 | PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */ | |
165 | PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */ | |
166 | PHM_PlatformCaps_DBRamping, /* for dI/dT feature */ | |
167 | PHM_PlatformCaps_TDRamping, /* for dI/dT feature */ | |
168 | PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */ | |
169 | PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */ | |
170 | PHM_PlatformCaps_FPS, /* FPS support */ | |
171 | PHM_PlatformCaps_ACP, /* ACP support */ | |
172 | PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */ | |
173 | PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */ | |
174 | PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */ | |
175 | PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */ | |
176 | PHM_PlatformCaps_VddNBDirectRequest, | |
177 | PHM_PlatformCaps_PauseMMSessions, | |
178 | PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */ | |
179 | PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */ | |
180 | PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */ | |
181 | PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */ | |
182 | PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */ | |
183 | PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */ | |
184 | PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */ | |
185 | PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */ | |
186 | PHM_PlatformCaps_IOIC3, | |
187 | PHM_PlatformCaps_ConnectedStandby, | |
188 | PHM_PlatformCaps_EVV, | |
189 | PHM_PlatformCaps_EnableLongIdleBACOSupport, | |
190 | PHM_PlatformCaps_CombinePCCWithThermalSignal, | |
191 | PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc, | |
192 | PHM_PlatformCaps_StablePState, | |
193 | PHM_PlatformCaps_OD6PlusinACSupport, | |
194 | PHM_PlatformCaps_OD6PlusinDCSupport, | |
195 | PHM_PlatformCaps_ODThermalLimitUnlock, | |
196 | PHM_PlatformCaps_ReducePowerLimit, | |
197 | PHM_PlatformCaps_ODFuzzyFanControlSupport, | |
198 | PHM_PlatformCaps_GeminiRegulatorFanControlSupport, | |
199 | PHM_PlatformCaps_ControlVDDGFX, | |
200 | PHM_PlatformCaps_BBBSupported, | |
201 | PHM_PlatformCaps_DisableVoltageIsland, | |
202 | PHM_PlatformCaps_FanSpeedInTableIsRPM, | |
203 | PHM_PlatformCaps_GFXClockGatingManagedInCAIL, | |
204 | PHM_PlatformCaps_IcelandULPSSWWorkAround, | |
205 | PHM_PlatformCaps_FPSEnhancement, | |
206 | PHM_PlatformCaps_LoadPostProductionFirmware, | |
207 | PHM_PlatformCaps_VpuRecoveryInProgress, | |
208 | PHM_PlatformCaps_Falcon_QuickTransition, | |
209 | PHM_PlatformCaps_AVFS, | |
210 | PHM_PlatformCaps_ClockStretcher, | |
211 | PHM_PlatformCaps_TablelessHardwareInterface, | |
212 | PHM_PlatformCaps_EnableDriverEVV, | |
213 | PHM_PlatformCaps_Max | |
214 | }; | |
215 | ||
216 | #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8) | |
217 | ||
218 | /* Number of uint32_t entries used by CAPS table */ | |
219 | #define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \ | |
220 | ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD)) | |
221 | ||
222 | struct pp_hw_descriptor { | |
223 | uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; | |
224 | }; | |
225 | ||
28a18bab RZ |
226 | enum PHM_PerformanceLevelDesignation { |
227 | PHM_PerformanceLevelDesignation_Activity, | |
228 | PHM_PerformanceLevelDesignation_PowerContainment | |
229 | }; | |
230 | ||
231 | typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation; | |
232 | ||
233 | struct PHM_PerformanceLevel { | |
c82baa28 | 234 | uint32_t coreClock; |
235 | uint32_t memory_clock; | |
236 | uint32_t vddc; | |
237 | uint32_t vddci; | |
238 | uint32_t nonLocalMemoryFreq; | |
239 | uint32_t nonLocalMemoryWidth; | |
28a18bab RZ |
240 | }; |
241 | ||
242 | typedef struct PHM_PerformanceLevel PHM_PerformanceLevel; | |
243 | ||
3bace359 JZ |
244 | /* Function for setting a platform cap */ |
245 | static inline void phm_cap_set(uint32_t *caps, | |
246 | enum phm_platform_caps c) | |
247 | { | |
248 | caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL << | |
249 | (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); | |
250 | } | |
251 | ||
252 | static inline void phm_cap_unset(uint32_t *caps, | |
253 | enum phm_platform_caps c) | |
254 | { | |
255 | caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); | |
256 | } | |
257 | ||
258 | static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c) | |
259 | { | |
260 | return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] & | |
261 | (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); | |
262 | } | |
263 | ||
28a18bab RZ |
264 | #define PP_PCIEGenInvalid 0xffff |
265 | enum PP_PCIEGen { | |
c82baa28 | 266 | PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */ |
267 | PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */ | |
268 | PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */ | |
28a18bab RZ |
269 | }; |
270 | ||
271 | typedef enum PP_PCIEGen PP_PCIEGen; | |
272 | ||
273 | #define PP_Min_PCIEGen PP_PCIEGen1 | |
274 | #define PP_Max_PCIEGen PP_PCIEGen3 | |
275 | #define PP_Min_PCIELane 1 | |
276 | #define PP_Max_PCIELane 32 | |
277 | ||
3bace359 JZ |
278 | enum phm_clock_Type { |
279 | PHM_DispClock = 1, | |
280 | PHM_SClock, | |
281 | PHM_MemClock | |
282 | }; | |
283 | ||
284 | #define MAX_NUM_CLOCKS 16 | |
285 | ||
286 | struct PP_Clocks { | |
287 | uint32_t engineClock; | |
288 | uint32_t memoryClock; | |
289 | uint32_t BusBandwidth; | |
290 | uint32_t engineClockInSR; | |
291 | }; | |
292 | ||
293 | struct phm_platform_descriptor { | |
294 | uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; | |
295 | uint32_t vbiosInterruptId; | |
296 | struct PP_Clocks overdriveLimit; | |
297 | struct PP_Clocks clockStep; | |
298 | uint32_t hardwareActivityPerformanceLevels; | |
299 | uint32_t minimumClocksReductionPercentage; | |
300 | uint32_t minOverdriveVDDC; | |
301 | uint32_t maxOverdriveVDDC; | |
302 | uint32_t overdriveVDDCStep; | |
303 | uint32_t hardwarePerformanceLevels; | |
304 | uint16_t powerBudget; | |
305 | uint32_t TDPLimit; | |
306 | uint32_t nearTDPLimit; | |
307 | uint32_t nearTDPLimitAdjusted; | |
308 | uint32_t SQRampingThreshold; | |
309 | uint32_t CACLeakage; | |
310 | uint16_t TDPODLimit; | |
311 | uint32_t TDPAdjustment; | |
312 | bool TDPAdjustmentPolarity; | |
313 | uint16_t LoadLineSlope; | |
314 | uint32_t VidMinLimit; | |
315 | uint32_t VidMaxLimit; | |
316 | uint32_t VidStep; | |
317 | uint32_t VidAdjustment; | |
318 | bool VidAdjustmentPolarity; | |
319 | }; | |
320 | ||
321 | struct phm_clocks { | |
322 | uint32_t num_of_entries; | |
323 | uint32_t clock[MAX_NUM_CLOCKS]; | |
324 | }; | |
09b4c872 | 325 | |
28a18bab RZ |
326 | extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr); |
327 | extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate); | |
328 | extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate); | |
329 | extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr); | |
3bace359 JZ |
330 | extern int phm_setup_asic(struct pp_hwmgr *hwmgr); |
331 | extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr); | |
332 | extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr); | |
28a18bab RZ |
333 | extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr); |
334 | extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block); | |
335 | extern int phm_set_power_state(struct pp_hwmgr *hwmgr, | |
336 | const struct pp_hw_power_state *pcurrent_state, | |
337 | const struct pp_hw_power_state *pnew_power_state); | |
338 | ||
339 | extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, | |
340 | struct pp_power_state *adjusted_ps, | |
341 | const struct pp_power_state *current_ps); | |
342 | ||
343 | extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level); | |
6f3bf747 RZ |
344 | extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr); |
345 | extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); | |
fba4eef5 RZ |
346 | extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info); |
347 | extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range); | |
348 | extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr); | |
09b4c872 RZ |
349 | extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr); |
350 | ||
351 | extern int phm_check_states_equal(struct pp_hwmgr *hwmgr, | |
352 | const struct pp_hw_power_state *pstate1, | |
353 | const struct pp_hw_power_state *pstate2, | |
354 | bool *equal); | |
355 | ||
7fb72a1f RZ |
356 | extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, |
357 | const struct amd_pp_display_configuration *display_config); | |
358 | ||
73afe621 RZ |
359 | extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr); |
360 | ||
3bace359 | 361 | #endif /* _HARDWARE_MANAGER_H_ */ |
fba4eef5 | 362 |