[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / inc / amdgpu_smu.h

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __AMDGPU_SMU_H__
#define __AMDGPU_SMU_H__

#include "amdgpu.h"

enum smu_message_type
{
	SMU_MSG_TestMessage = 0,
	SMU_MSG_GetSmuVersion,
	SMU_MSG_GetDriverIfVersion,
	SMU_MSG_SetAllowedFeaturesMaskLow,
	SMU_MSG_SetAllowedFeaturesMaskHigh,
	SMU_MSG_EnableAllSmuFeatures,
	SMU_MSG_DisableAllSmuFeatures,
	SMU_MSG_EnableSmuFeaturesLow,
	SMU_MSG_EnableSmuFeaturesHigh,
	SMU_MSG_DisableSmuFeaturesLow,
	SMU_MSG_DisableSmuFeaturesHigh,
	SMU_MSG_GetEnabledSmuFeaturesLow,
	SMU_MSG_GetEnabledSmuFeaturesHigh,
	SMU_MSG_SetWorkloadMask,
	SMU_MSG_SetPptLimit,
	SMU_MSG_SetDriverDramAddrHigh,
	SMU_MSG_SetDriverDramAddrLow,
	SMU_MSG_SetToolsDramAddrHigh,
	SMU_MSG_SetToolsDramAddrLow,
	SMU_MSG_TransferTableSmu2Dram,
	SMU_MSG_TransferTableDram2Smu,
	SMU_MSG_UseDefaultPPTable,
	SMU_MSG_UseBackupPPTable,
	SMU_MSG_RunBtc,
	SMU_MSG_RequestI2CBus,
	SMU_MSG_ReleaseI2CBus,
	SMU_MSG_SetFloorSocVoltage,
	SMU_MSG_SoftReset,
	SMU_MSG_StartBacoMonitor,
	SMU_MSG_CancelBacoMonitor,
	SMU_MSG_EnterBaco,
	SMU_MSG_SetSoftMinByFreq,
	SMU_MSG_SetSoftMaxByFreq,
	SMU_MSG_SetHardMinByFreq,
	SMU_MSG_SetHardMaxByFreq,
	SMU_MSG_GetMinDpmFreq,
	SMU_MSG_GetMaxDpmFreq,
	SMU_MSG_GetDpmFreqByIndex,
	SMU_MSG_GetDpmClockFreq,
	SMU_MSG_GetSsVoltageByDpm,
	SMU_MSG_SetMemoryChannelConfig,
	SMU_MSG_SetGeminiMode,
	SMU_MSG_SetGeminiApertureHigh,
	SMU_MSG_SetGeminiApertureLow,
	SMU_MSG_SetMinLinkDpmByIndex,
	SMU_MSG_OverridePcieParameters,
	SMU_MSG_OverDriveSetPercentage,
	SMU_MSG_SetMinDeepSleepDcefclk,
	SMU_MSG_ReenableAcDcInterrupt,
	SMU_MSG_NotifyPowerSource,
	SMU_MSG_SetUclkFastSwitch,
	SMU_MSG_SetUclkDownHyst,
	SMU_MSG_GfxDeviceDriverReset,
	SMU_MSG_GetCurrentRpm,
	SMU_MSG_SetVideoFps,
	SMU_MSG_SetTjMax,
	SMU_MSG_SetFanTemperatureTarget,
	SMU_MSG_PrepareMp1ForUnload,
	SMU_MSG_DramLogSetDramAddrHigh,
	SMU_MSG_DramLogSetDramAddrLow,
	SMU_MSG_DramLogSetDramSize,
	SMU_MSG_SetFanMaxRpm,
	SMU_MSG_SetFanMinPwm,
	SMU_MSG_ConfigureGfxDidt,
	SMU_MSG_NumOfDisplays,
	SMU_MSG_RemoveMargins,
	SMU_MSG_ReadSerialNumTop32,
	SMU_MSG_ReadSerialNumBottom32,
	SMU_MSG_SetSystemVirtualDramAddrHigh,
	SMU_MSG_SetSystemVirtualDramAddrLow,
	SMU_MSG_WaflTest,
	SMU_MSG_SetFclkGfxClkRatio,
	SMU_MSG_AllowGfxOff,
	SMU_MSG_DisallowGfxOff,
	SMU_MSG_GetPptLimit,
	SMU_MSG_GetDcModeMaxDpmFreq,
	SMU_MSG_GetDebugData,
	SMU_MSG_SetXgmiMode,
	SMU_MSG_RunAfllBtc,
	SMU_MSG_ExitBaco,
	SMU_MSG_PrepareMp1ForReset,
	SMU_MSG_PrepareMp1ForShutdown,
	SMU_MSG_SetMGpuFanBoostLimitRpm,
	SMU_MSG_GetAVFSVoltageByDpm,
	SMU_MSG_MAX_COUNT,
};

enum smu_memory_pool_size
{
    SMU_MEMORY_POOL_SIZE_ZERO   = 0,
    SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
    SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
    SMU_MEMORY_POOL_SIZE_1_GB   = 0x40000000,
    SMU_MEMORY_POOL_SIZE_2_GB   = 0x80000000,
};

#define SMU_TABLE_INIT(tables, table_id, s, a, d)	\
	do {						\
		tables[table_id].size = s;		\
		tables[table_id].align = a;		\
		tables[table_id].domain = d;		\
	} while (0)

struct smu_table {
	uint64_t size;
	uint32_t align;
	uint8_t domain;
	uint64_t mc_address;
	void *cpu_addr;
	struct amdgpu_bo *bo;
};

struct smu_bios_boot_up_values
{
	uint32_t			revision;
	uint32_t			gfxclk;
	uint32_t			uclk;
	uint32_t			socclk;
	uint32_t			dcefclk;
	uint16_t			vddc;
	uint16_t			vddci;
	uint16_t			mvddc;
	uint16_t			vdd_gfx;
	uint8_t				cooling_id;
	uint32_t			pp_table_id;
};

struct smu_table_context
{
	void				*power_play_table;
	uint32_t			power_play_table_size;

	void				*max_sustainable_clocks;
	struct smu_bios_boot_up_values	boot_values;
	void                            *driver_pptable;
	struct smu_table		*tables;
	uint32_t			table_count;
	struct smu_table		memory_pool;
};

struct smu_dpm_context {
	void *dpm_context;
	uint32_t dpm_context_size;
};

struct smu_power_context {
	void *power_context;
	uint32_t power_context_size;
};


#define SMU_FEATURE_MAX	(64)
struct smu_feature
{
	uint32_t feature_num;
	DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
	DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
	DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
};

struct smu_context
{
	struct amdgpu_device            *adev;

	const struct smu_funcs		*funcs;
	const struct pptable_funcs	*ppt_funcs;
	struct mutex			mutex;
	uint64_t pool_size;

	struct smu_table_context	smu_table;
	struct smu_dpm_context		smu_dpm;
	struct smu_power_context	smu_power;
	struct smu_feature		smu_feature;

	uint32_t pstate_sclk;
	uint32_t pstate_mclk;

	uint32_t power_limit;
	uint32_t default_power_limit;
};

struct pptable_funcs {
	int (*alloc_dpm_context)(struct smu_context *smu);
	int (*store_powerplay_table)(struct smu_context *smu);
	int (*check_powerplay_table)(struct smu_context *smu);
	int (*append_powerplay_table)(struct smu_context *smu);
	int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
	int (*run_afll_btc)(struct smu_context *smu);
	int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
	int (*set_default_dpm_table)(struct smu_context *smu);
	int (*populate_umd_state_clk)(struct smu_context *smu);
	int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
};

struct smu_funcs
{
	int (*init_microcode)(struct smu_context *smu);
	int (*init_smc_tables)(struct smu_context *smu);
	int (*fini_smc_tables)(struct smu_context *smu);
	int (*init_power)(struct smu_context *smu);
	int (*fini_power)(struct smu_context *smu);
	int (*load_microcode)(struct smu_context *smu);
	int (*check_fw_status)(struct smu_context *smu);
	int (*read_pptable_from_vbios)(struct smu_context *smu);
	int (*get_vbios_bootup_values)(struct smu_context *smu);
	int (*get_clk_info_from_vbios)(struct smu_context *smu);
	int (*check_pptable)(struct smu_context *smu);
	int (*parse_pptable)(struct smu_context *smu);
	int (*populate_smc_pptable)(struct smu_context *smu);
	int (*check_fw_version)(struct smu_context *smu);
	int (*write_pptable)(struct smu_context *smu);
	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
	int (*set_tool_table_location)(struct smu_context *smu);
	int (*notify_memory_pool_location)(struct smu_context *smu);
	int (*write_watermarks_table)(struct smu_context *smu);
	int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
	int (*system_features_control)(struct smu_context *smu, bool en);
	int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
	int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
	int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
	int (*init_display)(struct smu_context *smu);
	int (*set_allowed_mask)(struct smu_context *smu);
	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
	int (*enable_all_mask)(struct smu_context *smu);
	int (*disable_all_mask)(struct smu_context *smu);
	int (*notify_display_change)(struct smu_context *smu);
	int (*get_power_limit)(struct smu_context *smu);
	int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
	int (*init_max_sustainable_clocks)(struct smu_context *smu);
};

#define smu_init_microcode(smu) \
	((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
#define smu_init_smc_tables(smu) \
	((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
#define smu_fini_smc_tables(smu) \
	((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
#define smu_init_power(smu) \
	((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
#define smu_fini_power(smu) \
	((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
#define smu_load_microcode(smu) \
	((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
#define smu_check_fw_status(smu) \
	((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
#define smu_read_pptable_from_vbios(smu) \
	((smu)->funcs->read_pptable_from_vbios ? (smu)->funcs->read_pptable_from_vbios((smu)) : 0)
#define smu_get_vbios_bootup_values(smu) \
	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
	((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
#define smu_check_pptable(smu) \
	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
#define smu_parse_pptable(smu) \
	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
#define smu_populate_smc_pptable(smu) \
	((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
#define smu_check_fw_version(smu) \
	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
#define smu_write_pptable(smu) \
	((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
#define smu_set_min_dcef_deep_sleep(smu) \
	((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
#define smu_set_tool_table_location(smu) \
	((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
#define smu_notify_memory_pool_location(smu) \
	((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
#define smu_write_watermarks_table(smu) \
	((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
	((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
#define smu_system_features_control(smu, en) \
	((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
#define smu_init_max_sustainable_clocks(smu) \
	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_send_smc_msg(smu, msg) \
	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
	((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
#define smu_read_smc_arg(smu, arg) \
	((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
#define smu_alloc_dpm_context(smu) \
	((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
#define smu_init_display(smu) \
	((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
#define smu_feature_set_allowed_mask(smu) \
	((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
#define smu_feature_get_enabled_mask(smu, mask, num) \
	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
#define smu_feature_enable_all(smu) \
	((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
#define smu_feature_disable_all(smu) \
	((smu)->funcs->disable_all_mask? (smu)->funcs->disable_all_mask((smu)) : 0)
#define smu_notify_display_change(smu) \
	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
#define smu_store_powerplay_table(smu) \
	((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
	((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
#define smu_append_powerplay_table(smu) \
	((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
#define smu_set_default_dpm_table(smu) \
	((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
#define smu_populate_umd_state_clk(smu) \
	((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_get_power_limit(smu) \
	((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
#define smu_get_current_clk_freq(smu, clk_id, value) \
	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
#define smu_print_clk_levels(smu, type, buf) \
	((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)

#define smu_msg_get_index(smu, msg) \
	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
#define smu_run_afll_btc(smu) \
	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
#define smu_get_unallowed_feature_mask(smu, feature_mask, num) \
	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_unallowed_feature_mask? (smu)->ppt_funcs->get_unallowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)

extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
				   uint16_t *size, uint8_t *frev, uint8_t *crev,
				   uint8_t **addr);

extern const struct amd_ip_funcs smu_ip_funcs;

extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
extern int smu_feature_init_dpm(struct smu_context *smu);

extern int smu_feature_is_enabled(struct smu_context *smu, int feature_id);
extern int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool enable);
extern int smu_feature_is_supported(struct smu_context *smu, int feature_id);
extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bool enable);

#endif
Commit	Line	Data
137d63ab HR	1	/*
	2	* Copyright 2019 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#ifndef __AMDGPU_SMU_H__
	23	#define __AMDGPU_SMU_H__
	24
	25	#include "amdgpu.h"
	26
64136ea6 KW	27	enum smu_message_type
	28	{
	29	SMU_MSG_TestMessage = 0,
	30	SMU_MSG_GetSmuVersion,
	31	SMU_MSG_GetDriverIfVersion,
	32	SMU_MSG_SetAllowedFeaturesMaskLow,
	33	SMU_MSG_SetAllowedFeaturesMaskHigh,
	34	SMU_MSG_EnableAllSmuFeatures,
	35	SMU_MSG_DisableAllSmuFeatures,
	36	SMU_MSG_EnableSmuFeaturesLow,
	37	SMU_MSG_EnableSmuFeaturesHigh,
	38	SMU_MSG_DisableSmuFeaturesLow,
	39	SMU_MSG_DisableSmuFeaturesHigh,
	40	SMU_MSG_GetEnabledSmuFeaturesLow,
	41	SMU_MSG_GetEnabledSmuFeaturesHigh,
	42	SMU_MSG_SetWorkloadMask,
	43	SMU_MSG_SetPptLimit,
	44	SMU_MSG_SetDriverDramAddrHigh,
	45	SMU_MSG_SetDriverDramAddrLow,
	46	SMU_MSG_SetToolsDramAddrHigh,
	47	SMU_MSG_SetToolsDramAddrLow,
	48	SMU_MSG_TransferTableSmu2Dram,
	49	SMU_MSG_TransferTableDram2Smu,
	50	SMU_MSG_UseDefaultPPTable,
	51	SMU_MSG_UseBackupPPTable,
	52	SMU_MSG_RunBtc,
	53	SMU_MSG_RequestI2CBus,
	54	SMU_MSG_ReleaseI2CBus,
	55	SMU_MSG_SetFloorSocVoltage,
	56	SMU_MSG_SoftReset,
	57	SMU_MSG_StartBacoMonitor,
	58	SMU_MSG_CancelBacoMonitor,
	59	SMU_MSG_EnterBaco,
	60	SMU_MSG_SetSoftMinByFreq,
	61	SMU_MSG_SetSoftMaxByFreq,
	62	SMU_MSG_SetHardMinByFreq,
	63	SMU_MSG_SetHardMaxByFreq,
	64	SMU_MSG_GetMinDpmFreq,
	65	SMU_MSG_GetMaxDpmFreq,
	66	SMU_MSG_GetDpmFreqByIndex,
	67	SMU_MSG_GetDpmClockFreq,
	68	SMU_MSG_GetSsVoltageByDpm,
	69	SMU_MSG_SetMemoryChannelConfig,
	70	SMU_MSG_SetGeminiMode,
	71	SMU_MSG_SetGeminiApertureHigh,
	72	SMU_MSG_SetGeminiApertureLow,
	73	SMU_MSG_SetMinLinkDpmByIndex,
	74	SMU_MSG_OverridePcieParameters,
	75	SMU_MSG_OverDriveSetPercentage,
	76	SMU_MSG_SetMinDeepSleepDcefclk,
	77	SMU_MSG_ReenableAcDcInterrupt,
	78	SMU_MSG_NotifyPowerSource,
	79	SMU_MSG_SetUclkFastSwitch,
	80	SMU_MSG_SetUclkDownHyst,
	81	SMU_MSG_GfxDeviceDriverReset,
	82	SMU_MSG_GetCurrentRpm,
	83	SMU_MSG_SetVideoFps,
	84	SMU_MSG_SetTjMax,
	85	SMU_MSG_SetFanTemperatureTarget,
	86	SMU_MSG_PrepareMp1ForUnload,
	87	SMU_MSG_DramLogSetDramAddrHigh,
	88	SMU_MSG_DramLogSetDramAddrLow,
	89	SMU_MSG_DramLogSetDramSize,
	90	SMU_MSG_SetFanMaxRpm,
91	SMU_MSG_SetFanMinPwm,
92	SMU_MSG_ConfigureGfxDidt,
93	SMU_MSG_NumOfDisplays,
94	SMU_MSG_RemoveMargins,
95	SMU_MSG_ReadSerialNumTop32,
96	SMU_MSG_ReadSerialNumBottom32,
97	SMU_MSG_SetSystemVirtualDramAddrHigh,
98	SMU_MSG_SetSystemVirtualDramAddrLow,
99	SMU_MSG_WaflTest,
100	SMU_MSG_SetFclkGfxClkRatio,
101	SMU_MSG_AllowGfxOff,
102	SMU_MSG_DisallowGfxOff,
103	SMU_MSG_GetPptLimit,
104	SMU_MSG_GetDcModeMaxDpmFreq,
105	SMU_MSG_GetDebugData,
106	SMU_MSG_SetXgmiMode,
107	SMU_MSG_RunAfllBtc,
108	SMU_MSG_ExitBaco,
109	SMU_MSG_PrepareMp1ForReset,
110	SMU_MSG_PrepareMp1ForShutdown,
111	SMU_MSG_SetMGpuFanBoostLimitRpm,
112	SMU_MSG_GetAVFSVoltageByDpm,
113	SMU_MSG_MAX_COUNT,
114	};
115
0b51d993 KW	116	enum smu_memory_pool_size
	117	{
	118	SMU_MEMORY_POOL_SIZE_ZERO = 0,
	119	SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
	120	SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
	121	SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
	122	SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
	123	};
	124
813ce279 KW	125	#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
	126	do { \
	127	tables[table_id].size = s; \
	128	tables[table_id].align = a; \
	129	tables[table_id].domain = d; \
	130	} while (0)
	131
	132	struct smu_table {
	133	uint64_t size;
	134	uint32_t align;
	135	uint8_t domain;
	136	uint64_t mc_address;
	137	void *cpu_addr;
	138	struct amdgpu_bo *bo;
e98499b4	139	};
813ce279	140
e98499b4 HR	141	struct smu_bios_boot_up_values
	142	{
	143	uint32_t revision;
	144	uint32_t gfxclk;
	145	uint32_t uclk;
	146	uint32_t socclk;
	147	uint32_t dcefclk;
	148	uint16_t vddc;
	149	uint16_t vddci;
	150	uint16_t mvddc;
	151	uint16_t vdd_gfx;
	152	uint8_t cooling_id;
	153	uint32_t pp_table_id;
813ce279 KW	154	};
813ce279 KW	155
2cf543ed HR	156	struct smu_table_context
	157	{
	158	void *power_play_table;
	159	uint32_t power_play_table_size;
e98499b4	160
7457cf02	161	void *max_sustainable_clocks;
e98499b4	162	struct smu_bios_boot_up_values boot_values;
3e333c6c	163	void *driver_pptable;
813ce279 KW	164	struct smu_table *tables;
813ce279 KW	165	uint32_t table_count;
0b51d993	166	struct smu_table memory_pool;
2cf543ed HR	167	};
2cf543ed HR	168
142dec62 KW	169	struct smu_dpm_context {
	170	void *dpm_context;
	171	uint32_t dpm_context_size;
	172	};
	173
8bf16963 KW	174	struct smu_power_context {
	175	void *power_context;
	176	uint32_t power_context_size;
	177	};
	178
6b816d73 KW	179
	180	#define SMU_FEATURE_MAX (64)
	181	struct smu_feature
	182	{
	183	uint32_t feature_num;
	184	DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
	185	DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
	186	DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
	187	};
	188
137d63ab HR	189	struct smu_context
	190	{
	191	struct amdgpu_device *adev;
	192
	193	const struct smu_funcs *funcs;
74e07f9d	194	const struct pptable_funcs *ppt_funcs;
137d63ab	195	struct mutex mutex;
0b51d993	196	uint64_t pool_size;
2cf543ed HR	197
2cf543ed HR	198	struct smu_table_context smu_table;
142dec62	199	struct smu_dpm_context smu_dpm;
8bf16963	200	struct smu_power_context smu_power;
6b816d73	201	struct smu_feature smu_feature;
133438fa LG	202
	203	uint32_t pstate_sclk;
	204	uint32_t pstate_mclk;
e66adb1e LG	205
	206	uint32_t power_limit;
	207	uint32_t default_power_limit;
137d63ab HR	208	};
137d63ab HR	209
74e07f9d	210	struct pptable_funcs {
d76c9e24	211	int (alloc_dpm_context)(struct smu_context smu);
74e07f9d	212	int (store_powerplay_table)(struct smu_context smu);
c6eef2d0	213	int (check_powerplay_table)(struct smu_context smu);
c5895273	214	int (append_powerplay_table)(struct smu_context smu);
78031c2c	215	int (get_smu_msg_index)(struct smu_context smu, uint32_t index);
f6a6b952	216	int (run_afll_btc)(struct smu_context smu);
6b816d73	217	int (get_unallowed_feature_mask)(struct smu_context smu, uint32_t *feature_mask, uint32_t num);
d6a4aa82	218	int (set_default_dpm_table)(struct smu_context smu);
133438fa	219	int (populate_umd_state_clk)(struct smu_context smu);
86ac8803	220	int (print_clk_levels)(struct smu_context smu, enum pp_clock_type type, char *buf);
74e07f9d HR	221	};
74e07f9d HR	222
137d63ab HR	223	struct smu_funcs
	224	{
	225	int (init_microcode)(struct smu_context smu);
cabd44c0	226	int (init_smc_tables)(struct smu_context smu);
813ce279	227	int (fini_smc_tables)(struct smu_context smu);
17e6081b	228	int (init_power)(struct smu_context smu);
8bf16963	229	int (fini_power)(struct smu_context smu);
3d2f5200	230	int (load_microcode)(struct smu_context smu);
e11c4fd5	231	int (check_fw_status)(struct smu_context smu);
05cadcd3	232	int (read_pptable_from_vbios)(struct smu_context smu);
a6b35900	233	int (get_vbios_bootup_values)(struct smu_context smu);
08115f87	234	int (get_clk_info_from_vbios)(struct smu_context smu);
46126e6d	235	int (check_pptable)(struct smu_context smu);
9e4848a4	236	int (parse_pptable)(struct smu_context smu);
86187fec	237	int (populate_smc_pptable)(struct smu_context smu);
a751b095	238	int (check_fw_version)(struct smu_context smu);
31b5ae49	239	int (write_pptable)(struct smu_context smu);
a7ebb6d2	240	int (set_min_dcef_deep_sleep)(struct smu_context smu);
206bc589	241	int (set_tool_table_location)(struct smu_context smu);
c56de9e8	242	int (notify_memory_pool_location)(struct smu_context smu);
38f8a2e6 HR	243	int (write_watermarks_table)(struct smu_context smu);
	244	int (set_last_dcef_min_deep_sleep_clk)(struct smu_context smu);
	245	int (system_features_control)(struct smu_context smu, bool en);
b0b4b413 KW	246	int (send_smc_msg)(struct smu_context smu, uint16_t msg);
b0b4b413 KW	247	int (send_smc_msg_with_param)(struct smu_context smu, uint16_t msg, uint32_t param);
00bfaec8	248	int (read_smc_arg)(struct smu_context smu, uint32_t *arg);
56c53ad6	249	int (init_display)(struct smu_context smu);
6b816d73 KW	250	int (set_allowed_mask)(struct smu_context smu);
	251	int (get_enabled_mask)(struct smu_context smu, uint32_t *feature_mask, uint32_t num);
	252	int (enable_all_mask)(struct smu_context smu);
	253	int (disable_all_mask)(struct smu_context smu);
e1c6f86a	254	int (notify_display_change)(struct smu_context smu);
e66adb1e	255	int (get_power_limit)(struct smu_context smu);
bed3b3a1	256	int (get_current_clk_freq)(struct smu_context smu, uint32_t clk_id, uint32_t *value);
7457cf02	257	int (init_max_sustainable_clocks)(struct smu_context smu);
137d63ab HR	258	};
	259
	260	#define smu_init_microcode(smu) \
	261	((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
cabd44c0 HR	262	#define smu_init_smc_tables(smu) \
cabd44c0 HR	263	((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
813ce279 KW	264	#define smu_fini_smc_tables(smu) \
813ce279 KW	265	((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
17e6081b HR	266	#define smu_init_power(smu) \
17e6081b HR	267	((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
8bf16963 KW	268	#define smu_fini_power(smu) \
8bf16963 KW	269	((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
3d2f5200 HR	270	#define smu_load_microcode(smu) \
3d2f5200 HR	271	((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
e11c4fd5 HR	272	#define smu_check_fw_status(smu) \
e11c4fd5 HR	273	((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
05cadcd3 HR	274	#define smu_read_pptable_from_vbios(smu) \
05cadcd3 HR	275	((smu)->funcs->read_pptable_from_vbios ? (smu)->funcs->read_pptable_from_vbios((smu)) : 0)
a6b35900 HR	276	#define smu_get_vbios_bootup_values(smu) \
a6b35900 HR	277	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
08115f87 HR	278	#define smu_get_clk_info_from_vbios(smu) \
08115f87 HR	279	((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
46126e6d HR	280	#define smu_check_pptable(smu) \
46126e6d HR	281	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
9e4848a4 HR	282	#define smu_parse_pptable(smu) \
9e4848a4 HR	283	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
86187fec HR	284	#define smu_populate_smc_pptable(smu) \
86187fec HR	285	((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
a751b095 HR	286	#define smu_check_fw_version(smu) \
a751b095 HR	287	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
31b5ae49 HR	288	#define smu_write_pptable(smu) \
31b5ae49 HR	289	((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
a7ebb6d2 HR	290	#define smu_set_min_dcef_deep_sleep(smu) \
a7ebb6d2 HR	291	((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
206bc589 HR	292	#define smu_set_tool_table_location(smu) \
206bc589 HR	293	((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
c56de9e8 HR	294	#define smu_notify_memory_pool_location(smu) \
c56de9e8 HR	295	((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
38f8a2e6 HR	296	#define smu_write_watermarks_table(smu) \
	297	((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
	298	#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
	299	((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
	300	#define smu_system_features_control(smu, en) \
	301	((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
7457cf02 HR	302	#define smu_init_max_sustainable_clocks(smu) \
7457cf02 HR	303	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
b0b4b413 KW	304	#define smu_send_smc_msg(smu, msg) \
	305	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
	306	#define smu_send_smc_msg_with_param(smu, msg, param) \
	307	((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
00bfaec8 LG	308	#define smu_read_smc_arg(smu, arg) \
00bfaec8 LG	309	((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
d76c9e24 LG	310	#define smu_alloc_dpm_context(smu) \
d76c9e24 LG	311	((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
56c53ad6 KW	312	#define smu_init_display(smu) \
56c53ad6 KW	313	((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
6b816d73 KW	314	#define smu_feature_set_allowed_mask(smu) \
	315	((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
	316	#define smu_feature_get_enabled_mask(smu, mask, num) \
	317	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
	318	#define smu_feature_enable_all(smu) \
	319	((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
	320	#define smu_feature_disable_all(smu) \
	321	((smu)->funcs->disable_all_mask? (smu)->funcs->disable_all_mask((smu)) : 0)
e1c6f86a KW	322	#define smu_notify_display_change(smu) \
e1c6f86a KW	323	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
3e333c6c LG	324	#define smu_store_powerplay_table(smu) \
3e333c6c LG	325	((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
c6eef2d0 LG	326	#define smu_check_powerplay_table(smu) \
c6eef2d0 LG	327	((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
c5895273 HR	328	#define smu_append_powerplay_table(smu) \
c5895273 HR	329	((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
d6a4aa82 LG	330	#define smu_set_default_dpm_table(smu) \
d6a4aa82 LG	331	((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
133438fa LG	332	#define smu_populate_umd_state_clk(smu) \
133438fa LG	333	((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
e66adb1e LG	334	#define smu_get_power_limit(smu) \
e66adb1e LG	335	((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
bed3b3a1 KW	336	#define smu_get_current_clk_freq(smu, clk_id, value) \
bed3b3a1 KW	337	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
86ac8803 LG	338	#define smu_print_clk_levels(smu, type, buf) \
86ac8803 LG	339	((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
137d63ab	340
78031c2c KW	341	#define smu_msg_get_index(smu, msg) \
78031c2c KW	342	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
f6a6b952 KW	343	#define smu_run_afll_btc(smu) \
f6a6b952 KW	344	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
6b816d73 KW	345	#define smu_get_unallowed_feature_mask(smu, feature_mask, num) \
6b816d73 KW	346	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_unallowed_feature_mask? (smu)->ppt_funcs->get_unallowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
78031c2c	347
e15da5a4 HR	348	extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
	349	uint16_t size, uint8_t frev, uint8_t *crev,
	350	uint8_t **addr);
	351
137d63ab HR	352	extern const struct amd_ip_funcs smu_ip_funcs;
137d63ab HR	353
07845526	354	extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
6b816d73	355	extern int smu_feature_init_dpm(struct smu_context *smu);
07845526	356
2f25158d KW	357	extern int smu_feature_is_enabled(struct smu_context *smu, int feature_id);
	358	extern int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool enable);
	359	extern int smu_feature_is_supported(struct smu_context *smu, int feature_id);
	360	extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bool enable);
	361
137d63ab	362	#endif