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Merge branch 'for-5.4/apple' into for-linus
[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / inc / amdgpu_smu.h
CommitLineData
137d63ab
HR		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#ifndef __AMDGPU_SMU_H__
23#define __AMDGPU_SMU_H__
24
25#include "amdgpu.h"
4a5a2de6 26#include "kgd_pp_interface.h"
94ed6d0c 27#include "dm_pp_interface.h"
a18bf0ca 28#include "dm_pp_smu.h"
137d63ab 29
e211580d
HZ		 30#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
31#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
32#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
33
8554e67d
CG		 34struct smu_hw_power_state {
35 unsigned int magic;
36};
37
38struct smu_power_state;
39
40enum smu_state_ui_label {
41 SMU_STATE_UI_LABEL_NONE,
42 SMU_STATE_UI_LABEL_BATTERY,
43 SMU_STATE_UI_TABEL_MIDDLE_LOW,
44 SMU_STATE_UI_LABEL_BALLANCED,
45 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
46 SMU_STATE_UI_LABEL_PERFORMANCE,
47 SMU_STATE_UI_LABEL_BACO,
48};
49
50enum smu_state_classification_flag {
51 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
52 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
53 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
54 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
55 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
56 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
57 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
58 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
59 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
60 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
61 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
62 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
63 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
64 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
65 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
66 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
67 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
68 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
69 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
70 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
71 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
72};
73
74struct smu_state_classification_block {
75 enum smu_state_ui_label ui_label;
76 enum smu_state_classification_flag flags;
77 int bios_index;
78 bool temporary_state;
79 bool to_be_deleted;
80};
81
82struct smu_state_pcie_block {
83 unsigned int lanes;
84};
85
86enum smu_refreshrate_source {
87 SMU_REFRESHRATE_SOURCE_EDID,
88 SMU_REFRESHRATE_SOURCE_EXPLICIT
89};
90
91struct smu_state_display_block {
92 bool disable_frame_modulation;
93 bool limit_refreshrate;
94 enum smu_refreshrate_source refreshrate_source;
95 int explicit_refreshrate;
96 int edid_refreshrate_index;
97 bool enable_vari_bright;
98};
99
100struct smu_state_memroy_block {
101 bool dll_off;
102 uint8_t m3arb;
103 uint8_t unused[3];
104};
105
106struct smu_state_software_algorithm_block {
107 bool disable_load_balancing;
108 bool enable_sleep_for_timestamps;
109};
110
111struct smu_temperature_range {
112 int min;
113 int max;
e211580d
HZ		 114 int edge_emergency_max;
115 int hotspot_min;
116 int hotspot_crit_max;
117 int hotspot_emergency_max;
118 int mem_min;
119 int mem_crit_max;
120 int mem_emergency_max;
8554e67d
CG		 121};
122
123struct smu_state_validation_block {
124 bool single_display_only;
125 bool disallow_on_dc;
126 uint8_t supported_power_levels;
127};
128
129struct smu_uvd_clocks {
130 uint32_t vclk;
131 uint32_t dclk;
132};
133
134/**
135* Structure to hold a SMU Power State.
136*/
137struct smu_power_state {
138 uint32_t id;
139 struct list_head ordered_list;
140 struct list_head all_states_list;
141
142 struct smu_state_classification_block classification;
143 struct smu_state_validation_block validation;
144 struct smu_state_pcie_block pcie;
145 struct smu_state_display_block display;
146 struct smu_state_memroy_block memory;
147 struct smu_temperature_range temperatures;
148 struct smu_state_software_algorithm_block software;
149 struct smu_uvd_clocks uvd_clocks;
150 struct smu_hw_power_state hardware;
151};
152
64136ea6
KW		 153enum smu_message_type
154{
155 SMU_MSG_TestMessage = 0,
156 SMU_MSG_GetSmuVersion,
157 SMU_MSG_GetDriverIfVersion,
158 SMU_MSG_SetAllowedFeaturesMaskLow,
159 SMU_MSG_SetAllowedFeaturesMaskHigh,
160 SMU_MSG_EnableAllSmuFeatures,
161 SMU_MSG_DisableAllSmuFeatures,
162 SMU_MSG_EnableSmuFeaturesLow,
163 SMU_MSG_EnableSmuFeaturesHigh,
164 SMU_MSG_DisableSmuFeaturesLow,
165 SMU_MSG_DisableSmuFeaturesHigh,
166 SMU_MSG_GetEnabledSmuFeaturesLow,
167 SMU_MSG_GetEnabledSmuFeaturesHigh,
168 SMU_MSG_SetWorkloadMask,
169 SMU_MSG_SetPptLimit,
170 SMU_MSG_SetDriverDramAddrHigh,
171 SMU_MSG_SetDriverDramAddrLow,
172 SMU_MSG_SetToolsDramAddrHigh,
173 SMU_MSG_SetToolsDramAddrLow,
174 SMU_MSG_TransferTableSmu2Dram,
175 SMU_MSG_TransferTableDram2Smu,
176 SMU_MSG_UseDefaultPPTable,
177 SMU_MSG_UseBackupPPTable,
178 SMU_MSG_RunBtc,
179 SMU_MSG_RequestI2CBus,
180 SMU_MSG_ReleaseI2CBus,
181 SMU_MSG_SetFloorSocVoltage,
182 SMU_MSG_SoftReset,
183 SMU_MSG_StartBacoMonitor,
184 SMU_MSG_CancelBacoMonitor,
185 SMU_MSG_EnterBaco,
186 SMU_MSG_SetSoftMinByFreq,
187 SMU_MSG_SetSoftMaxByFreq,
188 SMU_MSG_SetHardMinByFreq,
189 SMU_MSG_SetHardMaxByFreq,
190 SMU_MSG_GetMinDpmFreq,
191 SMU_MSG_GetMaxDpmFreq,
192 SMU_MSG_GetDpmFreqByIndex,
193 SMU_MSG_GetDpmClockFreq,
194 SMU_MSG_GetSsVoltageByDpm,
195 SMU_MSG_SetMemoryChannelConfig,
196 SMU_MSG_SetGeminiMode,
197 SMU_MSG_SetGeminiApertureHigh,
198 SMU_MSG_SetGeminiApertureLow,
199 SMU_MSG_SetMinLinkDpmByIndex,
200 SMU_MSG_OverridePcieParameters,
201 SMU_MSG_OverDriveSetPercentage,
202 SMU_MSG_SetMinDeepSleepDcefclk,
203 SMU_MSG_ReenableAcDcInterrupt,
204 SMU_MSG_NotifyPowerSource,
205 SMU_MSG_SetUclkFastSwitch,
206 SMU_MSG_SetUclkDownHyst,
207 SMU_MSG_GfxDeviceDriverReset,
208 SMU_MSG_GetCurrentRpm,
209 SMU_MSG_SetVideoFps,
210 SMU_MSG_SetTjMax,
211 SMU_MSG_SetFanTemperatureTarget,
212 SMU_MSG_PrepareMp1ForUnload,
213 SMU_MSG_DramLogSetDramAddrHigh,
214 SMU_MSG_DramLogSetDramAddrLow,
215 SMU_MSG_DramLogSetDramSize,
216 SMU_MSG_SetFanMaxRpm,
217 SMU_MSG_SetFanMinPwm,
218 SMU_MSG_ConfigureGfxDidt,
219 SMU_MSG_NumOfDisplays,
220 SMU_MSG_RemoveMargins,
221 SMU_MSG_ReadSerialNumTop32,
222 SMU_MSG_ReadSerialNumBottom32,
223 SMU_MSG_SetSystemVirtualDramAddrHigh,
224 SMU_MSG_SetSystemVirtualDramAddrLow,
225 SMU_MSG_WaflTest,
226 SMU_MSG_SetFclkGfxClkRatio,
227 SMU_MSG_AllowGfxOff,
228 SMU_MSG_DisallowGfxOff,
229 SMU_MSG_GetPptLimit,
230 SMU_MSG_GetDcModeMaxDpmFreq,
231 SMU_MSG_GetDebugData,
232 SMU_MSG_SetXgmiMode,
233 SMU_MSG_RunAfllBtc,
234 SMU_MSG_ExitBaco,
235 SMU_MSG_PrepareMp1ForReset,
236 SMU_MSG_PrepareMp1ForShutdown,
237 SMU_MSG_SetMGpuFanBoostLimitRpm,
238 SMU_MSG_GetAVFSVoltageByDpm,
a8179d62
KF		 239 SMU_MSG_PowerUpVcn,
240 SMU_MSG_PowerDownVcn,
241 SMU_MSG_PowerUpJpeg,
242 SMU_MSG_PowerDownJpeg,
26e2b581 243 SMU_MSG_BacoAudioD3PME,
767acabd 244 SMU_MSG_ArmD3,
64136ea6
KW		 245 SMU_MSG_MAX_COUNT,
246};
247
0de94acf
HR		 248enum smu_clk_type
249{
250 SMU_GFXCLK,
251 SMU_VCLK,
252 SMU_DCLK,
253 SMU_ECLK,
254 SMU_SOCCLK,
255 SMU_UCLK,
256 SMU_DCEFCLK,
257 SMU_DISPCLK,
258 SMU_PIXCLK,
259 SMU_PHYCLK,
260 SMU_FCLK,
b1e7e224
KW		 261 SMU_SCLK,
262 SMU_MCLK,
263 SMU_PCIE,
264 SMU_OD_SCLK,
265 SMU_OD_MCLK,
266 SMU_OD_VDDC_CURVE,
267 SMU_OD_RANGE,
0de94acf
HR		 268 SMU_CLK_COUNT,
269};
270
8890fe5f
HR		 271enum smu_power_src_type
272{
273 SMU_POWER_SOURCE_AC,
274 SMU_POWER_SOURCE_DC,
275 SMU_POWER_SOURCE_COUNT,
276};
277
ffcb08df
HR		 278enum smu_feature_mask
279{
280 SMU_FEATURE_DPM_PREFETCHER_BIT,
281 SMU_FEATURE_DPM_GFXCLK_BIT,
282 SMU_FEATURE_DPM_UCLK_BIT,
283 SMU_FEATURE_DPM_SOCCLK_BIT,
284 SMU_FEATURE_DPM_UVD_BIT,
285 SMU_FEATURE_DPM_VCE_BIT,
286 SMU_FEATURE_ULV_BIT,
287 SMU_FEATURE_DPM_MP0CLK_BIT,
288 SMU_FEATURE_DPM_LINK_BIT,
289 SMU_FEATURE_DPM_DCEFCLK_BIT,
290 SMU_FEATURE_DS_GFXCLK_BIT,
291 SMU_FEATURE_DS_SOCCLK_BIT,
292 SMU_FEATURE_DS_LCLK_BIT,
293 SMU_FEATURE_PPT_BIT,
294 SMU_FEATURE_TDC_BIT,
295 SMU_FEATURE_THERMAL_BIT,
296 SMU_FEATURE_GFX_PER_CU_CG_BIT,
297 SMU_FEATURE_RM_BIT,
298 SMU_FEATURE_DS_DCEFCLK_BIT,
299 SMU_FEATURE_ACDC_BIT,
300 SMU_FEATURE_VR0HOT_BIT,
301 SMU_FEATURE_VR1HOT_BIT,
302 SMU_FEATURE_FW_CTF_BIT,
303 SMU_FEATURE_LED_DISPLAY_BIT,
304 SMU_FEATURE_FAN_CONTROL_BIT,
305 SMU_FEATURE_GFX_EDC_BIT,
306 SMU_FEATURE_GFXOFF_BIT,
307 SMU_FEATURE_CG_BIT,
308 SMU_FEATURE_DPM_FCLK_BIT,
309 SMU_FEATURE_DS_FCLK_BIT,
310 SMU_FEATURE_DS_MP1CLK_BIT,
311 SMU_FEATURE_DS_MP0CLK_BIT,
312 SMU_FEATURE_XGMI_BIT,
313 SMU_FEATURE_DPM_GFX_PACE_BIT,
314 SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
315 SMU_FEATURE_MEM_MVDD_SCALING_BIT,
316 SMU_FEATURE_DS_UCLK_BIT,
317 SMU_FEATURE_GFX_ULV_BIT,
318 SMU_FEATURE_FW_DSTATE_BIT,
319 SMU_FEATURE_BACO_BIT,
320 SMU_FEATURE_VCN_PG_BIT,
321 SMU_FEATURE_JPEG_PG_BIT,
322 SMU_FEATURE_USB_PG_BIT,
323 SMU_FEATURE_RSMU_SMN_CG_BIT,
324 SMU_FEATURE_APCC_PLUS_BIT,
325 SMU_FEATURE_GTHR_BIT,
326 SMU_FEATURE_GFX_DCS_BIT,
327 SMU_FEATURE_GFX_SS_BIT,
328 SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
329 SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
330 SMU_FEATURE_MMHUB_PG_BIT,
331 SMU_FEATURE_ATHUB_PG_BIT,
332 SMU_FEATURE_COUNT,
333};
334
0b51d993
KW		 335enum smu_memory_pool_size
336{
337 SMU_MEMORY_POOL_SIZE_ZERO = 0,
338 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
339 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
340 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
341 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
342};
343
813ce279
KW		 344#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
345 do { \
346 tables[table_id].size = s; \
347 tables[table_id].align = a; \
348 tables[table_id].domain = d; \
349 } while (0)
350
351struct smu_table {
352 uint64_t size;
353 uint32_t align;
354 uint8_t domain;
355 uint64_t mc_address;
356 void *cpu_addr;
357 struct amdgpu_bo *bo;
e98499b4 358};
813ce279 359
64461900
HR		 360enum smu_perf_level_designation {
361 PERF_LEVEL_ACTIVITY,
362 PERF_LEVEL_POWER_CONTAINMENT,
363};
364
365struct smu_performance_level {
366 uint32_t core_clock;
367 uint32_t memory_clock;
368 uint32_t vddc;
369 uint32_t vddci;
370 uint32_t non_local_mem_freq;
371 uint32_t non_local_mem_width;
372};
373
8021816c
HR		 374struct smu_clock_info {
375 uint32_t min_mem_clk;
376 uint32_t max_mem_clk;
377 uint32_t min_eng_clk;
378 uint32_t max_eng_clk;
379 uint32_t min_bus_bandwidth;
380 uint32_t max_bus_bandwidth;
381};
382
e98499b4
HR		 383struct smu_bios_boot_up_values
384{
385 uint32_t revision;
386 uint32_t gfxclk;
387 uint32_t uclk;
388 uint32_t socclk;
389 uint32_t dcefclk;
83e21f57
LG		 390 uint32_t eclk;
391 uint32_t vclk;
392 uint32_t dclk;
e98499b4
HR		 393 uint16_t vddc;
394 uint16_t vddci;
395 uint16_t mvddc;
396 uint16_t vdd_gfx;
397 uint8_t cooling_id;
398 uint32_t pp_table_id;
813ce279
KW		 399};
400
2436911b
HR		 401enum smu_table_id
402{
403 SMU_TABLE_PPTABLE = 0,
404 SMU_TABLE_WATERMARKS,
405 SMU_TABLE_AVFS,
406 SMU_TABLE_AVFS_PSM_DEBUG,
407 SMU_TABLE_AVFS_FUSE_OVERRIDE,
408 SMU_TABLE_PMSTATUSLOG,
409 SMU_TABLE_SMU_METRICS,
410 SMU_TABLE_DRIVER_SMU_CONFIG,
411 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
412 SMU_TABLE_OVERDRIVE,
413 SMU_TABLE_I2C_COMMANDS,
414 SMU_TABLE_PACE,
415 SMU_TABLE_COUNT,
416};
417
2cf543ed
HR		 418struct smu_table_context
419{
420 void *power_play_table;
421 uint32_t power_play_table_size;
289921b0 422 void *hardcode_pptable;
62b9a88c
KW		 423 unsigned long metrics_time;
424 void *metrics_table;
e98499b4 425
7457cf02 426 void *max_sustainable_clocks;
e98499b4 427 struct smu_bios_boot_up_values boot_values;
3e333c6c 428 void *driver_pptable;
813ce279
KW		 429 struct smu_table *tables;
430 uint32_t table_count;
0b51d993 431 struct smu_table memory_pool;
74ba3553 432 uint8_t thermal_controller_type;
07740adc 433 uint16_t TDPODLimit;
b55ca3bd 434
2c80abe3 435 void *overdrive_table;
2cf543ed
HR		 436};
437
142dec62 438struct smu_dpm_context {
142dec62 439 uint32_t dpm_context_size;
95add959
LG		 440 void *dpm_context;
441 void *golden_dpm_context;
49d27e91
CG		 442 bool enable_umd_pstate;
443 enum amd_dpm_forced_level dpm_level;
444 enum amd_dpm_forced_level saved_dpm_level;
445 enum amd_dpm_forced_level requested_dpm_level;
8554e67d
CG		 446 struct smu_power_state *dpm_request_power_state;
447 struct smu_power_state *dpm_current_power_state;
b3c139d5 448 struct mclock_latency_table *mclk_latency_table;
142dec62
KW		 449};
450
162aa5c3
KF		 451struct smu_power_gate {
452 bool uvd_gated;
453 bool vce_gated;
b8870118 454 bool vcn_gated;
162aa5c3
KF		 455};
456
8bf16963
KW		 457struct smu_power_context {
458 void *power_context;
459 uint32_t power_context_size;
162aa5c3 460 struct smu_power_gate power_gate;
8bf16963
KW		 461};
462
6b816d73
KW		 463
464#define SMU_FEATURE_MAX (64)
465struct smu_feature
466{
467 uint32_t feature_num;
468 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
469 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
470 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
f14a323d 471 struct mutex mutex;
6b816d73
KW		 472};
473
b3c139d5
CG		 474struct smu_clocks {
475 uint32_t engine_clock;
476 uint32_t memory_clock;
477 uint32_t bus_bandwidth;
478 uint32_t engine_clock_in_sr;
479 uint32_t dcef_clock;
480 uint32_t dcef_clock_in_sr;
481};
482
483#define MAX_REGULAR_DPM_NUM 16
484struct mclk_latency_entries {
485 uint32_t frequency;
486 uint32_t latency;
487};
488struct mclock_latency_table {
489 uint32_t count;
490 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
491};
492
767acabd
KW		 493enum smu_baco_state
494{
495 SMU_BACO_STATE_ENTER = 0,
496 SMU_BACO_STATE_EXIT,
497};
498
499struct smu_baco_context
500{
501 struct mutex mutex;
502 uint32_t state;
503 bool platform_support;
504};
505
16177fd0 506#define WORKLOAD_POLICY_MAX 7
137d63ab
HR		 507struct smu_context
508{
509 struct amdgpu_device *adev;
5e6d2665 510 struct amdgpu_irq_src *irq_source;
137d63ab
HR		 511
512 const struct smu_funcs *funcs;
74e07f9d 513 const struct pptable_funcs *ppt_funcs;
137d63ab 514 struct mutex mutex;
0b51d993 515 uint64_t pool_size;
2cf543ed
HR		 516
517 struct smu_table_context smu_table;
142dec62 518 struct smu_dpm_context smu_dpm;
8bf16963 519 struct smu_power_context smu_power;
6b816d73 520 struct smu_feature smu_feature;
379a4454 521 struct amd_pp_display_configuration *display_config;
767acabd 522 struct smu_baco_context smu_baco;
0c83d32c 523 void *od_settings;
133438fa
LG		 524
525 uint32_t pstate_sclk;
526 uint32_t pstate_mclk;
e66adb1e 527
3b94fb10 528 bool od_enabled;
e66adb1e
LG		 529 uint32_t power_limit;
530 uint32_t default_power_limit;
5e2d3881 531
879af1c6
HR		 532 /* soft pptable */
533 uint32_t ppt_offset_bytes;
534 uint32_t ppt_size_bytes;
535 uint8_t *ppt_start_addr;
536
5e2d3881 537 bool support_power_containment;
2e069391
HR		 538 bool disable_watermark;
539
540#define WATERMARKS_EXIST (1 << 0)
541#define WATERMARKS_LOADED (1 << 1)
542 uint32_t watermarks_bitmap;
16177fd0
CG		 543
544 uint32_t workload_mask;
545 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
546 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
547 uint32_t power_profile_mode;
548 uint32_t default_power_profile_mode;
a254bfa2 549 bool pm_enabled;
1fb4f155
KW		 550
551 uint32_t smc_if_version;
1de888e8 552
137d63ab
HR		 553};
554
74e07f9d 555struct pptable_funcs {
d76c9e24 556 int (*alloc_dpm_context)(struct smu_context *smu);
74e07f9d 557 int (*store_powerplay_table)(struct smu_context *smu);
c6eef2d0 558 int (*check_powerplay_table)(struct smu_context *smu);
c5895273 559 int (*append_powerplay_table)(struct smu_context *smu);
78031c2c 560 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
0de94acf 561 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
ffcb08df 562 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
2436911b 563 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
8890fe5f 564 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
6c6187ec 565 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
f6a6b952 566 int (*run_afll_btc)(struct smu_context *smu);
74c958a3 567 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
8554e67d 568 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
d6a4aa82 569 int (*set_default_dpm_table)(struct smu_context *smu);
8554e67d 570 int (*set_power_state)(struct smu_context *smu);
133438fa 571 int (*populate_umd_state_clk)(struct smu_context *smu);
b1e7e224 572 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
db439ca2 573 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
2c80abe3 574 int (*set_default_od8_settings)(struct smu_context *smu);
c7a063a2 575 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
e9c5b46e 576 int (*set_od_percentage)(struct smu_context *smu,
c7a063a2 577 enum smu_clk_type clk_type,
e9c5b46e 578 uint32_t value);
e388cc47
LG		 579 int (*od_edit_dpm_table)(struct smu_context *smu,
580 enum PP_OD_DPM_TABLE_COMMAND type,
581 long *input, uint32_t size);
e5e4e223 582 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
a43913ea 583 enum smu_clk_type clk_type,
e5e4e223
HR		 584 struct
585 pp_clock_levels_with_latency
586 *clocks);
1e33d4d4
HR		 587 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
588 enum amd_pp_clock_type type,
589 struct
590 pp_clock_levels_with_voltage
591 *clocks);
16177fd0
CG		 592 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
593 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
86eb3ed3
KW		 594 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
595 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
6d22f1aa
KW		 596 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
597 void *data, uint32_t *size);
bc0fcffd
LG		 598 int (*pre_display_config_changed)(struct smu_context *smu);
599 int (*display_config_changed)(struct smu_context *smu);
600 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
601 int (*notify_smc_dispaly_config)(struct smu_context *smu);
602 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
4b77faaf 603 int (*unforce_dpm_levels)(struct smu_context *smu);
bc0fcffd
LG		 604 int (*get_profiling_clk_mask)(struct smu_context *smu,
605 enum amd_dpm_forced_level level,
606 uint32_t *sclk_mask,
607 uint32_t *mclk_mask,
608 uint32_t *soc_mask);
609 int (*set_cpu_power_state)(struct smu_context *smu);
fe75a323
EQ		 610 int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
611 int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
e1798053 612 bool (*is_dpm_running)(struct smu_context *smu);
62b9a88c 613 int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
ee0db820
HR		 614 int (*set_thermal_fan_table)(struct smu_context *smu);
615 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
1bcff326 616 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
97384904
HR		 617 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
618 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
98e1a543
KW		 619 int (*get_current_clk_freq_by_table)(struct smu_context *smu,
620 enum smu_clk_type clk_type,
621 uint32_t *value);
e211580d 622 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
f4b3295f 623 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
8f30a16d 624 int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
b840e4d5 625 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
74e07f9d
HR		 626};
627
137d63ab
HR		 628struct smu_funcs
629{
630 int (*init_microcode)(struct smu_context *smu);
cabd44c0 631 int (*init_smc_tables)(struct smu_context *smu);
813ce279 632 int (*fini_smc_tables)(struct smu_context *smu);
17e6081b 633 int (*init_power)(struct smu_context *smu);
8bf16963 634 int (*fini_power)(struct smu_context *smu);
3d2f5200 635 int (*load_microcode)(struct smu_context *smu);
e11c4fd5 636 int (*check_fw_status)(struct smu_context *smu);
b55c83a7 637 int (*setup_pptable)(struct smu_context *smu);
a6b35900 638 int (*get_vbios_bootup_values)(struct smu_context *smu);
08115f87 639 int (*get_clk_info_from_vbios)(struct smu_context *smu);
46126e6d 640 int (*check_pptable)(struct smu_context *smu);
9e4848a4 641 int (*parse_pptable)(struct smu_context *smu);
86187fec 642 int (*populate_smc_pptable)(struct smu_context *smu);
a751b095 643 int (*check_fw_version)(struct smu_context *smu);
31b5ae49 644 int (*write_pptable)(struct smu_context *smu);
a7ebb6d2 645 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
206bc589 646 int (*set_tool_table_location)(struct smu_context *smu);
c56de9e8 647 int (*notify_memory_pool_location)(struct smu_context *smu);
38f8a2e6
HR		 648 int (*write_watermarks_table)(struct smu_context *smu);
649 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
650 int (*system_features_control)(struct smu_context *smu, bool en);
b0b4b413
KW		 651 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
652 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
00bfaec8 653 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
2e13c755 654 int (*init_display_count)(struct smu_context *smu, uint32_t count);
6b816d73
KW		 655 int (*set_allowed_mask)(struct smu_context *smu);
656 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
f14a323d 657 int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
e1c6f86a 658 int (*notify_display_change)(struct smu_context *smu);
014c4440
CG		 659 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
660 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
0de94acf 661 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
7457cf02 662 int (*init_max_sustainable_clocks)(struct smu_context *smu);
74ba3553 663 int (*start_thermal_control)(struct smu_context *smu);
4a5a2de6
KW		 664 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
665 void *data, uint32_t *size);
e73cf108 666 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
44dd54ee
HR		 667 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
668 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
669 bool cc6_disable, bool pstate_disable,
670 bool pstate_switch_disable);
b3ea88fe
HR		 671 int (*get_clock_by_type)(struct smu_context *smu,
672 enum amd_pp_clock_type type,
673 struct amd_pp_clocks *clocks);
6ec82684
HR		 674 int (*get_max_high_clocks)(struct smu_context *smu,
675 struct amd_pp_simple_clock_info *clocks);
04885368
HR		 676 int (*display_clock_voltage_request)(struct smu_context *smu, struct
677 pp_display_clock_request
678 *clock_req);
98a64c15
HR		 679 int (*get_dal_power_level)(struct smu_context *smu,
680 struct amd_pp_simple_clock_info *clocks);
64461900
HR		 681 int (*get_perf_level)(struct smu_context *smu,
682 enum smu_perf_level_designation designation,
683 struct smu_performance_level *level);
8021816c
HR		 684 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
685 struct smu_clock_info *clocks);
367eeed4 686 int (*notify_smu_enable_pwe)(struct smu_context *smu);
2e069391
HR		 687 int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
688 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
16177fd0 689 int (*conv_power_profile_to_pplib_workload)(int power_profile);
008a9524 690 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
a76ff5af 691 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
008a9524 692 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
96026ce0 693 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
e911671c 694 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
bca32528 695 int (*gfx_off_control)(struct smu_context *smu, bool enable);
5e6d2665 696 int (*register_irq_handler)(struct smu_context *smu);
26e2b581 697 int (*set_azalia_d3_pme)(struct smu_context *smu);
a18bf0ca 698 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
767acabd
KW		 699 bool (*baco_is_support)(struct smu_context *smu);
700 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
701 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
702 int (*baco_reset)(struct smu_context *smu);
703
137d63ab
HR		 704};
705
706#define smu_init_microcode(smu) \
707 ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
cabd44c0
HR		 708#define smu_init_smc_tables(smu) \
709 ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
813ce279
KW		 710#define smu_fini_smc_tables(smu) \
711 ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
17e6081b
HR		 712#define smu_init_power(smu) \
713 ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
8bf16963
KW		 714#define smu_fini_power(smu) \
715 ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
3d2f5200
HR		 716#define smu_load_microcode(smu) \
717 ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
e11c4fd5
HR		 718#define smu_check_fw_status(smu) \
719 ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
b55c83a7
KW		 720#define smu_setup_pptable(smu) \
721 ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
a6b35900
HR		 722#define smu_get_vbios_bootup_values(smu) \
723 ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
08115f87
HR		 724#define smu_get_clk_info_from_vbios(smu) \
725 ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
46126e6d
HR		 726#define smu_check_pptable(smu) \
727 ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
9e4848a4
HR		 728#define smu_parse_pptable(smu) \
729 ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
86187fec
HR		 730#define smu_populate_smc_pptable(smu) \
731 ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
a751b095
HR		 732#define smu_check_fw_version(smu) \
733 ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
31b5ae49
HR		 734#define smu_write_pptable(smu) \
735 ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
a7ebb6d2
HR		 736#define smu_set_min_dcef_deep_sleep(smu) \
737 ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
206bc589
HR		 738#define smu_set_tool_table_location(smu) \
739 ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
c56de9e8
HR		 740#define smu_notify_memory_pool_location(smu) \
741 ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
bca32528
KF		 742#define smu_gfx_off_control(smu, enable) \
743 ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
744
38f8a2e6
HR		 745#define smu_write_watermarks_table(smu) \
746 ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
747#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
748 ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
749#define smu_system_features_control(smu, en) \
750 ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
7457cf02
HR		 751#define smu_init_max_sustainable_clocks(smu) \
752 ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
8f30a16d
KW		 753#define smu_set_default_od_settings(smu, initialize) \
754 ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
96026ce0
LG		 755#define smu_set_fan_speed_rpm(smu, speed) \
756 ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
b0b4b413
KW		 757#define smu_send_smc_msg(smu, msg) \
758 ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
759#define smu_send_smc_msg_with_param(smu, msg, param) \
760 ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
00bfaec8
LG		 761#define smu_read_smc_arg(smu, arg) \
762 ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
d76c9e24
LG		 763#define smu_alloc_dpm_context(smu) \
764 ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
2e13c755 765#define smu_init_display_count(smu, count) \
766 ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
6b816d73
KW		 767#define smu_feature_set_allowed_mask(smu) \
768 ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
769#define smu_feature_get_enabled_mask(smu, mask, num) \
770 ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
9ebbc1bb 771#define smu_is_dpm_running(smu) \
e1798053 772 ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
f14a323d
KW		 773#define smu_feature_update_enable_state(smu, feature_id, enabled) \
774 ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
e1c6f86a
KW		 775#define smu_notify_display_change(smu) \
776 ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
3e333c6c
LG		 777#define smu_store_powerplay_table(smu) \
778 ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
c6eef2d0
LG		 779#define smu_check_powerplay_table(smu) \
780 ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
c5895273
HR		 781#define smu_append_powerplay_table(smu) \
782 ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
d6a4aa82
LG		 783#define smu_set_default_dpm_table(smu) \
784 ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
133438fa
LG		 785#define smu_populate_umd_state_clk(smu) \
786 ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
2c80abe3
LG		 787#define smu_set_default_od8_settings(smu) \
788 ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
014c4440
CG		 789#define smu_get_power_limit(smu, limit, def) \
790 ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
791#define smu_set_power_limit(smu, limit) \
792 ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
bed3b3a1
KW		 793#define smu_get_current_clk_freq(smu, clk_id, value) \
794 ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
b1e7e224
KW		 795#define smu_print_clk_levels(smu, clk_type, buf) \
796 ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
db439ca2
KW		 797#define smu_force_clk_levels(smu, clk_type, level) \
798 ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
6d7c8302
LG		 799#define smu_get_od_percentage(smu, type) \
800 ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
e9c5b46e
LG		 801#define smu_set_od_percentage(smu, type, value) \
802 ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
e388cc47
LG		 803#define smu_od_edit_dpm_table(smu, type, input, size) \
804 ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
22c9c6ca
HR		 805#define smu_tables_init(smu, tab) \
806 ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
ee0db820
HR		 807#define smu_set_thermal_fan_table(smu) \
808 ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
74ba3553
LG		 809#define smu_start_thermal_control(smu) \
810 ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
4a5a2de6
KW		 811#define smu_read_sensor(smu, sensor, data, size) \
812 ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
6d22f1aa
KW		 813#define smu_asic_read_sensor(smu, sensor, data, size) \
814 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
16177fd0 815#define smu_get_power_profile_mode(smu, buf) \
667273c1 816 ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
16177fd0 817#define smu_set_power_profile_mode(smu, param, param_size) \
667273c1 818 ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
bc0fcffd
LG		 819#define smu_pre_display_config_changed(smu) \
820 ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
821#define smu_display_config_changed(smu) \
822 ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
823#define smu_apply_clocks_adjust_rules(smu) \
824 ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
825#define smu_notify_smc_dispaly_config(smu) \
826 ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
827#define smu_force_dpm_limit_value(smu, highest) \
828 ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
4b77faaf
LG		 829#define smu_unforce_dpm_levels(smu) \
830 ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
bc0fcffd
LG		 831#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
832 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
833#define smu_set_cpu_power_state(smu) \
834 ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
008a9524
CG		 835#define smu_get_fan_control_mode(smu) \
836 ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
a76ff5af
CG		 837#define smu_set_fan_control_mode(smu, value) \
838 ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
008a9524 839#define smu_get_fan_speed_percent(smu, speed) \
ee0db820 840 ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
008a9524
CG		 841#define smu_set_fan_speed_percent(smu, speed) \
842 ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
1bcff326
AD		 843#define smu_get_fan_speed_rpm(smu, speed) \
844 ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
137d63ab 845
78031c2c
KW		 846#define smu_msg_get_index(smu, msg) \
847 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
0de94acf
HR		 848#define smu_clk_get_index(smu, msg) \
849 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
ffcb08df
HR		 850#define smu_feature_get_index(smu, msg) \
851 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
2436911b
HR		 852#define smu_table_get_index(smu, tab) \
853 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
8890fe5f
HR		 854#define smu_power_get_index(smu, src) \
855 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
6c6187ec
KW		 856#define smu_workload_get_type(smu, profile) \
857 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
f6a6b952
KW		 858#define smu_run_afll_btc(smu) \
859 ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
74c958a3
KW		 860#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
861 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
e73cf108
HR		 862#define smu_set_deep_sleep_dcefclk(smu, clk) \
863 ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
44dd54ee
HR		 864#define smu_set_active_display_count(smu, count) \
865 ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
866#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
867 ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
b3ea88fe
HR		 868#define smu_get_clock_by_type(smu, type, clocks) \
869 ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
6ec82684
HR		 870#define smu_get_max_high_clocks(smu, clocks) \
871 ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
a43913ea
KW		 872#define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
873 ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
1e33d4d4
HR		 874#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
875 ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
04885368
HR		 876#define smu_display_clock_voltage_request(smu, clock_req) \
877 ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
98a64c15
HR		 878#define smu_get_dal_power_level(smu, clocks) \
879 ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
64461900
HR		 880#define smu_get_perf_level(smu, designation, level) \
881 ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
8021816c
HR		 882#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
883 ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
367eeed4
HR		 884#define smu_notify_smu_enable_pwe(smu) \
885 ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
2e069391
HR		 886#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
887 ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
d57a87ad 888#define smu_dpm_set_uvd_enable(smu, enable) \
86eb3ed3 889 ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
d57a87ad 890#define smu_dpm_set_vce_enable(smu, enable) \
86eb3ed3 891 ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
e911671c 892#define smu_set_xgmi_pstate(smu, pstate) \
893 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
fe75a323
EQ		 894#define smu_set_ppfeature_status(smu, ppfeatures) \
895 ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
896#define smu_get_ppfeature_status(smu, buf) \
897 ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
97384904
HR		 898#define smu_set_watermarks_table(smu, tab, clock_ranges) \
899 ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
98e1a543
KW		 900#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
901 ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
be9a7355 902#define smu_thermal_temperature_range_update(smu, range, rw) \
903 ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
e211580d
HZ		 904#define smu_get_thermal_temperature_range(smu, range) \
905 ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
5e6d2665
KW		 906#define smu_register_irq_handler(smu) \
907 ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
26e2b581 908#define smu_set_azalia_d3_pme(smu) \
909 ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
f4b3295f 910#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
911 ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
a18bf0ca 912#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
913 ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
be9a7355 914#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
915 ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
767acabd
KW		 916#define smu_baco_is_support(smu) \
917 ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
918#define smu_baco_get_state(smu, state) \
919 ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
920#define smu_baco_reset(smu) \
921 ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
b840e4d5
KW		 922#define smu_asic_set_performance_level(smu, level) \
923 ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
924
78031c2c 925
e15da5a4
HR		 926extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
927 uint16_t *size, uint8_t *frev, uint8_t *crev,
928 uint8_t **addr);
929
137d63ab
HR		 930extern const struct amd_ip_funcs smu_ip_funcs;
931
07845526 932extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
6b816d73 933extern int smu_feature_init_dpm(struct smu_context *smu);
07845526 934
ffcb08df
HR		 935extern int smu_feature_is_enabled(struct smu_context *smu,
936 enum smu_feature_mask mask);
937extern int smu_feature_set_enabled(struct smu_context *smu,
938 enum smu_feature_mask mask, bool enable);
939extern int smu_feature_is_supported(struct smu_context *smu,
940 enum smu_feature_mask mask);
941extern int smu_feature_set_supported(struct smu_context *smu,
942 enum smu_feature_mask mask, bool enable);
2f25158d 943
0d9d78b5 944int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
dbe6a970 945 void *table_data, bool drv2smu);
4825d8d6 946
dc8e3a0c 947bool is_support_sw_smu(struct amdgpu_device *adev);
289921b0 948int smu_reset(struct smu_context *smu);
143c75d6
KW		 949int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
950 void *data, uint32_t *size);
289921b0
KW		 951int smu_sys_get_pp_table(struct smu_context *smu, void **table);
952int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
09895323 953int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
ea2d0bf8 954enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
dbe6a970 955
94ed6d0c
HR		 956/* smu to display interface */
957extern int smu_display_configuration_change(struct smu_context *smu, const
958 struct amd_pp_display_configuration
959 *display_config);
5e2d3881
HR		 960extern int smu_get_current_clocks(struct smu_context *smu,
961 struct amd_pp_clock_info *clocks);
72e91f37 962extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
bc0fcffd
LG		 963extern int smu_handle_task(struct smu_context *smu,
964 enum amd_dpm_forced_level level,
965 enum amd_pp_task task_id);
4fde03a7 966int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
3ac54a50
KW		 967int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
968 uint16_t level, uint32_t *value);
969int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
970 uint32_t *value);
8b3d243e
KW		 971int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
972 uint32_t *min, uint32_t *max);
0d7cbd28
KW		 973int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
974 uint32_t min, uint32_t max);
33665617
KW		 975int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
976 uint32_t min, uint32_t max);
a38470f0
KW		 977enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
978int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
2e13c755 979int smu_set_display_count(struct smu_context *smu, uint32_t count);
54728170 980bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
2e13c755 981
137d63ab 982#endif
Linux 6.x block layer and io_uring tree(s)