[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / inc / amd_powerplay.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _AMD_POWERPLAY_H_
#define _AMD_POWERPLAY_H_

#include <linux/seq_file.h>
#include <linux/types.h>
#include <linux/errno.h>
#include "amd_shared.h"
#include "cgs_common.h"
#include "dm_pp_interface.h"

extern const struct amd_ip_funcs pp_ip_funcs;
extern const struct amd_pm_funcs pp_dpm_funcs;

#define PP_DPM_DISABLED 0xCCCC

enum amd_pp_sensors {
	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
	AMDGPU_PP_SENSOR_VDDNB,
	AMDGPU_PP_SENSOR_VDDGFX,
	AMDGPU_PP_SENSOR_UVD_VCLK,
	AMDGPU_PP_SENSOR_UVD_DCLK,
	AMDGPU_PP_SENSOR_VCE_ECCLK,
	AMDGPU_PP_SENSOR_GPU_LOAD,
	AMDGPU_PP_SENSOR_GFX_MCLK,
	AMDGPU_PP_SENSOR_GPU_TEMP,
	AMDGPU_PP_SENSOR_VCE_POWER,
	AMDGPU_PP_SENSOR_UVD_POWER,
	AMDGPU_PP_SENSOR_GPU_POWER,
};

enum amd_pp_task {
	AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
	AMD_PP_TASK_ENABLE_USER_STATE,
	AMD_PP_TASK_READJUST_POWER_STATE,
	AMD_PP_TASK_COMPLETE_INIT,
	AMD_PP_TASK_MAX
};

struct amd_pp_init {
	struct cgs_device *device;
	uint32_t chip_family;
	uint32_t chip_id;
	bool pm_en;
	uint32_t feature_mask;
};

enum amd_pp_display_config_type{
	AMD_PP_DisplayConfigType_None = 0,
	AMD_PP_DisplayConfigType_DP54 ,
	AMD_PP_DisplayConfigType_DP432 ,
	AMD_PP_DisplayConfigType_DP324 ,
	AMD_PP_DisplayConfigType_DP27,
	AMD_PP_DisplayConfigType_DP243,
	AMD_PP_DisplayConfigType_DP216,
	AMD_PP_DisplayConfigType_DP162,
	AMD_PP_DisplayConfigType_HDMI6G ,
	AMD_PP_DisplayConfigType_HDMI297 ,
	AMD_PP_DisplayConfigType_HDMI162,
	AMD_PP_DisplayConfigType_LVDS,
	AMD_PP_DisplayConfigType_DVI,
	AMD_PP_DisplayConfigType_WIRELESS,
	AMD_PP_DisplayConfigType_VGA
};

struct single_display_configuration
{
	uint32_t controller_index;
	uint32_t controller_id;
	uint32_t signal_type;
	uint32_t display_state;
	/* phy id for the primary internal transmitter */
	uint8_t primary_transmitter_phyi_d;
	/* bitmap with the active lanes */
	uint8_t primary_transmitter_active_lanemap;
	/* phy id for the secondary internal transmitter (for dual-link dvi) */
	uint8_t secondary_transmitter_phy_id;
	/* bitmap with the active lanes */
	uint8_t secondary_transmitter_active_lanemap;
	/* misc phy settings for SMU. */
	uint32_t config_flags;
	uint32_t display_type;
	uint32_t view_resolution_cx;
	uint32_t view_resolution_cy;
	enum amd_pp_display_config_type displayconfigtype;
	uint32_t vertical_refresh; /* for active display */
};

#define MAX_NUM_DISPLAY 32

struct amd_pp_display_configuration {
	bool nb_pstate_switch_disable;/* controls NB PState switch */
	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
	bool cpu_pstate_disable;
	uint32_t cpu_pstate_separation_time;

	uint32_t num_display;  /* total number of display*/
	uint32_t num_path_including_non_display;
	uint32_t crossfire_display_index;
	uint32_t min_mem_set_clock;
	uint32_t min_core_set_clock;
	/* unit 10KHz x bit*/
	uint32_t min_bus_bandwidth;
	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
	uint32_t min_core_set_clock_in_sr;

	struct single_display_configuration displays[MAX_NUM_DISPLAY];

	uint32_t vrefresh; /* for active display*/

	uint32_t min_vblank_time; /* for active display*/
	bool multi_monitor_in_sync;
	/* Controller Index of primary display - used in MCLK SMC switching hang
	 * SW Workaround*/
	uint32_t crtc_index;
	/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
	uint32_t line_time_in_us;
	bool invalid_vblank_time;

	uint32_t display_clk;
	/*
	 * for given display configuration if multimonitormnsync == false then
	 * Memory clock DPMS with this latency or below is allowed, DPMS with
	 * higher latency not allowed.
	 */
	uint32_t dce_tolerable_mclk_in_active_latency;
	uint32_t min_dcef_set_clk;
	uint32_t min_dcef_deep_sleep_set_clk;
};

struct amd_pp_simple_clock_info {
	uint32_t	engine_max_clock;
	uint32_t	memory_max_clock;
	uint32_t	level;
};

enum PP_DAL_POWERLEVEL {
	PP_DAL_POWERLEVEL_INVALID = 0,
	PP_DAL_POWERLEVEL_ULTRALOW,
	PP_DAL_POWERLEVEL_LOW,
	PP_DAL_POWERLEVEL_NOMINAL,
	PP_DAL_POWERLEVEL_PERFORMANCE,

	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
};

struct amd_pp_clock_info {
	uint32_t min_engine_clock;
	uint32_t max_engine_clock;
	uint32_t min_memory_clock;
	uint32_t max_memory_clock;
	uint32_t min_bus_bandwidth;
	uint32_t max_bus_bandwidth;
	uint32_t max_engine_clock_in_sr;
	uint32_t min_engine_clock_in_sr;
	enum PP_DAL_POWERLEVEL max_clocks_state;
};

enum amd_pp_clock_type {
	amd_pp_disp_clock = 1,
	amd_pp_sys_clock,
	amd_pp_mem_clock,
	amd_pp_dcef_clock,
	amd_pp_soc_clock,
	amd_pp_pixel_clock,
	amd_pp_phy_clock,
	amd_pp_dcf_clock,
	amd_pp_dpp_clock,
	amd_pp_f_clock = amd_pp_dcef_clock,
};

#define MAX_NUM_CLOCKS 16

struct amd_pp_clocks {
	uint32_t count;
	uint32_t clock[MAX_NUM_CLOCKS];
	uint32_t latency[MAX_NUM_CLOCKS];
};


enum {
	PP_GROUP_UNKNOWN = 0,
	PP_GROUP_GFX = 1,
	PP_GROUP_SYS,
	PP_GROUP_MAX
};

struct pp_states_info {
	uint32_t nums;
	uint32_t states[16];
};

struct pp_gpu_power {
	uint32_t vddc_power;
	uint32_t vddci_power;
	uint32_t max_gpu_power;
	uint32_t average_gpu_power;
};

struct pp_display_clock_request {
	enum amd_pp_clock_type clock_type;
	uint32_t clock_freq_in_khz;
};

#define PP_GROUP_MASK        0xF0000000
#define PP_GROUP_SHIFT       28

#define PP_BLOCK_MASK        0x0FFFFF00
#define PP_BLOCK_SHIFT       8

#define PP_BLOCK_GFX_CG         0x01
#define PP_BLOCK_GFX_MG         0x02
#define PP_BLOCK_GFX_3D         0x04
#define PP_BLOCK_GFX_RLC        0x08
#define PP_BLOCK_GFX_CP         0x10
#define PP_BLOCK_SYS_BIF        0x01
#define PP_BLOCK_SYS_MC         0x02
#define PP_BLOCK_SYS_ROM        0x04
#define PP_BLOCK_SYS_DRM        0x08
#define PP_BLOCK_SYS_HDP        0x10
#define PP_BLOCK_SYS_SDMA       0x20

#define PP_STATE_MASK           0x0000000F
#define PP_STATE_SHIFT          0
#define PP_STATE_SUPPORT_MASK   0x000000F0
#define PP_STATE_SUPPORT_SHIFT  0

#define PP_STATE_CG             0x01
#define PP_STATE_LS             0x02
#define PP_STATE_DS             0x04
#define PP_STATE_SD             0x08
#define PP_STATE_SUPPORT_CG     0x10
#define PP_STATE_SUPPORT_LS     0x20
#define PP_STATE_SUPPORT_DS     0x40
#define PP_STATE_SUPPORT_SD     0x80

#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
								block << PP_BLOCK_SHIFT |\
								support << PP_STATE_SUPPORT_SHIFT |\
								state << PP_STATE_SHIFT)

struct amd_powerplay {
	struct cgs_device *cgs_device;
	void *pp_handle;
	const struct amd_ip_funcs *ip_funcs;
	const struct amd_pm_funcs *pp_funcs;
};

int amd_powerplay_create(struct amd_pp_init *pp_init,
				void **handle);

int amd_powerplay_destroy(void *handle);

int amd_powerplay_reset(void *handle);

int amd_powerplay_display_configuration_change(void *handle,
		const struct amd_pp_display_configuration *input);

int amd_powerplay_get_display_power_level(void *handle,
		struct amd_pp_simple_clock_info *output);

int amd_powerplay_get_current_clocks(void *handle,
		struct amd_pp_clock_info *output);

int amd_powerplay_get_clock_by_type(void *handle,
		enum amd_pp_clock_type type,
		struct amd_pp_clocks *clocks);

int amd_powerplay_get_clock_by_type_with_latency(void *handle,
		enum amd_pp_clock_type type,
		struct pp_clock_levels_with_latency *clocks);

int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
		enum amd_pp_clock_type type,
		struct pp_clock_levels_with_voltage *clocks);

int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);

int amd_powerplay_display_clock_voltage_request(void *handle,
		struct pp_display_clock_request *clock);

int amd_powerplay_get_display_mode_validation_clocks(void *handle,
		struct amd_pp_simple_clock_info *output);

int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);

#endif /* _AMD_POWERPLAY_H_ */
Commit	Line	Data
1f7371b2 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef _AMD_POWERPLAY_H_
	24	#define _AMD_POWERPLAY_H_
	25
	26	#include <linux/seq_file.h>
	27	#include <linux/types.h>
fd3e14ff	28	#include <linux/errno.h>
1f7371b2 AD	29	#include "amd_shared.h"
1f7371b2 AD	30	#include "cgs_common.h"
d0187727	31	#include "dm_pp_interface.h"
1f7371b2	32
1c863802	33	extern const struct amd_ip_funcs pp_ip_funcs;
f93f0c3a	34	extern const struct amd_pm_funcs pp_dpm_funcs;
1c863802 RZ	35
1c863802 RZ	36	#define PP_DPM_DISABLED 0xCCCC
ba5f884c	37
a6e36952 TSD	38	enum amd_pp_sensors {
	39	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
	40	AMDGPU_PP_SENSOR_VDDNB,
	41	AMDGPU_PP_SENSOR_VDDGFX,
	42	AMDGPU_PP_SENSOR_UVD_VCLK,
	43	AMDGPU_PP_SENSOR_UVD_DCLK,
	44	AMDGPU_PP_SENSOR_VCE_ECCLK,
	45	AMDGPU_PP_SENSOR_GPU_LOAD,
	46	AMDGPU_PP_SENSOR_GFX_MCLK,
	47	AMDGPU_PP_SENSOR_GPU_TEMP,
3de4ec57 TSD	48	AMDGPU_PP_SENSOR_VCE_POWER,
3de4ec57 TSD	49	AMDGPU_PP_SENSOR_UVD_POWER,
4f9afc9b	50	AMDGPU_PP_SENSOR_GPU_POWER,
a6e36952	51	};
e273b041	52
df1e6394 RZ	53	enum amd_pp_task {
	54	AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
	55	AMD_PP_TASK_ENABLE_USER_STATE,
	56	AMD_PP_TASK_READJUST_POWER_STATE,
	57	AMD_PP_TASK_COMPLETE_INIT,
	58	AMD_PP_TASK_MAX
1f7371b2 AD	59	};
1f7371b2 AD	60
1f7371b2 AD	61	struct amd_pp_init {
	62	struct cgs_device *device;
	63	uint32_t chip_family;
	64	uint32_t chip_id;
1c863802 RZ	65	bool pm_en;
1c863802 RZ	66	uint32_t feature_mask;
1f7371b2	67	};
af223dfa	68
14f63411 EY	69	enum amd_pp_display_config_type{
	70	AMD_PP_DisplayConfigType_None = 0,
	71	AMD_PP_DisplayConfigType_DP54 ,
	72	AMD_PP_DisplayConfigType_DP432 ,
	73	AMD_PP_DisplayConfigType_DP324 ,
	74	AMD_PP_DisplayConfigType_DP27,
	75	AMD_PP_DisplayConfigType_DP243,
	76	AMD_PP_DisplayConfigType_DP216,
	77	AMD_PP_DisplayConfigType_DP162,
	78	AMD_PP_DisplayConfigType_HDMI6G ,
	79	AMD_PP_DisplayConfigType_HDMI297 ,
	80	AMD_PP_DisplayConfigType_HDMI162,
	81	AMD_PP_DisplayConfigType_LVDS,
	82	AMD_PP_DisplayConfigType_DVI,
	83	AMD_PP_DisplayConfigType_WIRELESS,
	84	AMD_PP_DisplayConfigType_VGA
	85	};
	86
	87	struct single_display_configuration
	88	{
	89	uint32_t controller_index;
	90	uint32_t controller_id;
	91	uint32_t signal_type;
	92	uint32_t display_state;
	93	/* phy id for the primary internal transmitter */
	94	uint8_t primary_transmitter_phyi_d;
	95	/* bitmap with the active lanes */
	96	uint8_t primary_transmitter_active_lanemap;
	97	/* phy id for the secondary internal transmitter (for dual-link dvi) */
	98	uint8_t secondary_transmitter_phy_id;
	99	/* bitmap with the active lanes */
	100	uint8_t secondary_transmitter_active_lanemap;
	101	/* misc phy settings for SMU. */
	102	uint32_t config_flags;
	103	uint32_t display_type;
	104	uint32_t view_resolution_cx;
	105	uint32_t view_resolution_cy;
	106	enum amd_pp_display_config_type displayconfigtype;
	107	uint32_t vertical_refresh; /* for active display */
	108	};
	109
	110	#define MAX_NUM_DISPLAY 32
1f7371b2	111
7fb72a1f RZ	112	struct amd_pp_display_configuration {
	113	bool nb_pstate_switch_disable;/* controls NB PState switch */
	114	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
	115	bool cpu_pstate_disable;
	116	uint32_t cpu_pstate_separation_time;
14f63411 EY	117
	118	uint32_t num_display; /* total number of display*/
	119	uint32_t num_path_including_non_display;
	120	uint32_t crossfire_display_index;
	121	uint32_t min_mem_set_clock;
	122	uint32_t min_core_set_clock;
	123	/* unit 10KHz x bit*/
	124	uint32_t min_bus_bandwidth;
	125	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
	126	uint32_t min_core_set_clock_in_sr;
	127
	128	struct single_display_configuration displays[MAX_NUM_DISPLAY];
	129
	130	uint32_t vrefresh; /* for active display*/
	131
	132	uint32_t min_vblank_time; /* for active display*/
	133	bool multi_monitor_in_sync;
	134	/* Controller Index of primary display - used in MCLK SMC switching hang
	135	* SW Workaround*/
	136	uint32_t crtc_index;
	137	/* htotal1000/pixelclk - used in MCLK SMC switching hang SW Workaround/
	138	uint32_t line_time_in_us;
	139	bool invalid_vblank_time;
	140
	141	uint32_t display_clk;
	142	/*
	143	* for given display configuration if multimonitormnsync == false then
	144	* Memory clock DPMS with this latency or below is allowed, DPMS with
	145	* higher latency not allowed.
	146	*/
	147	uint32_t dce_tolerable_mclk_in_active_latency;
d0187727 EH	148	uint32_t min_dcef_set_clk;
d0187727 EH	149	uint32_t min_dcef_deep_sleep_set_clk;
7fb72a1f RZ	150	};
7fb72a1f RZ	151
47329134	152	struct amd_pp_simple_clock_info {
c4dd206b VP	153	uint32_t engine_max_clock;
	154	uint32_t memory_max_clock;
	155	uint32_t level;
	156	};
	157
e273b041 RZ	158	enum PP_DAL_POWERLEVEL {
	159	PP_DAL_POWERLEVEL_INVALID = 0,
	160	PP_DAL_POWERLEVEL_ULTRALOW,
	161	PP_DAL_POWERLEVEL_LOW,
	162	PP_DAL_POWERLEVEL_NOMINAL,
	163	PP_DAL_POWERLEVEL_PERFORMANCE,
	164
	165	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
	166	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
	167	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
	168	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
	169	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
	170	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
	171	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
	172	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
	173	};
	174
	175	struct amd_pp_clock_info {
	176	uint32_t min_engine_clock;
	177	uint32_t max_engine_clock;
	178	uint32_t min_memory_clock;
	179	uint32_t max_memory_clock;
	180	uint32_t min_bus_bandwidth;
	181	uint32_t max_bus_bandwidth;
	182	uint32_t max_engine_clock_in_sr;
	183	uint32_t min_engine_clock_in_sr;
	184	enum PP_DAL_POWERLEVEL max_clocks_state;
	185	};
	186
	187	enum amd_pp_clock_type {
	188	amd_pp_disp_clock = 1,
	189	amd_pp_sys_clock,
d0187727 EH	190	amd_pp_mem_clock,
	191	amd_pp_dcef_clock,
	192	amd_pp_soc_clock,
	193	amd_pp_pixel_clock,
a960d61c	194	amd_pp_phy_clock,
746eb864 RZ	195	amd_pp_dcf_clock,
	196	amd_pp_dpp_clock,
	197	amd_pp_f_clock = amd_pp_dcef_clock,
e273b041 RZ	198	};
	199
	200	#define MAX_NUM_CLOCKS 16
	201
	202	struct amd_pp_clocks {
	203	uint32_t count;
	204	uint32_t clock[MAX_NUM_CLOCKS];
6a99a964	205	uint32_t latency[MAX_NUM_CLOCKS];
e273b041 RZ	206	};
	207
	208
3cec76f9 RZ	209	enum {
	210	PP_GROUP_UNKNOWN = 0,
	211	PP_GROUP_GFX = 1,
	212	PP_GROUP_SYS,
	213	PP_GROUP_MAX
	214	};
	215
f3898ea1 EH	216	struct pp_states_info {
	217	uint32_t nums;
	218	uint32_t states[16];
	219	};
	220
4f9afc9b EH	221	struct pp_gpu_power {
	222	uint32_t vddc_power;
	223	uint32_t vddci_power;
	224	uint32_t max_gpu_power;
	225	uint32_t average_gpu_power;
	226	};
	227
d0187727 EH	228	struct pp_display_clock_request {
	229	enum amd_pp_clock_type clock_type;
	230	uint32_t clock_freq_in_khz;
	231	};
	232
3cec76f9 RZ	233	#define PP_GROUP_MASK 0xF0000000
	234	#define PP_GROUP_SHIFT 28
	235
	236	#define PP_BLOCK_MASK 0x0FFFFF00
	237	#define PP_BLOCK_SHIFT 8
	238
	239	#define PP_BLOCK_GFX_CG 0x01
	240	#define PP_BLOCK_GFX_MG 0x02
03e3905f EH	241	#define PP_BLOCK_GFX_3D 0x04
	242	#define PP_BLOCK_GFX_RLC 0x08
	243	#define PP_BLOCK_GFX_CP 0x10
3cec76f9 RZ	244	#define PP_BLOCK_SYS_BIF 0x01
	245	#define PP_BLOCK_SYS_MC 0x02
	246	#define PP_BLOCK_SYS_ROM 0x04
	247	#define PP_BLOCK_SYS_DRM 0x08
	248	#define PP_BLOCK_SYS_HDP 0x10
	249	#define PP_BLOCK_SYS_SDMA 0x20
	250
	251	#define PP_STATE_MASK 0x0000000F
	252	#define PP_STATE_SHIFT 0
	253	#define PP_STATE_SUPPORT_MASK 0x000000F0
	254	#define PP_STATE_SUPPORT_SHIFT 0
	255
	256	#define PP_STATE_CG 0x01
	257	#define PP_STATE_LS 0x02
	258	#define PP_STATE_DS 0x04
	259	#define PP_STATE_SD 0x08
	260	#define PP_STATE_SUPPORT_CG 0x10
	261	#define PP_STATE_SUPPORT_LS 0x20
	262	#define PP_STATE_SUPPORT_DS 0x40
	263	#define PP_STATE_SUPPORT_SD 0x80
	264
	265	#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT \|\
	266	block << PP_BLOCK_SHIFT \|\
	267	support << PP_STATE_SUPPORT_SHIFT \|\
	268	state << PP_STATE_SHIFT)
	269
1f7371b2	270	struct amd_powerplay {
d04f2576	271	struct cgs_device *cgs_device;
1f7371b2 AD	272	void *pp_handle;
1f7371b2 AD	273	const struct amd_ip_funcs *ip_funcs;
f93f0c3a	274	const struct amd_pm_funcs *pp_funcs;
1f7371b2 AD	275	};
1f7371b2 AD	276
1c863802 RZ	277	int amd_powerplay_create(struct amd_pp_init *pp_init,
1c863802 RZ	278	void **handle);
155f1127	279
1c863802	280	int amd_powerplay_destroy(void *handle);
1f7371b2	281
4dcf9e6f EH	282	int amd_powerplay_reset(void *handle);
4dcf9e6f EH	283
155f1127 DR	284	int amd_powerplay_display_configuration_change(void *handle,
155f1127 DR	285	const struct amd_pp_display_configuration *input);
7fb72a1f	286
1c9a9082	287	int amd_powerplay_get_display_power_level(void *handle,
47329134	288	struct amd_pp_simple_clock_info *output);
c4dd206b	289
155f1127 DR	290	int amd_powerplay_get_current_clocks(void *handle,
155f1127 DR	291	struct amd_pp_clock_info *output);
e273b041	292
155f1127 DR	293	int amd_powerplay_get_clock_by_type(void *handle,
	294	enum amd_pp_clock_type type,
	295	struct amd_pp_clocks *clocks);
e273b041	296
d0187727 EH	297	int amd_powerplay_get_clock_by_type_with_latency(void *handle,
	298	enum amd_pp_clock_type type,
	299	struct pp_clock_levels_with_latency *clocks);
	300
	301	int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
	302	enum amd_pp_clock_type type,
	303	struct pp_clock_levels_with_voltage *clocks);
	304
	305	int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
	306	struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
	307
	308	int amd_powerplay_display_clock_voltage_request(void *handle,
	309	struct pp_display_clock_request *clock);
	310
155f1127 DR	311	int amd_powerplay_get_display_mode_validation_clocks(void *handle,
155f1127 DR	312	struct amd_pp_simple_clock_info *output);
c4dd206b	313
465f96e2 RZ	314	int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
465f96e2 RZ	315
1f7371b2	316	#endif /* _AMD_POWERPLAY_H_ */