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drm/amdgpu: Constify some tables
[linux-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / tonga_hwmgr.c
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c82baa28 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include "linux/delay.h"
27#include "pp_acpi.h"
28#include "hwmgr.h"
29#include <atombios.h>
30#include "tonga_hwmgr.h"
31#include "pptable.h"
32#include "processpptables.h"
33#include "tonga_processpptables.h"
34#include "tonga_pptable.h"
35#include "pp_debug.h"
36#include "tonga_ppsmc.h"
37#include "cgs_common.h"
38#include "pppcielanes.h"
39#include "tonga_dyn_defaults.h"
40#include "smumgr.h"
41#include "tonga_smumgr.h"
0859ed3d 42#include "tonga_clockpowergating.h"
1e4854e9 43#include "tonga_thermal.h"
c82baa28 44
45#include "smu/smu_7_1_2_d.h"
46#include "smu/smu_7_1_2_sh_mask.h"
47
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50
51#include "bif/bif_5_0_d.h"
52#include "bif/bif_5_0_sh_mask.h"
53
7e8d1fbd
AD		 54#include "dce/dce_10_0_d.h"
55#include "dce/dce_10_0_sh_mask.h"
56
1e4854e9
RZ		 57#include "cgs_linux.h"
58#include "eventmgr.h"
16881da6 59#include "amd_pcie_helpers.h"
1e4854e9 60
c82baa28 61#define MC_CG_ARB_FREQ_F0 0x0a
62#define MC_CG_ARB_FREQ_F1 0x0b
63#define MC_CG_ARB_FREQ_F2 0x0c
64#define MC_CG_ARB_FREQ_F3 0x0d
65
66#define MC_CG_SEQ_DRAMCONF_S0 0x05
67#define MC_CG_SEQ_DRAMCONF_S1 0x06
68#define MC_CG_SEQ_YCLK_SUSPEND 0x04
69#define MC_CG_SEQ_YCLK_RESUME 0x0a
70
71#define PCIE_BUS_CLK 10000
72#define TCLK (PCIE_BUS_CLK / 10)
73
74#define SMC_RAM_END 0x40000
75#define SMC_CG_IND_START 0xc0030000
76#define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/
77
78#define VOLTAGE_SCALE 4
79#define VOLTAGE_VID_OFFSET_SCALE1 625
80#define VOLTAGE_VID_OFFSET_SCALE2 100
81
82#define VDDC_VDDCI_DELTA 200
83#define VDDC_VDDGFX_DELTA 300
84
85#define MC_SEQ_MISC0_GDDR5_SHIFT 28
86#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
87#define MC_SEQ_MISC0_GDDR5_VALUE 5
88
89typedef uint32_t PECI_RegistryValue;
90
91/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
f498d9ed 92static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
c82baa28 93 {600, 1050, 3, 0},
94 {600, 1050, 6, 1} };
95
96/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
f498d9ed 97static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
c82baa28 98 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
99 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
100
101/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
f498d9ed 102static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
c82baa28 103 {0, 1, 3, 2, 4, 5},
104 {0, 2, 4, 5, 6, 5} };
105
106/* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
107enum DPM_EVENT_SRC {
108 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
109 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
110 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
111 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
112 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
113};
114typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
115
f498d9ed 116static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
c82baa28 117
118struct tonga_power_state *cast_phw_tonga_power_state(
119 struct pp_hw_power_state *hw_ps)
120{
c15c8d70
RZ		 121 if (hw_ps == NULL)
122 return NULL;
123
c82baa28 124 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
125 "Invalid Powerstate Type!",
c15c8d70 126 return NULL);
c82baa28 127
128 return (struct tonga_power_state *)hw_ps;
129}
130
131const struct tonga_power_state *cast_const_phw_tonga_power_state(
132 const struct pp_hw_power_state *hw_ps)
133{
c15c8d70
RZ		 134 if (hw_ps == NULL)
135 return NULL;
136
c82baa28 137 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
138 "Invalid Powerstate Type!",
c15c8d70 139 return NULL);
c82baa28 140
141 return (const struct tonga_power_state *)hw_ps;
142}
143
144int tonga_add_voltage(struct pp_hwmgr *hwmgr,
145 phm_ppt_v1_voltage_lookup_table *look_up_table,
146 phm_ppt_v1_voltage_lookup_record *record)
147{
148 uint32_t i;
149 PP_ASSERT_WITH_CODE((NULL != look_up_table),
150 "Lookup Table empty.", return -1;);
151 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
152 "Lookup Table empty.", return -1;);
153 PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
154 "Lookup Table is full.", return -1;);
155
156 /* This is to avoid entering duplicate calculated records. */
157 for (i = 0; i < look_up_table->count; i++) {
158 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
159 if (look_up_table->entries[i].us_calculated == 1)
160 return 0;
161 else
162 break;
163 }
164 }
165
166 look_up_table->entries[i].us_calculated = 1;
167 look_up_table->entries[i].us_vdd = record->us_vdd;
168 look_up_table->entries[i].us_cac_low = record->us_cac_low;
169 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
170 look_up_table->entries[i].us_cac_high = record->us_cac_high;
171 /* Only increment the count when we're appending, not replacing duplicate entry. */
172 if (i == look_up_table->count)
173 look_up_table->count++;
174
175 return 0;
176}
177
bbb207f3
RZ		 178int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
179{
180 PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
181
182 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
183}
184
c82baa28 185uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
186 uint32_t voltage)
187{
188 uint8_t count = (uint8_t) (voltage_table->count);
189 uint8_t i = 0;
190
191 PP_ASSERT_WITH_CODE((NULL != voltage_table),
192 "Voltage Table empty.", return 0;);
193 PP_ASSERT_WITH_CODE((0 != count),
194 "Voltage Table empty.", return 0;);
195
196 for (i = 0; i < count; i++) {
197 /* find first voltage bigger than requested */
198 if (voltage_table->entries[i].value >= voltage)
199 return i;
200 }
201
202 /* voltage is bigger than max voltage in the table */
203 return i - 1;
204}
205
206/**
207 * @brief PhwTonga_GetVoltageOrder
208 * Returns index of requested voltage record in lookup(table)
209 * @param hwmgr - pointer to hardware manager
210 * @param lookupTable - lookup list to search in
211 * @param voltage - voltage to look for
212 * @return 0 on success
213 */
214uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
215 uint16_t voltage)
216{
217 uint8_t count = (uint8_t) (look_up_table->count);
218 uint8_t i;
219
220 PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
221 PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
222
223 for (i = 0; i < count; i++) {
224 /* find first voltage equal or bigger than requested */
225 if (look_up_table->entries[i].us_vdd >= voltage)
226 return i;
227 }
228
229 /* voltage is bigger than max voltage in the table */
230 return i-1;
231}
232
233bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
234{
235 /*
236 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
237 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
238 * whereas voltage control is a fundemental change that will not be disabled
239 */
240
241 return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
242 FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
243}
244
245/**
246 * Re-generate the DPM level mask value
247 * @param hwmgr the address of the hardware manager
248 */
249static uint32_t tonga_get_dpm_level_enable_mask_value(
250 struct tonga_single_dpm_table * dpm_table)
251{
252 uint32_t i;
253 uint32_t mask_value = 0;
254
255 for (i = dpm_table->count; i > 0; i--) {
256 mask_value = mask_value << 1;
257
258 if (dpm_table->dpm_levels[i-1].enabled)
259 mask_value |= 0x1;
260 else
261 mask_value &= 0xFFFFFFFE;
262 }
263 return mask_value;
264}
265
266/**
267 * Retrieve DPM default values from registry (if available)
268 *
269 * @param hwmgr the address of the powerplay hardware manager.
270 */
271void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
272{
273 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
274 phw_tonga_ulv_parm *ulv = &(data->ulv);
275 uint32_t tmp;
276
277 ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
278 data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
279 data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
280 data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
281 data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
282 data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
283 data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
284 data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
285 data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
286
287 data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
288 data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
289
290 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_ABM);
292 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
293 PHM_PlatformCaps_NonABMSupportInPPLib);
294
295 tmp = 0;
296 if (tmp == 0)
297 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
298 PHM_PlatformCaps_DynamicACTiming);
299
300 tmp = 0;
301 if (0 != tmp)
302 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
303 PHM_PlatformCaps_DisableMemoryTransition);
304
305 data->mclk_strobe_mode_threshold = 40000;
306 data->mclk_stutter_mode_threshold = 30000;
307 data->mclk_edc_enable_threshold = 40000;
308 data->mclk_edc_wr_enable_threshold = 40000;
309
310 tmp = 0;
311 if (tmp != 0)
312 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
313 PHM_PlatformCaps_DisableMCLS);
314
315 data->pcie_gen_performance.max = PP_PCIEGen1;
316 data->pcie_gen_performance.min = PP_PCIEGen3;
317 data->pcie_gen_power_saving.max = PP_PCIEGen1;
318 data->pcie_gen_power_saving.min = PP_PCIEGen3;
319
320 data->pcie_lane_performance.max = 0;
321 data->pcie_lane_performance.min = 16;
322 data->pcie_lane_power_saving.max = 0;
323 data->pcie_lane_power_saving.min = 16;
324
325 tmp = 0;
326
327 if (tmp)
328 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
329 PHM_PlatformCaps_SclkThrottleLowNotification);
330
331 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
332 PHM_PlatformCaps_DynamicUVDState);
333
334}
335
336int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
337{
338 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
339
340 int result = 0;
341 uint32_t low_sclk_interrupt_threshold = 0;
342
343 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
344 PHM_PlatformCaps_SclkThrottleLowNotification)
345 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
346 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
347 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
348
349 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
350
351 result = tonga_copy_bytes_to_smc(
352 hwmgr->smumgr,
353 data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
354 LowSclkInterruptThreshold),
355 (uint8_t *)&low_sclk_interrupt_threshold,
356 sizeof(uint32_t),
357 data->sram_end
358 );
359 }
360
361 return result;
362}
363
364/**
365 * Find SCLK value that is associated with specified virtual_voltage_Id.
366 *
367 * @param hwmgr the address of the powerplay hardware manager.
368 * @param virtual_voltage_Id voltageId to look for.
369 * @param sclk output value .
370 * @return always 0 if success and 2 if association not found
371 */
372static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
373 phm_ppt_v1_voltage_lookup_table *lookup_table,
374 uint16_t virtual_voltage_id, uint32_t *sclk)
375{
376 uint8_t entryId;
377 uint8_t voltageId;
378 struct phm_ppt_v1_information *pptable_info =
379 (struct phm_ppt_v1_information *)(hwmgr->pptable);
380
381 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
382
383 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
384 for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
385 voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
386 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
387 break;
388 }
389
390 PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
391 "Can't find requested voltage id in vdd_dep_on_sclk table!",
392 return -1;
393 );
394
395 *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
396
397 return 0;
398}
399
400/**
401 * Get Leakage VDDC based on leakage ID.
402 *
403 * @param hwmgr the address of the powerplay hardware manager.
404 * @return 2 if vddgfx returned is greater than 2V or if BIOS
405 */
406int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
407{
408 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
409 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
410 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
411 uint16_t virtual_voltage_id;
412 uint16_t vddc = 0;
413 uint16_t vddgfx = 0;
414 uint16_t i, j;
415 uint32_t sclk = 0;
416
417 /* retrieve voltage for leakage ID (0xff01 + i) */
418 for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
419 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
420
421 /* in split mode we should have only vddgfx EVV leakages */
422 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
423 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
424 pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
425 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
426 PHM_PlatformCaps_ClockStretcher)) {
427 for (j = 1; j < sclk_table->count; j++) {
428 if (sclk_table->entries[j].clk == sclk &&
429 sclk_table->entries[j].cks_enable == 0) {
430 sclk += 5000;
431 break;
432 }
433 }
434 }
ac0cc350
MK		 435 if (0 == atomctrl_get_voltage_evv_on_sclk
436 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
437 virtual_voltage_id, &vddgfx)) {
438 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
439 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
440
441 /* the voltage should not be zero nor equal to leakage ID */
442 if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
443 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
444 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
445 data->vddcgfx_leakage.count++;
446 }
447 } else {
448 printk("Error retrieving EVV voltage value!\n");
c82baa28 449 }
450 }
451 } else {
452 /* in merged mode we have only vddc EVV leakages */
453 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
454 pptable_info->vddc_lookup_table,
455 virtual_voltage_id, &sclk)) {
ac0cc350
MK		 456 if (0 == atomctrl_get_voltage_evv_on_sclk
457 (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
458 virtual_voltage_id, &vddc)) {
459 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
460 PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
461
462 /* the voltage should not be zero nor equal to leakage ID */
463 if (vddc != 0 && vddc != virtual_voltage_id) {
464 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
465 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
466 data->vddc_leakage.count++;
467 }
468 } else {
469 printk("Error retrieving EVV voltage value!\n");
c82baa28 470 }
471 }
472 }
473 }
474
475 return 0;
476}
477
478int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
479{
480 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
481
482 /* enable SCLK dpm */
483 if (0 == data->sclk_dpm_key_disabled) {
484 PP_ASSERT_WITH_CODE(
485 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
486 PPSMC_MSG_DPM_Enable)),
487 "Failed to enable SCLK DPM during DPM Start Function!",
488 return -1);
489 }
490
491 /* enable MCLK dpm */
492 if (0 == data->mclk_dpm_key_disabled) {
493 PP_ASSERT_WITH_CODE(
494 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
495 PPSMC_MSG_MCLKDPM_Enable)),
496 "Failed to enable MCLK DPM during DPM Start Function!",
497 return -1);
498
499 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
500
501 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
502 ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
503 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
504 ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
505 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
506 ixLCAC_CPL_CNTL, 0x100005);/*Read */
507
508 udelay(10);
509
510 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
511 ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
512 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
513 ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
514 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
515 ixLCAC_CPL_CNTL, 0x500005);/* write */
516
517 }
518
519 return 0;
520}
521
522int tonga_start_dpm(struct pp_hwmgr *hwmgr)
523{
524 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
525
526 /* enable general power management */
527 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
528 /* enable sclk deep sleep */
529 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
530
531 /* prepare for PCIE DPM */
532 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
533 offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
534
535 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
536
537 PP_ASSERT_WITH_CODE(
538 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
539 PPSMC_MSG_Voltage_Cntl_Enable)),
540 "Failed to enable voltage DPM during DPM Start Function!",
541 return -1);
542
543 if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
544 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
545 }
546
547 /* enable PCIE dpm */
548 if (0 == data->pcie_dpm_key_disabled) {
549 PP_ASSERT_WITH_CODE(
550 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
551 PPSMC_MSG_PCIeDPM_Enable)),
552 "Failed to enable pcie DPM during DPM Start Function!",
553 return -1
554 );
555 }
556
557 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
558 PHM_PlatformCaps_Falcon_QuickTransition)) {
559 smum_send_msg_to_smc(hwmgr->smumgr,
560 PPSMC_MSG_EnableACDCGPIOInterrupt);
561 }
562
563 return 0;
564}
565
566int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
567{
568 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
569
570 /* disable SCLK dpm */
571 if (0 == data->sclk_dpm_key_disabled) {
572 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
573 PP_ASSERT_WITH_CODE(
574 (0 == tonga_is_dpm_running(hwmgr)),
575 "Trying to Disable SCLK DPM when DPM is disabled",
576 return -1
577 );
578
579 PP_ASSERT_WITH_CODE(
580 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
581 PPSMC_MSG_DPM_Disable)),
582 "Failed to disable SCLK DPM during DPM stop Function!",
583 return -1);
584 }
585
586 /* disable MCLK dpm */
587 if (0 == data->mclk_dpm_key_disabled) {
588 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
589 PP_ASSERT_WITH_CODE(
590 (0 == tonga_is_dpm_running(hwmgr)),
591 "Trying to Disable MCLK DPM when DPM is disabled",
592 return -1
593 );
594
595 PP_ASSERT_WITH_CODE(
596 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
597 PPSMC_MSG_MCLKDPM_Disable)),
598 "Failed to Disable MCLK DPM during DPM stop Function!",
599 return -1);
600 }
601
602 return 0;
603}
604
605int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
606{
607 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
608
609 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
610 /* disable sclk deep sleep*/
611 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
612
613 /* disable PCIE dpm */
614 if (0 == data->pcie_dpm_key_disabled) {
615 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
616 PP_ASSERT_WITH_CODE(
617 (0 == tonga_is_dpm_running(hwmgr)),
618 "Trying to Disable PCIE DPM when DPM is disabled",
619 return -1
620 );
621 PP_ASSERT_WITH_CODE(
622 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
623 PPSMC_MSG_PCIeDPM_Disable)),
624 "Failed to disable pcie DPM during DPM stop Function!",
625 return -1);
626 }
627
628 if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
629 PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
630
631 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
632 PP_ASSERT_WITH_CODE(
633 (0 == tonga_is_dpm_running(hwmgr)),
634 "Trying to Disable Voltage CNTL when DPM is disabled",
635 return -1
636 );
637
638 PP_ASSERT_WITH_CODE(
639 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
640 PPSMC_MSG_Voltage_Cntl_Disable)),
641 "Failed to disable voltage DPM during DPM stop Function!",
642 return -1);
643
644 return 0;
645}
646
647int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
648{
649 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
650
651 return 0;
652}
653
654/**
655 * Send a message to the SMC and return a parameter
656 *
657 * @param hwmgr: the address of the powerplay hardware manager.
658 * @param msg: the message to send.
659 * @param parameter: pointer to the received parameter
660 * @return The response that came from the SMC.
661 */
662PPSMC_Result tonga_send_msg_to_smc_return_parameter(
663 struct pp_hwmgr *hwmgr,
664 PPSMC_Msg msg,
665 uint32_t *parameter)
666{
667 int result;
668
669 result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
670
671 if ((0 == result) && parameter) {
672 *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
673 }
674
675 return result;
676}
677
678/**
679 * force DPM power State
680 *
681 * @param hwmgr: the address of the powerplay hardware manager.
682 * @param n : DPM level
683 * @return The response that came from the SMC.
684 */
685int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
686{
687 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
688 uint32_t level_mask = 1 << n;
689
690 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
691 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
692 "Trying to force SCLK when DPM is disabled", return -1;);
693 if (0 == data->sclk_dpm_key_disabled)
694 return (0 == smum_send_msg_to_smc_with_parameter(
695 hwmgr->smumgr,
696 (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
697 level_mask) ? 0 : 1);
698
699 return 0;
700}
701
702/**
703 * force DPM power State
704 *
705 * @param hwmgr: the address of the powerplay hardware manager.
706 * @param n : DPM level
707 * @return The response that came from the SMC.
708 */
709int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
710{
711 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
712 uint32_t level_mask = 1 << n;
713
714 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
715 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
716 "Trying to Force MCLK when DPM is disabled", return -1;);
717 if (0 == data->mclk_dpm_key_disabled)
718 return (0 == smum_send_msg_to_smc_with_parameter(
719 hwmgr->smumgr,
720 (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
721 level_mask) ? 0 : 1);
722
723 return 0;
724}
725
726/**
727 * force DPM power State
728 *
729 * @param hwmgr: the address of the powerplay hardware manager.
730 * @param n : DPM level
731 * @return The response that came from the SMC.
732 */
733int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
734{
735 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
736
737 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
738 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
739 "Trying to Force PCIE level when DPM is disabled", return -1;);
740 if (0 == data->pcie_dpm_key_disabled)
741 return (0 == smum_send_msg_to_smc_with_parameter(
742 hwmgr->smumgr,
743 (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
744 n) ? 0 : 1);
745
746 return 0;
747}
748
749/**
750 * Set the initial state by calling SMC to switch to this state directly
751 *
752 * @param hwmgr the address of the powerplay hardware manager.
753 * @return always 0
754 */
755int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
756{
757 /*
758 * SMC only stores one state that SW will ask to switch too,
759 * so we switch the the just uploaded one
760 */
761 return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
762}
763
764/**
765 * Get the location of various tables inside the FW image.
766 *
767 * @param hwmgr the address of the powerplay hardware manager.
768 * @return always 0
769 */
770int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
771{
772 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
773 struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
774
775 uint32_t tmp;
776 int result;
777 bool error = 0;
778
779 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
780 SMU72_FIRMWARE_HEADER_LOCATION +
781 offsetof(SMU72_Firmware_Header, DpmTable),
782 &tmp, data->sram_end);
783
784 if (0 == result) {
785 data->dpm_table_start = tmp;
786 }
787
788 error |= (0 != result);
789
790 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
791 SMU72_FIRMWARE_HEADER_LOCATION +
792 offsetof(SMU72_Firmware_Header, SoftRegisters),
793 &tmp, data->sram_end);
794
795 if (0 == result) {
796 data->soft_regs_start = tmp;
797 tonga_smu->ulSoftRegsStart = tmp;
798 }
799
800 error |= (0 != result);
801
802
803 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
804 SMU72_FIRMWARE_HEADER_LOCATION +
805 offsetof(SMU72_Firmware_Header, mcRegisterTable),
806 &tmp, data->sram_end);
807
808 if (0 == result) {
809 data->mc_reg_table_start = tmp;
810 }
811
812 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
813 SMU72_FIRMWARE_HEADER_LOCATION +
814 offsetof(SMU72_Firmware_Header, FanTable),
815 &tmp, data->sram_end);
816
817 if (0 == result) {
818 data->fan_table_start = tmp;
819 }
820
821 error |= (0 != result);
822
823 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
824 SMU72_FIRMWARE_HEADER_LOCATION +
825 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
826 &tmp, data->sram_end);
827
828 if (0 == result) {
829 data->arb_table_start = tmp;
830 }
831
832 error |= (0 != result);
833
834
835 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
836 SMU72_FIRMWARE_HEADER_LOCATION +
837 offsetof(SMU72_Firmware_Header, Version),
838 &tmp, data->sram_end);
839
840 if (0 == result) {
841 hwmgr->microcode_version_info.SMC = tmp;
842 }
843
844 error |= (0 != result);
845
846 return error ? 1 : 0;
847}
848
849/**
850 * Read clock related registers.
851 *
852 * @param hwmgr the address of the powerplay hardware manager.
853 * @return always 0
854 */
855int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
856{
857 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
858
859 data->clock_registers.vCG_SPLL_FUNC_CNTL =
860 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
861 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
862 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
863 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
864 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
865 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
866 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
867 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
868 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
869 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
870 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
871 data->clock_registers.vDLL_CNTL =
872 cgs_read_register(hwmgr->device, mmDLL_CNTL);
873 data->clock_registers.vMCLK_PWRMGT_CNTL =
874 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
875 data->clock_registers.vMPLL_AD_FUNC_CNTL =
876 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
877 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
878 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
879 data->clock_registers.vMPLL_FUNC_CNTL =
880 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
881 data->clock_registers.vMPLL_FUNC_CNTL_1 =
882 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
883 data->clock_registers.vMPLL_FUNC_CNTL_2 =
884 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
885 data->clock_registers.vMPLL_SS1 =
886 cgs_read_register(hwmgr->device, mmMPLL_SS1);
887 data->clock_registers.vMPLL_SS2 =
888 cgs_read_register(hwmgr->device, mmMPLL_SS2);
889
890 return 0;
891}
892
893/**
894 * Find out if memory is GDDR5.
895 *
896 * @param hwmgr the address of the powerplay hardware manager.
897 * @return always 0
898 */
899int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
900{
901 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
902 uint32_t temp;
903
904 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
905
906 data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
907 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
908 MC_SEQ_MISC0_GDDR5_SHIFT));
909
910 return 0;
911}
912
913/**
914 * Enables Dynamic Power Management by SMC
915 *
916 * @param hwmgr the address of the powerplay hardware manager.
917 * @return always 0
918 */
919int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
920{
921 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
922
923 return 0;
924}
925
926/**
927 * Initialize PowerGating States for different engines
928 *
929 * @param hwmgr the address of the powerplay hardware manager.
930 * @return always 0
931 */
932int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
933{
934 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
935
936 data->uvd_power_gated = 0;
937 data->vce_power_gated = 0;
938 data->samu_power_gated = 0;
939 data->acp_power_gated = 0;
940 data->pg_acp_init = 1;
941
942 return 0;
943}
944
945/**
946 * Checks if DPM is enabled
947 *
948 * @param hwmgr the address of the powerplay hardware manager.
949 * @return always 0
950 */
951int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
952{
953 /*
954 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
955 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
956 * whereas voltage control is a fundemental change that will not be disabled
957 */
958 return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
959}
960
961/**
962 * Checks if DPM is stopped
963 *
964 * @param hwmgr the address of the powerplay hardware manager.
965 * @return always 0
966 */
967int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
968{
969 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
970
971 if (0 != tonga_is_dpm_running(hwmgr)) {
972 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
973 if (!data->dpm_table_start) {
974 return 1;
975 }
976 }
977
978 return 0;
979}
980
981/**
982 * Remove repeated voltage values and create table with unique values.
983 *
984 * @param hwmgr the address of the powerplay hardware manager.
985 * @param voltage_table the pointer to changing voltage table
986 * @return 1 in success
987 */
988
989static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
990 pp_atomctrl_voltage_table *voltage_table)
991{
992 uint32_t table_size, i, j;
993 uint16_t vvalue;
994 bool bVoltageFound = 0;
995 pp_atomctrl_voltage_table *table;
996
997 PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
998 table_size = sizeof(pp_atomctrl_voltage_table);
999 table = kzalloc(table_size, GFP_KERNEL);
1000
1001 if (NULL == table)
1002 return -ENOMEM;
1003
1004 memset(table, 0x00, table_size);
1005 table->mask_low = voltage_table->mask_low;
1006 table->phase_delay = voltage_table->phase_delay;
1007
1008 for (i = 0; i < voltage_table->count; i++) {
1009 vvalue = voltage_table->entries[i].value;
1010 bVoltageFound = 0;
1011
1012 for (j = 0; j < table->count; j++) {
1013 if (vvalue == table->entries[j].value) {
1014 bVoltageFound = 1;
1015 break;
1016 }
1017 }
1018
1019 if (!bVoltageFound) {
1020 table->entries[table->count].value = vvalue;
1021 table->entries[table->count].smio_low =
1022 voltage_table->entries[i].smio_low;
1023 table->count++;
1024 }
1025 }
1026
1027 memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
1028
1029 kfree(table);
1030
1031 return 0;
1032}
1033
1034static int tonga_get_svi2_vdd_ci_voltage_table(
1035 struct pp_hwmgr *hwmgr,
1036 phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
1037{
1038 uint32_t i;
1039 int result;
1040 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1041 pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
1042
1043 PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
1044 "Voltage Dependency Table empty.", return -1;);
1045
1046 vddci_voltage_table->mask_low = 0;
1047 vddci_voltage_table->phase_delay = 0;
1048 vddci_voltage_table->count = voltage_dependency_table->count;
1049
1050 for (i = 0; i < voltage_dependency_table->count; i++) {
1051 vddci_voltage_table->entries[i].value =
1052 voltage_dependency_table->entries[i].vddci;
1053 vddci_voltage_table->entries[i].smio_low = 0;
1054 }
1055
1056 result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
1057 PP_ASSERT_WITH_CODE((0 == result),
1058 "Failed to trim VDDCI table.", return result;);
1059
1060 return 0;
1061}
1062
1063
1064
1065static int tonga_get_svi2_vdd_voltage_table(
1066 struct pp_hwmgr *hwmgr,
1067 phm_ppt_v1_voltage_lookup_table *look_up_table,
1068 pp_atomctrl_voltage_table *voltage_table)
1069{
1070 uint8_t i = 0;
1071
1072 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1073 "Voltage Lookup Table empty.", return -1;);
1074
1075 voltage_table->mask_low = 0;
1076 voltage_table->phase_delay = 0;
1077
1078 voltage_table->count = look_up_table->count;
1079
1080 for (i = 0; i < voltage_table->count; i++) {
1081 voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
1082 voltage_table->entries[i].smio_low = 0;
1083 }
1084
1085 return 0;
1086}
1087
1088/*
1089 * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
1090 * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
1091 */
1092
1093static void tonga_trim_voltage_table_to_fit_state_table(
1094 struct pp_hwmgr *hwmgr,
1095 uint32_t max_voltage_steps,
1096 pp_atomctrl_voltage_table *voltage_table)
1097{
1098 unsigned int i, diff;
1099
1100 if (voltage_table->count <= max_voltage_steps) {
1101 return;
1102 }
1103
1104 diff = voltage_table->count - max_voltage_steps;
1105
1106 for (i = 0; i < max_voltage_steps; i++) {
1107 voltage_table->entries[i] = voltage_table->entries[i + diff];
1108 }
1109
1110 voltage_table->count = max_voltage_steps;
1111
1112 return;
1113}
1114
1115/**
1116 * Create Voltage Tables.
1117 *
1118 * @param hwmgr the address of the powerplay hardware manager.
1119 * @return always 0
1120 */
1121int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1122{
1123 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1124 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1125 int result;
1126
1127 /* MVDD has only GPIO voltage control */
1128 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1129 result = atomctrl_get_voltage_table_v3(hwmgr,
1130 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
1131 PP_ASSERT_WITH_CODE((0 == result),
1132 "Failed to retrieve MVDD table.", return result;);
1133 }
1134
1135 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1136 /* GPIO voltage */
1137 result = atomctrl_get_voltage_table_v3(hwmgr,
1138 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
1139 PP_ASSERT_WITH_CODE((0 == result),
1140 "Failed to retrieve VDDCI table.", return result;);
1141 } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1142 /* SVI2 voltage */
1143 result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
1144 pptable_info->vdd_dep_on_mclk);
1145 PP_ASSERT_WITH_CODE((0 == result),
1146 "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
1147 }
1148
1149 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1150 /* VDDGFX has only SVI2 voltage control */
1151 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1152 pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
1153 PP_ASSERT_WITH_CODE((0 == result),
1154 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
1155 }
1156
1157 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1158 /* VDDC has only SVI2 voltage control */
1159 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1160 pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
1161 PP_ASSERT_WITH_CODE((0 == result),
1162 "Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
1163 }
1164
1165 PP_ASSERT_WITH_CODE(
1166 (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
1167 "Too many voltage values for VDDC. Trimming to fit state table.",
1168 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1169 SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
1170 );
1171
1172 PP_ASSERT_WITH_CODE(
1173 (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
1174 "Too many voltage values for VDDGFX. Trimming to fit state table.",
1175 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1176 SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
1177 );
1178
1179 PP_ASSERT_WITH_CODE(
1180 (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
1181 "Too many voltage values for VDDCI. Trimming to fit state table.",
1182 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1183 SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
1184 );
1185
1186 PP_ASSERT_WITH_CODE(
1187 (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
1188 "Too many voltage values for MVDD. Trimming to fit state table.",
1189 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1190 SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
1191 );
1192
1193 return 0;
1194}
1195
1196/**
1197 * Vddc table preparation for SMC.
1198 *
1199 * @param hwmgr the address of the hardware manager
1200 * @param table the SMC DPM table structure to be populated
1201 * @return always 0
1202 */
1203static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1204 SMU72_Discrete_DpmTable *table)
1205{
1206 unsigned int count;
1207 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1208
1209 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1210 table->VddcLevelCount = data->vddc_voltage_table.count;
1211 for (count = 0; count < table->VddcLevelCount; count++) {
1212 table->VddcTable[count] =
1213 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
1214 }
1215 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1216 }
1217 return 0;
1218}
1219
1220/**
1221 * VddGfx table preparation for SMC.
1222 *
1223 * @param hwmgr the address of the hardware manager
1224 * @param table the SMC DPM table structure to be populated
1225 * @return always 0
1226 */
1227static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
1228 SMU72_Discrete_DpmTable *table)
1229{
1230 unsigned int count;
1231 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1232
1233 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1234 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
1235 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
1236 table->VddGfxTable[count] =
1237 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
1238 }
1239 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
1240 }
1241 return 0;
1242}
1243
1244/**
1245 * Vddci table preparation for SMC.
1246 *
1247 * @param *hwmgr The address of the hardware manager.
1248 * @param *table The SMC DPM table structure to be populated.
1249 * @return 0
1250 */
1251static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1252 SMU72_Discrete_DpmTable *table)
1253{
1254 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1255 uint32_t count;
1256
1257 table->VddciLevelCount = data->vddci_voltage_table.count;
1258 for (count = 0; count < table->VddciLevelCount; count++) {
1259 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1260 table->VddciTable[count] =
1261 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1262 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1263 table->SmioTable1.Pattern[count].Voltage =
1264 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1265 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
1266 table->SmioTable1.Pattern[count].Smio =
1267 (uint8_t) count;
1268 table->Smio[count] |=
1269 data->vddci_voltage_table.entries[count].smio_low;
1270 table->VddciTable[count] =
1271 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1272 }
1273 }
1274
1275 table->SmioMask1 = data->vddci_voltage_table.mask_low;
1276 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
1277
1278 return 0;
1279}
1280
1281/**
1282 * Mvdd table preparation for SMC.
1283 *
1284 * @param *hwmgr The address of the hardware manager.
1285 * @param *table The SMC DPM table structure to be populated.
1286 * @return 0
1287 */
1288static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1289 SMU72_Discrete_DpmTable *table)
1290{
1291 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1292 uint32_t count;
1293
1294 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1295 table->MvddLevelCount = data->mvdd_voltage_table.count;
1296 for (count = 0; count < table->MvddLevelCount; count++) {
1297 table->SmioTable2.Pattern[count].Voltage =
1298 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
1299 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
1300 table->SmioTable2.Pattern[count].Smio =
1301 (uint8_t) count;
1302 table->Smio[count] |=
1303 data->mvdd_voltage_table.entries[count].smio_low;
1304 }
1305 table->SmioMask2 = data->vddci_voltage_table.mask_low;
1306
1307 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1308 }
1309
1310 return 0;
1311}
1312
1313/**
1314 * Convert a voltage value in mv unit to VID number required by SMU firmware
1315 */
1316static uint8_t convert_to_vid(uint16_t vddc)
1317{
1318 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1319}
1320
1321
1322/**
1323 * Preparation of vddc and vddgfx CAC tables for SMC.
1324 *
1325 * @param hwmgr the address of the hardware manager
1326 * @param table the SMC DPM table structure to be populated
1327 * @return always 0
1328 */
1329static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
1330 SMU72_Discrete_DpmTable *table)
1331{
1332 uint32_t count;
1333 uint8_t index;
1334 int result = 0;
1335 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1336 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1337 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
1338 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
1339
1340 /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
1341 uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
1342 uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
1343
1344 for (count = 0; count < vddcLevelCount; count++) {
1345 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
1346 index = tonga_get_voltage_index(vddc_lookup_table,
1347 data->vddc_voltage_table.entries[count].value);
1348 table->BapmVddcVidLoSidd[count] =
1349 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1350 table->BapmVddcVidHiSidd[count] =
1351 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1352 table->BapmVddcVidHiSidd2[count] =
1353 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1354 }
1355
1356 if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
1357 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
1358 for (count = 0; count < vddgfxLevelCount; count++) {
1359 index = tonga_get_voltage_index(vddgfx_lookup_table,
1360 data->vddgfx_voltage_table.entries[count].value);
1361 table->BapmVddGfxVidLoSidd[count] =
1362 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
1363 table->BapmVddGfxVidHiSidd[count] =
1364 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
1365 table->BapmVddGfxVidHiSidd2[count] =
1366 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
1367 }
1368 } else {
1369 for (count = 0; count < vddcLevelCount; count++) {
1370 index = tonga_get_voltage_index(vddc_lookup_table,
1371 data->vddc_voltage_table.entries[count].value);
1372 table->BapmVddGfxVidLoSidd[count] =
1373 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1374 table->BapmVddGfxVidHiSidd[count] =
1375 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1376 table->BapmVddGfxVidHiSidd2[count] =
1377 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1378 }
1379 }
1380
1381 return result;
1382}
1383
1384
1385/**
1386 * Preparation of voltage tables for SMC.
1387 *
1388 * @param hwmgr the address of the hardware manager
1389 * @param table the SMC DPM table structure to be populated
1390 * @return always 0
1391 */
1392
1393int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1394 SMU72_Discrete_DpmTable *table)
1395{
1396 int result;
1397
1398 result = tonga_populate_smc_vddc_table(hwmgr, table);
1399 PP_ASSERT_WITH_CODE(0 == result,
1400 "can not populate VDDC voltage table to SMC", return -1);
1401
1402 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
1403 PP_ASSERT_WITH_CODE(0 == result,
1404 "can not populate VDDCI voltage table to SMC", return -1);
1405
1406 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
1407 PP_ASSERT_WITH_CODE(0 == result,
1408 "can not populate VDDGFX voltage table to SMC", return -1);
1409
1410 result = tonga_populate_smc_mvdd_table(hwmgr, table);
1411 PP_ASSERT_WITH_CODE(0 == result,
1412 "can not populate MVDD voltage table to SMC", return -1);
1413
1414 result = tonga_populate_cac_tables(hwmgr, table);
1415 PP_ASSERT_WITH_CODE(0 == result,
1416 "can not populate CAC voltage tables to SMC", return -1);
1417
1418 return 0;
1419}
1420
1421/**
1422 * Populates the SMC VRConfig field in DPM table.
1423 *
1424 * @param hwmgr the address of the hardware manager
1425 * @param table the SMC DPM table structure to be populated
1426 * @return always 0
1427 */
1428static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1429 SMU72_Discrete_DpmTable *table)
1430{
1431 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1432 uint16_t config;
1433
1434 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1435 /* Splitted mode */
1436 config = VR_SVI2_PLANE_1;
1437 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1438
1439 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1440 config = VR_SVI2_PLANE_2;
1441 table->VRConfig |= config;
1442 } else {
1443 printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
1444 }
1445 } else {
1446 /* Merged mode */
1447 config = VR_MERGED_WITH_VDDC;
1448 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1449
1450 /* Set Vddc Voltage Controller */
1451 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1452 config = VR_SVI2_PLANE_1;
1453 table->VRConfig |= config;
1454 } else {
1455 printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
1456 }
1457 }
1458
1459 /* Set Vddci Voltage Controller */
1460 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1461 config = VR_SVI2_PLANE_2; /* only in merged mode */
1462 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1463 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1464 config = VR_SMIO_PATTERN_1;
1465 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1466 }
1467
1468 /* Set Mvdd Voltage Controller */
1469 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1470 config = VR_SMIO_PATTERN_2;
1471 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1472 }
1473
1474 return 0;
1475}
1476
1477static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1478 phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
1479 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1480{
1481 uint32_t i = 0;
1482 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1483 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1484
1485 /* clock - voltage dependency table is empty table */
1486 if (allowed_clock_voltage_table->count == 0)
1487 return -1;
1488
1489 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1490 /* find first sclk bigger than request */
1491 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1492 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1493 allowed_clock_voltage_table->entries[i].vddgfx);
1494
1495 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1496 allowed_clock_voltage_table->entries[i].vddc);
1497
1498 if (allowed_clock_voltage_table->entries[i].vddci) {
1499 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1500 allowed_clock_voltage_table->entries[i].vddci);
1501 } else {
1502 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1503 allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
1504 }
1505
1506 if (allowed_clock_voltage_table->entries[i].mvdd) {
1507 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
1508 }
1509
1510 voltage->Phases = 1;
1511 return 0;
1512 }
1513 }
1514
1515 /* sclk is bigger than max sclk in the dependence table */
1516 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1517 allowed_clock_voltage_table->entries[i-1].vddgfx);
1518 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1519 allowed_clock_voltage_table->entries[i-1].vddc);
1520
1521 if (allowed_clock_voltage_table->entries[i-1].vddci) {
1522 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1523 allowed_clock_voltage_table->entries[i-1].vddci);
1524 }
1525 if (allowed_clock_voltage_table->entries[i-1].mvdd) {
1526 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
1527 }
1528
1529 return 0;
1530}
1531
1532/**
1533 * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1534 *
1535 * @param hwmgr the address of the powerplay hardware manager.
1536 * @return always 0
1537 */
1538int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
1539{
1540 return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
1541}
1542
1543int tonga_populate_memory_timing_parameters(
1544 struct pp_hwmgr *hwmgr,
1545 uint32_t engine_clock,
1546 uint32_t memory_clock,
1547 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1548 )
1549{
1550 uint32_t dramTiming;
1551 uint32_t dramTiming2;
1552 uint32_t burstTime;
1553 int result;
1554
1555 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1556 engine_clock, memory_clock);
1557
1558 PP_ASSERT_WITH_CODE(result == 0,
1559 "Error calling VBIOS to set DRAM_TIMING.", return result);
1560
1561 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1562 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1563 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1564
1565 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1566 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1567 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1568
1569 return 0;
1570}
1571
1572/**
1573 * Setup parameters for the MC ARB.
1574 *
1575 * @param hwmgr the address of the powerplay hardware manager.
1576 * @return always 0
1577 * This function is to be called from the SetPowerState table.
1578 */
1579int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1580{
1581 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1582 int result = 0;
1583 SMU72_Discrete_MCArbDramTimingTable arb_regs;
1584 uint32_t i, j;
1585
1586 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1587
1588 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1589 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1590 result = tonga_populate_memory_timing_parameters
1591 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1592 data->dpm_table.mclk_table.dpm_levels[j].value,
1593 &arb_regs.entries[i][j]);
1594
1595 if (0 != result) {
1596 break;
1597 }
1598 }
1599 }
1600
1601 if (0 == result) {
1602 result = tonga_copy_bytes_to_smc(
1603 hwmgr->smumgr,
1604 data->arb_table_start,
1605 (uint8_t *)&arb_regs,
1606 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1607 data->sram_end
1608 );
1609 }
1610
1611 return result;
1612}
1613
1614static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
1615{
1616 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1617 struct tonga_dpm_table *dpm_table = &data->dpm_table;
1618 uint32_t i;
1619
1620 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1621 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1622 table->LinkLevel[i].PcieGenSpeed =
1623 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1624 table->LinkLevel[i].PcieLaneCount =
1625 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1626 table->LinkLevel[i].EnabledForActivity =
1627 1;
1628 table->LinkLevel[i].SPC =
1629 (uint8_t)(data->pcie_spc_cap & 0xff);
1630 table->LinkLevel[i].DownThreshold =
1631 PP_HOST_TO_SMC_UL(5);
1632 table->LinkLevel[i].UpThreshold =
1633 PP_HOST_TO_SMC_UL(30);
1634 }
1635
1636 data->smc_state_table.LinkLevelCount =
1637 (uint8_t)dpm_table->pcie_speed_table.count;
1638 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1639 tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1640
1641 return 0;
1642}
1643
0104aa21
AD		 1644static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1645 SMU72_Discrete_DpmTable *table)
1646{
1647 int result = 0;
1648
1649 uint8_t count;
1650 pp_atomctrl_clock_dividers_vi dividers;
1651 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1652 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1653 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1654
1655 table->UvdLevelCount = (uint8_t) (mm_table->count);
1656 table->UvdBootLevel = 0;
1657
1658 for (count = 0; count < table->UvdLevelCount; count++) {
1659 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1660 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1661 table->UvdLevel[count].MinVoltage.Vddc =
1662 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1663 mm_table->entries[count].vddc);
1664 table->UvdLevel[count].MinVoltage.VddGfx =
1665 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1666 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1667 mm_table->entries[count].vddgfx) : 0;
1668 table->UvdLevel[count].MinVoltage.Vddci =
1669 tonga_get_voltage_id(&data->vddci_voltage_table,
1670 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1671 table->UvdLevel[count].MinVoltage.Phases = 1;
1672
1673 /* retrieve divider value for VBIOS */
1674 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1675 table->UvdLevel[count].VclkFrequency, &dividers);
1676 PP_ASSERT_WITH_CODE((0 == result),
1677 "can not find divide id for Vclk clock", return result);
1678
1679 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1680
1681 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1682 table->UvdLevel[count].DclkFrequency, &dividers);
1683 PP_ASSERT_WITH_CODE((0 == result),
1684 "can not find divide id for Dclk clock", return result);
1685
1686 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1687
1688 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1689 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1690 //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
c15c8d70 1691 }
0104aa21 1692
c15c8d70 1693 return result;
0104aa21
AD		 1694
1695}
c82baa28 1696
1697static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1698 SMU72_Discrete_DpmTable *table)
1699{
1700 int result = 0;
1701
1702 uint8_t count;
1703 pp_atomctrl_clock_dividers_vi dividers;
1704 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1705 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1706 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1707
1708 table->VceLevelCount = (uint8_t) (mm_table->count);
1709 table->VceBootLevel = 0;
1710
1711 for (count = 0; count < table->VceLevelCount; count++) {
1712 table->VceLevel[count].Frequency =
1713 mm_table->entries[count].eclk;
1714 table->VceLevel[count].MinVoltage.Vddc =
1715 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1716 mm_table->entries[count].vddc);
1717 table->VceLevel[count].MinVoltage.VddGfx =
1718 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1719 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1720 mm_table->entries[count].vddgfx) : 0;
1721 table->VceLevel[count].MinVoltage.Vddci =
1722 tonga_get_voltage_id(&data->vddci_voltage_table,
1723 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1724 table->VceLevel[count].MinVoltage.Phases = 1;
1725
1726 /* retrieve divider value for VBIOS */
1727 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1728 table->VceLevel[count].Frequency, &dividers);
1729 PP_ASSERT_WITH_CODE((0 == result),
1730 "can not find divide id for VCE engine clock", return result);
1731
c15c8d70 1732 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
c82baa28 1733
1734 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1735 }
1736
1737 return result;
1738}
1739
1740static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1741 SMU72_Discrete_DpmTable *table)
1742{
1743 int result = 0;
1744 uint8_t count;
1745 pp_atomctrl_clock_dividers_vi dividers;
1746 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1747 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1748 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1749
1750 table->AcpLevelCount = (uint8_t) (mm_table->count);
1751 table->AcpBootLevel = 0;
1752
1753 for (count = 0; count < table->AcpLevelCount; count++) {
1754 table->AcpLevel[count].Frequency =
1755 pptable_info->mm_dep_table->entries[count].aclk;
1756 table->AcpLevel[count].MinVoltage.Vddc =
1757 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1758 mm_table->entries[count].vddc);
1759 table->AcpLevel[count].MinVoltage.VddGfx =
1760 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1761 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1762 mm_table->entries[count].vddgfx) : 0;
1763 table->AcpLevel[count].MinVoltage.Vddci =
1764 tonga_get_voltage_id(&data->vddci_voltage_table,
1765 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1766 table->AcpLevel[count].MinVoltage.Phases = 1;
1767
1768 /* retrieve divider value for VBIOS */
1769 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1770 table->AcpLevel[count].Frequency, &dividers);
1771 PP_ASSERT_WITH_CODE((0 == result),
1772 "can not find divide id for engine clock", return result);
1773
1774 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1775
1776 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1777 }
1778
1779 return result;
1780}
1781
1782static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1783 SMU72_Discrete_DpmTable *table)
1784{
1785 int result = 0;
1786 uint8_t count;
1787 pp_atomctrl_clock_dividers_vi dividers;
1788 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1789 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1790 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1791
1792 table->SamuBootLevel = 0;
1793 table->SamuLevelCount = (uint8_t) (mm_table->count);
1794
1795 for (count = 0; count < table->SamuLevelCount; count++) {
1796 /* not sure whether we need evclk or not */
1797 table->SamuLevel[count].Frequency =
1798 pptable_info->mm_dep_table->entries[count].samclock;
1799 table->SamuLevel[count].MinVoltage.Vddc =
1800 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1801 mm_table->entries[count].vddc);
1802 table->SamuLevel[count].MinVoltage.VddGfx =
1803 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1804 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1805 mm_table->entries[count].vddgfx) : 0;
1806 table->SamuLevel[count].MinVoltage.Vddci =
1807 tonga_get_voltage_id(&data->vddci_voltage_table,
1808 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1809 table->SamuLevel[count].MinVoltage.Phases = 1;
1810
1811 /* retrieve divider value for VBIOS */
1812 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1813 table->SamuLevel[count].Frequency, &dividers);
1814 PP_ASSERT_WITH_CODE((0 == result),
1815 "can not find divide id for samu clock", return result);
1816
c15c8d70 1817 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
c82baa28 1818
1819 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1820 }
1821
1822 return result;
1823}
1824
1825/**
1826 * Populates the SMC MCLK structure using the provided memory clock
1827 *
1828 * @param hwmgr the address of the hardware manager
1829 * @param memory_clock the memory clock to use to populate the structure
1830 * @param sclk the SMC SCLK structure to be populated
1831 */
1832static int tonga_calculate_mclk_params(
1833 struct pp_hwmgr *hwmgr,
1834 uint32_t memory_clock,
1835 SMU72_Discrete_MemoryLevel *mclk,
1836 bool strobe_mode,
1837 bool dllStateOn
1838 )
1839{
1840 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1841 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1842 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1843 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1844 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1845 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1846 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1847 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1848 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1849 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1850
1851 pp_atomctrl_memory_clock_param mpll_param;
1852 int result;
1853
1854 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1855 memory_clock, &mpll_param, strobe_mode);
1856 PP_ASSERT_WITH_CODE(0 == result,
1857 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1858
1859 /* MPLL_FUNC_CNTL setup*/
c15c8d70 1860 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
c82baa28 1861
1862 /* MPLL_FUNC_CNTL_1 setup*/
1863 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1864 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1865 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1866 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1867 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1868 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1869
1870 /* MPLL_AD_FUNC_CNTL setup*/
1871 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1872 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1873
1874 if (data->is_memory_GDDR5) {
1875 /* MPLL_DQ_FUNC_CNTL setup*/
1876 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1877 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1878 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1879 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1880 }
1881
1882 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1883 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1884 /*
1885 ************************************
1886 Fref = Reference Frequency
1887 NF = Feedback divider ratio
1888 NR = Reference divider ratio
1889 Fnom = Nominal VCO output frequency = Fref * NF / NR
1890 Fs = Spreading Rate
1891 D = Percentage down-spread / 2
1892 Fint = Reference input frequency to PFD = Fref / NR
1893 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1894 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1895 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1896 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1897 *************************************
1898 */
1899 pp_atomctrl_internal_ss_info ss_info;
1900 uint32_t freq_nom;
1901 uint32_t tmp;
1902 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1903
1904 /* for GDDR5 for all modes and DDR3 */
1905 if (1 == mpll_param.qdr)
1906 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1907 else
1908 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1909
1910 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1911 tmp = (freq_nom / reference_clock);
1912 tmp = tmp * tmp;
1913
1914 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1915 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1916 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1917 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1918 /* = reference_clock * 5 / speed_spectrum_rate */
1919 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1920
1921 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1922 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1923 uint32_t clkv =
1924 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1925 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1926
1927 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1928 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1929 }
1930 }
1931
1932 /* MCLK_PWRMGT_CNTL setup */
1933 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1934 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1935 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1936 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1937 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1938 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1939
1940
1941 /* Save the result data to outpupt memory level structure */
1942 mclk->MclkFrequency = memory_clock;
1943 mclk->MpllFuncCntl = mpll_func_cntl;
1944 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1945 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1946 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1947 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1948 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1949 mclk->DllCntl = dll_cntl;
1950 mclk->MpllSs1 = mpll_ss1;
1951 mclk->MpllSs2 = mpll_ss2;
1952
1953 return 0;
1954}
1955
1956static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
1957 bool strobe_mode)
1958{
1959 uint8_t mc_para_index;
1960
1961 if (strobe_mode) {
1962 if (memory_clock < 12500) {
1963 mc_para_index = 0x00;
1964 } else if (memory_clock > 47500) {
1965 mc_para_index = 0x0f;
1966 } else {
1967 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1968 }
1969 } else {
1970 if (memory_clock < 65000) {
1971 mc_para_index = 0x00;
1972 } else if (memory_clock > 135000) {
1973 mc_para_index = 0x0f;
1974 } else {
1975 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1976 }
1977 }
1978
1979 return mc_para_index;
1980}
1981
1982static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1983{
1984 uint8_t mc_para_index;
1985
1986 if (memory_clock < 10000) {
1987 mc_para_index = 0;
1988 } else if (memory_clock >= 80000) {
1989 mc_para_index = 0x0f;
1990 } else {
1991 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1992 }
1993
1994 return mc_para_index;
1995}
1996
1997static int tonga_populate_single_memory_level(
1998 struct pp_hwmgr *hwmgr,
1999 uint32_t memory_clock,
2000 SMU72_Discrete_MemoryLevel *memory_level
2001 )
2002{
2003 uint32_t minMvdd = 0;
2004 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2005 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2006 int result = 0;
2007 bool dllStateOn;
2008 struct cgs_display_info info = {0};
2009
2010
2011 if (NULL != pptable_info->vdd_dep_on_mclk) {
2012 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2013 pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
2014 PP_ASSERT_WITH_CODE((0 == result),
2015 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
2016 }
2017
2018 if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
2019 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
2020 } else {
2021 memory_level->MinMvdd = minMvdd;
2022 }
2023 memory_level->EnabledForThrottle = 1;
2024 memory_level->EnabledForActivity = 0;
2025 memory_level->UpHyst = 0;
2026 memory_level->DownHyst = 100;
2027 memory_level->VoltageDownHyst = 0;
2028
2029 /* Indicates maximum activity level for this performance level.*/
2030 memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2031 memory_level->StutterEnable = 0;
2032 memory_level->StrobeEnable = 0;
2033 memory_level->EdcReadEnable = 0;
2034 memory_level->EdcWriteEnable = 0;
2035 memory_level->RttEnable = 0;
2036
2037 /* default set to low watermark. Highest level will be set to high later.*/
2038 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2039
2040 cgs_get_active_displays_info(hwmgr->device, &info);
2041 data->display_timing.num_existing_displays = info.display_count;
2042
2043 if ((data->mclk_stutter_mode_threshold != 0) &&
7e8d1fbd
AD		 2044 (memory_clock <= data->mclk_stutter_mode_threshold) &&
2045 (data->is_uvd_enabled == 0)
2046 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
2047 && (data->display_timing.num_existing_displays <= 2)
2048 && (data->display_timing.num_existing_displays != 0))
c82baa28 2049 memory_level->StutterEnable = 1;
2050
2051 /* decide strobe mode*/
2052 memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
2053 (memory_clock <= data->mclk_strobe_mode_threshold);
2054
2055 /* decide EDC mode and memory clock ratio*/
2056 if (data->is_memory_GDDR5) {
2057 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
2058 memory_level->StrobeEnable);
2059
2060 if ((data->mclk_edc_enable_threshold != 0) &&
2061 (memory_clock > data->mclk_edc_enable_threshold)) {
2062 memory_level->EdcReadEnable = 1;
2063 }
2064
2065 if ((data->mclk_edc_wr_enable_threshold != 0) &&
2066 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
2067 memory_level->EdcWriteEnable = 1;
2068 }
2069
2070 if (memory_level->StrobeEnable) {
2071 if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
2072 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
2073 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2074 } else {
2075 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
2076 }
2077
2078 } else {
2079 dllStateOn = data->dll_defaule_on;
2080 }
2081 } else {
2082 memory_level->StrobeRatio =
2083 tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
2084 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2085 }
2086
2087 result = tonga_calculate_mclk_params(hwmgr,
2088 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
2089
2090 if (0 == result) {
2091 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
2092 /* MCLK frequency in units of 10KHz*/
2093 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
2094 /* Indicates maximum activity level for this performance level.*/
2095 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
2096 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
2097 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
2098 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
2099 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2100 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2101 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2102 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2103 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2104 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2105 }
2106
2107 return result;
2108}
2109
2110/**
2111 * Populates the SMC MVDD structure using the provided memory clock.
2112 *
2113 * @param hwmgr the address of the hardware manager
2114 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2115 * @param voltage the SMC VOLTAGE structure to be populated
2116 */
2117int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
2118{
2119 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2120 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2121 uint32_t i = 0;
2122
2123 if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2124 /* find mvdd value which clock is more than request */
2125 for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
2126 if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
2127 /* Always round to higher voltage. */
2128 smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
2129 break;
2130 }
2131 }
2132
2133 PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
2134 "MVDD Voltage is outside the supported range.", return -1);
2135
2136 } else {
2137 return -1;
2138 }
2139
2140 return 0;
2141}
2142
2143
2144static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
2145 SMU72_Discrete_DpmTable *table)
2146{
2147 int result = 0;
2148 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2149 pp_atomctrl_clock_dividers_vi dividers;
2150 SMIO_Pattern voltage_level;
2151 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2152 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2153 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
2154 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
2155
2156 /* The ACPI state should not do DPM on DC (or ever).*/
2157 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2158
2159 table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
2160
2161 /* assign zero for now*/
2162 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2163
2164 /* get the engine clock dividers for this clock value*/
2165 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2166 table->ACPILevel.SclkFrequency, &dividers);
2167
2168 PP_ASSERT_WITH_CODE(result == 0,
2169 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2170
2171 /* divider ID for required SCLK*/
2172 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2173 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2174 table->ACPILevel.DeepSleepDivId = 0;
2175
2176 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2177 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
2178 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2179 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
2180 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
2181 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
2182
2183 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2184 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2185 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2186 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2187 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2188 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2189 table->ACPILevel.CcPwrDynRm = 0;
2190 table->ACPILevel.CcPwrDynRm1 = 0;
2191
2192
2193 /* For various features to be enabled/disabled while this level is active.*/
2194 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2195 /* SCLK frequency in units of 10KHz*/
2196 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2197 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2198 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2199 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2200 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2201 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2202 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2203 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2204 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2205
2206 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
2207 table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
2208
2209 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2210
2211 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
2212 table->MemoryACPILevel.MinMvdd =
2213 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2214 else
2215 table->MemoryACPILevel.MinMvdd = 0;
2216
2217 /* Force reset on DLL*/
2218 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2219 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2220 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2221 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2222
2223 /* Disable DLL in ACPIState*/
2224 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2225 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2226 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2227 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2228
2229 /* Enable DLL bypass signal*/
2230 dll_cntl = PHM_SET_FIELD(dll_cntl,
2231 DLL_CNTL, MRDCK0_BYPASS, 0);
2232 dll_cntl = PHM_SET_FIELD(dll_cntl,
2233 DLL_CNTL, MRDCK1_BYPASS, 0);
2234
2235 table->MemoryACPILevel.DllCntl =
2236 PP_HOST_TO_SMC_UL(dll_cntl);
2237 table->MemoryACPILevel.MclkPwrmgtCntl =
2238 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2239 table->MemoryACPILevel.MpllAdFuncCntl =
2240 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2241 table->MemoryACPILevel.MpllDqFuncCntl =
2242 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2243 table->MemoryACPILevel.MpllFuncCntl =
2244 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2245 table->MemoryACPILevel.MpllFuncCntl_1 =
2246 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2247 table->MemoryACPILevel.MpllFuncCntl_2 =
2248 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2249 table->MemoryACPILevel.MpllSs1 =
2250 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2251 table->MemoryACPILevel.MpllSs2 =
2252 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2253
2254 table->MemoryACPILevel.EnabledForThrottle = 0;
2255 table->MemoryACPILevel.EnabledForActivity = 0;
2256 table->MemoryACPILevel.UpHyst = 0;
2257 table->MemoryACPILevel.DownHyst = 100;
2258 table->MemoryACPILevel.VoltageDownHyst = 0;
2259 /* Indicates maximum activity level for this performance level.*/
2260 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2261
2262 table->MemoryACPILevel.StutterEnable = 0;
2263 table->MemoryACPILevel.StrobeEnable = 0;
2264 table->MemoryACPILevel.EdcReadEnable = 0;
2265 table->MemoryACPILevel.EdcWriteEnable = 0;
2266 table->MemoryACPILevel.RttEnable = 0;
2267
2268 return result;
2269}
2270
2271static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2272{
2273 int result = 0;
2274 uint32_t i;
2275
2276 for (i = 0; i < table->count; i++) {
2277 if (value == table->dpm_levels[i].value) {
2278 *boot_level = i;
2279 result = 0;
2280 }
2281 }
2282 return result;
2283}
2284
2285static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2286 SMU72_Discrete_DpmTable *table)
2287{
2288 int result = 0;
2289 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2290
2291 table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2292 table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2293
2294 /* find boot level from dpm table*/
2295 result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
2296 data->vbios_boot_state.sclk_bootup_value,
2297 (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2298
2299 if (0 != result) {
2300 data->smc_state_table.GraphicsBootLevel = 0;
2301 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2302 in dependency table. Using Graphics DPM level 0!");
2303 result = 0;
2304 }
2305
2306 result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
2307 data->vbios_boot_state.mclk_bootup_value,
2308 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2309
2310 if (0 != result) {
2311 data->smc_state_table.MemoryBootLevel = 0;
2312 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2313 in dependency table. Using Memory DPM level 0!");
2314 result = 0;
2315 }
2316
2317 table->BootVoltage.Vddc =
2318 tonga_get_voltage_id(&(data->vddc_voltage_table),
2319 data->vbios_boot_state.vddc_bootup_value);
2320 table->BootVoltage.VddGfx =
2321 tonga_get_voltage_id(&(data->vddgfx_voltage_table),
2322 data->vbios_boot_state.vddgfx_bootup_value);
2323 table->BootVoltage.Vddci =
2324 tonga_get_voltage_id(&(data->vddci_voltage_table),
2325 data->vbios_boot_state.vddci_bootup_value);
2326 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2327
2328 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2329
2330 return result;
2331}
2332
2333
2334/**
2335 * Calculates the SCLK dividers using the provided engine clock
2336 *
2337 * @param hwmgr the address of the hardware manager
2338 * @param engine_clock the engine clock to use to populate the structure
2339 * @param sclk the SMC SCLK structure to be populated
2340 */
2341int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2342 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
2343{
2344 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2345 pp_atomctrl_clock_dividers_vi dividers;
2346 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2347 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2348 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2349 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2350 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2351 uint32_t reference_clock;
2352 uint32_t reference_divider;
2353 uint32_t fbdiv;
2354 int result;
2355
2356 /* get the engine clock dividers for this clock value*/
2357 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
2358
2359 PP_ASSERT_WITH_CODE(result == 0,
2360 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2361
2362 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2363 reference_clock = atomctrl_get_reference_clock(hwmgr);
2364
2365 reference_divider = 1 + dividers.uc_pll_ref_div;
2366
2367 /* low 14 bits is fraction and high 12 bits is divider*/
2368 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2369
2370 /* SPLL_FUNC_CNTL setup*/
2371 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2372 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2373 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2374 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
2375
2376 /* SPLL_FUNC_CNTL_3 setup*/
2377 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2378 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2379
2380 /* set to use fractional accumulation*/
2381 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2382 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2383
2384 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2385 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2386 pp_atomctrl_internal_ss_info ss_info;
2387
2388 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2389 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2390 /*
2391 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2392 * ss_info.speed_spectrum_rate -- in unit of khz
2393 */
2394 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2395 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2396
2397 /* clkv = 2 * D * fbdiv / NS */
2398 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2399
2400 cg_spll_spread_spectrum =
2401 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2402 cg_spll_spread_spectrum =
2403 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2404 cg_spll_spread_spectrum_2 =
2405 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2406 }
2407 }
2408
2409 sclk->SclkFrequency = engine_clock;
2410 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2411 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2412 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2413 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2414 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
2415
2416 return 0;
2417}
2418
a4333b4c
EH		 2419static uint8_t tonga_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
2420 uint32_t engine_clock, uint32_t min_engine_clock_in_sr)
2421{
2422 uint32_t i, temp;
2423 uint32_t min = (min_engine_clock_in_sr > TONGA_MINIMUM_ENGINE_CLOCK) ?
2424 min_engine_clock_in_sr : TONGA_MINIMUM_ENGINE_CLOCK;
2425
2426 PP_ASSERT_WITH_CODE((engine_clock >= min),
2427 "Engine clock can't satisfy stutter requirement!", return 0);
2428
2429 for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
2430 temp = engine_clock / (1 << i);
2431
2432 if(temp >= min || i == 0)
2433 break;
2434 }
2435 return (uint8_t)i;
2436}
2437
c82baa28 2438/**
2439 * Populates single SMC SCLK structure using the provided engine clock
2440 *
2441 * @param hwmgr the address of the hardware manager
2442 * @param engine_clock the engine clock to use to populate the structure
2443 * @param sclk the SMC SCLK structure to be populated
2444 */
2445static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
2446{
2447 int result;
2448 uint32_t threshold;
2449 uint32_t mvdd;
2450 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2451 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2452
2453 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2454
2455
2456 /* populate graphics levels*/
2457 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2458 pptable_info->vdd_dep_on_sclk, engine_clock,
2459 &graphic_level->MinVoltage, &mvdd);
2460 PP_ASSERT_WITH_CODE((0 == result),
2461 "can not find VDDC voltage value for VDDC \
2462 engine clock dependency table", return result);
2463
2464 /* SCLK frequency in units of 10KHz*/
2465 graphic_level->SclkFrequency = engine_clock;
2466
2467 /* Indicates maximum activity level for this performance level. 50% for now*/
2468 graphic_level->ActivityLevel = sclk_activity_level_threshold;
2469
2470 graphic_level->CcPwrDynRm = 0;
2471 graphic_level->CcPwrDynRm1 = 0;
2472 /* this level can be used if activity is high enough.*/
2473 graphic_level->EnabledForActivity = 0;
2474 /* this level can be used for throttling.*/
2475 graphic_level->EnabledForThrottle = 1;
2476 graphic_level->UpHyst = 0;
2477 graphic_level->DownHyst = 0;
2478 graphic_level->VoltageDownHyst = 0;
2479 graphic_level->PowerThrottle = 0;
2480
2481 threshold = engine_clock * data->fast_watemark_threshold / 100;
2482/*
2483 *get the DAL clock. do it in funture.
2484 PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
2485 data->display_timing.min_clock_insr = minClocks.engineClockInSR;
c82baa28 2486*/
a4333b4c
EH		 2487 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2488 PHM_PlatformCaps_SclkDeepSleep))
2489 graphic_level->DeepSleepDivId =
2490 tonga_get_sleep_divider_id_from_clock(hwmgr, engine_clock,
2491 data->display_timing.min_clock_insr);
c82baa28 2492
2493 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2494 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2495
2496 if (0 == result) {
2497 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2498 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
2499 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2500 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2501 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2502 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2503 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2504 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2505 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2506 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2507 }
2508
2509 return result;
2510}
2511
2512/**
2513 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2514 *
2515 * @param hwmgr the address of the hardware manager
2516 */
2517static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2518{
2519 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2520 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2521 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2522 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2523 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2524 int result = 0;
2525 uint32_t level_array_adress = data->dpm_table_start +
2526 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
2527 uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
2528 SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/
2529 SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2530 uint32_t i, maxEntry;
2531 uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2532 PECI_RegistryValue reg_value;
2533 memset(levels, 0x00, level_array_size);
2534
2535 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2536 result = tonga_populate_single_graphic_level(hwmgr,
2537 dpm_table->sclk_table.dpm_levels[i].value,
2538 (uint16_t)data->activity_target[i],
2539 &(data->smc_state_table.GraphicsLevel[i]));
2540
2541 if (0 != result)
2542 return result;
2543
2544 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2545 if (i > 1)
2546 data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2547
2548 if (0 == i) {
2549 reg_value = 0;
2550 if (reg_value != 0)
2551 data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
2552 }
2553
2554 if (1 == i) {
2555 reg_value = 0;
2556 if (reg_value != 0)
2557 data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
2558 }
2559 }
2560
2561 /* Only enable level 0 for now. */
2562 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2563
2564 /* set highest level watermark to high */
2565 if (dpm_table->sclk_table.count > 1)
2566 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2567 PPSMC_DISPLAY_WATERMARK_HIGH;
2568
2569 data->smc_state_table.GraphicsDpmLevelCount =
2570 (uint8_t)dpm_table->sclk_table.count;
2571 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2572 tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2573
2574 if (pcie_table != NULL) {
2575 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
2576 "There must be 1 or more PCIE levels defined in PPTable.", return -1);
2577 maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
2578 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2579 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
2580 (uint8_t) ((i < maxEntry) ? i : maxEntry);
2581 }
2582 } else {
2583 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
2584 printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
2585
2586 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2587 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2588 (1<<(highest_pcie_level_enabled+1))) != 0)) {
2589 highest_pcie_level_enabled++;
2590 }
2591
2592 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2593 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2594 (1<<lowest_pcie_level_enabled)) == 0)) {
2595 lowest_pcie_level_enabled++;
2596 }
2597
2598 while ((count < highest_pcie_level_enabled) &&
2599 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2600 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
2601 count++;
2602 }
2603 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2604 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
2605
2606
2607 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2608 for (i = 2; i < dpm_table->sclk_table.count; i++) {
2609 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2610 }
2611
2612 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2613 data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2614
2615 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2616 data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2617 }
2618 /* level count will send to smc once at init smc table and never change*/
2619 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2620
2621 if (0 != result)
2622 return result;
2623
2624 return 0;
2625}
2626
2627/**
2628 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2629 *
2630 * @param hwmgr the address of the hardware manager
2631 */
2632
2633static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2634{
2635 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2636 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2637 int result;
2638 /* populate MCLK dpm table to SMU7 */
2639 uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
2640 uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
2641 SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2642 uint32_t i;
2643
2644 memset(levels, 0x00, level_array_size);
2645
2646 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2647 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2648 "can not populate memory level as memory clock is zero", return -1);
2649 result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2650 &(data->smc_state_table.MemoryLevel[i]));
2651 if (0 != result) {
2652 return result;
2653 }
2654 }
2655
2656 /* Only enable level 0 for now.*/
2657 data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2658
2659 /*
2660 * in order to prevent MC activity from stutter mode to push DPM up.
2661 * the UVD change complements this by putting the MCLK in a higher state
2662 * by default such that we are not effected by up threshold or and MCLK DPM latency.
2663 */
2664 data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2665 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2666
2667 data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2668 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2669 /* set highest level watermark to high*/
2670 data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2671
2672 /* level count will send to smc once at init smc table and never change*/
2673 result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
2674 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2675
2676 if (0 != result) {
2677 return result;
2678 }
2679
2680 return 0;
2681}
2682
2683struct TONGA_DLL_SPEED_SETTING {
2684 uint16_t Min; /* Minimum Data Rate*/
2685 uint16_t Max; /* Maximum Data Rate*/
2686 uint32_t dll_speed; /* The desired DLL_SPEED setting*/
2687};
2688
2689static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2690{
2691 return 0;
2692}
2693
2694/* ---------------------------------------- ULV related functions ----------------------------------------------------*/
2695
2696
2697static int tonga_reset_single_dpm_table(
2698 struct pp_hwmgr *hwmgr,
2699 struct tonga_single_dpm_table *dpm_table,
2700 uint32_t count)
2701{
2702 uint32_t i;
2703 if (!(count <= MAX_REGULAR_DPM_NUMBER))
2704 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
2705 table entries to exceed max number! \n");
2706
2707 dpm_table->count = count;
2708 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
2709 dpm_table->dpm_levels[i].enabled = 0;
2710 }
2711
2712 return 0;
2713}
2714
2715static void tonga_setup_pcie_table_entry(
2716 struct tonga_single_dpm_table *dpm_table,
2717 uint32_t index, uint32_t pcie_gen,
2718 uint32_t pcie_lanes)
2719{
2720 dpm_table->dpm_levels[index].value = pcie_gen;
2721 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2722 dpm_table->dpm_levels[index].enabled = 1;
2723}
2724
c82baa28 2725static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2726{
2727 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2728 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2729 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2730 uint32_t i, maxEntry;
2731
2732 if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
2733 data->pcie_gen_power_saving = data->pcie_gen_performance;
2734 data->pcie_lane_power_saving = data->pcie_lane_performance;
2735 } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
2736 data->pcie_gen_performance = data->pcie_gen_power_saving;
2737 data->pcie_lane_performance = data->pcie_lane_power_saving;
2738 }
2739
2740 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
2741
2742 if (pcie_table != NULL) {
2743 /*
2744 * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
2745 * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
2746 */
2747 maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
2748 SMU72_MAX_LEVELS_LINK : pcie_table->count;
2749 for (i = 1; i < maxEntry; i++) {
2750 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
2751 get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
2752 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2753 }
2754 data->dpm_table.pcie_speed_table.count = maxEntry - 1;
2755 } else {
2756 /* Hardcode Pcie Table */
2757 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
2758 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2759 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2760 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
2761 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2762 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2763 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
2764 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2765 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2766 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
2767 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2768 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2769 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
2770 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2771 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2772 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
2773 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2774 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2775 data->dpm_table.pcie_speed_table.count = 6;
2776 }
2777 /* Populate last level for boot PCIE level, but do not increment count. */
2778 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
2779 data->dpm_table.pcie_speed_table.count,
2780 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2781 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2782
2783 return 0;
2784
2785}
2786
2787/*
2788 * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
2789 * Dynamic state patching function will then trim these state tables to the allowed range based
2790 * on the power policy or external client requests, such as UVD request, etc.
2791 */
2792static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
2793{
2794 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2795 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2796 uint32_t i;
2797
2798 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
2799 pptable_info->vdd_dep_on_sclk;
2800 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
2801 pptable_info->vdd_dep_on_mclk;
2802
2803 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2804 "SCLK dependency table is missing. This table is mandatory", return -1);
2805 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
2806 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
2807
2808 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2809 "MCLK dependency table is missing. This table is mandatory", return -1);
2810 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
2811 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
2812
2813 /* clear the state table to reset everything to default */
2814 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
2815 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
2816 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
2817 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
2818 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
2819 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
2820 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
2821
2822 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2823 "SCLK dependency table is missing. This table is mandatory", return -1);
2824 /* Initialize Sclk DPM table based on allow Sclk values*/
2825 data->dpm_table.sclk_table.count = 0;
2826
2827 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2828 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
2829 allowed_vdd_sclk_table->entries[i].clk) {
2830 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
2831 allowed_vdd_sclk_table->entries[i].clk;
2832 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
2833 data->dpm_table.sclk_table.count++;
2834 }
2835 }
2836
2837 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2838 "MCLK dependency table is missing. This table is mandatory", return -1);
2839 /* Initialize Mclk DPM table based on allow Mclk values */
2840 data->dpm_table.mclk_table.count = 0;
2841 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2842 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
2843 allowed_vdd_mclk_table->entries[i].clk) {
2844 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
2845 allowed_vdd_mclk_table->entries[i].clk;
2846 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
2847 data->dpm_table.mclk_table.count++;
2848 }
2849 }
2850
2851 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
2852 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2853 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
2854 /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
2855 /* param1 is for corresponding std voltage */
2856 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
2857 }
2858 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
2859
2860 if (NULL != allowed_vdd_mclk_table) {
2861 /* Initialize Vddci DPM table based on allow Mclk values */
2862 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2863 data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
2864 data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
2865 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
2866 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
2867 }
2868 data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
2869 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
2870 }
2871
2872 /* setup PCIE gen speed levels*/
2873 tonga_setup_default_pcie_tables(hwmgr);
2874
2875 /* save a copy of the default DPM table*/
2876 memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
2877
2878 return 0;
2879}
2880
2881int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
2882 const struct tonga_power_state *bootState)
2883{
2884 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2885 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2886 uint8_t count, level;
2887
2888 count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
2889 for (level = 0; level < count; level++) {
2890 if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
2891 bootState->performance_levels[0].engine_clock) {
2892 data->smc_state_table.GraphicsBootLevel = level;
2893 break;
2894 }
2895 }
2896
2897 count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
2898 for (level = 0; level < count; level++) {
2899 if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
2900 bootState->performance_levels[0].memory_clock) {
2901 data->smc_state_table.MemoryBootLevel = level;
2902 break;
2903 }
2904 }
2905
2906 return 0;
2907}
2908
2909/**
2910 * Initializes the SMC table and uploads it
2911 *
2912 * @param hwmgr the address of the powerplay hardware manager.
2913 * @param pInput the pointer to input data (PowerState)
2914 * @return always 0
2915 */
2916int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2917{
2918 int result;
2919 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2920 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2921 SMU72_Discrete_DpmTable *table = &(data->smc_state_table);
2922 const phw_tonga_ulv_parm *ulv = &(data->ulv);
2923 uint8_t i;
2924 PECI_RegistryValue reg_value;
2925 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2926
2927 result = tonga_setup_default_dpm_tables(hwmgr);
2928 PP_ASSERT_WITH_CODE(0 == result,
2929 "Failed to setup default DPM tables!", return result;);
2930 memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2931 if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2932 tonga_populate_smc_voltage_tables(hwmgr, table);
2933 }
2934
2935 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2936 PHM_PlatformCaps_AutomaticDCTransition)) {
2937 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2938 }
2939
2940 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2941 PHM_PlatformCaps_StepVddc)) {
2942 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2943 }
2944
2945 if (data->is_memory_GDDR5) {
2946 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2947 }
2948
2949 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2950
2951 if (i == 1 || i == 0) {
2952 table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
2953 }
2954
2955 if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
2956 PP_ASSERT_WITH_CODE(0 == result,
2957 "Failed to initialize ULV state!", return result;);
2958
2959 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2960 ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
2961 }
2962
2963 result = tonga_populate_smc_link_level(hwmgr, table);
2964 PP_ASSERT_WITH_CODE(0 == result,
2965 "Failed to initialize Link Level!", return result;);
2966
2967 result = tonga_populate_all_graphic_levels(hwmgr);
2968 PP_ASSERT_WITH_CODE(0 == result,
2969 "Failed to initialize Graphics Level!", return result;);
2970
2971 result = tonga_populate_all_memory_levels(hwmgr);
2972 PP_ASSERT_WITH_CODE(0 == result,
2973 "Failed to initialize Memory Level!", return result;);
2974
2975 result = tonga_populate_smv_acpi_level(hwmgr, table);
2976 PP_ASSERT_WITH_CODE(0 == result,
2977 "Failed to initialize ACPI Level!", return result;);
2978
2979 result = tonga_populate_smc_vce_level(hwmgr, table);
2980 PP_ASSERT_WITH_CODE(0 == result,
2981 "Failed to initialize VCE Level!", return result;);
2982
2983 result = tonga_populate_smc_acp_level(hwmgr, table);
2984 PP_ASSERT_WITH_CODE(0 == result,
2985 "Failed to initialize ACP Level!", return result;);
2986
2987 result = tonga_populate_smc_samu_level(hwmgr, table);
2988 PP_ASSERT_WITH_CODE(0 == result,
2989 "Failed to initialize SAMU Level!", return result;);
2990
2991 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2992 /* need to populate the ARB settings for the initial state. */
2993 result = tonga_program_memory_timing_parameters(hwmgr);
2994 PP_ASSERT_WITH_CODE(0 == result,
2995 "Failed to Write ARB settings for the initial state.", return result;);
2996
0104aa21
AD		 2997 result = tonga_populate_smc_uvd_level(hwmgr, table);
2998 PP_ASSERT_WITH_CODE(0 == result,
2999 "Failed to initialize UVD Level!", return result;);
3000
c82baa28 3001 result = tonga_populate_smc_boot_level(hwmgr, table);
3002 PP_ASSERT_WITH_CODE(0 == result,
3003 "Failed to initialize Boot Level!", return result;);
3004
3005 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3006 PHM_PlatformCaps_ClockStretcher)) {
3007 result = tonga_populate_clock_stretcher_data_table(hwmgr);
3008 PP_ASSERT_WITH_CODE(0 == result,
3009 "Failed to populate Clock Stretcher Data Table!", return result;);
3010 }
3011 table->GraphicsVoltageChangeEnable = 1;
3012 table->GraphicsThermThrottleEnable = 1;
3013 table->GraphicsInterval = 1;
3014 table->VoltageInterval = 1;
3015 table->ThermalInterval = 1;
3016 table->TemperatureLimitHigh =
3017 pptable_info->cac_dtp_table->usTargetOperatingTemp *
3018 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3019 table->TemperatureLimitLow =
3020 (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3021 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3022 table->MemoryVoltageChangeEnable = 1;
3023 table->MemoryInterval = 1;
3024 table->VoltageResponseTime = 0;
3025 table->PhaseResponseTime = 0;
3026 table->MemoryThermThrottleEnable = 1;
3027
3028 /*
3029 * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
3030 * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
3031 * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
3032 * To avoid it, we set PCIeBootLinkLevel to highest dpm level
3033 */
3034 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
3035 "There must be 1 or more PCIE levels defined in PPTable.",
3036 return -1);
3037
3038 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
3039
3040 table->PCIeGenInterval = 1;
3041
3042 result = tonga_populate_vr_config(hwmgr, table);
3043 PP_ASSERT_WITH_CODE(0 == result,
3044 "Failed to populate VRConfig setting!", return result);
3045
3046 table->ThermGpio = 17;
3047 table->SclkStepSize = 0x4000;
3048
3049 reg_value = 0;
3050 if ((0 == reg_value) &&
3051 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3052 VDDC_VRHOT_GPIO_PINID, &gpio_pin_assignment))) {
3053 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3054 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3055 PHM_PlatformCaps_RegulatorHot);
3056 } else {
3057 table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
3058 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3059 PHM_PlatformCaps_RegulatorHot);
3060 }
3061
3062 /* ACDC Switch GPIO */
3063 reg_value = 0;
3064 if ((0 == reg_value) &&
3065 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3066 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin_assignment))) {
3067 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3068 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3069 PHM_PlatformCaps_AutomaticDCTransition);
3070 } else {
3071 table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
3072 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3073 PHM_PlatformCaps_AutomaticDCTransition);
3074 }
3075
3076 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3077 PHM_PlatformCaps_Falcon_QuickTransition);
3078
3079 reg_value = 0;
3080 if (1 == reg_value) {
3081 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3082 PHM_PlatformCaps_AutomaticDCTransition);
3083 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3084 PHM_PlatformCaps_Falcon_QuickTransition);
3085 }
3086
3087 reg_value = 0;
3088 if ((0 == reg_value) &&
3089 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3090 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
3091 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3092 PHM_PlatformCaps_ThermalOutGPIO);
3093
3094 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3095
3096 table->ThermOutPolarity =
3097 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3098 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
3099
3100 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3101
3102 /* if required, combine VRHot/PCC with thermal out GPIO*/
3103 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3104 PHM_PlatformCaps_RegulatorHot) &&
3105 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3106 PHM_PlatformCaps_CombinePCCWithThermalSignal)){
3107 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3108 }
3109 } else {
3110 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3111 PHM_PlatformCaps_ThermalOutGPIO);
3112
3113 table->ThermOutGpio = 17;
3114 table->ThermOutPolarity = 1;
3115 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3116 }
3117
3118 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
3119 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3120 }
3121 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3122 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3123 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3124 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3125 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3126 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3127 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3128 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3129 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3130
3131 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3132 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
3133 offsetof(SMU72_Discrete_DpmTable, SystemFlags),
3134 (uint8_t *)&(table->SystemFlags),
3135 sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
3136 data->sram_end);
3137
3138 PP_ASSERT_WITH_CODE(0 == result,
3139 "Failed to upload dpm data to SMC memory!", return result;);
3140
3141 return result;
3142}
3143
3144/* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
3145static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
3146{
3147 return;
3148}
3149
3150int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3151{
3152 PPSMC_Result result;
3153 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3154
3155 /* Apply minimum voltage based on DAL's request level */
3156 tonga_apply_dal_minimum_voltage_request(hwmgr);
3157
3158 if (0 == data->sclk_dpm_key_disabled) {
3159 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3160 if (0 != tonga_is_dpm_running(hwmgr))
3161 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3162
3163 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3164 result = smum_send_msg_to_smc_with_parameter(
3165 hwmgr->smumgr,
3166 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
3167 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3168 PP_ASSERT_WITH_CODE((0 == result),
3169 "Set Sclk Dpm enable Mask failed", return -1);
3170 }
3171 }
3172
3173 if (0 == data->mclk_dpm_key_disabled) {
3174 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3175 if (0 != tonga_is_dpm_running(hwmgr))
3176 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3177
3178 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3179 result = smum_send_msg_to_smc_with_parameter(
3180 hwmgr->smumgr,
3181 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
3182 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3183 PP_ASSERT_WITH_CODE((0 == result),
3184 "Set Mclk Dpm enable Mask failed", return -1);
3185 }
3186 }
3187
3188 return 0;
3189}
3190
3191
3192int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
3193{
3194 uint32_t level, tmp;
3195 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3196
3197 if (0 == data->pcie_dpm_key_disabled) {
3198 /* PCIE */
3199 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3200 level = 0;
3201 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3202 while (tmp >>= 1)
3203 level++ ;
3204
3205 if (0 != level) {
3206 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3207 "force highest pcie dpm state failed!", return -1);
3208 }
3209 }
3210 }
3211
3212 if (0 == data->sclk_dpm_key_disabled) {
3213 /* SCLK */
3214 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
3215 level = 0;
3216 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3217 while (tmp >>= 1)
3218 level++ ;
3219
3220 if (0 != level) {
3221 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3222 "force highest sclk dpm state failed!", return -1);
3223 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3224 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3225 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3226 Curr_Sclk_Index does not match the level \n");
3227
3228 }
3229 }
3230 }
3231
3232 if (0 == data->mclk_dpm_key_disabled) {
3233 /* MCLK */
3234 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3235 level = 0;
3236 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3237 while (tmp >>= 1)
3238 level++ ;
3239
3240 if (0 != level) {
3241 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3242 "force highest mclk dpm state failed!", return -1);
3243 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3244 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3245 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
9fe1837d 3246 Curr_Mclk_Index does not match the level \n");
c82baa28 3247 }
3248 }
3249 }
3250
3251 return 0;
3252}
3253
3254/**
3255 * Find the MC microcode version and store it in the HwMgr struct
3256 *
3257 * @param hwmgr the address of the powerplay hardware manager.
3258 * @return always 0
3259 */
3260int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
3261{
3262 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
3263
3264 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3265
3266 return 0;
3267}
3268
3269/**
3270 * Initialize Dynamic State Adjustment Rule Settings
3271 *
3272 * @param hwmgr the address of the powerplay hardware manager.
3273 */
3274int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3275{
3276 uint32_t table_size;
3277 struct phm_clock_voltage_dependency_table *table_clk_vlt;
3278 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3279
3280 hwmgr->dyn_state.mclk_sclk_ratio = 4;
3281 hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */
3282 hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */
3283
3284 /* initialize vddc_dep_on_dal_pwrl table */
3285 table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3286 table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
3287
3288 if (NULL == table_clk_vlt) {
3289 printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3290 return -ENOMEM;
3291 } else {
3292 table_clk_vlt->count = 4;
3293 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3294 table_clk_vlt->entries[0].v = 0;
3295 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3296 table_clk_vlt->entries[1].v = 720;
3297 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3298 table_clk_vlt->entries[2].v = 810;
3299 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3300 table_clk_vlt->entries[3].v = 900;
3301 pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
3302 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3303 }
3304
3305 return 0;
3306}
3307
3308static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3309{
3310 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3311 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3312
3313 phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3314 pptable_info->vdd_dep_on_sclk;
3315 phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3316 pptable_info->vdd_dep_on_mclk;
3317
3318 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3319 "VDD dependency on SCLK table is missing. \
3320 This table is mandatory", return -1);
3321 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3322 "VDD dependency on SCLK table has to have is missing. \
3323 This table is mandatory", return -1);
3324
3325 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3326 "VDD dependency on MCLK table is missing. \
3327 This table is mandatory", return -1);
3328 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3329 "VDD dependency on MCLK table has to have is missing. \
3330 This table is mandatory", return -1);
3331
3332 data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
3333 data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3334
3335 pptable_info->max_clock_voltage_on_ac.sclk =
3336 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3337 pptable_info->max_clock_voltage_on_ac.mclk =
3338 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3339 pptable_info->max_clock_voltage_on_ac.vddc =
3340 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3341 pptable_info->max_clock_voltage_on_ac.vddci =
3342 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3343
3344 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3345 pptable_info->max_clock_voltage_on_ac.sclk;
3346 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3347 pptable_info->max_clock_voltage_on_ac.mclk;
3348 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3349 pptable_info->max_clock_voltage_on_ac.vddc;
3350 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
3351 pptable_info->max_clock_voltage_on_ac.vddci;
3352
3353 return 0;
3354}
3355
3356int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3357{
3358 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3359 int result = 1;
3360
3361 PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr),
3362 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3363 return result);
3364
3365 if (0 == data->pcie_dpm_key_disabled) {
3366 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
3367 hwmgr->smumgr,
3368 PPSMC_MSG_PCIeDPM_UnForceLevel)),
3369 "unforce pcie level failed!",
3370 return -1);
3371 }
3372
3373 result = tonga_upload_dpm_level_enable_mask(hwmgr);
3374
3375 return result;
3376}
3377
3378static uint32_t tonga_get_lowest_enable_level(
3379 struct pp_hwmgr *hwmgr, uint32_t level_mask)
3380{
3381 uint32_t level = 0;
3382
3383 while (0 == (level_mask & (1 << level)))
3384 level++;
3385
3386 return level;
3387}
3388
3389static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3390{
9fe1837d 3391 uint32_t level;
c82baa28 3392 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3393
9fe1837d
AD		 3394 if (0 == data->pcie_dpm_key_disabled) {
3395 /* PCIE */
3396 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3397 level = tonga_get_lowest_enable_level(hwmgr,
3398 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3399 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3400 "force lowest pcie dpm state failed!", return -1);
3401 }
3402 }
3403
3404 if (0 == data->sclk_dpm_key_disabled) {
3405 /* SCLK */
3406 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3407 level = tonga_get_lowest_enable_level(hwmgr,
3408 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
c82baa28 3409
9fe1837d
AD		 3410 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3411 "force sclk dpm state failed!", return -1);
c82baa28 3412
9fe1837d
AD		 3413 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3414 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3415 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
c82baa28 3416 Curr_Sclk_Index does not match the level \n");
9fe1837d
AD		 3417 }
3418 }
3419
3420 if (0 == data->mclk_dpm_key_disabled) {
3421 /* MCLK */
3422 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3423 level = tonga_get_lowest_enable_level(hwmgr,
3424 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3425 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3426 "force lowest mclk dpm state failed!", return -1);
3427 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3428 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3429 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3430 Curr_Mclk_Index does not match the level \n");
3431 }
c82baa28 3432 }
3433
3434 return 0;
3435}
3436
3437static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
3438{
3439 uint8_t entryId;
3440 uint8_t voltageId;
3441 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3442 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3443
3444 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3445 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3446 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3447
3448 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3449 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3450 voltageId = sclk_table->entries[entryId].vddInd;
3451 sclk_table->entries[entryId].vddgfx =
3452 pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
3453 }
3454 } else {
3455 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3456 voltageId = sclk_table->entries[entryId].vddInd;
3457 sclk_table->entries[entryId].vddc =
3458 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3459 }
3460 }
3461
3462 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3463 voltageId = mclk_table->entries[entryId].vddInd;
3464 mclk_table->entries[entryId].vddc =
3465 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3466 }
3467
3468 for (entryId = 0; entryId < mm_table->count; ++entryId) {
3469 voltageId = mm_table->entries[entryId].vddcInd;
3470 mm_table->entries[entryId].vddc =
3471 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3472 }
3473
3474 return 0;
3475
3476}
3477
3478static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3479{
3480 uint8_t entryId;
3481 phm_ppt_v1_voltage_lookup_record v_record;
3482 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3483 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3484
3485 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3486 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3487
3488 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3489 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3490 if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
3491 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3492 sclk_table->entries[entryId].vdd_offset - 0xFFFF;
3493 else
3494 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3495 sclk_table->entries[entryId].vdd_offset;
3496
3497 sclk_table->entries[entryId].vddc =
3498 v_record.us_cac_low = v_record.us_cac_mid =
3499 v_record.us_cac_high = v_record.us_vdd;
3500
3501 tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
3502 }
3503
3504 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3505 if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
3506 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3507 mclk_table->entries[entryId].vdd_offset - 0xFFFF;
3508 else
3509 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3510 mclk_table->entries[entryId].vdd_offset;
3511
3512 mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
3513 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3514 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3515 }
3516 }
3517
3518 return 0;
3519
3520}
3521
3522static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3523{
3524 uint32_t entryId;
3525 phm_ppt_v1_voltage_lookup_record v_record;
3526 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3527 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3528 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3529
3530 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3531 for (entryId = 0; entryId < mm_table->count; entryId++) {
3532 if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
3533 v_record.us_vdd = mm_table->entries[entryId].vddc +
3534 mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
3535 else
3536 v_record.us_vdd = mm_table->entries[entryId].vddc +
3537 mm_table->entries[entryId].vddgfx_offset;
3538
3539 /* Add the calculated VDDGFX to the VDDGFX lookup table */
3540 mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
3541 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3542 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3543 }
3544 }
3545 return 0;
3546}
3547
3548
3549/**
3550 * Change virtual leakage voltage to actual value.
3551 *
3552 * @param hwmgr the address of the powerplay hardware manager.
3553 * @param pointer to changing voltage
3554 * @param pointer to leakage table
3555 */
3556static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
3557 uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
3558{
3559 uint32_t leakage_index;
3560
3561 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3562 for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
3563 /* if this voltage matches a leakage voltage ID */
3564 /* patch with actual leakage voltage */
3565 if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
3566 *voltage = pLeakageTable->actual_voltage[leakage_index];
3567 break;
3568 }
3569 }
3570
3571 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
3572 printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
3573}
3574
3575/**
3576 * Patch voltage lookup table by EVV leakages.
3577 *
3578 * @param hwmgr the address of the powerplay hardware manager.
3579 * @param pointer to voltage lookup table
3580 * @param pointer to leakage table
3581 * @return always 0
3582 */
3583static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
3584 phm_ppt_v1_voltage_lookup_table *lookup_table,
3585 phw_tonga_leakage_voltage *pLeakageTable)
3586{
3587 uint32_t i;
3588
3589 for (i = 0; i < lookup_table->count; i++) {
3590 tonga_patch_with_vdd_leakage(hwmgr,
3591 &lookup_table->entries[i].us_vdd, pLeakageTable);
3592 }
3593
3594 return 0;
3595}
3596
3597static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3598 phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
3599{
3600 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3601
3602 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
3603 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
3604 pptable_info->max_clock_voltage_on_dc.vddc;
3605
3606 return 0;
3607}
3608
3609static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
3610 struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
3611 uint16_t *Vddgfx)
3612{
3613 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
3614 return 0;
3615}
3616
3617int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
3618 phm_ppt_v1_voltage_lookup_table *lookup_table)
3619{
3620 uint32_t table_size, i, j;
3621 phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3622 table_size = lookup_table->count;
3623
3624 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3625 "Lookup table is empty", return -1);
3626
3627 /* Sorting voltages */
3628 for (i = 0; i < table_size - 1; i++) {
3629 for (j = i + 1; j > 0; j--) {
3630 if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
3631 tmp_voltage_lookup_record = lookup_table->entries[j-1];
3632 lookup_table->entries[j-1] = lookup_table->entries[j];
3633 lookup_table->entries[j] = tmp_voltage_lookup_record;
3634 }
3635 }
3636 }
3637
3638 return 0;
3639}
3640
3641static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3642{
3643 int result = 0;
3644 int tmp_result;
3645 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3646 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3647
3648 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3649 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3650 pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
3651 if (tmp_result != 0)
3652 result = tmp_result;
3653
3654 tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
3655 &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
3656 if (tmp_result != 0)
3657 result = tmp_result;
3658 } else {
3659 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3660 pptable_info->vddc_lookup_table, &(data->vddc_leakage));
3661 if (tmp_result != 0)
3662 result = tmp_result;
3663
3664 tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
3665 &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
3666 if (tmp_result != 0)
3667 result = tmp_result;
3668 }
3669
3670 tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3671 if (tmp_result != 0)
3672 result = tmp_result;
3673
3674 tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
3675 if (tmp_result != 0)
3676 result = tmp_result;
3677
3678 tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
3679 if (tmp_result != 0)
3680 result = tmp_result;
3681
3682 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
3683 if (tmp_result != 0)
3684 result = tmp_result;
3685
3686 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
3687 if (tmp_result != 0)
3688 result = tmp_result;
3689
3690 return result;
3691}
3692
3693int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3694{
3695 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3696 data->low_sclk_interrupt_threshold = 0;
3697
3698 return 0;
3699}
3700
3701int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
3702{
3703 int tmp_result, result = 0;
3704
3705 tmp_result = tonga_read_clock_registers(hwmgr);
3706 PP_ASSERT_WITH_CODE((0 == tmp_result),
3707 "Failed to read clock registers!", result = tmp_result);
3708
3709 tmp_result = tonga_get_memory_type(hwmgr);
3710 PP_ASSERT_WITH_CODE((0 == tmp_result),
3711 "Failed to get memory type!", result = tmp_result);
3712
3713 tmp_result = tonga_enable_acpi_power_management(hwmgr);
3714 PP_ASSERT_WITH_CODE((0 == tmp_result),
3715 "Failed to enable ACPI power management!", result = tmp_result);
3716
3717 tmp_result = tonga_init_power_gate_state(hwmgr);
3718 PP_ASSERT_WITH_CODE((0 == tmp_result),
3719 "Failed to init power gate state!", result = tmp_result);
3720
3721 tmp_result = tonga_get_mc_microcode_version(hwmgr);
3722 PP_ASSERT_WITH_CODE((0 == tmp_result),
3723 "Failed to get MC microcode version!", result = tmp_result);
3724
3725 tmp_result = tonga_init_sclk_threshold(hwmgr);
3726 PP_ASSERT_WITH_CODE((0 == tmp_result),
3727 "Failed to init sclk threshold!", result = tmp_result);
3728
3729 return result;
3730}
3731
3732/**
3733 * Enable voltage control
3734 *
3735 * @param hwmgr the address of the powerplay hardware manager.
3736 * @return always 0
3737 */
3738int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
3739{
3740 /* enable voltage control */
3741 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
3742
3743 return 0;
3744}
3745
3746/**
3747 * Checks if we want to support voltage control
3748 *
3749 * @param hwmgr the address of the powerplay hardware manager.
3750 */
3751bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
3752{
3753 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3754
3755 return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
3756}
3757
3758/*---------------------------MC----------------------------*/
3759
3760uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
3761{
3762 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
3763}
3764
3765bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
3766{
3767 bool result = 1;
3768
3769 switch (inReg) {
3770 case mmMC_SEQ_RAS_TIMING:
3771 *outReg = mmMC_SEQ_RAS_TIMING_LP;
3772 break;
3773
3774 case mmMC_SEQ_DLL_STBY:
3775 *outReg = mmMC_SEQ_DLL_STBY_LP;
3776 break;
3777
3778 case mmMC_SEQ_G5PDX_CMD0:
3779 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
3780 break;
3781
3782 case mmMC_SEQ_G5PDX_CMD1:
3783 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
3784 break;
3785
3786 case mmMC_SEQ_G5PDX_CTRL:
3787 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
3788 break;
3789
3790 case mmMC_SEQ_CAS_TIMING:
3791 *outReg = mmMC_SEQ_CAS_TIMING_LP;
3792 break;
3793
3794 case mmMC_SEQ_MISC_TIMING:
3795 *outReg = mmMC_SEQ_MISC_TIMING_LP;
3796 break;
3797
3798 case mmMC_SEQ_MISC_TIMING2:
3799 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
3800 break;
3801
3802 case mmMC_SEQ_PMG_DVS_CMD:
3803 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
3804 break;
3805
3806 case mmMC_SEQ_PMG_DVS_CTL:
3807 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
3808 break;
3809
3810 case mmMC_SEQ_RD_CTL_D0:
3811 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
3812 break;
3813
3814 case mmMC_SEQ_RD_CTL_D1:
3815 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
3816 break;
3817
3818 case mmMC_SEQ_WR_CTL_D0:
3819 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
3820 break;
3821
3822 case mmMC_SEQ_WR_CTL_D1:
3823 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
3824 break;
3825
3826 case mmMC_PMG_CMD_EMRS:
3827 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
3828 break;
3829
3830 case mmMC_PMG_CMD_MRS:
3831 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
3832 break;
3833
3834 case mmMC_PMG_CMD_MRS1:
3835 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
3836 break;
3837
3838 case mmMC_SEQ_PMG_TIMING:
3839 *outReg = mmMC_SEQ_PMG_TIMING_LP;
3840 break;
3841
3842 case mmMC_PMG_CMD_MRS2:
3843 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
3844 break;
3845
3846 case mmMC_SEQ_WR_CTL_2:
3847 *outReg = mmMC_SEQ_WR_CTL_2_LP;
3848 break;
3849
3850 default:
3851 result = 0;
3852 break;
3853 }
3854
3855 return result;
3856}
3857
3858int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
3859{
3860 uint32_t i;
3861 uint16_t address;
3862
3863 for (i = 0; i < table->last; i++) {
3864 table->mc_reg_address[i].s0 =
3865 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
3866 ? address : table->mc_reg_address[i].s1;
3867 }
3868 return 0;
3869}
3870
3871int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
3872{
3873 uint8_t i, j;
3874
3875 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3876 "Invalid VramInfo table.", return -1);
3877 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3878 "Invalid VramInfo table.", return -1);
3879
3880 for (i = 0; i < table->last; i++) {
3881 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3882 }
3883 ni_table->last = table->last;
3884
3885 for (i = 0; i < table->num_entries; i++) {
3886 ni_table->mc_reg_table_entry[i].mclk_max =
3887 table->mc_reg_table_entry[i].mclk_max;
3888 for (j = 0; j < table->last; j++) {
3889 ni_table->mc_reg_table_entry[i].mc_data[j] =
3890 table->mc_reg_table_entry[i].mc_data[j];
3891 }
3892 }
c15c8d70 3893
c82baa28 3894 ni_table->num_entries = table->num_entries;
3895
3896 return 0;
3897}
3898
3899/**
3900 * VBIOS omits some information to reduce size, we need to recover them here.
3901 * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3902 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3903 * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
3904 * 3. need to set these data for each clock range
3905 *
3906 * @param hwmgr the address of the powerplay hardware manager.
3907 * @param table the address of MCRegTable
3908 * @return always 0
3909 */
3910int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
3911{
3912 uint8_t i, j, k;
3913 uint32_t temp_reg;
3914 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3915
3916 for (i = 0, j = table->last; i < table->last; i++) {
3917 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3918 "Invalid VramInfo table.", return -1);
3919 switch (table->mc_reg_address[i].s1) {
3920 /*
3921 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3922 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3923 */
3924 case mmMC_SEQ_MISC1:
3925 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
3926 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3927 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3928 for (k = 0; k < table->num_entries; k++) {
3929 table->mc_reg_table_entry[k].mc_data[j] =
3930 ((temp_reg & 0xffff0000)) |
3931 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3932 }
3933 j++;
3934 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3935 "Invalid VramInfo table.", return -1);
3936
3937 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3938 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3939 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3940 for (k = 0; k < table->num_entries; k++) {
3941 table->mc_reg_table_entry[k].mc_data[j] =
3942 (temp_reg & 0xffff0000) |
3943 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3944
3945 if (!data->is_memory_GDDR5) {
3946 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3947 }
3948 }
3949 j++;
3950 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3951 "Invalid VramInfo table.", return -1);
3952
3953 if (!data->is_memory_GDDR5) {
3954 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3955 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3956 for (k = 0; k < table->num_entries; k++) {
3957 table->mc_reg_table_entry[k].mc_data[j] =
3958 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3959 }
3960 j++;
3961 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3962 "Invalid VramInfo table.", return -1);
3963 }
3964
3965 break;
3966
3967 case mmMC_SEQ_RESERVE_M:
3968 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3969 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3970 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3971 for (k = 0; k < table->num_entries; k++) {
3972 table->mc_reg_table_entry[k].mc_data[j] =
3973 (temp_reg & 0xffff0000) |
3974 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3975 }
3976 j++;
3977 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3978 "Invalid VramInfo table.", return -1);
3979 break;
3980
3981 default:
3982 break;
3983 }
3984
3985 }
3986
3987 table->last = j;
3988
3989 return 0;
3990}
3991
3992int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
3993{
3994 uint8_t i, j;
3995 for (i = 0; i < table->last; i++) {
3996 for (j = 1; j < table->num_entries; j++) {
3997 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3998 table->mc_reg_table_entry[j].mc_data[i]) {
3999 table->validflag |= (1<<i);
4000 break;
4001 }
4002 }
4003 }
4004
4005 return 0;
4006}
4007
4008int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
4009{
4010 int result;
4011 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4012 pp_atomctrl_mc_reg_table *table;
4013 phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
4014 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
4015
4016 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
4017
4018 if (NULL == table)
c15c8d70 4019 return -ENOMEM;
c82baa28 4020
4021 /* Program additional LP registers that are no longer programmed by VBIOS */
4022 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
4023 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
4024 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
4025 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
4026 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
4027 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
4028 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
4029 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
4030 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
4031 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
4032 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
4033 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
4034 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
4035 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
4036 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
4037 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
4038 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
4039 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
4040 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
4041 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
4042
4043 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
4044
4045 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
4046
4047 if (0 == result)
4048 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
4049
4050 if (0 == result) {
4051 tonga_set_s0_mc_reg_index(ni_table);
4052 result = tonga_set_mc_special_registers(hwmgr, ni_table);
4053 }
4054
4055 if (0 == result)
4056 tonga_set_valid_flag(ni_table);
4057
4058 kfree(table);
4059 return result;
4060}
4061
4062/*
4063* Copy one arb setting to another and then switch the active set.
4064* arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
4065*/
4066int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
4067 uint32_t arbFreqSrc, uint32_t arbFreqDest)
4068{
4069 uint32_t mc_arb_dram_timing;
4070 uint32_t mc_arb_dram_timing2;
4071 uint32_t burst_time;
4072 uint32_t mc_cg_config;
4073
4074 switch (arbFreqSrc) {
4075 case MC_CG_ARB_FREQ_F0:
4076 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
4077 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
4078 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
4079 break;
4080
4081 case MC_CG_ARB_FREQ_F1:
4082 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
4083 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
4084 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
4085 break;
4086
4087 default:
4088 return -1;
4089 }
4090
4091 switch (arbFreqDest) {
4092 case MC_CG_ARB_FREQ_F0:
4093 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
4094 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
4095 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
4096 break;
4097
4098 case MC_CG_ARB_FREQ_F1:
4099 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
4100 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
4101 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
4102 break;
4103
4104 default:
4105 return -1;
4106 }
4107
4108 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
4109 mc_cg_config |= 0x0000000F;
4110 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
4111 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
4112
4113 return 0;
4114}
4115
4116/**
4117 * Initial switch from ARB F0->F1
4118 *
4119 * @param hwmgr the address of the powerplay hardware manager.
4120 * @return always 0
4121 * This function is to be called from the SetPowerState table.
4122 */
4123int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
4124{
4125 return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4126}
4127
4128/**
4129 * Initialize the ARB DRAM timing table's index field.
4130 *
4131 * @param hwmgr the address of the powerplay hardware manager.
4132 * @return always 0
4133 */
4134int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
4135{
4136 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4137 uint32_t tmp;
4138 int result;
4139
4140 /*
4141 * This is a read-modify-write on the first byte of the ARB table.
4142 * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
4143 * This solution is ugly, but we never write the whole table only individual fields in it.
4144 * In reality this field should not be in that structure but in a soft register.
4145 */
4146 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
4147 data->arb_table_start, &tmp, data->sram_end);
4148
4149 if (0 != result)
4150 return result;
4151
4152 tmp &= 0x00FFFFFF;
4153 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
4154
4155 return tonga_write_smc_sram_dword(hwmgr->smumgr,
4156 data->arb_table_start, tmp, data->sram_end);
4157}
4158
4159int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
4160{
4161 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4162
4163 uint32_t i, j;
4164
4165 for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
4166 if (data->tonga_mc_reg_table.validflag & 1<<j) {
4167 PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
4168 "Index of mc_reg_table->address[] array out of boundary", return -1);
4169 mc_reg_table->address[i].s0 =
4170 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
4171 mc_reg_table->address[i].s1 =
4172 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
4173 i++;
4174 }
4175 }
4176
4177 mc_reg_table->last = (uint8_t)i;
4178
4179 return 0;
4180}
4181
4182/*convert register values from driver to SMC format */
4183void tonga_convert_mc_registers(
4184 const phw_tonga_mc_reg_entry * pEntry,
4185 SMU72_Discrete_MCRegisterSet *pData,
4186 uint32_t numEntries, uint32_t validflag)
4187{
4188 uint32_t i, j;
4189
4190 for (i = 0, j = 0; j < numEntries; j++) {
4191 if (validflag & 1<<j) {
4192 pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
4193 i++;
4194 }
4195 }
4196}
4197
4198/* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
4199int tonga_convert_mc_reg_table_entry_to_smc(
4200 struct pp_hwmgr *hwmgr,
4201 const uint32_t memory_clock,
4202 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
4203 )
4204{
4205 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4206 uint32_t i = 0;
4207
4208 for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
4209 if (memory_clock <=
4210 data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
4211 break;
4212 }
4213 }
4214
4215 if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
4216 --i;
4217
4218 tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
4219 mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
4220
4221 return 0;
4222}
4223
4224int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
4225 SMU72_Discrete_MCRegisters *mc_reg_table)
4226{
4227 int result = 0;
4228 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4229 int res;
4230 uint32_t i;
4231
4232 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
4233 res = tonga_convert_mc_reg_table_entry_to_smc(
4234 hwmgr,
4235 data->dpm_table.mclk_table.dpm_levels[i].value,
4236 &mc_reg_table->data[i]
4237 );
4238
4239 if (0 != res)
4240 result = res;
4241 }
4242
4243 return result;
4244}
4245
4246int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
4247{
4248 int result;
4249 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4250
4251 memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
4252 result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
4253 PP_ASSERT_WITH_CODE(0 == result,
4254 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
4255
4256 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
4257 PP_ASSERT_WITH_CODE(0 == result,
4258 "Failed to initialize MCRegTable for driver state!", return result;);
4259
4260 return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
4261 (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
4262}
4263
4264/**
4265 * Programs static screed detection parameters
4266 *
4267 * @param hwmgr the address of the powerplay hardware manager.
4268 * @return always 0
4269 */
4270int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
4271{
4272 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4273
4274 /* Set static screen threshold unit*/
4275 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4276 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
4277 data->static_screen_threshold_unit);
4278 /* Set static screen threshold*/
4279 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4280 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
4281 data->static_screen_threshold);
4282
4283 return 0;
4284}
4285
4286/**
4287 * Setup display gap for glitch free memory clock switching.
4288 *
4289 * @param hwmgr the address of the powerplay hardware manager.
4290 * @return always 0
4291 */
4292int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
4293{
4294 uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4295 CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4296
4297 display_gap = PHM_SET_FIELD(display_gap,
4298 CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
4299
4300 display_gap = PHM_SET_FIELD(display_gap,
4301 CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
4302
4303 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4304 ixCG_DISPLAY_GAP_CNTL, display_gap);
4305
4306 return 0;
4307}
4308
4309/**
4310 * Programs activity state transition voting clients
4311 *
4312 * @param hwmgr the address of the powerplay hardware manager.
4313 * @return always 0
4314 */
4315int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
4316{
4317 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4318
4319 /* Clear reset for voting clients before enabling DPM */
4320 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4321 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
4322 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4323 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
4324
4325 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4326 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
4327 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4328 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
4329 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4330 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
4331 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4332 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
4333 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4334 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
4335 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4336 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
4337 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4338 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
4339 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4340 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
4341
4342 return 0;
4343}
4344
4345
4346int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
4347{
4348 int tmp_result, result = 0;
4349
4350 tmp_result = tonga_check_for_dpm_stopped(hwmgr);
4351
4352 if (cf_tonga_voltage_control(hwmgr)) {
4353 tmp_result = tonga_enable_voltage_control(hwmgr);
4354 PP_ASSERT_WITH_CODE((0 == tmp_result),
4355 "Failed to enable voltage control!", result = tmp_result);
4356
4357 tmp_result = tonga_construct_voltage_tables(hwmgr);
4358 PP_ASSERT_WITH_CODE((0 == tmp_result),
4359 "Failed to contruct voltage tables!", result = tmp_result);
4360 }
4361
4362 tmp_result = tonga_initialize_mc_reg_table(hwmgr);
4363 PP_ASSERT_WITH_CODE((0 == tmp_result),
4364 "Failed to initialize MC reg table!", result = tmp_result);
4365
4366 tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
4367 PP_ASSERT_WITH_CODE((0 == tmp_result),
4368 "Failed to program static screen threshold parameters!", result = tmp_result);
4369
4370 tmp_result = tonga_enable_display_gap(hwmgr);
4371 PP_ASSERT_WITH_CODE((0 == tmp_result),
4372 "Failed to enable display gap!", result = tmp_result);
4373
4374 tmp_result = tonga_program_voting_clients(hwmgr);
4375 PP_ASSERT_WITH_CODE((0 == tmp_result),
4376 "Failed to program voting clients!", result = tmp_result);
4377
4378 tmp_result = tonga_process_firmware_header(hwmgr);
4379 PP_ASSERT_WITH_CODE((0 == tmp_result),
4380 "Failed to process firmware header!", result = tmp_result);
4381
4382 tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
4383 PP_ASSERT_WITH_CODE((0 == tmp_result),
4384 "Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
4385
4386 tmp_result = tonga_init_smc_table(hwmgr);
4387 PP_ASSERT_WITH_CODE((0 == tmp_result),
4388 "Failed to initialize SMC table!", result = tmp_result);
4389
4390 tmp_result = tonga_init_arb_table_index(hwmgr);
4391 PP_ASSERT_WITH_CODE((0 == tmp_result),
4392 "Failed to initialize ARB table index!", result = tmp_result);
4393
4394 tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
4395 PP_ASSERT_WITH_CODE((0 == tmp_result),
4396 "Failed to populate initialize MC Reg table!", result = tmp_result);
4397
bbb207f3
RZ		 4398 tmp_result = tonga_notify_smc_display_change(hwmgr, false);
4399 PP_ASSERT_WITH_CODE((0 == tmp_result),
4400 "Failed to notify no display!", result = tmp_result);
4401
c82baa28 4402 /* enable SCLK control */
4403 tmp_result = tonga_enable_sclk_control(hwmgr);
4404 PP_ASSERT_WITH_CODE((0 == tmp_result),
4405 "Failed to enable SCLK control!", result = tmp_result);
4406
4407 /* enable DPM */
4408 tmp_result = tonga_start_dpm(hwmgr);
4409 PP_ASSERT_WITH_CODE((0 == tmp_result),
4410 "Failed to start DPM!", result = tmp_result);
4411
4412 return result;
4413}
4414
4415int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4416{
4417 int tmp_result, result = 0;
4418
4419 tmp_result = tonga_check_for_dpm_running(hwmgr);
4420 PP_ASSERT_WITH_CODE((0 == tmp_result),
4421 "SMC is still running!", return 0);
4422
4423 tmp_result = tonga_stop_dpm(hwmgr);
4424 PP_ASSERT_WITH_CODE((0 == tmp_result),
4425 "Failed to stop DPM!", result = tmp_result);
4426
4427 tmp_result = tonga_reset_to_default(hwmgr);
4428 PP_ASSERT_WITH_CODE((0 == tmp_result),
4429 "Failed to reset to default!", result = tmp_result);
4430
4431 return result;
4432}
4433
4434int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
4435{
4436 int result;
4437
4438 result = tonga_set_boot_state(hwmgr);
4439 if (0 != result)
4440 printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
4441
4442 return result;
4443}
4444
4445int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
4446{
92dea67d 4447 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
c82baa28 4448
92dea67d
EH		 4449 if (data->soft_pp_table) {
4450 kfree(data->soft_pp_table);
4451 data->soft_pp_table = NULL;
c82baa28 4452 }
4453
92dea67d 4454 return phm_hwmgr_backend_fini(hwmgr);
c82baa28 4455}
4456
4457/**
4458 * Initializes the Volcanic Islands Hardware Manager
4459 *
4460 * @param hwmgr the address of the powerplay hardware manager.
4461 * @return 1 if success; otherwise appropriate error code.
4462 */
4463int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4464{
4465 int result = 0;
4466 SMU72_Discrete_DpmTable *table = NULL;
4467 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4468 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4469 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4470 phw_tonga_ulv_parm *ulv;
52b52a87 4471 struct cgs_system_info sys_info = {0};
c82baa28 4472
4473 PP_ASSERT_WITH_CODE((NULL != hwmgr),
4474 "Invalid Parameter!", return -1;);
4475
4476 data->dll_defaule_on = 0;
4477 data->sram_end = SMC_RAM_END;
4478
4479 data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
4480 data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
4481 data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
4482 data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
4483 data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
4484 data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
4485 data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
4486 data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
4487
4488 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
4489 data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
4490 data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
4491
4492 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4493 PHM_PlatformCaps_DisableVoltageIsland);
4494
4495 data->sclk_dpm_key_disabled = 0;
4496 data->mclk_dpm_key_disabled = 0;
4497 data->pcie_dpm_key_disabled = 0;
4498 data->pcc_monitor_enabled = 0;
4499
4500 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4501 PHM_PlatformCaps_UnTabledHardwareInterface);
4502
4503 data->gpio_debug = 0;
4504 data->engine_clock_data = 0;
4505 data->memory_clock_data = 0;
4506 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4507 PHM_PlatformCaps_DynamicPatchPowerState);
4508
4509 /* need to set voltage control types before EVV patching*/
4510 data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
4511 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4512 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4513 data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4514
3ec2cdb8 4515 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4516 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
4517 data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4518 }
4519
4520 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4521 PHM_PlatformCaps_ControlVDDGFX)) {
3ec2cdb8 4522 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4523 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
4524 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4525 }
4526 }
4527
4528 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
4529 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4530 PHM_PlatformCaps_ControlVDDGFX);
4531 }
4532
4533 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4534 PHM_PlatformCaps_EnableMVDDControl)) {
3ec2cdb8 4535 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4536 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
4537 data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4538 }
4539 }
4540
4541 if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
4542 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4543 PHM_PlatformCaps_EnableMVDDControl);
4544 }
4545
4546 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4547 PHM_PlatformCaps_ControlVDDCI)) {
3ec2cdb8 4548 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4549 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
4550 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
3ec2cdb8 4551 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4552 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
4553 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4554 }
4555
4556 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
4557 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4558 PHM_PlatformCaps_ControlVDDCI);
4559
4560 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4561 PHM_PlatformCaps_TablelessHardwareInterface);
4562
4563 if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
4564 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4565 PHM_PlatformCaps_ClockStretcher);
4566
4567 /* Initializes DPM default values*/
4568 tonga_initialize_dpm_defaults(hwmgr);
4569
4570 /* Get leakage voltage based on leakage ID.*/
4571 PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
4572 "Get EVV Voltage Failed. Abort Driver loading!", return -1);
4573
4574 tonga_complete_dependency_tables(hwmgr);
4575
4576 /* Parse pptable data read from VBIOS*/
4577 tonga_set_private_var_based_on_pptale(hwmgr);
4578
4579 /* ULV Support*/
4580 ulv = &(data->ulv);
4581 ulv->ulv_supported = 0;
4582
4583 /* Initalize Dynamic State Adjustment Rule Settings*/
4584 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
aa22ae4b
AD		 4585 if (result)
4586 printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
c82baa28 4587 data->uvd_enabled = 0;
4588
4589 table = &(data->smc_state_table);
4590
4591 /*
4592 * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
4593 * Peak Current Control feature is enabled and we should program PCC HW register
4594 */
4595 if (0 == atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
4596 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
4597 CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
4598
4599 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
4600 case 0:
4601 temp_reg = PHM_SET_FIELD(temp_reg,
4602 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
4603 break;
4604 case 1:
4605 temp_reg = PHM_SET_FIELD(temp_reg,
4606 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
4607 break;
4608 case 2:
4609 temp_reg = PHM_SET_FIELD(temp_reg,
4610 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
4611 break;
4612 case 3:
4613 temp_reg = PHM_SET_FIELD(temp_reg,
4614 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
4615 break;
4616 case 4:
4617 temp_reg = PHM_SET_FIELD(temp_reg,
4618 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
4619 break;
4620 default:
4621 printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \
4622 Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
4623 break;
4624 }
4625 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4626 ixCNB_PWRMGT_CNTL, temp_reg);
4627 }
4628
4629 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4630 PHM_PlatformCaps_EnableSMU7ThermalManagement);
4631 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4632 PHM_PlatformCaps_SMU7);
4633
4634 data->vddc_phase_shed_control = 0;
4635
3d5afb41
AD		 4636 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4637 PHM_PlatformCaps_UVDPowerGating);
f997e6f2
AD		 4638 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4639 PHM_PlatformCaps_VCEPowerGating);
52b52a87
AD		 4640 sys_info.size = sizeof(struct cgs_system_info);
4641 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
4642 result = cgs_query_system_info(hwmgr->device, &sys_info);
4643 if (!result) {
4644 if (sys_info.value & AMD_PG_SUPPORT_UVD)
4645 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4646 PHM_PlatformCaps_UVDPowerGating);
4647 if (sys_info.value & AMD_PG_SUPPORT_VCE)
4648 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4649 PHM_PlatformCaps_VCEPowerGating);
4650 }
834b694c 4651
c82baa28 4652 if (0 == result) {
4653 data->is_tlu_enabled = 0;
4654 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4655 TONGA_MAX_HARDWARE_POWERLEVELS;
4656 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
4657 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
4658
834b694c
AD		 4659 sys_info.size = sizeof(struct cgs_system_info);
4660 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
4661 result = cgs_query_system_info(hwmgr->device, &sys_info);
4662 if (result)
4663 data->pcie_gen_cap = 0x30007;
4664 else
4665 data->pcie_gen_cap = (uint32_t)sys_info.value;
4666 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
4667 data->pcie_spc_cap = 20;
4668 sys_info.size = sizeof(struct cgs_system_info);
4669 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
4670 result = cgs_query_system_info(hwmgr->device, &sys_info);
4671 if (result)
4672 data->pcie_lane_cap = 0x2f0000;
4673 else
4674 data->pcie_lane_cap = (uint32_t)sys_info.value;
c82baa28 4675 } else {
4676 /* Ignore return value in here, we are cleaning up a mess. */
4677 tonga_hwmgr_backend_fini(hwmgr);
4678 }
4679
4680 return result;
4681}
4682
4683static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
4684 enum amd_dpm_forced_level level)
4685{
4686 int ret = 0;
4687
4688 switch (level) {
4689 case AMD_DPM_FORCED_LEVEL_HIGH:
4690 ret = tonga_force_dpm_highest(hwmgr);
4691 if (ret)
4692 return ret;
4693 break;
4694 case AMD_DPM_FORCED_LEVEL_LOW:
4695 ret = tonga_force_dpm_lowest(hwmgr);
4696 if (ret)
4697 return ret;
4698 break;
4699 case AMD_DPM_FORCED_LEVEL_AUTO:
4700 ret = tonga_unforce_dpm_levels(hwmgr);
4701 if (ret)
4702 return ret;
4703 break;
4704 default:
4705 break;
4706 }
4707
4708 hwmgr->dpm_level = level;
4709 return ret;
4710}
4711
4712static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4713 struct pp_power_state *prequest_ps,
4714 const struct pp_power_state *pcurrent_ps)
4715{
4716 struct tonga_power_state *tonga_ps =
4717 cast_phw_tonga_power_state(&prequest_ps->hardware);
4718
4719 uint32_t sclk;
4720 uint32_t mclk;
4721 struct PP_Clocks minimum_clocks = {0};
4722 bool disable_mclk_switching;
4723 bool disable_mclk_switching_for_frame_lock;
4724 struct cgs_display_info info = {0};
4725 const struct phm_clock_and_voltage_limits *max_limits;
4726 uint32_t i;
4727 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4728 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4729
4730 int32_t count;
4731 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4732
4733 data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
4734
4735 PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
4736 "VI should always have 2 performance levels",
4737 );
4738
4739 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4740 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4741 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4742
4743 if (PP_PowerSource_DC == hwmgr->power_source) {
4744 for (i = 0; i < tonga_ps->performance_level_count; i++) {
4745 if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
4746 tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
4747 if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
4748 tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
4749 }
4750 }
4751
4752 tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
4753 tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
4754
4755 tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4756
4757 cgs_get_active_displays_info(hwmgr->device, &info);
4758
4759 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4760
4761 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4762
4763 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4764
4765 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4766 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4767
4768 for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
4769 if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
4770 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
4771 break;
4772 }
4773 }
4774
4775 if (count < 0)
4776 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
4777
4778 stable_pstate_mclk = max_limits->mclk;
4779
4780 minimum_clocks.engineClock = stable_pstate_sclk;
4781 minimum_clocks.memoryClock = stable_pstate_mclk;
4782 }
4783
4784 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4785 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4786
4787 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4788 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4789
4790 tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4791
4792 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4793 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
4794 "Overdrive sclk exceeds limit",
4795 hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
4796
4797 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4798 tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4799 }
4800
4801 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4802 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4803 "Overdrive mclk exceeds limit",
4804 hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4805
4806 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4807 tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4808 }
4809
4810 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4811 hwmgr->platform_descriptor.platformCaps,
4812 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4813
4814 disable_mclk_switching = (1 < info.display_count) ||
4815 disable_mclk_switching_for_frame_lock;
4816
4817 sclk = tonga_ps->performance_levels[0].engine_clock;
4818 mclk = tonga_ps->performance_levels[0].memory_clock;
4819
4820 if (disable_mclk_switching)
4821 mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
4822
4823 if (sclk < minimum_clocks.engineClock)
4824 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4825
4826 if (mclk < minimum_clocks.memoryClock)
4827 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4828
4829 tonga_ps->performance_levels[0].engine_clock = sclk;
4830 tonga_ps->performance_levels[0].memory_clock = mclk;
4831
4832 tonga_ps->performance_levels[1].engine_clock =
4833 (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
4834 tonga_ps->performance_levels[1].engine_clock :
4835 tonga_ps->performance_levels[0].engine_clock;
4836
4837 if (disable_mclk_switching) {
4838 if (mclk < tonga_ps->performance_levels[1].memory_clock)
4839 mclk = tonga_ps->performance_levels[1].memory_clock;
4840
4841 tonga_ps->performance_levels[0].memory_clock = mclk;
4842 tonga_ps->performance_levels[1].memory_clock = mclk;
4843 } else {
4844 if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
4845 tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
4846 }
4847
4848 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4849 for (i=0; i < tonga_ps->performance_level_count; i++) {
4850 tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4851 tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4852 tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4853 tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4854 }
4855 }
4856
4857 return 0;
4858}
4859
4860int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
4861{
4862 return sizeof(struct tonga_power_state);
4863}
4864
4865static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4866{
4867 struct pp_power_state *ps;
4868 struct tonga_power_state *tonga_ps;
4869
4870 if (hwmgr == NULL)
4871 return -EINVAL;
4872
4873 ps = hwmgr->request_ps;
4874
4875 if (ps == NULL)
4876 return -EINVAL;
4877
4878 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4879
4880 if (low)
4881 return tonga_ps->performance_levels[0].memory_clock;
4882 else
4883 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
4884}
4885
4886static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4887{
4888 struct pp_power_state *ps;
4889 struct tonga_power_state *tonga_ps;
4890
4891 if (hwmgr == NULL)
4892 return -EINVAL;
4893
4894 ps = hwmgr->request_ps;
4895
4896 if (ps == NULL)
4897 return -EINVAL;
4898
4899 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4900
4901 if (low)
4902 return tonga_ps->performance_levels[0].engine_clock;
4903 else
4904 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
4905}
4906
4907static uint16_t tonga_get_current_pcie_speed(
4908 struct pp_hwmgr *hwmgr)
4909{
4910 uint32_t speed_cntl = 0;
4911
4912 speed_cntl = cgs_read_ind_register(hwmgr->device,
4913 CGS_IND_REG__PCIE,
4914 ixPCIE_LC_SPEED_CNTL);
4915 return((uint16_t)PHM_GET_FIELD(speed_cntl,
4916 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4917}
4918
4919static int tonga_get_current_pcie_lane_number(
4920 struct pp_hwmgr *hwmgr)
4921{
4922 uint32_t link_width;
4923
4924 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4925 CGS_IND_REG__PCIE,
4926 PCIE_LC_LINK_WIDTH_CNTL,
4927 LC_LINK_WIDTH_RD);
4928
4929 PP_ASSERT_WITH_CODE((7 >= link_width),
4930 "Invalid PCIe lane width!", return 0);
4931
4932 return decode_pcie_lane_width(link_width);
4933}
4934
4935static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4936 struct pp_hw_power_state *hw_ps)
4937{
4938 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4939 struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
4940 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4941 uint16_t size;
4942 uint8_t frev, crev;
4943 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4944
4945 /* First retrieve the Boot clocks and VDDC from the firmware info table.
4946 * We assume here that fw_info is unchanged if this call fails.
4947 */
4948 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4949 hwmgr->device, index,
4950 &size, &frev, &crev);
4951 if (!fw_info)
4952 /* During a test, there is no firmware info table. */
4953 return 0;
4954
4955 /* Patch the state. */
4956 data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock);
4957 data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4958 data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4959 data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4960 data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4961 data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
4962 data->vbios_boot_state.pcie_lane_bootup_value =
4963 (uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
4964
4965 /* set boot power state */
4966 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4967 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4968 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4969 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4970
4971 return 0;
4972}
4973
4974static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4975 void *state, struct pp_power_state *power_state,
4976 void *pp_table, uint32_t classification_flag)
4977{
4978 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4979
4980 struct tonga_power_state *tonga_ps =
4981 (struct tonga_power_state *)(&(power_state->hardware));
4982
4983 struct tonga_performance_level *performance_level;
4984
4985 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
4986
4987 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
4988 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
4989
4990 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
4991 (ATOM_Tonga_SCLK_Dependency_Table *)
c9fe74e6 4992 (((unsigned long)powerplay_table) +
c82baa28 4993 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
4994
4995 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
4996 (ATOM_Tonga_MCLK_Dependency_Table *)
c9fe74e6 4997 (((unsigned long)powerplay_table) +
c82baa28 4998 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
4999
5000 /* The following fields are not initialized here: id orderedList allStatesList */
5001 power_state->classification.ui_label =
5002 (le16_to_cpu(state_entry->usClassification) &
5003 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
5004 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
5005 power_state->classification.flags = classification_flag;
5006 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
5007
5008 power_state->classification.temporary_state = false;
5009 power_state->classification.to_be_deleted = false;
5010
5011 power_state->validation.disallowOnDC =
5012 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
5013
5014 power_state->pcie.lanes = 0;
5015
5016 power_state->display.disableFrameModulation = false;
5017 power_state->display.limitRefreshrate = false;
5018 power_state->display.enableVariBright =
5019 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
5020
5021 power_state->validation.supportedPowerLevels = 0;
5022 power_state->uvd_clocks.VCLK = 0;
5023 power_state->uvd_clocks.DCLK = 0;
5024 power_state->temperatures.min = 0;
5025 power_state->temperatures.max = 0;
5026
5027 performance_level = &(tonga_ps->performance_levels
5028 [tonga_ps->performance_level_count++]);
5029
5030 PP_ASSERT_WITH_CODE(
5031 (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
5032 "Performance levels exceeds SMC limit!",
5033 return -1);
5034
5035 PP_ASSERT_WITH_CODE(
5036 (tonga_ps->performance_level_count <=
5037 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
5038 "Performance levels exceeds Driver limit!",
5039 return -1);
5040
5041 /* Performance levels are arranged from low to high. */
5042 performance_level->memory_clock =
5043 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
5044
5045 performance_level->engine_clock =
5046 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
5047
5048 performance_level->pcie_gen = get_pcie_gen_support(
5049 data->pcie_gen_cap,
5050 state_entry->ucPCIEGenLow);
5051
5052 performance_level->pcie_lane = get_pcie_lane_support(
5053 data->pcie_lane_cap,
5054 state_entry->ucPCIELaneHigh);
5055
5056 performance_level =
5057 &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
5058
5059 performance_level->memory_clock =
5060 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
5061
5062 performance_level->engine_clock =
5063 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
5064
5065 performance_level->pcie_gen = get_pcie_gen_support(
5066 data->pcie_gen_cap,
5067 state_entry->ucPCIEGenHigh);
5068
5069 performance_level->pcie_lane = get_pcie_lane_support(
5070 data->pcie_lane_cap,
5071 state_entry->ucPCIELaneHigh);
5072
5073 return 0;
5074}
5075
5076static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5077 unsigned long entry_index, struct pp_power_state *ps)
5078{
5079 int result;
5080 struct tonga_power_state *tonga_ps;
5081 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5082
5083 struct phm_ppt_v1_information *table_info =
5084 (struct phm_ppt_v1_information *)(hwmgr->pptable);
5085
5086 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5087 table_info->vdd_dep_on_mclk;
5088
5089 ps->hardware.magic = PhwTonga_Magic;
5090
5091 tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
5092
5093 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
5094 tonga_get_pp_table_entry_callback_func);
5095
5096 /* This is the earliest time we have all the dependency table and the VBIOS boot state
5097 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
5098 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
5099 */
5100 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5101 if (dep_mclk_table->entries[0].clk !=
5102 data->vbios_boot_state.mclk_bootup_value)
5103 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5104 "does not match VBIOS boot MCLK level");
5105 if (dep_mclk_table->entries[0].vddci !=
5106 data->vbios_boot_state.vddci_bootup_value)
5107 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5108 "does not match VBIOS boot VDDCI level");
5109 }
5110
5111 /* set DC compatible flag if this state supports DC */
5112 if (!ps->validation.disallowOnDC)
5113 tonga_ps->dc_compatible = true;
5114
5115 if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
5116 data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
5117 else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
5118 if (data->bacos.best_match == 0xffff) {
5119 /* For V.I. use boot state as base BACO state */
5120 data->bacos.best_match = PP_StateClassificationFlag_Boot;
5121 data->bacos.performance_level = tonga_ps->performance_levels[0];
5122 }
5123 }
5124
5125 tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
5126 tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
5127
5128 if (!result) {
5129 uint32_t i;
5130
5131 switch (ps->classification.ui_label) {
5132 case PP_StateUILabel_Performance:
5133 data->use_pcie_performance_levels = true;
5134
5135 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5136 if (data->pcie_gen_performance.max <
5137 tonga_ps->performance_levels[i].pcie_gen)
5138 data->pcie_gen_performance.max =
5139 tonga_ps->performance_levels[i].pcie_gen;
5140
5141 if (data->pcie_gen_performance.min >
5142 tonga_ps->performance_levels[i].pcie_gen)
5143 data->pcie_gen_performance.min =
5144 tonga_ps->performance_levels[i].pcie_gen;
5145
5146 if (data->pcie_lane_performance.max <
5147 tonga_ps->performance_levels[i].pcie_lane)
5148 data->pcie_lane_performance.max =
5149 tonga_ps->performance_levels[i].pcie_lane;
5150
5151 if (data->pcie_lane_performance.min >
5152 tonga_ps->performance_levels[i].pcie_lane)
5153 data->pcie_lane_performance.min =
5154 tonga_ps->performance_levels[i].pcie_lane;
5155 }
5156 break;
5157 case PP_StateUILabel_Battery:
5158 data->use_pcie_power_saving_levels = true;
5159
5160 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5161 if (data->pcie_gen_power_saving.max <
5162 tonga_ps->performance_levels[i].pcie_gen)
5163 data->pcie_gen_power_saving.max =
5164 tonga_ps->performance_levels[i].pcie_gen;
5165
5166 if (data->pcie_gen_power_saving.min >
5167 tonga_ps->performance_levels[i].pcie_gen)
5168 data->pcie_gen_power_saving.min =
5169 tonga_ps->performance_levels[i].pcie_gen;
5170
5171 if (data->pcie_lane_power_saving.max <
5172 tonga_ps->performance_levels[i].pcie_lane)
5173 data->pcie_lane_power_saving.max =
5174 tonga_ps->performance_levels[i].pcie_lane;
5175
5176 if (data->pcie_lane_power_saving.min >
5177 tonga_ps->performance_levels[i].pcie_lane)
5178 data->pcie_lane_power_saving.min =
5179 tonga_ps->performance_levels[i].pcie_lane;
5180 }
5181 break;
5182 default:
5183 break;
5184 }
5185 }
5186 return 0;
5187}
5188
5189static void
5190tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5191{
ab4f4b14 5192 uint32_t sclk, mclk, activity_percent;
9c5f8de6
RZ		 5193 uint32_t offset;
5194 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
c82baa28 5195
5196 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5197
5198 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5199
5200 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5201
5202 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5203 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);
9c5f8de6 5204
9c5f8de6 5205 offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
ab4f4b14
RZ		 5206 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
5207 activity_percent += 0x80;
5208 activity_percent >>= 8;
9c5f8de6 5209
ab4f4b14 5210 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
9c5f8de6 5211
d27d4941
RZ		 5212 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
5213
5214 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
c82baa28 5215}
5216
5217static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
5218{
5219 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5220 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5221 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5222 struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
5223 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5224 struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
5225 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5226 struct PP_Clocks min_clocks = {0};
5227 uint32_t i;
5228 struct cgs_display_info info = {0};
5229
5230 data->need_update_smu7_dpm_table = 0;
5231
5232 for (i = 0; i < psclk_table->count; i++) {
5233 if (sclk == psclk_table->dpm_levels[i].value)
5234 break;
5235 }
5236
5237 if (i >= psclk_table->count)
5238 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5239 else {
5240 /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
5241 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
5242 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
5243 }
5244
5245 for (i=0; i < pmclk_table->count; i++) {
5246 if (mclk == pmclk_table->dpm_levels[i].value)
5247 break;
5248 }
5249
5250 if (i >= pmclk_table->count)
5251 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5252
5253 cgs_get_active_displays_info(hwmgr->device, &info);
5254
5255 if (data->display_timing.num_existing_displays != info.display_count)
5256 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
5257
5258 return 0;
5259}
5260
5261static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
5262{
5263 uint32_t i;
5264 uint32_t sclk, max_sclk = 0;
5265 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5266 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5267
5268 for (i = 0; i < hw_ps->performance_level_count; i++) {
5269 sclk = hw_ps->performance_levels[i].engine_clock;
5270 if (max_sclk < sclk)
5271 max_sclk = sclk;
5272 }
5273
5274 for (i = 0; i < pdpm_table->sclk_table.count; i++) {
5275 if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
5276 return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
5277 pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
5278 pdpm_table->pcie_speed_table.dpm_levels[i].value);
5279 }
5280
5281 return 0;
5282}
5283
5284static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
5285{
5286 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5287 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5288 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5289 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5290
5291 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
5292 uint16_t current_link_speed;
5293
5294 if (data->force_pcie_gen == PP_PCIEGenInvalid)
5295 current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
5296 else
5297 current_link_speed = data->force_pcie_gen;
5298
5299 data->force_pcie_gen = PP_PCIEGenInvalid;
5300 data->pspp_notify_required = false;
5301 if (target_link_speed > current_link_speed) {
5302 switch(target_link_speed) {
5303 case PP_PCIEGen3:
5304 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
5305 break;
5306 data->force_pcie_gen = PP_PCIEGen2;
5307 if (current_link_speed == PP_PCIEGen2)
5308 break;
5309 case PP_PCIEGen2:
5310 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
5311 break;
5312 default:
5313 data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
5314 break;
5315 }
5316 } else {
5317 if (target_link_speed < current_link_speed)
5318 data->pspp_notify_required = true;
5319 }
5320
5321 return 0;
5322}
5323
5324static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5325{
5326 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5327
5328 if (0 == data->need_update_smu7_dpm_table)
5329 return 0;
5330
5331 if ((0 == data->sclk_dpm_key_disabled) &&
5332 (data->need_update_smu7_dpm_table &
5333 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5334 PP_ASSERT_WITH_CODE(
5335 true == tonga_is_dpm_running(hwmgr),
5336 "Trying to freeze SCLK DPM when DPM is disabled",
5337 );
5338 PP_ASSERT_WITH_CODE(
5339 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5340 PPSMC_MSG_SCLKDPM_FreezeLevel),
5341 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
5342 return -1);
5343 }
5344
5345 if ((0 == data->mclk_dpm_key_disabled) &&
5346 (data->need_update_smu7_dpm_table &
5347 DPMTABLE_OD_UPDATE_MCLK)) {
5348 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5349 "Trying to freeze MCLK DPM when DPM is disabled",
5350 );
5351 PP_ASSERT_WITH_CODE(
5352 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5353 PPSMC_MSG_MCLKDPM_FreezeLevel),
5354 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
5355 return -1);
5356 }
5357
5358 return 0;
5359}
5360
5361static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
5362{
5363 int result = 0;
5364
5365 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5366 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5367 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5368 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5369 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5370 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5371
5372 struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
5373 uint32_t dpm_count, clock_percent;
5374 uint32_t i;
5375
5376 if (0 == data->need_update_smu7_dpm_table)
5377 return 0;
5378
5379 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
5380 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
5381
5382 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5383 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5384 /* Need to do calculation based on the golden DPM table
5385 * as the Heatmap GPU Clock axis is also based on the default values
5386 */
5387 PP_ASSERT_WITH_CODE(
5388 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
5389 "Divide by 0!",
5390 return -1);
5391 dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
5392 for (i = dpm_count; i > 1; i--) {
5393 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
5394 clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
5395 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5396
5397 pdpm_table->sclk_table.dpm_levels[i].value =
5398 pgolden_dpm_table->sclk_table.dpm_levels[i].value +
5399 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5400
5401 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
5402 clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
5403 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5404
5405 pdpm_table->sclk_table.dpm_levels[i].value =
5406 pgolden_dpm_table->sclk_table.dpm_levels[i].value -
5407 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5408 } else
5409 pdpm_table->sclk_table.dpm_levels[i].value =
5410 pgolden_dpm_table->sclk_table.dpm_levels[i].value;
5411 }
5412 }
5413 }
5414
5415 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
5416 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
5417
5418 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5419 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5420
5421 PP_ASSERT_WITH_CODE(
5422 (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
5423 "Divide by 0!",
5424 return -1);
5425 dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
5426 for (i = dpm_count; i > 1; i--) {
5427 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
5428 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
5429 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5430
5431 pdpm_table->mclk_table.dpm_levels[i].value =
5432 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
5433 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5434
5435 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
5436 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
5437 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5438
5439 pdpm_table->mclk_table.dpm_levels[i].value =
5440 pgolden_dpm_table->mclk_table.dpm_levels[i].value -
5441 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5442 } else
5443 pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
5444 }
5445 }
5446 }
5447
5448 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
5449 result = tonga_populate_all_memory_levels(hwmgr);
5450 PP_ASSERT_WITH_CODE((0 == result),
5451 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
5452 return result);
5453 }
5454
5455 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
5456 /*populate MCLK dpm table to SMU7 */
5457 result = tonga_populate_all_memory_levels(hwmgr);
5458 PP_ASSERT_WITH_CODE((0 == result),
5459 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
5460 return result);
5461 }
5462
5463 return result;
5464}
5465
5466static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
5467 struct tonga_single_dpm_table * pdpm_table,
5468 uint32_t low_limit, uint32_t high_limit)
5469{
5470 uint32_t i;
5471
5472 for (i = 0; i < pdpm_table->count; i++) {
5473 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
5474 (pdpm_table->dpm_levels[i].value > high_limit))
5475 pdpm_table->dpm_levels[i].enabled = false;
5476 else
5477 pdpm_table->dpm_levels[i].enabled = true;
5478 }
5479 return 0;
5480}
5481
5482static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
5483{
5484 int result = 0;
5485 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5486 uint32_t high_limit_count;
5487
5488 PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
5489 "power state did not have any performance level",
5490 return -1);
5491
5492 high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
5493
5494 tonga_trim_single_dpm_states(hwmgr,
5495 &(data->dpm_table.sclk_table),
5496 hw_state->performance_levels[0].engine_clock,
5497 hw_state->performance_levels[high_limit_count].engine_clock);
5498
5499 tonga_trim_single_dpm_states(hwmgr,
5500 &(data->dpm_table.mclk_table),
5501 hw_state->performance_levels[0].memory_clock,
5502 hw_state->performance_levels[high_limit_count].memory_clock);
5503
5504 return result;
5505}
5506
5507static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
5508{
5509 int result;
5510 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5511 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5512 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5513
c82baa28 5514 result = tonga_trim_dpm_states(hwmgr, tonga_ps);
5515 if (0 != result)
5516 return result;
5517
5518 data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
5519 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
5520 data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
5521 if (data->uvd_enabled)
5522 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
5523
5524 data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
5525
5526 return 0;
5527}
5528
0859ed3d 5529int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
c82baa28 5530{
0859ed3d 5531 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
c82baa28 5532 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
5533 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
5534}
5535
0859ed3d
RZ		 5536int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
5537{
5538 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5539 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
5540 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
5541}
5542
5543int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
5544{
5545 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5546 uint32_t mm_boot_level_offset, mm_boot_level_value;
5547 struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5548
5549 if (!bgate) {
5550 data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
5551 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
5552 mm_boot_level_offset /= 4;
5553 mm_boot_level_offset *= 4;
5554 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5555 mm_boot_level_value &= 0x00FFFFFF;
5556 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
5557 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5558
5559 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
5560 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5561 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5562 PPSMC_MSG_UVDDPM_SetEnabledMask,
5563 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
5564 }
5565
5566 return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
5567}
5568
5569int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
c82baa28 5570{
5571 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5572 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5573 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5574 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5575
5576 uint32_t mm_boot_level_offset, mm_boot_level_value;
5577 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5578
0859ed3d 5579 if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
c82baa28 5580 data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
5581
5582 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
5583 mm_boot_level_offset /= 4;
5584 mm_boot_level_offset *= 4;
5585 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5586 mm_boot_level_value &= 0xFF00FFFF;
5587 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
5588 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5589
0859ed3d
RZ		 5590 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5591 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5592 PPSMC_MSG_VCEDPM_SetEnabledMask,
5593 (uint32_t)(1 << data->smc_state_table.VceBootLevel));
c82baa28 5594
0859ed3d
RZ		 5595 tonga_enable_disable_vce_dpm(hwmgr, true);
5596 } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
5597 tonga_enable_disable_vce_dpm(hwmgr, false);
c82baa28 5598
5599 return 0;
5600}
5601
5602static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
5603{
5604 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5605
5606 uint32_t address;
5607 int32_t result;
5608
5609 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
5610 return 0;
5611
5612
5613 memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
5614
5615 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
5616
5617 if(result != 0)
5618 return result;
5619
5620
5621 address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
5622
5623 return tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
5624 (uint8_t *)&data->mc_reg_table.data[0],
5625 sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
5626 data->sram_end);
5627}
5628
5629static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
5630{
5631 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5632
5633 if (data->need_update_smu7_dpm_table &
5634 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
5635 return tonga_program_memory_timing_parameters(hwmgr);
5636
5637 return 0;
5638}
5639
5640static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5641{
5642 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5643
5644 if (0 == data->need_update_smu7_dpm_table)
5645 return 0;
5646
5647 if ((0 == data->sclk_dpm_key_disabled) &&
5648 (data->need_update_smu7_dpm_table &
5649 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5650
5651 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5652 "Trying to Unfreeze SCLK DPM when DPM is disabled",
5653 );
5654 PP_ASSERT_WITH_CODE(
5655 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5656 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5657 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
5658 return -1);
5659 }
5660
5661 if ((0 == data->mclk_dpm_key_disabled) &&
5662 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5663
5664 PP_ASSERT_WITH_CODE(
5665 true == tonga_is_dpm_running(hwmgr),
5666 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5667 );
5668 PP_ASSERT_WITH_CODE(
5669 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5670 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5671 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
5672 return -1);
5673 }
5674
5675 data->need_update_smu7_dpm_table = 0;
5676
5677 return 0;
5678}
5679
5680static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
5681{
5682 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5683 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5684 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5685 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
5686 uint8_t request;
5687
5688 if (data->pspp_notify_required ||
5689 data->pcie_performance_request) {
5690 if (target_link_speed == PP_PCIEGen3)
5691 request = PCIE_PERF_REQ_GEN3;
5692 else if (target_link_speed == PP_PCIEGen2)
5693 request = PCIE_PERF_REQ_GEN2;
5694 else
5695 request = PCIE_PERF_REQ_GEN1;
5696
5697 if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
5698 data->pcie_performance_request = false;
5699 return 0;
5700 }
5701
5702 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
5703 if (PP_PCIEGen2 == target_link_speed)
5704 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
5705 else
5706 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
5707 }
5708 }
5709
5710 data->pcie_performance_request = false;
5711 return 0;
5712}
5713
5714static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
5715{
5716 int tmp_result, result = 0;
5717
5718 tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
5719 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
5720
5721 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5722 tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
5723 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
5724 }
5725
5726 tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
5727 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
5728
5729 tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
5730 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
5731
5732 tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
5733 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
5734
5735 tmp_result = tonga_update_vce_dpm(hwmgr, input);
5736 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
5737
5738 tmp_result = tonga_update_sclk_threshold(hwmgr);
5739 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
5740
5741 tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
5742 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
5743
5744 tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
5745 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
5746
5747 tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
5748 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
5749
5750 tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
5751 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
5752
5753 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5754 tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
5755 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
5756 }
5757
5758 return result;
5759}
5760
1e4854e9
RZ		 5761/**
5762* Set maximum target operating fan output PWM
5763*
5764* @param pHwMgr: the address of the powerplay hardware manager.
5765* @param usMaxFanPwm: max operating fan PWM in percents
5766* @return The response that came from the SMC.
5767*/
5768static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5769{
5770 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5771
5772 if (phm_is_hw_access_blocked(hwmgr))
5773 return 0;
5774
c15c8d70 5775 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1);
1e4854e9 5776}
bbb207f3
RZ		 5777
5778int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5779{
5780 uint32_t num_active_displays = 0;
5781 struct cgs_display_info info = {0};
5782 info.mode_info = NULL;
5783
5784 cgs_get_active_displays_info(hwmgr->device, &info);
5785
5786 num_active_displays = info.display_count;
5787
5788 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5789 tonga_notify_smc_display_change(hwmgr, false);
5790 else
5791 tonga_notify_smc_display_change(hwmgr, true);
5792
5793 return 0;
5794}
5795
5796/**
5797* Programs the display gap
5798*
5799* @param hwmgr the address of the powerplay hardware manager.
5800* @return always OK
5801*/
5802int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
5803{
5804 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5805 uint32_t num_active_displays = 0;
5806 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5807 uint32_t display_gap2;
5808 uint32_t pre_vbi_time_in_us;
5809 uint32_t frame_time_in_us;
5810 uint32_t ref_clock;
5811 uint32_t refresh_rate = 0;
5812 struct cgs_display_info info = {0};
5813 struct cgs_mode_info mode_info;
5814
5815 info.mode_info = &mode_info;
5816
5817 cgs_get_active_displays_info(hwmgr->device, &info);
5818 num_active_displays = info.display_count;
5819
5820 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5821 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5822
5823 ref_clock = mode_info.ref_clock;
5824 refresh_rate = mode_info.refresh_rate;
5825
5826 if(0 == refresh_rate)
5827 refresh_rate = 60;
5828
5829 frame_time_in_us = 1000000 / refresh_rate;
5830
5831 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5832 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5833
5834 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5835
5836 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
5837
5838 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
5839
5840 if (num_active_displays == 1)
5841 tonga_notify_smc_display_change(hwmgr, true);
5842
5843 return 0;
5844}
5845
5846int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5847{
5848
5849 tonga_program_display_gap(hwmgr);
5850
5851 /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
5852 return 0;
5853}
5854
1e4854e9
RZ		 5855/**
5856* Set maximum target operating fan output RPM
5857*
5858* @param pHwMgr: the address of the powerplay hardware manager.
5859* @param usMaxFanRpm: max operating fan RPM value.
5860* @return The response that came from the SMC.
5861*/
5862static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5863{
5864 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5865
5866 if (phm_is_hw_access_blocked(hwmgr))
5867 return 0;
5868
c15c8d70 5869 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1);
1e4854e9
RZ		 5870}
5871
5872uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
5873{
5874 uint32_t reference_clock;
5875 uint32_t tc;
5876 uint32_t divide;
5877
5878 ATOM_FIRMWARE_INFO *fw_info;
5879 uint16_t size;
5880 uint8_t frev, crev;
5881 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5882
5883 tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5884
5885 if (tc)
5886 return TCLK;
5887
5888 fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5889 &size, &frev, &crev);
5890
5891 if (!fw_info)
5892 return 0;
5893
dcf799e5 5894 reference_clock = le16_to_cpu(fw_info->usReferenceClock);
1e4854e9
RZ		 5895
5896 divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5897
5898 if (0 != divide)
5899 return reference_clock / 4;
5900
5901 return reference_clock;
5902}
5903
5904int tonga_dpm_set_interrupt_state(void *private_data,
5905 unsigned src_id, unsigned type,
5906 int enabled)
5907{
5908 uint32_t cg_thermal_int;
5909 struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5910
5911 if (hwmgr == NULL)
5912 return -EINVAL;
5913
5914 switch (type) {
5915 case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5916 if (enabled) {
5917 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5918 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5919 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5920 } else {
5921 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5922 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5923 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5924 }
5925 break;
5926
5927 case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5928 if (enabled) {
5929 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5930 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5931 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5932 } else {
5933 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5934 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5935 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5936 }
5937 break;
5938 default:
5939 break;
5940 }
5941 return 0;
5942}
5943
5944int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5945 const void *thermal_interrupt_info)
5946{
5947 int result;
5948 const struct pp_interrupt_registration_info *info =
5949 (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5950
5951 if (info == NULL)
5952 return -EINVAL;
5953
5954 result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5955 tonga_dpm_set_interrupt_state,
5956 info->call_back, info->context);
5957
5958 if (result)
5959 return -EINVAL;
5960
5961 result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5962 tonga_dpm_set_interrupt_state,
5963 info->call_back, info->context);
5964
5965 if (result)
5966 return -EINVAL;
5967
5968 return 0;
5969}
5970
e829ecdb
RZ		 5971bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5972{
5973 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5974 bool is_update_required = false;
5975 struct cgs_display_info info = {0,0,NULL};
5976
5977 cgs_get_active_displays_info(hwmgr->device, &info);
5978
5979 if (data->display_timing.num_existing_displays != info.display_count)
5980 is_update_required = true;
5981/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5982 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5983 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5984 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5985 is_update_required = true;
5986*/
5987 return is_update_required;
5988}
5989
5990static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
5991 const struct tonga_performance_level *pl2)
5992{
5993 return ((pl1->memory_clock == pl2->memory_clock) &&
5994 (pl1->engine_clock == pl2->engine_clock) &&
5995 (pl1->pcie_gen == pl2->pcie_gen) &&
5996 (pl1->pcie_lane == pl2->pcie_lane));
5997}
5998
5999int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
6000{
6001 const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
6002 const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
6003 int i;
6004
c15c8d70 6005 if (equal == NULL || psa == NULL || psb == NULL)
e829ecdb
RZ		 6006 return -EINVAL;
6007
6008 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
6009 if (psa->performance_level_count != psb->performance_level_count) {
6010 *equal = false;
6011 return 0;
6012 }
6013
6014 for (i = 0; i < psa->performance_level_count; i++) {
6015 if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
6016 /* If we have found even one performance level pair that is different the states are different. */
6017 *equal = false;
6018 return 0;
6019 }
6020 }
6021
6022 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6023 *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
6024 *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
6025 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
6026 *equal &= (psa->acp_clk == psb->acp_clk);
6027
6028 return 0;
6029}
6030
9dcfc193
EH		 6031static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
6032{
6033 if (mode) {
6034 /* stop auto-manage */
6035 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
6036 PHM_PlatformCaps_MicrocodeFanControl))
6037 tonga_fan_ctrl_stop_smc_fan_control(hwmgr);
6038 tonga_fan_ctrl_set_static_mode(hwmgr, mode);
6039 } else
6040 /* restart auto-manage */
6041 tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr);
6042
6043 return 0;
6044}
6045
6046static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr)
6047{
6048 if (hwmgr->fan_ctrl_is_in_default_mode)
6049 return hwmgr->fan_ctrl_default_mode;
6050 else
6051 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
6052 CG_FDO_CTRL2, FDO_PWM_MODE);
6053}
6054
5d37a63d
EH		 6055static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
6056{
6057 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6058
92dea67d
EH		 6059 if (!data->soft_pp_table) {
6060 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
6061 if (!data->soft_pp_table)
6062 return -ENOMEM;
6063 memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
6064 hwmgr->soft_pp_table_size);
6065 }
6066
6067 *table = (char *)&data->soft_pp_table;
5d37a63d 6068
92dea67d 6069 return hwmgr->soft_pp_table_size;
5d37a63d
EH		 6070}
6071
6072static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
6073{
6074 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6075
92dea67d
EH		 6076 if (!data->soft_pp_table) {
6077 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
6078 if (!data->soft_pp_table)
6079 return -ENOMEM;
6080 }
6081
6082 memcpy(data->soft_pp_table, buf, size);
6083
6084 hwmgr->soft_pp_table = data->soft_pp_table;
5d37a63d 6085
92dea67d 6086 /* TODO: re-init powerplay to implement modified pptable */
5d37a63d
EH		 6087
6088 return 0;
6089}
6090
6091static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
5632708f 6092 enum pp_clock_type type, uint32_t mask)
5d37a63d
EH		 6093{
6094 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6095
6096 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
6097 return -EINVAL;
6098
6099 switch (type) {
6100 case PP_SCLK:
6101 if (!data->sclk_dpm_key_disabled)
6102 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6103 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5632708f 6104 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5d37a63d
EH		 6105 break;
6106 case PP_MCLK:
6107 if (!data->mclk_dpm_key_disabled)
6108 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6109 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5632708f 6110 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5d37a63d
EH		 6111 break;
6112 case PP_PCIE:
5632708f
EH		 6113 {
6114 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
6115 uint32_t level = 0;
6116
6117 while (tmp >>= 1)
6118 level++;
6119
5d37a63d
EH		 6120 if (!data->pcie_dpm_key_disabled)
6121 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6122 PPSMC_MSG_PCIeDPM_ForceLevel,
5632708f 6123 level);
5d37a63d 6124 break;
5632708f 6125 }
5d37a63d
EH		 6126 default:
6127 break;
6128 }
6129
6130 return 0;
6131}
6132
6133static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr,
6134 enum pp_clock_type type, char *buf)
6135{
6136 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6137 struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
6138 struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
6139 struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
6140 int i, now, size = 0;
6141 uint32_t clock, pcie_speed;
6142
6143 switch (type) {
6144 case PP_SCLK:
6145 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
6146 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6147
6148 for (i = 0; i < sclk_table->count; i++) {
6149 if (clock > sclk_table->dpm_levels[i].value)
6150 continue;
6151 break;
6152 }
6153 now = i;
6154
6155 for (i = 0; i < sclk_table->count; i++)
6156 size += sprintf(buf + size, "%d: %uMhz %s\n",
6157 i, sclk_table->dpm_levels[i].value / 100,
6158 (i == now) ? "*" : "");
6159 break;
6160 case PP_MCLK:
6161 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
6162 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6163
6164 for (i = 0; i < mclk_table->count; i++) {
6165 if (clock > mclk_table->dpm_levels[i].value)
6166 continue;
6167 break;
6168 }
6169 now = i;
6170
6171 for (i = 0; i < mclk_table->count; i++)
6172 size += sprintf(buf + size, "%d: %uMhz %s\n",
6173 i, mclk_table->dpm_levels[i].value / 100,
6174 (i == now) ? "*" : "");
6175 break;
6176 case PP_PCIE:
6177 pcie_speed = tonga_get_current_pcie_speed(hwmgr);
6178 for (i = 0; i < pcie_table->count; i++) {
6179 if (pcie_speed != pcie_table->dpm_levels[i].value)
6180 continue;
6181 break;
6182 }
6183 now = i;
6184
6185 for (i = 0; i < pcie_table->count; i++)
6186 size += sprintf(buf + size, "%d: %s %s\n", i,
6187 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
6188 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6189 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6190 (i == now) ? "*" : "");
6191 break;
6192 default:
6193 break;
6194 }
6195 return size;
6196}
6197
c82baa28 6198static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
6199 .backend_init = &tonga_hwmgr_backend_init,
6200 .backend_fini = &tonga_hwmgr_backend_fini,
6201 .asic_setup = &tonga_setup_asic_task,
6202 .dynamic_state_management_enable = &tonga_enable_dpm_tasks,
6203 .apply_state_adjust_rules = tonga_apply_state_adjust_rules,
6204 .force_dpm_level = &tonga_force_dpm_level,
6205 .power_state_set = tonga_set_power_state_tasks,
6206 .get_power_state_size = tonga_get_power_state_size,
6207 .get_mclk = tonga_dpm_get_mclk,
6208 .get_sclk = tonga_dpm_get_sclk,
6209 .patch_boot_state = tonga_dpm_patch_boot_state,
6210 .get_pp_table_entry = tonga_get_pp_table_entry,
6211 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
6212 .print_current_perforce_level = tonga_print_current_perforce_level,
0859ed3d
RZ		 6213 .powerdown_uvd = tonga_phm_powerdown_uvd,
6214 .powergate_uvd = tonga_phm_powergate_uvd,
6215 .powergate_vce = tonga_phm_powergate_vce,
6216 .disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
bbb207f3
RZ		 6217 .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
6218 .display_config_changed = tonga_display_configuration_changed_task,
1e4854e9
RZ		 6219 .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
6220 .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
6221 .get_temperature = tonga_thermal_get_temperature,
6222 .stop_thermal_controller = tonga_thermal_stop_thermal_controller,
6223 .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
6224 .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
6225 .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
6226 .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
6227 .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
6228 .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
6229 .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
6230 .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
e829ecdb
RZ		 6231 .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
6232 .check_states_equal = tonga_check_states_equal,
9dcfc193
EH		 6233 .set_fan_control_mode = tonga_set_fan_control_mode,
6234 .get_fan_control_mode = tonga_get_fan_control_mode,
5d37a63d
EH		 6235 .get_pp_table = tonga_get_pp_table,
6236 .set_pp_table = tonga_set_pp_table,
6237 .force_clock_level = tonga_force_clock_level,
6238 .print_clock_levels = tonga_print_clock_levels,
c82baa28 6239};
6240
6241int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
6242{
6243 tonga_hwmgr *data;
6244
6245 data = kzalloc (sizeof(tonga_hwmgr), GFP_KERNEL);
6246 if (data == NULL)
6247 return -ENOMEM;
6248 memset(data, 0x00, sizeof(tonga_hwmgr));
6249
6250 hwmgr->backend = data;
6251 hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
6252 hwmgr->pptable_func = &tonga_pptable_funcs;
1e4854e9 6253 pp_tonga_thermal_initialize(hwmgr);
c82baa28 6254 return 0;
6255}
6256
Linux 6.x block layer and io_uring tree(s)