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drm/amdgpu: Simplify calculation in *get_sleep_divider_id_from_clock
[linux-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / tonga_hwmgr.c
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c82baa28 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include "linux/delay.h"
27#include "pp_acpi.h"
28#include "hwmgr.h"
29#include <atombios.h>
30#include "tonga_hwmgr.h"
31#include "pptable.h"
32#include "processpptables.h"
33#include "tonga_processpptables.h"
34#include "tonga_pptable.h"
35#include "pp_debug.h"
36#include "tonga_ppsmc.h"
37#include "cgs_common.h"
38#include "pppcielanes.h"
39#include "tonga_dyn_defaults.h"
40#include "smumgr.h"
41#include "tonga_smumgr.h"
0859ed3d 42#include "tonga_clockpowergating.h"
1e4854e9 43#include "tonga_thermal.h"
c82baa28 44
45#include "smu/smu_7_1_2_d.h"
46#include "smu/smu_7_1_2_sh_mask.h"
47
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50
51#include "bif/bif_5_0_d.h"
52#include "bif/bif_5_0_sh_mask.h"
53
7e8d1fbd
AD		 54#include "dce/dce_10_0_d.h"
55#include "dce/dce_10_0_sh_mask.h"
56
1e4854e9
RZ		 57#include "cgs_linux.h"
58#include "eventmgr.h"
16881da6 59#include "amd_pcie_helpers.h"
1e4854e9 60
c82baa28 61#define MC_CG_ARB_FREQ_F0 0x0a
62#define MC_CG_ARB_FREQ_F1 0x0b
63#define MC_CG_ARB_FREQ_F2 0x0c
64#define MC_CG_ARB_FREQ_F3 0x0d
65
66#define MC_CG_SEQ_DRAMCONF_S0 0x05
67#define MC_CG_SEQ_DRAMCONF_S1 0x06
68#define MC_CG_SEQ_YCLK_SUSPEND 0x04
69#define MC_CG_SEQ_YCLK_RESUME 0x0a
70
71#define PCIE_BUS_CLK 10000
72#define TCLK (PCIE_BUS_CLK / 10)
73
74#define SMC_RAM_END 0x40000
75#define SMC_CG_IND_START 0xc0030000
76#define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/
77
78#define VOLTAGE_SCALE 4
79#define VOLTAGE_VID_OFFSET_SCALE1 625
80#define VOLTAGE_VID_OFFSET_SCALE2 100
81
82#define VDDC_VDDCI_DELTA 200
83#define VDDC_VDDGFX_DELTA 300
84
85#define MC_SEQ_MISC0_GDDR5_SHIFT 28
86#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
87#define MC_SEQ_MISC0_GDDR5_VALUE 5
88
89typedef uint32_t PECI_RegistryValue;
90
91/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
f498d9ed 92static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
c82baa28 93 {600, 1050, 3, 0},
94 {600, 1050, 6, 1} };
95
96/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
f498d9ed 97static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
c82baa28 98 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
99 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
100
101/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
f498d9ed 102static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
c82baa28 103 {0, 1, 3, 2, 4, 5},
104 {0, 2, 4, 5, 6, 5} };
105
106/* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
107enum DPM_EVENT_SRC {
108 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
109 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
110 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
111 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
112 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
113};
114typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
115
f498d9ed 116static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
c82baa28 117
118struct tonga_power_state *cast_phw_tonga_power_state(
119 struct pp_hw_power_state *hw_ps)
120{
c15c8d70
RZ		 121 if (hw_ps == NULL)
122 return NULL;
123
c82baa28 124 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
125 "Invalid Powerstate Type!",
c15c8d70 126 return NULL);
c82baa28 127
128 return (struct tonga_power_state *)hw_ps;
129}
130
131const struct tonga_power_state *cast_const_phw_tonga_power_state(
132 const struct pp_hw_power_state *hw_ps)
133{
c15c8d70
RZ		 134 if (hw_ps == NULL)
135 return NULL;
136
c82baa28 137 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
138 "Invalid Powerstate Type!",
c15c8d70 139 return NULL);
c82baa28 140
141 return (const struct tonga_power_state *)hw_ps;
142}
143
144int tonga_add_voltage(struct pp_hwmgr *hwmgr,
145 phm_ppt_v1_voltage_lookup_table *look_up_table,
146 phm_ppt_v1_voltage_lookup_record *record)
147{
148 uint32_t i;
149 PP_ASSERT_WITH_CODE((NULL != look_up_table),
150 "Lookup Table empty.", return -1;);
151 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
152 "Lookup Table empty.", return -1;);
153 PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
154 "Lookup Table is full.", return -1;);
155
156 /* This is to avoid entering duplicate calculated records. */
157 for (i = 0; i < look_up_table->count; i++) {
158 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
159 if (look_up_table->entries[i].us_calculated == 1)
160 return 0;
161 else
162 break;
163 }
164 }
165
166 look_up_table->entries[i].us_calculated = 1;
167 look_up_table->entries[i].us_vdd = record->us_vdd;
168 look_up_table->entries[i].us_cac_low = record->us_cac_low;
169 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
170 look_up_table->entries[i].us_cac_high = record->us_cac_high;
171 /* Only increment the count when we're appending, not replacing duplicate entry. */
172 if (i == look_up_table->count)
173 look_up_table->count++;
174
175 return 0;
176}
177
bbb207f3
RZ		 178int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
179{
180 PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
181
182 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
183}
184
c82baa28 185uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
186 uint32_t voltage)
187{
188 uint8_t count = (uint8_t) (voltage_table->count);
189 uint8_t i = 0;
190
191 PP_ASSERT_WITH_CODE((NULL != voltage_table),
192 "Voltage Table empty.", return 0;);
193 PP_ASSERT_WITH_CODE((0 != count),
194 "Voltage Table empty.", return 0;);
195
196 for (i = 0; i < count; i++) {
197 /* find first voltage bigger than requested */
198 if (voltage_table->entries[i].value >= voltage)
199 return i;
200 }
201
202 /* voltage is bigger than max voltage in the table */
203 return i - 1;
204}
205
206/**
207 * @brief PhwTonga_GetVoltageOrder
208 * Returns index of requested voltage record in lookup(table)
209 * @param hwmgr - pointer to hardware manager
210 * @param lookupTable - lookup list to search in
211 * @param voltage - voltage to look for
212 * @return 0 on success
213 */
214uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
215 uint16_t voltage)
216{
217 uint8_t count = (uint8_t) (look_up_table->count);
218 uint8_t i;
219
220 PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
221 PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
222
223 for (i = 0; i < count; i++) {
224 /* find first voltage equal or bigger than requested */
225 if (look_up_table->entries[i].us_vdd >= voltage)
226 return i;
227 }
228
229 /* voltage is bigger than max voltage in the table */
230 return i-1;
231}
232
233bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
234{
235 /*
236 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
237 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
238 * whereas voltage control is a fundemental change that will not be disabled
239 */
240
241 return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
242 FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
243}
244
245/**
246 * Re-generate the DPM level mask value
247 * @param hwmgr the address of the hardware manager
248 */
249static uint32_t tonga_get_dpm_level_enable_mask_value(
250 struct tonga_single_dpm_table * dpm_table)
251{
252 uint32_t i;
253 uint32_t mask_value = 0;
254
255 for (i = dpm_table->count; i > 0; i--) {
256 mask_value = mask_value << 1;
257
258 if (dpm_table->dpm_levels[i-1].enabled)
259 mask_value |= 0x1;
260 else
261 mask_value &= 0xFFFFFFFE;
262 }
263 return mask_value;
264}
265
266/**
267 * Retrieve DPM default values from registry (if available)
268 *
269 * @param hwmgr the address of the powerplay hardware manager.
270 */
271void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
272{
273 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
274 phw_tonga_ulv_parm *ulv = &(data->ulv);
275 uint32_t tmp;
276
277 ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
278 data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
279 data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
280 data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
281 data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
282 data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
283 data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
284 data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
285 data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
286
287 data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
288 data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
289
290 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_ABM);
292 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
293 PHM_PlatformCaps_NonABMSupportInPPLib);
294
295 tmp = 0;
296 if (tmp == 0)
297 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
298 PHM_PlatformCaps_DynamicACTiming);
299
300 tmp = 0;
301 if (0 != tmp)
302 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
303 PHM_PlatformCaps_DisableMemoryTransition);
304
305 data->mclk_strobe_mode_threshold = 40000;
306 data->mclk_stutter_mode_threshold = 30000;
307 data->mclk_edc_enable_threshold = 40000;
308 data->mclk_edc_wr_enable_threshold = 40000;
309
310 tmp = 0;
311 if (tmp != 0)
312 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
313 PHM_PlatformCaps_DisableMCLS);
314
315 data->pcie_gen_performance.max = PP_PCIEGen1;
316 data->pcie_gen_performance.min = PP_PCIEGen3;
317 data->pcie_gen_power_saving.max = PP_PCIEGen1;
318 data->pcie_gen_power_saving.min = PP_PCIEGen3;
319
320 data->pcie_lane_performance.max = 0;
321 data->pcie_lane_performance.min = 16;
322 data->pcie_lane_power_saving.max = 0;
323 data->pcie_lane_power_saving.min = 16;
324
325 tmp = 0;
326
327 if (tmp)
328 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
329 PHM_PlatformCaps_SclkThrottleLowNotification);
330
331 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
332 PHM_PlatformCaps_DynamicUVDState);
333
334}
335
336int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
337{
338 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
339
340 int result = 0;
341 uint32_t low_sclk_interrupt_threshold = 0;
342
343 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
344 PHM_PlatformCaps_SclkThrottleLowNotification)
345 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
346 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
347 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
348
349 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
350
351 result = tonga_copy_bytes_to_smc(
352 hwmgr->smumgr,
353 data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
354 LowSclkInterruptThreshold),
355 (uint8_t *)&low_sclk_interrupt_threshold,
356 sizeof(uint32_t),
357 data->sram_end
358 );
359 }
360
361 return result;
362}
363
364/**
365 * Find SCLK value that is associated with specified virtual_voltage_Id.
366 *
367 * @param hwmgr the address of the powerplay hardware manager.
368 * @param virtual_voltage_Id voltageId to look for.
369 * @param sclk output value .
370 * @return always 0 if success and 2 if association not found
371 */
372static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
373 phm_ppt_v1_voltage_lookup_table *lookup_table,
374 uint16_t virtual_voltage_id, uint32_t *sclk)
375{
376 uint8_t entryId;
377 uint8_t voltageId;
378 struct phm_ppt_v1_information *pptable_info =
379 (struct phm_ppt_v1_information *)(hwmgr->pptable);
380
381 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
382
383 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
384 for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
385 voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
386 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
387 break;
388 }
389
390 PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
391 "Can't find requested voltage id in vdd_dep_on_sclk table!",
392 return -1;
393 );
394
395 *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
396
397 return 0;
398}
399
400/**
401 * Get Leakage VDDC based on leakage ID.
402 *
403 * @param hwmgr the address of the powerplay hardware manager.
404 * @return 2 if vddgfx returned is greater than 2V or if BIOS
405 */
406int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
407{
408 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
409 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
410 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
411 uint16_t virtual_voltage_id;
412 uint16_t vddc = 0;
413 uint16_t vddgfx = 0;
414 uint16_t i, j;
415 uint32_t sclk = 0;
416
417 /* retrieve voltage for leakage ID (0xff01 + i) */
418 for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
419 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
420
421 /* in split mode we should have only vddgfx EVV leakages */
422 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
423 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
424 pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
425 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
426 PHM_PlatformCaps_ClockStretcher)) {
427 for (j = 1; j < sclk_table->count; j++) {
428 if (sclk_table->entries[j].clk == sclk &&
429 sclk_table->entries[j].cks_enable == 0) {
430 sclk += 5000;
431 break;
432 }
433 }
434 }
ac0cc350
MK		 435 if (0 == atomctrl_get_voltage_evv_on_sclk
436 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
437 virtual_voltage_id, &vddgfx)) {
438 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
439 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
440
441 /* the voltage should not be zero nor equal to leakage ID */
442 if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
443 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
444 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
445 data->vddcgfx_leakage.count++;
446 }
447 } else {
448 printk("Error retrieving EVV voltage value!\n");
c82baa28 449 }
450 }
451 } else {
452 /* in merged mode we have only vddc EVV leakages */
453 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
454 pptable_info->vddc_lookup_table,
455 virtual_voltage_id, &sclk)) {
ac0cc350
MK		 456 if (0 == atomctrl_get_voltage_evv_on_sclk
457 (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
458 virtual_voltage_id, &vddc)) {
459 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
460 PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
461
462 /* the voltage should not be zero nor equal to leakage ID */
463 if (vddc != 0 && vddc != virtual_voltage_id) {
464 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
465 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
466 data->vddc_leakage.count++;
467 }
468 } else {
469 printk("Error retrieving EVV voltage value!\n");
c82baa28 470 }
471 }
472 }
473 }
474
475 return 0;
476}
477
478int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
479{
480 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
481
482 /* enable SCLK dpm */
483 if (0 == data->sclk_dpm_key_disabled) {
484 PP_ASSERT_WITH_CODE(
485 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
486 PPSMC_MSG_DPM_Enable)),
487 "Failed to enable SCLK DPM during DPM Start Function!",
488 return -1);
489 }
490
491 /* enable MCLK dpm */
492 if (0 == data->mclk_dpm_key_disabled) {
493 PP_ASSERT_WITH_CODE(
494 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
495 PPSMC_MSG_MCLKDPM_Enable)),
496 "Failed to enable MCLK DPM during DPM Start Function!",
497 return -1);
498
499 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
500
501 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
502 ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
503 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
504 ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
505 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
506 ixLCAC_CPL_CNTL, 0x100005);/*Read */
507
508 udelay(10);
509
510 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
511 ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
512 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
513 ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
514 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
515 ixLCAC_CPL_CNTL, 0x500005);/* write */
516
517 }
518
519 return 0;
520}
521
522int tonga_start_dpm(struct pp_hwmgr *hwmgr)
523{
524 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
525
526 /* enable general power management */
527 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
528 /* enable sclk deep sleep */
529 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
530
531 /* prepare for PCIE DPM */
532 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
533 offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
534
535 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
536
537 PP_ASSERT_WITH_CODE(
538 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
539 PPSMC_MSG_Voltage_Cntl_Enable)),
540 "Failed to enable voltage DPM during DPM Start Function!",
541 return -1);
542
543 if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
544 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
545 }
546
547 /* enable PCIE dpm */
548 if (0 == data->pcie_dpm_key_disabled) {
549 PP_ASSERT_WITH_CODE(
550 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
551 PPSMC_MSG_PCIeDPM_Enable)),
552 "Failed to enable pcie DPM during DPM Start Function!",
553 return -1
554 );
555 }
556
557 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
558 PHM_PlatformCaps_Falcon_QuickTransition)) {
559 smum_send_msg_to_smc(hwmgr->smumgr,
560 PPSMC_MSG_EnableACDCGPIOInterrupt);
561 }
562
563 return 0;
564}
565
566int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
567{
568 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
569
570 /* disable SCLK dpm */
571 if (0 == data->sclk_dpm_key_disabled) {
572 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
573 PP_ASSERT_WITH_CODE(
574 (0 == tonga_is_dpm_running(hwmgr)),
575 "Trying to Disable SCLK DPM when DPM is disabled",
576 return -1
577 );
578
579 PP_ASSERT_WITH_CODE(
580 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
581 PPSMC_MSG_DPM_Disable)),
582 "Failed to disable SCLK DPM during DPM stop Function!",
583 return -1);
584 }
585
586 /* disable MCLK dpm */
587 if (0 == data->mclk_dpm_key_disabled) {
588 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
589 PP_ASSERT_WITH_CODE(
590 (0 == tonga_is_dpm_running(hwmgr)),
591 "Trying to Disable MCLK DPM when DPM is disabled",
592 return -1
593 );
594
595 PP_ASSERT_WITH_CODE(
596 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
597 PPSMC_MSG_MCLKDPM_Disable)),
598 "Failed to Disable MCLK DPM during DPM stop Function!",
599 return -1);
600 }
601
602 return 0;
603}
604
605int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
606{
607 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
608
609 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
610 /* disable sclk deep sleep*/
611 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
612
613 /* disable PCIE dpm */
614 if (0 == data->pcie_dpm_key_disabled) {
615 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
616 PP_ASSERT_WITH_CODE(
617 (0 == tonga_is_dpm_running(hwmgr)),
618 "Trying to Disable PCIE DPM when DPM is disabled",
619 return -1
620 );
621 PP_ASSERT_WITH_CODE(
622 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
623 PPSMC_MSG_PCIeDPM_Disable)),
624 "Failed to disable pcie DPM during DPM stop Function!",
625 return -1);
626 }
627
628 if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
629 PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
630
631 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
632 PP_ASSERT_WITH_CODE(
633 (0 == tonga_is_dpm_running(hwmgr)),
634 "Trying to Disable Voltage CNTL when DPM is disabled",
635 return -1
636 );
637
638 PP_ASSERT_WITH_CODE(
639 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
640 PPSMC_MSG_Voltage_Cntl_Disable)),
641 "Failed to disable voltage DPM during DPM stop Function!",
642 return -1);
643
644 return 0;
645}
646
647int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
648{
649 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
650
651 return 0;
652}
653
654/**
655 * Send a message to the SMC and return a parameter
656 *
657 * @param hwmgr: the address of the powerplay hardware manager.
658 * @param msg: the message to send.
659 * @param parameter: pointer to the received parameter
660 * @return The response that came from the SMC.
661 */
662PPSMC_Result tonga_send_msg_to_smc_return_parameter(
663 struct pp_hwmgr *hwmgr,
664 PPSMC_Msg msg,
665 uint32_t *parameter)
666{
667 int result;
668
669 result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
670
671 if ((0 == result) && parameter) {
672 *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
673 }
674
675 return result;
676}
677
678/**
679 * force DPM power State
680 *
681 * @param hwmgr: the address of the powerplay hardware manager.
682 * @param n : DPM level
683 * @return The response that came from the SMC.
684 */
685int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
686{
687 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
688 uint32_t level_mask = 1 << n;
689
690 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
691 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
692 "Trying to force SCLK when DPM is disabled", return -1;);
693 if (0 == data->sclk_dpm_key_disabled)
694 return (0 == smum_send_msg_to_smc_with_parameter(
695 hwmgr->smumgr,
696 (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
697 level_mask) ? 0 : 1);
698
699 return 0;
700}
701
702/**
703 * force DPM power State
704 *
705 * @param hwmgr: the address of the powerplay hardware manager.
706 * @param n : DPM level
707 * @return The response that came from the SMC.
708 */
709int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
710{
711 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
712 uint32_t level_mask = 1 << n;
713
714 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
715 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
716 "Trying to Force MCLK when DPM is disabled", return -1;);
717 if (0 == data->mclk_dpm_key_disabled)
718 return (0 == smum_send_msg_to_smc_with_parameter(
719 hwmgr->smumgr,
720 (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
721 level_mask) ? 0 : 1);
722
723 return 0;
724}
725
726/**
727 * force DPM power State
728 *
729 * @param hwmgr: the address of the powerplay hardware manager.
730 * @param n : DPM level
731 * @return The response that came from the SMC.
732 */
733int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
734{
735 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
736
737 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
738 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
739 "Trying to Force PCIE level when DPM is disabled", return -1;);
740 if (0 == data->pcie_dpm_key_disabled)
741 return (0 == smum_send_msg_to_smc_with_parameter(
742 hwmgr->smumgr,
743 (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
744 n) ? 0 : 1);
745
746 return 0;
747}
748
749/**
750 * Set the initial state by calling SMC to switch to this state directly
751 *
752 * @param hwmgr the address of the powerplay hardware manager.
753 * @return always 0
754 */
755int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
756{
757 /*
758 * SMC only stores one state that SW will ask to switch too,
759 * so we switch the the just uploaded one
760 */
761 return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
762}
763
764/**
765 * Get the location of various tables inside the FW image.
766 *
767 * @param hwmgr the address of the powerplay hardware manager.
768 * @return always 0
769 */
770int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
771{
772 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
773 struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
774
775 uint32_t tmp;
776 int result;
777 bool error = 0;
778
779 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
780 SMU72_FIRMWARE_HEADER_LOCATION +
781 offsetof(SMU72_Firmware_Header, DpmTable),
782 &tmp, data->sram_end);
783
784 if (0 == result) {
785 data->dpm_table_start = tmp;
786 }
787
788 error |= (0 != result);
789
790 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
791 SMU72_FIRMWARE_HEADER_LOCATION +
792 offsetof(SMU72_Firmware_Header, SoftRegisters),
793 &tmp, data->sram_end);
794
795 if (0 == result) {
796 data->soft_regs_start = tmp;
797 tonga_smu->ulSoftRegsStart = tmp;
798 }
799
800 error |= (0 != result);
801
802
803 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
804 SMU72_FIRMWARE_HEADER_LOCATION +
805 offsetof(SMU72_Firmware_Header, mcRegisterTable),
806 &tmp, data->sram_end);
807
808 if (0 == result) {
809 data->mc_reg_table_start = tmp;
810 }
811
812 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
813 SMU72_FIRMWARE_HEADER_LOCATION +
814 offsetof(SMU72_Firmware_Header, FanTable),
815 &tmp, data->sram_end);
816
817 if (0 == result) {
818 data->fan_table_start = tmp;
819 }
820
821 error |= (0 != result);
822
823 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
824 SMU72_FIRMWARE_HEADER_LOCATION +
825 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
826 &tmp, data->sram_end);
827
828 if (0 == result) {
829 data->arb_table_start = tmp;
830 }
831
832 error |= (0 != result);
833
834
835 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
836 SMU72_FIRMWARE_HEADER_LOCATION +
837 offsetof(SMU72_Firmware_Header, Version),
838 &tmp, data->sram_end);
839
840 if (0 == result) {
841 hwmgr->microcode_version_info.SMC = tmp;
842 }
843
844 error |= (0 != result);
845
846 return error ? 1 : 0;
847}
848
849/**
850 * Read clock related registers.
851 *
852 * @param hwmgr the address of the powerplay hardware manager.
853 * @return always 0
854 */
855int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
856{
857 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
858
859 data->clock_registers.vCG_SPLL_FUNC_CNTL =
860 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
861 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
862 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
863 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
864 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
865 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
866 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
867 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
868 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
869 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
870 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
871 data->clock_registers.vDLL_CNTL =
872 cgs_read_register(hwmgr->device, mmDLL_CNTL);
873 data->clock_registers.vMCLK_PWRMGT_CNTL =
874 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
875 data->clock_registers.vMPLL_AD_FUNC_CNTL =
876 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
877 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
878 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
879 data->clock_registers.vMPLL_FUNC_CNTL =
880 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
881 data->clock_registers.vMPLL_FUNC_CNTL_1 =
882 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
883 data->clock_registers.vMPLL_FUNC_CNTL_2 =
884 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
885 data->clock_registers.vMPLL_SS1 =
886 cgs_read_register(hwmgr->device, mmMPLL_SS1);
887 data->clock_registers.vMPLL_SS2 =
888 cgs_read_register(hwmgr->device, mmMPLL_SS2);
889
890 return 0;
891}
892
893/**
894 * Find out if memory is GDDR5.
895 *
896 * @param hwmgr the address of the powerplay hardware manager.
897 * @return always 0
898 */
899int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
900{
901 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
902 uint32_t temp;
903
904 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
905
906 data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
907 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
908 MC_SEQ_MISC0_GDDR5_SHIFT));
909
910 return 0;
911}
912
913/**
914 * Enables Dynamic Power Management by SMC
915 *
916 * @param hwmgr the address of the powerplay hardware manager.
917 * @return always 0
918 */
919int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
920{
921 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
922
923 return 0;
924}
925
926/**
927 * Initialize PowerGating States for different engines
928 *
929 * @param hwmgr the address of the powerplay hardware manager.
930 * @return always 0
931 */
932int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
933{
934 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
935
936 data->uvd_power_gated = 0;
937 data->vce_power_gated = 0;
938 data->samu_power_gated = 0;
939 data->acp_power_gated = 0;
940 data->pg_acp_init = 1;
941
942 return 0;
943}
944
945/**
946 * Checks if DPM is enabled
947 *
948 * @param hwmgr the address of the powerplay hardware manager.
949 * @return always 0
950 */
951int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
952{
953 /*
954 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
955 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
956 * whereas voltage control is a fundemental change that will not be disabled
957 */
958 return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
959}
960
961/**
962 * Checks if DPM is stopped
963 *
964 * @param hwmgr the address of the powerplay hardware manager.
965 * @return always 0
966 */
967int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
968{
969 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
970
971 if (0 != tonga_is_dpm_running(hwmgr)) {
972 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
973 if (!data->dpm_table_start) {
974 return 1;
975 }
976 }
977
978 return 0;
979}
980
981/**
982 * Remove repeated voltage values and create table with unique values.
983 *
984 * @param hwmgr the address of the powerplay hardware manager.
985 * @param voltage_table the pointer to changing voltage table
986 * @return 1 in success
987 */
988
989static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
990 pp_atomctrl_voltage_table *voltage_table)
991{
992 uint32_t table_size, i, j;
993 uint16_t vvalue;
994 bool bVoltageFound = 0;
995 pp_atomctrl_voltage_table *table;
996
997 PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
998 table_size = sizeof(pp_atomctrl_voltage_table);
999 table = kzalloc(table_size, GFP_KERNEL);
1000
1001 if (NULL == table)
1002 return -ENOMEM;
1003
1004 memset(table, 0x00, table_size);
1005 table->mask_low = voltage_table->mask_low;
1006 table->phase_delay = voltage_table->phase_delay;
1007
1008 for (i = 0; i < voltage_table->count; i++) {
1009 vvalue = voltage_table->entries[i].value;
1010 bVoltageFound = 0;
1011
1012 for (j = 0; j < table->count; j++) {
1013 if (vvalue == table->entries[j].value) {
1014 bVoltageFound = 1;
1015 break;
1016 }
1017 }
1018
1019 if (!bVoltageFound) {
1020 table->entries[table->count].value = vvalue;
1021 table->entries[table->count].smio_low =
1022 voltage_table->entries[i].smio_low;
1023 table->count++;
1024 }
1025 }
1026
1027 memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
1028
1029 kfree(table);
1030
1031 return 0;
1032}
1033
1034static int tonga_get_svi2_vdd_ci_voltage_table(
1035 struct pp_hwmgr *hwmgr,
1036 phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
1037{
1038 uint32_t i;
1039 int result;
1040 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1041 pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
1042
1043 PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
1044 "Voltage Dependency Table empty.", return -1;);
1045
1046 vddci_voltage_table->mask_low = 0;
1047 vddci_voltage_table->phase_delay = 0;
1048 vddci_voltage_table->count = voltage_dependency_table->count;
1049
1050 for (i = 0; i < voltage_dependency_table->count; i++) {
1051 vddci_voltage_table->entries[i].value =
1052 voltage_dependency_table->entries[i].vddci;
1053 vddci_voltage_table->entries[i].smio_low = 0;
1054 }
1055
1056 result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
1057 PP_ASSERT_WITH_CODE((0 == result),
1058 "Failed to trim VDDCI table.", return result;);
1059
1060 return 0;
1061}
1062
1063
1064
1065static int tonga_get_svi2_vdd_voltage_table(
1066 struct pp_hwmgr *hwmgr,
1067 phm_ppt_v1_voltage_lookup_table *look_up_table,
1068 pp_atomctrl_voltage_table *voltage_table)
1069{
1070 uint8_t i = 0;
1071
1072 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1073 "Voltage Lookup Table empty.", return -1;);
1074
1075 voltage_table->mask_low = 0;
1076 voltage_table->phase_delay = 0;
1077
1078 voltage_table->count = look_up_table->count;
1079
1080 for (i = 0; i < voltage_table->count; i++) {
1081 voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
1082 voltage_table->entries[i].smio_low = 0;
1083 }
1084
1085 return 0;
1086}
1087
1088/*
1089 * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
1090 * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
1091 */
1092
1093static void tonga_trim_voltage_table_to_fit_state_table(
1094 struct pp_hwmgr *hwmgr,
1095 uint32_t max_voltage_steps,
1096 pp_atomctrl_voltage_table *voltage_table)
1097{
1098 unsigned int i, diff;
1099
1100 if (voltage_table->count <= max_voltage_steps) {
1101 return;
1102 }
1103
1104 diff = voltage_table->count - max_voltage_steps;
1105
1106 for (i = 0; i < max_voltage_steps; i++) {
1107 voltage_table->entries[i] = voltage_table->entries[i + diff];
1108 }
1109
1110 voltage_table->count = max_voltage_steps;
1111
1112 return;
1113}
1114
1115/**
1116 * Create Voltage Tables.
1117 *
1118 * @param hwmgr the address of the powerplay hardware manager.
1119 * @return always 0
1120 */
1121int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1122{
1123 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1124 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1125 int result;
1126
1127 /* MVDD has only GPIO voltage control */
1128 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1129 result = atomctrl_get_voltage_table_v3(hwmgr,
1130 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
1131 PP_ASSERT_WITH_CODE((0 == result),
1132 "Failed to retrieve MVDD table.", return result;);
1133 }
1134
1135 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1136 /* GPIO voltage */
1137 result = atomctrl_get_voltage_table_v3(hwmgr,
1138 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
1139 PP_ASSERT_WITH_CODE((0 == result),
1140 "Failed to retrieve VDDCI table.", return result;);
1141 } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1142 /* SVI2 voltage */
1143 result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
1144 pptable_info->vdd_dep_on_mclk);
1145 PP_ASSERT_WITH_CODE((0 == result),
1146 "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
1147 }
1148
1149 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1150 /* VDDGFX has only SVI2 voltage control */
1151 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1152 pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
1153 PP_ASSERT_WITH_CODE((0 == result),
1154 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
1155 }
1156
1157 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1158 /* VDDC has only SVI2 voltage control */
1159 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1160 pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
1161 PP_ASSERT_WITH_CODE((0 == result),
1162 "Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
1163 }
1164
1165 PP_ASSERT_WITH_CODE(
1166 (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
1167 "Too many voltage values for VDDC. Trimming to fit state table.",
1168 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1169 SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
1170 );
1171
1172 PP_ASSERT_WITH_CODE(
1173 (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
1174 "Too many voltage values for VDDGFX. Trimming to fit state table.",
1175 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1176 SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
1177 );
1178
1179 PP_ASSERT_WITH_CODE(
1180 (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
1181 "Too many voltage values for VDDCI. Trimming to fit state table.",
1182 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1183 SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
1184 );
1185
1186 PP_ASSERT_WITH_CODE(
1187 (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
1188 "Too many voltage values for MVDD. Trimming to fit state table.",
1189 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1190 SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
1191 );
1192
1193 return 0;
1194}
1195
1196/**
1197 * Vddc table preparation for SMC.
1198 *
1199 * @param hwmgr the address of the hardware manager
1200 * @param table the SMC DPM table structure to be populated
1201 * @return always 0
1202 */
1203static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1204 SMU72_Discrete_DpmTable *table)
1205{
1206 unsigned int count;
1207 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1208
1209 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1210 table->VddcLevelCount = data->vddc_voltage_table.count;
1211 for (count = 0; count < table->VddcLevelCount; count++) {
1212 table->VddcTable[count] =
1213 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
1214 }
1215 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1216 }
1217 return 0;
1218}
1219
1220/**
1221 * VddGfx table preparation for SMC.
1222 *
1223 * @param hwmgr the address of the hardware manager
1224 * @param table the SMC DPM table structure to be populated
1225 * @return always 0
1226 */
1227static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
1228 SMU72_Discrete_DpmTable *table)
1229{
1230 unsigned int count;
1231 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1232
1233 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1234 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
1235 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
1236 table->VddGfxTable[count] =
1237 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
1238 }
1239 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
1240 }
1241 return 0;
1242}
1243
1244/**
1245 * Vddci table preparation for SMC.
1246 *
1247 * @param *hwmgr The address of the hardware manager.
1248 * @param *table The SMC DPM table structure to be populated.
1249 * @return 0
1250 */
1251static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1252 SMU72_Discrete_DpmTable *table)
1253{
1254 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1255 uint32_t count;
1256
1257 table->VddciLevelCount = data->vddci_voltage_table.count;
1258 for (count = 0; count < table->VddciLevelCount; count++) {
1259 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1260 table->VddciTable[count] =
1261 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1262 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1263 table->SmioTable1.Pattern[count].Voltage =
1264 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1265 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
1266 table->SmioTable1.Pattern[count].Smio =
1267 (uint8_t) count;
1268 table->Smio[count] |=
1269 data->vddci_voltage_table.entries[count].smio_low;
1270 table->VddciTable[count] =
1271 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1272 }
1273 }
1274
1275 table->SmioMask1 = data->vddci_voltage_table.mask_low;
1276 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
1277
1278 return 0;
1279}
1280
1281/**
1282 * Mvdd table preparation for SMC.
1283 *
1284 * @param *hwmgr The address of the hardware manager.
1285 * @param *table The SMC DPM table structure to be populated.
1286 * @return 0
1287 */
1288static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1289 SMU72_Discrete_DpmTable *table)
1290{
1291 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1292 uint32_t count;
1293
1294 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1295 table->MvddLevelCount = data->mvdd_voltage_table.count;
1296 for (count = 0; count < table->MvddLevelCount; count++) {
1297 table->SmioTable2.Pattern[count].Voltage =
1298 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
1299 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
1300 table->SmioTable2.Pattern[count].Smio =
1301 (uint8_t) count;
1302 table->Smio[count] |=
1303 data->mvdd_voltage_table.entries[count].smio_low;
1304 }
1305 table->SmioMask2 = data->vddci_voltage_table.mask_low;
1306
1307 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1308 }
1309
1310 return 0;
1311}
1312
1313/**
1314 * Convert a voltage value in mv unit to VID number required by SMU firmware
1315 */
1316static uint8_t convert_to_vid(uint16_t vddc)
1317{
1318 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1319}
1320
1321
1322/**
1323 * Preparation of vddc and vddgfx CAC tables for SMC.
1324 *
1325 * @param hwmgr the address of the hardware manager
1326 * @param table the SMC DPM table structure to be populated
1327 * @return always 0
1328 */
1329static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
1330 SMU72_Discrete_DpmTable *table)
1331{
1332 uint32_t count;
1333 uint8_t index;
1334 int result = 0;
1335 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1336 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1337 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
1338 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
1339
1340 /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
1341 uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
1342 uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
1343
1344 for (count = 0; count < vddcLevelCount; count++) {
1345 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
1346 index = tonga_get_voltage_index(vddc_lookup_table,
1347 data->vddc_voltage_table.entries[count].value);
1348 table->BapmVddcVidLoSidd[count] =
1349 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1350 table->BapmVddcVidHiSidd[count] =
1351 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1352 table->BapmVddcVidHiSidd2[count] =
1353 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1354 }
1355
1356 if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
1357 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
1358 for (count = 0; count < vddgfxLevelCount; count++) {
1359 index = tonga_get_voltage_index(vddgfx_lookup_table,
1360 data->vddgfx_voltage_table.entries[count].value);
1361 table->BapmVddGfxVidLoSidd[count] =
1362 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
1363 table->BapmVddGfxVidHiSidd[count] =
1364 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
1365 table->BapmVddGfxVidHiSidd2[count] =
1366 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
1367 }
1368 } else {
1369 for (count = 0; count < vddcLevelCount; count++) {
1370 index = tonga_get_voltage_index(vddc_lookup_table,
1371 data->vddc_voltage_table.entries[count].value);
1372 table->BapmVddGfxVidLoSidd[count] =
1373 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1374 table->BapmVddGfxVidHiSidd[count] =
1375 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1376 table->BapmVddGfxVidHiSidd2[count] =
1377 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1378 }
1379 }
1380
1381 return result;
1382}
1383
1384
1385/**
1386 * Preparation of voltage tables for SMC.
1387 *
1388 * @param hwmgr the address of the hardware manager
1389 * @param table the SMC DPM table structure to be populated
1390 * @return always 0
1391 */
1392
1393int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1394 SMU72_Discrete_DpmTable *table)
1395{
1396 int result;
1397
1398 result = tonga_populate_smc_vddc_table(hwmgr, table);
1399 PP_ASSERT_WITH_CODE(0 == result,
1400 "can not populate VDDC voltage table to SMC", return -1);
1401
1402 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
1403 PP_ASSERT_WITH_CODE(0 == result,
1404 "can not populate VDDCI voltage table to SMC", return -1);
1405
1406 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
1407 PP_ASSERT_WITH_CODE(0 == result,
1408 "can not populate VDDGFX voltage table to SMC", return -1);
1409
1410 result = tonga_populate_smc_mvdd_table(hwmgr, table);
1411 PP_ASSERT_WITH_CODE(0 == result,
1412 "can not populate MVDD voltage table to SMC", return -1);
1413
1414 result = tonga_populate_cac_tables(hwmgr, table);
1415 PP_ASSERT_WITH_CODE(0 == result,
1416 "can not populate CAC voltage tables to SMC", return -1);
1417
1418 return 0;
1419}
1420
1421/**
1422 * Populates the SMC VRConfig field in DPM table.
1423 *
1424 * @param hwmgr the address of the hardware manager
1425 * @param table the SMC DPM table structure to be populated
1426 * @return always 0
1427 */
1428static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1429 SMU72_Discrete_DpmTable *table)
1430{
1431 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1432 uint16_t config;
1433
1434 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1435 /* Splitted mode */
1436 config = VR_SVI2_PLANE_1;
1437 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1438
1439 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1440 config = VR_SVI2_PLANE_2;
1441 table->VRConfig |= config;
1442 } else {
1443 printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
1444 }
1445 } else {
1446 /* Merged mode */
1447 config = VR_MERGED_WITH_VDDC;
1448 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1449
1450 /* Set Vddc Voltage Controller */
1451 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1452 config = VR_SVI2_PLANE_1;
1453 table->VRConfig |= config;
1454 } else {
1455 printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
1456 }
1457 }
1458
1459 /* Set Vddci Voltage Controller */
1460 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1461 config = VR_SVI2_PLANE_2; /* only in merged mode */
1462 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1463 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1464 config = VR_SMIO_PATTERN_1;
1465 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1466 }
1467
1468 /* Set Mvdd Voltage Controller */
1469 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1470 config = VR_SMIO_PATTERN_2;
1471 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1472 }
1473
1474 return 0;
1475}
1476
1477static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1478 phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
1479 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1480{
1481 uint32_t i = 0;
1482 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1483 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1484
1485 /* clock - voltage dependency table is empty table */
1486 if (allowed_clock_voltage_table->count == 0)
1487 return -1;
1488
1489 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1490 /* find first sclk bigger than request */
1491 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1492 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1493 allowed_clock_voltage_table->entries[i].vddgfx);
1494
1495 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1496 allowed_clock_voltage_table->entries[i].vddc);
1497
1498 if (allowed_clock_voltage_table->entries[i].vddci) {
1499 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1500 allowed_clock_voltage_table->entries[i].vddci);
1501 } else {
1502 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1503 allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
1504 }
1505
1506 if (allowed_clock_voltage_table->entries[i].mvdd) {
1507 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
1508 }
1509
1510 voltage->Phases = 1;
1511 return 0;
1512 }
1513 }
1514
1515 /* sclk is bigger than max sclk in the dependence table */
1516 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1517 allowed_clock_voltage_table->entries[i-1].vddgfx);
1518 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1519 allowed_clock_voltage_table->entries[i-1].vddc);
1520
1521 if (allowed_clock_voltage_table->entries[i-1].vddci) {
1522 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1523 allowed_clock_voltage_table->entries[i-1].vddci);
1524 }
1525 if (allowed_clock_voltage_table->entries[i-1].mvdd) {
1526 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
1527 }
1528
1529 return 0;
1530}
1531
1532/**
1533 * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1534 *
1535 * @param hwmgr the address of the powerplay hardware manager.
1536 * @return always 0
1537 */
1538int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
1539{
1540 return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
1541}
1542
1543int tonga_populate_memory_timing_parameters(
1544 struct pp_hwmgr *hwmgr,
1545 uint32_t engine_clock,
1546 uint32_t memory_clock,
1547 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1548 )
1549{
1550 uint32_t dramTiming;
1551 uint32_t dramTiming2;
1552 uint32_t burstTime;
1553 int result;
1554
1555 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1556 engine_clock, memory_clock);
1557
1558 PP_ASSERT_WITH_CODE(result == 0,
1559 "Error calling VBIOS to set DRAM_TIMING.", return result);
1560
1561 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1562 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1563 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1564
1565 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1566 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1567 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1568
1569 return 0;
1570}
1571
1572/**
1573 * Setup parameters for the MC ARB.
1574 *
1575 * @param hwmgr the address of the powerplay hardware manager.
1576 * @return always 0
1577 * This function is to be called from the SetPowerState table.
1578 */
1579int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1580{
1581 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1582 int result = 0;
1583 SMU72_Discrete_MCArbDramTimingTable arb_regs;
1584 uint32_t i, j;
1585
1586 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1587
1588 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1589 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1590 result = tonga_populate_memory_timing_parameters
1591 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1592 data->dpm_table.mclk_table.dpm_levels[j].value,
1593 &arb_regs.entries[i][j]);
1594
1595 if (0 != result) {
1596 break;
1597 }
1598 }
1599 }
1600
1601 if (0 == result) {
1602 result = tonga_copy_bytes_to_smc(
1603 hwmgr->smumgr,
1604 data->arb_table_start,
1605 (uint8_t *)&arb_regs,
1606 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1607 data->sram_end
1608 );
1609 }
1610
1611 return result;
1612}
1613
1614static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
1615{
1616 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1617 struct tonga_dpm_table *dpm_table = &data->dpm_table;
1618 uint32_t i;
1619
1620 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1621 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1622 table->LinkLevel[i].PcieGenSpeed =
1623 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1624 table->LinkLevel[i].PcieLaneCount =
1625 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1626 table->LinkLevel[i].EnabledForActivity =
1627 1;
1628 table->LinkLevel[i].SPC =
1629 (uint8_t)(data->pcie_spc_cap & 0xff);
1630 table->LinkLevel[i].DownThreshold =
1631 PP_HOST_TO_SMC_UL(5);
1632 table->LinkLevel[i].UpThreshold =
1633 PP_HOST_TO_SMC_UL(30);
1634 }
1635
1636 data->smc_state_table.LinkLevelCount =
1637 (uint8_t)dpm_table->pcie_speed_table.count;
1638 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1639 tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1640
1641 return 0;
1642}
1643
0104aa21
AD		 1644static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1645 SMU72_Discrete_DpmTable *table)
1646{
1647 int result = 0;
1648
1649 uint8_t count;
1650 pp_atomctrl_clock_dividers_vi dividers;
1651 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1652 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1653 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1654
1655 table->UvdLevelCount = (uint8_t) (mm_table->count);
1656 table->UvdBootLevel = 0;
1657
1658 for (count = 0; count < table->UvdLevelCount; count++) {
1659 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1660 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1661 table->UvdLevel[count].MinVoltage.Vddc =
1662 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1663 mm_table->entries[count].vddc);
1664 table->UvdLevel[count].MinVoltage.VddGfx =
1665 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1666 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1667 mm_table->entries[count].vddgfx) : 0;
1668 table->UvdLevel[count].MinVoltage.Vddci =
1669 tonga_get_voltage_id(&data->vddci_voltage_table,
1670 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1671 table->UvdLevel[count].MinVoltage.Phases = 1;
1672
1673 /* retrieve divider value for VBIOS */
1674 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1675 table->UvdLevel[count].VclkFrequency, &dividers);
1676 PP_ASSERT_WITH_CODE((0 == result),
1677 "can not find divide id for Vclk clock", return result);
1678
1679 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1680
1681 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1682 table->UvdLevel[count].DclkFrequency, &dividers);
1683 PP_ASSERT_WITH_CODE((0 == result),
1684 "can not find divide id for Dclk clock", return result);
1685
1686 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1687
1688 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1689 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1690 //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
c15c8d70 1691 }
0104aa21 1692
c15c8d70 1693 return result;
0104aa21
AD		 1694
1695}
c82baa28 1696
1697static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1698 SMU72_Discrete_DpmTable *table)
1699{
1700 int result = 0;
1701
1702 uint8_t count;
1703 pp_atomctrl_clock_dividers_vi dividers;
1704 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1705 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1706 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1707
1708 table->VceLevelCount = (uint8_t) (mm_table->count);
1709 table->VceBootLevel = 0;
1710
1711 for (count = 0; count < table->VceLevelCount; count++) {
1712 table->VceLevel[count].Frequency =
1713 mm_table->entries[count].eclk;
1714 table->VceLevel[count].MinVoltage.Vddc =
1715 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1716 mm_table->entries[count].vddc);
1717 table->VceLevel[count].MinVoltage.VddGfx =
1718 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1719 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1720 mm_table->entries[count].vddgfx) : 0;
1721 table->VceLevel[count].MinVoltage.Vddci =
1722 tonga_get_voltage_id(&data->vddci_voltage_table,
1723 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1724 table->VceLevel[count].MinVoltage.Phases = 1;
1725
1726 /* retrieve divider value for VBIOS */
1727 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1728 table->VceLevel[count].Frequency, &dividers);
1729 PP_ASSERT_WITH_CODE((0 == result),
1730 "can not find divide id for VCE engine clock", return result);
1731
c15c8d70 1732 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
c82baa28 1733
1734 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1735 }
1736
1737 return result;
1738}
1739
1740static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1741 SMU72_Discrete_DpmTable *table)
1742{
1743 int result = 0;
1744 uint8_t count;
1745 pp_atomctrl_clock_dividers_vi dividers;
1746 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1747 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1748 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1749
1750 table->AcpLevelCount = (uint8_t) (mm_table->count);
1751 table->AcpBootLevel = 0;
1752
1753 for (count = 0; count < table->AcpLevelCount; count++) {
1754 table->AcpLevel[count].Frequency =
1755 pptable_info->mm_dep_table->entries[count].aclk;
1756 table->AcpLevel[count].MinVoltage.Vddc =
1757 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1758 mm_table->entries[count].vddc);
1759 table->AcpLevel[count].MinVoltage.VddGfx =
1760 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1761 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1762 mm_table->entries[count].vddgfx) : 0;
1763 table->AcpLevel[count].MinVoltage.Vddci =
1764 tonga_get_voltage_id(&data->vddci_voltage_table,
1765 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1766 table->AcpLevel[count].MinVoltage.Phases = 1;
1767
1768 /* retrieve divider value for VBIOS */
1769 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1770 table->AcpLevel[count].Frequency, &dividers);
1771 PP_ASSERT_WITH_CODE((0 == result),
1772 "can not find divide id for engine clock", return result);
1773
1774 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1775
1776 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1777 }
1778
1779 return result;
1780}
1781
1782static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1783 SMU72_Discrete_DpmTable *table)
1784{
1785 int result = 0;
1786 uint8_t count;
1787 pp_atomctrl_clock_dividers_vi dividers;
1788 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1789 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1790 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1791
1792 table->SamuBootLevel = 0;
1793 table->SamuLevelCount = (uint8_t) (mm_table->count);
1794
1795 for (count = 0; count < table->SamuLevelCount; count++) {
1796 /* not sure whether we need evclk or not */
1797 table->SamuLevel[count].Frequency =
1798 pptable_info->mm_dep_table->entries[count].samclock;
1799 table->SamuLevel[count].MinVoltage.Vddc =
1800 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1801 mm_table->entries[count].vddc);
1802 table->SamuLevel[count].MinVoltage.VddGfx =
1803 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1804 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1805 mm_table->entries[count].vddgfx) : 0;
1806 table->SamuLevel[count].MinVoltage.Vddci =
1807 tonga_get_voltage_id(&data->vddci_voltage_table,
1808 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1809 table->SamuLevel[count].MinVoltage.Phases = 1;
1810
1811 /* retrieve divider value for VBIOS */
1812 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1813 table->SamuLevel[count].Frequency, &dividers);
1814 PP_ASSERT_WITH_CODE((0 == result),
1815 "can not find divide id for samu clock", return result);
1816
c15c8d70 1817 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
c82baa28 1818
1819 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1820 }
1821
1822 return result;
1823}
1824
1825/**
1826 * Populates the SMC MCLK structure using the provided memory clock
1827 *
1828 * @param hwmgr the address of the hardware manager
1829 * @param memory_clock the memory clock to use to populate the structure
1830 * @param sclk the SMC SCLK structure to be populated
1831 */
1832static int tonga_calculate_mclk_params(
1833 struct pp_hwmgr *hwmgr,
1834 uint32_t memory_clock,
1835 SMU72_Discrete_MemoryLevel *mclk,
1836 bool strobe_mode,
1837 bool dllStateOn
1838 )
1839{
1840 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1841 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1842 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1843 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1844 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1845 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1846 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1847 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1848 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1849 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1850
1851 pp_atomctrl_memory_clock_param mpll_param;
1852 int result;
1853
1854 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1855 memory_clock, &mpll_param, strobe_mode);
1856 PP_ASSERT_WITH_CODE(0 == result,
1857 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1858
1859 /* MPLL_FUNC_CNTL setup*/
c15c8d70 1860 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
c82baa28 1861
1862 /* MPLL_FUNC_CNTL_1 setup*/
1863 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1864 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1865 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1866 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1867 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1868 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1869
1870 /* MPLL_AD_FUNC_CNTL setup*/
1871 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1872 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1873
1874 if (data->is_memory_GDDR5) {
1875 /* MPLL_DQ_FUNC_CNTL setup*/
1876 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1877 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1878 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1879 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1880 }
1881
1882 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1883 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1884 /*
1885 ************************************
1886 Fref = Reference Frequency
1887 NF = Feedback divider ratio
1888 NR = Reference divider ratio
1889 Fnom = Nominal VCO output frequency = Fref * NF / NR
1890 Fs = Spreading Rate
1891 D = Percentage down-spread / 2
1892 Fint = Reference input frequency to PFD = Fref / NR
1893 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1894 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1895 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1896 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1897 *************************************
1898 */
1899 pp_atomctrl_internal_ss_info ss_info;
1900 uint32_t freq_nom;
1901 uint32_t tmp;
1902 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1903
1904 /* for GDDR5 for all modes and DDR3 */
1905 if (1 == mpll_param.qdr)
1906 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1907 else
1908 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1909
1910 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1911 tmp = (freq_nom / reference_clock);
1912 tmp = tmp * tmp;
1913
1914 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1915 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1916 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1917 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1918 /* = reference_clock * 5 / speed_spectrum_rate */
1919 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1920
1921 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1922 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1923 uint32_t clkv =
1924 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1925 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1926
1927 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1928 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1929 }
1930 }
1931
1932 /* MCLK_PWRMGT_CNTL setup */
1933 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1934 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1935 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1936 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1937 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1938 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1939
1940
1941 /* Save the result data to outpupt memory level structure */
1942 mclk->MclkFrequency = memory_clock;
1943 mclk->MpllFuncCntl = mpll_func_cntl;
1944 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1945 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1946 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1947 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1948 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1949 mclk->DllCntl = dll_cntl;
1950 mclk->MpllSs1 = mpll_ss1;
1951 mclk->MpllSs2 = mpll_ss2;
1952
1953 return 0;
1954}
1955
1956static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
1957 bool strobe_mode)
1958{
1959 uint8_t mc_para_index;
1960
1961 if (strobe_mode) {
1962 if (memory_clock < 12500) {
1963 mc_para_index = 0x00;
1964 } else if (memory_clock > 47500) {
1965 mc_para_index = 0x0f;
1966 } else {
1967 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1968 }
1969 } else {
1970 if (memory_clock < 65000) {
1971 mc_para_index = 0x00;
1972 } else if (memory_clock > 135000) {
1973 mc_para_index = 0x0f;
1974 } else {
1975 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1976 }
1977 }
1978
1979 return mc_para_index;
1980}
1981
1982static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1983{
1984 uint8_t mc_para_index;
1985
1986 if (memory_clock < 10000) {
1987 mc_para_index = 0;
1988 } else if (memory_clock >= 80000) {
1989 mc_para_index = 0x0f;
1990 } else {
1991 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1992 }
1993
1994 return mc_para_index;
1995}
1996
1997static int tonga_populate_single_memory_level(
1998 struct pp_hwmgr *hwmgr,
1999 uint32_t memory_clock,
2000 SMU72_Discrete_MemoryLevel *memory_level
2001 )
2002{
2003 uint32_t minMvdd = 0;
2004 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2005 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2006 int result = 0;
2007 bool dllStateOn;
2008 struct cgs_display_info info = {0};
2009
2010
2011 if (NULL != pptable_info->vdd_dep_on_mclk) {
2012 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2013 pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
2014 PP_ASSERT_WITH_CODE((0 == result),
2015 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
2016 }
2017
2018 if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
2019 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
2020 } else {
2021 memory_level->MinMvdd = minMvdd;
2022 }
2023 memory_level->EnabledForThrottle = 1;
2024 memory_level->EnabledForActivity = 0;
2025 memory_level->UpHyst = 0;
2026 memory_level->DownHyst = 100;
2027 memory_level->VoltageDownHyst = 0;
2028
2029 /* Indicates maximum activity level for this performance level.*/
2030 memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2031 memory_level->StutterEnable = 0;
2032 memory_level->StrobeEnable = 0;
2033 memory_level->EdcReadEnable = 0;
2034 memory_level->EdcWriteEnable = 0;
2035 memory_level->RttEnable = 0;
2036
2037 /* default set to low watermark. Highest level will be set to high later.*/
2038 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2039
2040 cgs_get_active_displays_info(hwmgr->device, &info);
2041 data->display_timing.num_existing_displays = info.display_count;
2042
2043 if ((data->mclk_stutter_mode_threshold != 0) &&
7e8d1fbd
AD		 2044 (memory_clock <= data->mclk_stutter_mode_threshold) &&
2045 (data->is_uvd_enabled == 0)
2046 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
2047 && (data->display_timing.num_existing_displays <= 2)
2048 && (data->display_timing.num_existing_displays != 0))
c82baa28 2049 memory_level->StutterEnable = 1;
2050
2051 /* decide strobe mode*/
2052 memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
2053 (memory_clock <= data->mclk_strobe_mode_threshold);
2054
2055 /* decide EDC mode and memory clock ratio*/
2056 if (data->is_memory_GDDR5) {
2057 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
2058 memory_level->StrobeEnable);
2059
2060 if ((data->mclk_edc_enable_threshold != 0) &&
2061 (memory_clock > data->mclk_edc_enable_threshold)) {
2062 memory_level->EdcReadEnable = 1;
2063 }
2064
2065 if ((data->mclk_edc_wr_enable_threshold != 0) &&
2066 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
2067 memory_level->EdcWriteEnable = 1;
2068 }
2069
2070 if (memory_level->StrobeEnable) {
2071 if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
2072 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
2073 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2074 } else {
2075 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
2076 }
2077
2078 } else {
2079 dllStateOn = data->dll_defaule_on;
2080 }
2081 } else {
2082 memory_level->StrobeRatio =
2083 tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
2084 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2085 }
2086
2087 result = tonga_calculate_mclk_params(hwmgr,
2088 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
2089
2090 if (0 == result) {
2091 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
2092 /* MCLK frequency in units of 10KHz*/
2093 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
2094 /* Indicates maximum activity level for this performance level.*/
2095 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
2096 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
2097 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
2098 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
2099 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2100 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2101 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2102 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2103 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2104 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2105 }
2106
2107 return result;
2108}
2109
2110/**
2111 * Populates the SMC MVDD structure using the provided memory clock.
2112 *
2113 * @param hwmgr the address of the hardware manager
2114 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2115 * @param voltage the SMC VOLTAGE structure to be populated
2116 */
2117int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
2118{
2119 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2120 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2121 uint32_t i = 0;
2122
2123 if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2124 /* find mvdd value which clock is more than request */
2125 for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
2126 if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
2127 /* Always round to higher voltage. */
2128 smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
2129 break;
2130 }
2131 }
2132
2133 PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
2134 "MVDD Voltage is outside the supported range.", return -1);
2135
2136 } else {
2137 return -1;
2138 }
2139
2140 return 0;
2141}
2142
2143
2144static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
2145 SMU72_Discrete_DpmTable *table)
2146{
2147 int result = 0;
2148 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2149 pp_atomctrl_clock_dividers_vi dividers;
2150 SMIO_Pattern voltage_level;
2151 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2152 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2153 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
2154 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
2155
2156 /* The ACPI state should not do DPM on DC (or ever).*/
2157 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2158
2159 table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
2160
2161 /* assign zero for now*/
2162 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2163
2164 /* get the engine clock dividers for this clock value*/
2165 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2166 table->ACPILevel.SclkFrequency, &dividers);
2167
2168 PP_ASSERT_WITH_CODE(result == 0,
2169 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2170
2171 /* divider ID for required SCLK*/
2172 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2173 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2174 table->ACPILevel.DeepSleepDivId = 0;
2175
2176 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2177 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
2178 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2179 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
2180 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
2181 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
2182
2183 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2184 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2185 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2186 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2187 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2188 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2189 table->ACPILevel.CcPwrDynRm = 0;
2190 table->ACPILevel.CcPwrDynRm1 = 0;
2191
2192
2193 /* For various features to be enabled/disabled while this level is active.*/
2194 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2195 /* SCLK frequency in units of 10KHz*/
2196 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2197 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2198 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2199 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2200 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2201 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2202 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2203 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2204 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2205
2206 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
2207 table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
2208
2209 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2210
2211 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
2212 table->MemoryACPILevel.MinMvdd =
2213 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2214 else
2215 table->MemoryACPILevel.MinMvdd = 0;
2216
2217 /* Force reset on DLL*/
2218 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2219 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2220 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2221 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2222
2223 /* Disable DLL in ACPIState*/
2224 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2225 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2226 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2227 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2228
2229 /* Enable DLL bypass signal*/
2230 dll_cntl = PHM_SET_FIELD(dll_cntl,
2231 DLL_CNTL, MRDCK0_BYPASS, 0);
2232 dll_cntl = PHM_SET_FIELD(dll_cntl,
2233 DLL_CNTL, MRDCK1_BYPASS, 0);
2234
2235 table->MemoryACPILevel.DllCntl =
2236 PP_HOST_TO_SMC_UL(dll_cntl);
2237 table->MemoryACPILevel.MclkPwrmgtCntl =
2238 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2239 table->MemoryACPILevel.MpllAdFuncCntl =
2240 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2241 table->MemoryACPILevel.MpllDqFuncCntl =
2242 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2243 table->MemoryACPILevel.MpllFuncCntl =
2244 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2245 table->MemoryACPILevel.MpllFuncCntl_1 =
2246 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2247 table->MemoryACPILevel.MpllFuncCntl_2 =
2248 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2249 table->MemoryACPILevel.MpllSs1 =
2250 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2251 table->MemoryACPILevel.MpllSs2 =
2252 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2253
2254 table->MemoryACPILevel.EnabledForThrottle = 0;
2255 table->MemoryACPILevel.EnabledForActivity = 0;
2256 table->MemoryACPILevel.UpHyst = 0;
2257 table->MemoryACPILevel.DownHyst = 100;
2258 table->MemoryACPILevel.VoltageDownHyst = 0;
2259 /* Indicates maximum activity level for this performance level.*/
2260 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2261
2262 table->MemoryACPILevel.StutterEnable = 0;
2263 table->MemoryACPILevel.StrobeEnable = 0;
2264 table->MemoryACPILevel.EdcReadEnable = 0;
2265 table->MemoryACPILevel.EdcWriteEnable = 0;
2266 table->MemoryACPILevel.RttEnable = 0;
2267
2268 return result;
2269}
2270
2271static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2272{
2273 int result = 0;
2274 uint32_t i;
2275
2276 for (i = 0; i < table->count; i++) {
2277 if (value == table->dpm_levels[i].value) {
2278 *boot_level = i;
2279 result = 0;
2280 }
2281 }
2282 return result;
2283}
2284
2285static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2286 SMU72_Discrete_DpmTable *table)
2287{
2288 int result = 0;
2289 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2290
2291 table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2292 table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2293
2294 /* find boot level from dpm table*/
2295 result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
2296 data->vbios_boot_state.sclk_bootup_value,
2297 (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2298
2299 if (0 != result) {
2300 data->smc_state_table.GraphicsBootLevel = 0;
2301 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2302 in dependency table. Using Graphics DPM level 0!");
2303 result = 0;
2304 }
2305
2306 result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
2307 data->vbios_boot_state.mclk_bootup_value,
2308 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2309
2310 if (0 != result) {
2311 data->smc_state_table.MemoryBootLevel = 0;
2312 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2313 in dependency table. Using Memory DPM level 0!");
2314 result = 0;
2315 }
2316
2317 table->BootVoltage.Vddc =
2318 tonga_get_voltage_id(&(data->vddc_voltage_table),
2319 data->vbios_boot_state.vddc_bootup_value);
2320 table->BootVoltage.VddGfx =
2321 tonga_get_voltage_id(&(data->vddgfx_voltage_table),
2322 data->vbios_boot_state.vddgfx_bootup_value);
2323 table->BootVoltage.Vddci =
2324 tonga_get_voltage_id(&(data->vddci_voltage_table),
2325 data->vbios_boot_state.vddci_bootup_value);
2326 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2327
2328 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2329
2330 return result;
2331}
2332
2333
2334/**
2335 * Calculates the SCLK dividers using the provided engine clock
2336 *
2337 * @param hwmgr the address of the hardware manager
2338 * @param engine_clock the engine clock to use to populate the structure
2339 * @param sclk the SMC SCLK structure to be populated
2340 */
2341int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2342 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
2343{
2344 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2345 pp_atomctrl_clock_dividers_vi dividers;
2346 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2347 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2348 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2349 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2350 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2351 uint32_t reference_clock;
2352 uint32_t reference_divider;
2353 uint32_t fbdiv;
2354 int result;
2355
2356 /* get the engine clock dividers for this clock value*/
2357 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
2358
2359 PP_ASSERT_WITH_CODE(result == 0,
2360 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2361
2362 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2363 reference_clock = atomctrl_get_reference_clock(hwmgr);
2364
2365 reference_divider = 1 + dividers.uc_pll_ref_div;
2366
2367 /* low 14 bits is fraction and high 12 bits is divider*/
2368 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2369
2370 /* SPLL_FUNC_CNTL setup*/
2371 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2372 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2373 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2374 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
2375
2376 /* SPLL_FUNC_CNTL_3 setup*/
2377 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2378 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2379
2380 /* set to use fractional accumulation*/
2381 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2382 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2383
2384 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2385 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2386 pp_atomctrl_internal_ss_info ss_info;
2387
2388 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2389 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2390 /*
2391 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2392 * ss_info.speed_spectrum_rate -- in unit of khz
2393 */
2394 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2395 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2396
2397 /* clkv = 2 * D * fbdiv / NS */
2398 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2399
2400 cg_spll_spread_spectrum =
2401 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2402 cg_spll_spread_spectrum =
2403 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2404 cg_spll_spread_spectrum_2 =
2405 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2406 }
2407 }
2408
2409 sclk->SclkFrequency = engine_clock;
2410 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2411 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2412 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2413 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2414 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
2415
2416 return 0;
2417}
2418
a4333b4c
EH		 2419static uint8_t tonga_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
2420 uint32_t engine_clock, uint32_t min_engine_clock_in_sr)
2421{
2422 uint32_t i, temp;
9887e425 2423 uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK);
a4333b4c
EH		 2424
2425 PP_ASSERT_WITH_CODE((engine_clock >= min),
2426 "Engine clock can't satisfy stutter requirement!", return 0);
2427
2428 for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
354ef928 2429 temp = engine_clock >> i;
a4333b4c
EH		 2430
2431 if(temp >= min || i == 0)
2432 break;
2433 }
2434 return (uint8_t)i;
2435}
2436
c82baa28 2437/**
2438 * Populates single SMC SCLK structure using the provided engine clock
2439 *
2440 * @param hwmgr the address of the hardware manager
2441 * @param engine_clock the engine clock to use to populate the structure
2442 * @param sclk the SMC SCLK structure to be populated
2443 */
2444static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
2445{
2446 int result;
2447 uint32_t threshold;
2448 uint32_t mvdd;
2449 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2450 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2451
2452 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2453
2454
2455 /* populate graphics levels*/
2456 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2457 pptable_info->vdd_dep_on_sclk, engine_clock,
2458 &graphic_level->MinVoltage, &mvdd);
2459 PP_ASSERT_WITH_CODE((0 == result),
2460 "can not find VDDC voltage value for VDDC \
2461 engine clock dependency table", return result);
2462
2463 /* SCLK frequency in units of 10KHz*/
2464 graphic_level->SclkFrequency = engine_clock;
2465
2466 /* Indicates maximum activity level for this performance level. 50% for now*/
2467 graphic_level->ActivityLevel = sclk_activity_level_threshold;
2468
2469 graphic_level->CcPwrDynRm = 0;
2470 graphic_level->CcPwrDynRm1 = 0;
2471 /* this level can be used if activity is high enough.*/
2472 graphic_level->EnabledForActivity = 0;
2473 /* this level can be used for throttling.*/
2474 graphic_level->EnabledForThrottle = 1;
2475 graphic_level->UpHyst = 0;
2476 graphic_level->DownHyst = 0;
2477 graphic_level->VoltageDownHyst = 0;
2478 graphic_level->PowerThrottle = 0;
2479
2480 threshold = engine_clock * data->fast_watemark_threshold / 100;
2481/*
2482 *get the DAL clock. do it in funture.
2483 PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
2484 data->display_timing.min_clock_insr = minClocks.engineClockInSR;
c82baa28 2485*/
a4333b4c
EH		 2486 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2487 PHM_PlatformCaps_SclkDeepSleep))
2488 graphic_level->DeepSleepDivId =
2489 tonga_get_sleep_divider_id_from_clock(hwmgr, engine_clock,
2490 data->display_timing.min_clock_insr);
c82baa28 2491
2492 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2493 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2494
2495 if (0 == result) {
2496 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2497 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
2498 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2499 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2500 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2501 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2502 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2503 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2504 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2505 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2506 }
2507
2508 return result;
2509}
2510
2511/**
2512 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2513 *
2514 * @param hwmgr the address of the hardware manager
2515 */
2516static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2517{
2518 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2519 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2520 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2521 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2522 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2523 int result = 0;
2524 uint32_t level_array_adress = data->dpm_table_start +
2525 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
2526 uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
2527 SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/
2528 SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2529 uint32_t i, maxEntry;
2530 uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2531 PECI_RegistryValue reg_value;
2532 memset(levels, 0x00, level_array_size);
2533
2534 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2535 result = tonga_populate_single_graphic_level(hwmgr,
2536 dpm_table->sclk_table.dpm_levels[i].value,
2537 (uint16_t)data->activity_target[i],
2538 &(data->smc_state_table.GraphicsLevel[i]));
2539
2540 if (0 != result)
2541 return result;
2542
2543 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2544 if (i > 1)
2545 data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2546
2547 if (0 == i) {
2548 reg_value = 0;
2549 if (reg_value != 0)
2550 data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
2551 }
2552
2553 if (1 == i) {
2554 reg_value = 0;
2555 if (reg_value != 0)
2556 data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
2557 }
2558 }
2559
2560 /* Only enable level 0 for now. */
2561 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2562
2563 /* set highest level watermark to high */
2564 if (dpm_table->sclk_table.count > 1)
2565 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2566 PPSMC_DISPLAY_WATERMARK_HIGH;
2567
2568 data->smc_state_table.GraphicsDpmLevelCount =
2569 (uint8_t)dpm_table->sclk_table.count;
2570 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2571 tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2572
2573 if (pcie_table != NULL) {
2574 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
2575 "There must be 1 or more PCIE levels defined in PPTable.", return -1);
2576 maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
2577 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2578 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
2579 (uint8_t) ((i < maxEntry) ? i : maxEntry);
2580 }
2581 } else {
2582 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
2583 printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
2584
2585 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2586 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2587 (1<<(highest_pcie_level_enabled+1))) != 0)) {
2588 highest_pcie_level_enabled++;
2589 }
2590
2591 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2592 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2593 (1<<lowest_pcie_level_enabled)) == 0)) {
2594 lowest_pcie_level_enabled++;
2595 }
2596
2597 while ((count < highest_pcie_level_enabled) &&
2598 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2599 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
2600 count++;
2601 }
2602 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2603 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
2604
2605
2606 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2607 for (i = 2; i < dpm_table->sclk_table.count; i++) {
2608 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2609 }
2610
2611 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2612 data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2613
2614 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2615 data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2616 }
2617 /* level count will send to smc once at init smc table and never change*/
2618 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2619
2620 if (0 != result)
2621 return result;
2622
2623 return 0;
2624}
2625
2626/**
2627 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2628 *
2629 * @param hwmgr the address of the hardware manager
2630 */
2631
2632static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2633{
2634 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2635 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2636 int result;
2637 /* populate MCLK dpm table to SMU7 */
2638 uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
2639 uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
2640 SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2641 uint32_t i;
2642
2643 memset(levels, 0x00, level_array_size);
2644
2645 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2646 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2647 "can not populate memory level as memory clock is zero", return -1);
2648 result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2649 &(data->smc_state_table.MemoryLevel[i]));
2650 if (0 != result) {
2651 return result;
2652 }
2653 }
2654
2655 /* Only enable level 0 for now.*/
2656 data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2657
2658 /*
2659 * in order to prevent MC activity from stutter mode to push DPM up.
2660 * the UVD change complements this by putting the MCLK in a higher state
2661 * by default such that we are not effected by up threshold or and MCLK DPM latency.
2662 */
2663 data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2664 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2665
2666 data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2667 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2668 /* set highest level watermark to high*/
2669 data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2670
2671 /* level count will send to smc once at init smc table and never change*/
2672 result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
2673 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2674
2675 if (0 != result) {
2676 return result;
2677 }
2678
2679 return 0;
2680}
2681
2682struct TONGA_DLL_SPEED_SETTING {
2683 uint16_t Min; /* Minimum Data Rate*/
2684 uint16_t Max; /* Maximum Data Rate*/
edf600da 2685 uint32_t dll_speed; /* The desired DLL_SPEED setting*/
c82baa28 2686};
2687
2688static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2689{
2690 return 0;
2691}
2692
2693/* ---------------------------------------- ULV related functions ----------------------------------------------------*/
2694
2695
2696static int tonga_reset_single_dpm_table(
2697 struct pp_hwmgr *hwmgr,
2698 struct tonga_single_dpm_table *dpm_table,
2699 uint32_t count)
2700{
2701 uint32_t i;
2702 if (!(count <= MAX_REGULAR_DPM_NUMBER))
2703 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
2704 table entries to exceed max number! \n");
2705
2706 dpm_table->count = count;
2707 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
2708 dpm_table->dpm_levels[i].enabled = 0;
2709 }
2710
2711 return 0;
2712}
2713
2714static void tonga_setup_pcie_table_entry(
2715 struct tonga_single_dpm_table *dpm_table,
2716 uint32_t index, uint32_t pcie_gen,
2717 uint32_t pcie_lanes)
2718{
2719 dpm_table->dpm_levels[index].value = pcie_gen;
2720 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2721 dpm_table->dpm_levels[index].enabled = 1;
2722}
2723
c82baa28 2724static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2725{
2726 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2727 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2728 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2729 uint32_t i, maxEntry;
2730
2731 if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
2732 data->pcie_gen_power_saving = data->pcie_gen_performance;
2733 data->pcie_lane_power_saving = data->pcie_lane_performance;
2734 } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
2735 data->pcie_gen_performance = data->pcie_gen_power_saving;
2736 data->pcie_lane_performance = data->pcie_lane_power_saving;
2737 }
2738
2739 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
2740
2741 if (pcie_table != NULL) {
2742 /*
2743 * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
2744 * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
2745 */
2746 maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
2747 SMU72_MAX_LEVELS_LINK : pcie_table->count;
2748 for (i = 1; i < maxEntry; i++) {
2749 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
2750 get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
2751 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2752 }
2753 data->dpm_table.pcie_speed_table.count = maxEntry - 1;
2754 } else {
2755 /* Hardcode Pcie Table */
2756 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
2757 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2758 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2759 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
2760 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2761 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2762 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
2763 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2764 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2765 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
2766 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2767 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2768 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
2769 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2770 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2771 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
2772 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2773 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2774 data->dpm_table.pcie_speed_table.count = 6;
2775 }
2776 /* Populate last level for boot PCIE level, but do not increment count. */
2777 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
2778 data->dpm_table.pcie_speed_table.count,
2779 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2780 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2781
2782 return 0;
2783
2784}
2785
2786/*
2787 * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
2788 * Dynamic state patching function will then trim these state tables to the allowed range based
2789 * on the power policy or external client requests, such as UVD request, etc.
2790 */
2791static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
2792{
2793 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2794 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2795 uint32_t i;
2796
2797 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
2798 pptable_info->vdd_dep_on_sclk;
2799 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
2800 pptable_info->vdd_dep_on_mclk;
2801
2802 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2803 "SCLK dependency table is missing. This table is mandatory", return -1);
2804 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
2805 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
2806
2807 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2808 "MCLK dependency table is missing. This table is mandatory", return -1);
2809 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
2810 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
2811
2812 /* clear the state table to reset everything to default */
2813 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
2814 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
2815 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
2816 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
2817 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
2818 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
2819 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
2820
2821 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2822 "SCLK dependency table is missing. This table is mandatory", return -1);
2823 /* Initialize Sclk DPM table based on allow Sclk values*/
2824 data->dpm_table.sclk_table.count = 0;
2825
2826 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2827 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
2828 allowed_vdd_sclk_table->entries[i].clk) {
2829 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
2830 allowed_vdd_sclk_table->entries[i].clk;
2831 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
2832 data->dpm_table.sclk_table.count++;
2833 }
2834 }
2835
2836 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2837 "MCLK dependency table is missing. This table is mandatory", return -1);
2838 /* Initialize Mclk DPM table based on allow Mclk values */
2839 data->dpm_table.mclk_table.count = 0;
2840 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2841 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
2842 allowed_vdd_mclk_table->entries[i].clk) {
2843 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
2844 allowed_vdd_mclk_table->entries[i].clk;
2845 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
2846 data->dpm_table.mclk_table.count++;
2847 }
2848 }
2849
2850 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
2851 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2852 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
2853 /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
2854 /* param1 is for corresponding std voltage */
2855 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
2856 }
2857 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
2858
2859 if (NULL != allowed_vdd_mclk_table) {
2860 /* Initialize Vddci DPM table based on allow Mclk values */
2861 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2862 data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
2863 data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
2864 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
2865 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
2866 }
2867 data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
2868 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
2869 }
2870
2871 /* setup PCIE gen speed levels*/
2872 tonga_setup_default_pcie_tables(hwmgr);
2873
2874 /* save a copy of the default DPM table*/
2875 memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
2876
2877 return 0;
2878}
2879
2880int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
2881 const struct tonga_power_state *bootState)
2882{
2883 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2884 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2885 uint8_t count, level;
2886
2887 count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
2888 for (level = 0; level < count; level++) {
2889 if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
2890 bootState->performance_levels[0].engine_clock) {
2891 data->smc_state_table.GraphicsBootLevel = level;
2892 break;
2893 }
2894 }
2895
2896 count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
2897 for (level = 0; level < count; level++) {
2898 if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
2899 bootState->performance_levels[0].memory_clock) {
2900 data->smc_state_table.MemoryBootLevel = level;
2901 break;
2902 }
2903 }
2904
2905 return 0;
2906}
2907
2908/**
2909 * Initializes the SMC table and uploads it
2910 *
2911 * @param hwmgr the address of the powerplay hardware manager.
2912 * @param pInput the pointer to input data (PowerState)
2913 * @return always 0
2914 */
2915int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2916{
2917 int result;
2918 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2919 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2920 SMU72_Discrete_DpmTable *table = &(data->smc_state_table);
2921 const phw_tonga_ulv_parm *ulv = &(data->ulv);
2922 uint8_t i;
2923 PECI_RegistryValue reg_value;
2924 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2925
2926 result = tonga_setup_default_dpm_tables(hwmgr);
2927 PP_ASSERT_WITH_CODE(0 == result,
2928 "Failed to setup default DPM tables!", return result;);
2929 memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2930 if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2931 tonga_populate_smc_voltage_tables(hwmgr, table);
2932 }
2933
2934 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2935 PHM_PlatformCaps_AutomaticDCTransition)) {
2936 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2937 }
2938
2939 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2940 PHM_PlatformCaps_StepVddc)) {
2941 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2942 }
2943
2944 if (data->is_memory_GDDR5) {
2945 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2946 }
2947
2948 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2949
2950 if (i == 1 || i == 0) {
2951 table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
2952 }
2953
2954 if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
2955 PP_ASSERT_WITH_CODE(0 == result,
2956 "Failed to initialize ULV state!", return result;);
2957
2958 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2959 ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
2960 }
2961
2962 result = tonga_populate_smc_link_level(hwmgr, table);
2963 PP_ASSERT_WITH_CODE(0 == result,
2964 "Failed to initialize Link Level!", return result;);
2965
2966 result = tonga_populate_all_graphic_levels(hwmgr);
2967 PP_ASSERT_WITH_CODE(0 == result,
2968 "Failed to initialize Graphics Level!", return result;);
2969
2970 result = tonga_populate_all_memory_levels(hwmgr);
2971 PP_ASSERT_WITH_CODE(0 == result,
2972 "Failed to initialize Memory Level!", return result;);
2973
2974 result = tonga_populate_smv_acpi_level(hwmgr, table);
2975 PP_ASSERT_WITH_CODE(0 == result,
2976 "Failed to initialize ACPI Level!", return result;);
2977
2978 result = tonga_populate_smc_vce_level(hwmgr, table);
2979 PP_ASSERT_WITH_CODE(0 == result,
2980 "Failed to initialize VCE Level!", return result;);
2981
2982 result = tonga_populate_smc_acp_level(hwmgr, table);
2983 PP_ASSERT_WITH_CODE(0 == result,
2984 "Failed to initialize ACP Level!", return result;);
2985
2986 result = tonga_populate_smc_samu_level(hwmgr, table);
2987 PP_ASSERT_WITH_CODE(0 == result,
2988 "Failed to initialize SAMU Level!", return result;);
2989
2990 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2991 /* need to populate the ARB settings for the initial state. */
2992 result = tonga_program_memory_timing_parameters(hwmgr);
2993 PP_ASSERT_WITH_CODE(0 == result,
2994 "Failed to Write ARB settings for the initial state.", return result;);
2995
0104aa21
AD		 2996 result = tonga_populate_smc_uvd_level(hwmgr, table);
2997 PP_ASSERT_WITH_CODE(0 == result,
2998 "Failed to initialize UVD Level!", return result;);
2999
c82baa28 3000 result = tonga_populate_smc_boot_level(hwmgr, table);
3001 PP_ASSERT_WITH_CODE(0 == result,
3002 "Failed to initialize Boot Level!", return result;);
3003
3004 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3005 PHM_PlatformCaps_ClockStretcher)) {
3006 result = tonga_populate_clock_stretcher_data_table(hwmgr);
3007 PP_ASSERT_WITH_CODE(0 == result,
3008 "Failed to populate Clock Stretcher Data Table!", return result;);
3009 }
3010 table->GraphicsVoltageChangeEnable = 1;
3011 table->GraphicsThermThrottleEnable = 1;
3012 table->GraphicsInterval = 1;
3013 table->VoltageInterval = 1;
3014 table->ThermalInterval = 1;
3015 table->TemperatureLimitHigh =
3016 pptable_info->cac_dtp_table->usTargetOperatingTemp *
3017 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3018 table->TemperatureLimitLow =
3019 (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3020 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3021 table->MemoryVoltageChangeEnable = 1;
3022 table->MemoryInterval = 1;
3023 table->VoltageResponseTime = 0;
3024 table->PhaseResponseTime = 0;
3025 table->MemoryThermThrottleEnable = 1;
3026
3027 /*
3028 * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
3029 * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
3030 * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
3031 * To avoid it, we set PCIeBootLinkLevel to highest dpm level
3032 */
3033 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
3034 "There must be 1 or more PCIE levels defined in PPTable.",
3035 return -1);
3036
3037 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
3038
3039 table->PCIeGenInterval = 1;
3040
3041 result = tonga_populate_vr_config(hwmgr, table);
3042 PP_ASSERT_WITH_CODE(0 == result,
3043 "Failed to populate VRConfig setting!", return result);
3044
3045 table->ThermGpio = 17;
3046 table->SclkStepSize = 0x4000;
3047
3048 reg_value = 0;
3049 if ((0 == reg_value) &&
3050 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3051 VDDC_VRHOT_GPIO_PINID, &gpio_pin_assignment))) {
3052 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3053 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3054 PHM_PlatformCaps_RegulatorHot);
3055 } else {
3056 table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
3057 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3058 PHM_PlatformCaps_RegulatorHot);
3059 }
3060
3061 /* ACDC Switch GPIO */
3062 reg_value = 0;
3063 if ((0 == reg_value) &&
3064 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3065 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin_assignment))) {
3066 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3067 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3068 PHM_PlatformCaps_AutomaticDCTransition);
3069 } else {
3070 table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
3071 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3072 PHM_PlatformCaps_AutomaticDCTransition);
3073 }
3074
3075 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3076 PHM_PlatformCaps_Falcon_QuickTransition);
3077
3078 reg_value = 0;
3079 if (1 == reg_value) {
3080 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3081 PHM_PlatformCaps_AutomaticDCTransition);
3082 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3083 PHM_PlatformCaps_Falcon_QuickTransition);
3084 }
3085
3086 reg_value = 0;
3087 if ((0 == reg_value) &&
3088 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3089 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
3090 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3091 PHM_PlatformCaps_ThermalOutGPIO);
3092
3093 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3094
3095 table->ThermOutPolarity =
3096 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3097 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
3098
3099 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3100
3101 /* if required, combine VRHot/PCC with thermal out GPIO*/
3102 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3103 PHM_PlatformCaps_RegulatorHot) &&
3104 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3105 PHM_PlatformCaps_CombinePCCWithThermalSignal)){
3106 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3107 }
3108 } else {
3109 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3110 PHM_PlatformCaps_ThermalOutGPIO);
3111
3112 table->ThermOutGpio = 17;
3113 table->ThermOutPolarity = 1;
3114 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3115 }
3116
3117 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
3118 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3119 }
3120 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3121 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3122 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3123 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3124 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3125 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3126 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3127 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3128 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3129
3130 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3131 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
3132 offsetof(SMU72_Discrete_DpmTable, SystemFlags),
3133 (uint8_t *)&(table->SystemFlags),
3134 sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
3135 data->sram_end);
3136
3137 PP_ASSERT_WITH_CODE(0 == result,
3138 "Failed to upload dpm data to SMC memory!", return result;);
3139
3140 return result;
3141}
3142
3143/* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
3144static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
3145{
3146 return;
3147}
3148
3149int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3150{
3151 PPSMC_Result result;
3152 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3153
3154 /* Apply minimum voltage based on DAL's request level */
3155 tonga_apply_dal_minimum_voltage_request(hwmgr);
3156
3157 if (0 == data->sclk_dpm_key_disabled) {
3158 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3159 if (0 != tonga_is_dpm_running(hwmgr))
3160 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3161
3162 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3163 result = smum_send_msg_to_smc_with_parameter(
3164 hwmgr->smumgr,
3165 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
3166 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3167 PP_ASSERT_WITH_CODE((0 == result),
3168 "Set Sclk Dpm enable Mask failed", return -1);
3169 }
3170 }
3171
3172 if (0 == data->mclk_dpm_key_disabled) {
3173 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3174 if (0 != tonga_is_dpm_running(hwmgr))
3175 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3176
3177 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3178 result = smum_send_msg_to_smc_with_parameter(
3179 hwmgr->smumgr,
3180 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
3181 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3182 PP_ASSERT_WITH_CODE((0 == result),
3183 "Set Mclk Dpm enable Mask failed", return -1);
3184 }
3185 }
3186
3187 return 0;
3188}
3189
3190
3191int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
3192{
3193 uint32_t level, tmp;
3194 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3195
3196 if (0 == data->pcie_dpm_key_disabled) {
3197 /* PCIE */
3198 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3199 level = 0;
3200 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3201 while (tmp >>= 1)
3202 level++ ;
3203
3204 if (0 != level) {
3205 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3206 "force highest pcie dpm state failed!", return -1);
3207 }
3208 }
3209 }
3210
3211 if (0 == data->sclk_dpm_key_disabled) {
3212 /* SCLK */
3213 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
3214 level = 0;
3215 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3216 while (tmp >>= 1)
3217 level++ ;
3218
3219 if (0 != level) {
3220 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3221 "force highest sclk dpm state failed!", return -1);
3222 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3223 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3224 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3225 Curr_Sclk_Index does not match the level \n");
3226
3227 }
3228 }
3229 }
3230
3231 if (0 == data->mclk_dpm_key_disabled) {
3232 /* MCLK */
3233 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3234 level = 0;
3235 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3236 while (tmp >>= 1)
3237 level++ ;
3238
3239 if (0 != level) {
3240 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3241 "force highest mclk dpm state failed!", return -1);
3242 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3243 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3244 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
9fe1837d 3245 Curr_Mclk_Index does not match the level \n");
c82baa28 3246 }
3247 }
3248 }
3249
3250 return 0;
3251}
3252
3253/**
3254 * Find the MC microcode version and store it in the HwMgr struct
3255 *
3256 * @param hwmgr the address of the powerplay hardware manager.
3257 * @return always 0
3258 */
3259int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
3260{
3261 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
3262
3263 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3264
3265 return 0;
3266}
3267
3268/**
3269 * Initialize Dynamic State Adjustment Rule Settings
3270 *
3271 * @param hwmgr the address of the powerplay hardware manager.
3272 */
3273int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3274{
3275 uint32_t table_size;
3276 struct phm_clock_voltage_dependency_table *table_clk_vlt;
3277 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3278
3279 hwmgr->dyn_state.mclk_sclk_ratio = 4;
3280 hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */
3281 hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */
3282
3283 /* initialize vddc_dep_on_dal_pwrl table */
3284 table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3285 table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
3286
3287 if (NULL == table_clk_vlt) {
3288 printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3289 return -ENOMEM;
3290 } else {
3291 table_clk_vlt->count = 4;
3292 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3293 table_clk_vlt->entries[0].v = 0;
3294 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3295 table_clk_vlt->entries[1].v = 720;
3296 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3297 table_clk_vlt->entries[2].v = 810;
3298 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3299 table_clk_vlt->entries[3].v = 900;
3300 pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
3301 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3302 }
3303
3304 return 0;
3305}
3306
3307static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3308{
3309 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3310 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3311
3312 phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3313 pptable_info->vdd_dep_on_sclk;
3314 phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3315 pptable_info->vdd_dep_on_mclk;
3316
3317 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
edf600da 3318 "VDD dependency on SCLK table is missing. \
c82baa28 3319 This table is mandatory", return -1);
3320 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
edf600da 3321 "VDD dependency on SCLK table has to have is missing. \
c82baa28 3322 This table is mandatory", return -1);
3323
3324 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
edf600da 3325 "VDD dependency on MCLK table is missing. \
c82baa28 3326 This table is mandatory", return -1);
3327 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3328 "VDD dependency on MCLK table has to have is missing. \
3329 This table is mandatory", return -1);
3330
3331 data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
3332 data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3333
3334 pptable_info->max_clock_voltage_on_ac.sclk =
3335 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3336 pptable_info->max_clock_voltage_on_ac.mclk =
3337 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3338 pptable_info->max_clock_voltage_on_ac.vddc =
3339 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3340 pptable_info->max_clock_voltage_on_ac.vddci =
3341 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3342
3343 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3344 pptable_info->max_clock_voltage_on_ac.sclk;
3345 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3346 pptable_info->max_clock_voltage_on_ac.mclk;
3347 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3348 pptable_info->max_clock_voltage_on_ac.vddc;
3349 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
3350 pptable_info->max_clock_voltage_on_ac.vddci;
3351
3352 return 0;
3353}
3354
3355int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3356{
3357 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3358 int result = 1;
3359
3360 PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr),
3361 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3362 return result);
3363
3364 if (0 == data->pcie_dpm_key_disabled) {
3365 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
3366 hwmgr->smumgr,
3367 PPSMC_MSG_PCIeDPM_UnForceLevel)),
3368 "unforce pcie level failed!",
3369 return -1);
3370 }
3371
3372 result = tonga_upload_dpm_level_enable_mask(hwmgr);
3373
3374 return result;
3375}
3376
3377static uint32_t tonga_get_lowest_enable_level(
3378 struct pp_hwmgr *hwmgr, uint32_t level_mask)
3379{
3380 uint32_t level = 0;
3381
3382 while (0 == (level_mask & (1 << level)))
3383 level++;
3384
3385 return level;
3386}
3387
3388static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3389{
9fe1837d 3390 uint32_t level;
c82baa28 3391 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3392
9fe1837d
AD		 3393 if (0 == data->pcie_dpm_key_disabled) {
3394 /* PCIE */
3395 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3396 level = tonga_get_lowest_enable_level(hwmgr,
3397 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3398 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3399 "force lowest pcie dpm state failed!", return -1);
3400 }
3401 }
3402
3403 if (0 == data->sclk_dpm_key_disabled) {
3404 /* SCLK */
3405 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3406 level = tonga_get_lowest_enable_level(hwmgr,
3407 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
c82baa28 3408
9fe1837d
AD		 3409 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3410 "force sclk dpm state failed!", return -1);
c82baa28 3411
9fe1837d
AD		 3412 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3413 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3414 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
c82baa28 3415 Curr_Sclk_Index does not match the level \n");
9fe1837d
AD		 3416 }
3417 }
3418
3419 if (0 == data->mclk_dpm_key_disabled) {
3420 /* MCLK */
3421 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3422 level = tonga_get_lowest_enable_level(hwmgr,
3423 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3424 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3425 "force lowest mclk dpm state failed!", return -1);
3426 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3427 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3428 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3429 Curr_Mclk_Index does not match the level \n");
3430 }
c82baa28 3431 }
3432
3433 return 0;
3434}
3435
3436static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
3437{
3438 uint8_t entryId;
3439 uint8_t voltageId;
3440 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3441 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3442
3443 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3444 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3445 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3446
3447 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3448 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3449 voltageId = sclk_table->entries[entryId].vddInd;
3450 sclk_table->entries[entryId].vddgfx =
3451 pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
3452 }
3453 } else {
3454 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3455 voltageId = sclk_table->entries[entryId].vddInd;
3456 sclk_table->entries[entryId].vddc =
3457 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3458 }
3459 }
3460
3461 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3462 voltageId = mclk_table->entries[entryId].vddInd;
3463 mclk_table->entries[entryId].vddc =
3464 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3465 }
3466
3467 for (entryId = 0; entryId < mm_table->count; ++entryId) {
3468 voltageId = mm_table->entries[entryId].vddcInd;
3469 mm_table->entries[entryId].vddc =
3470 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3471 }
3472
3473 return 0;
3474
3475}
3476
3477static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3478{
3479 uint8_t entryId;
3480 phm_ppt_v1_voltage_lookup_record v_record;
3481 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3482 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3483
3484 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3485 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3486
3487 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3488 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3489 if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
3490 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3491 sclk_table->entries[entryId].vdd_offset - 0xFFFF;
3492 else
3493 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3494 sclk_table->entries[entryId].vdd_offset;
3495
3496 sclk_table->entries[entryId].vddc =
3497 v_record.us_cac_low = v_record.us_cac_mid =
3498 v_record.us_cac_high = v_record.us_vdd;
3499
3500 tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
3501 }
3502
3503 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3504 if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
3505 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3506 mclk_table->entries[entryId].vdd_offset - 0xFFFF;
3507 else
3508 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3509 mclk_table->entries[entryId].vdd_offset;
3510
3511 mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
3512 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3513 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3514 }
3515 }
3516
3517 return 0;
3518
3519}
3520
3521static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3522{
3523 uint32_t entryId;
3524 phm_ppt_v1_voltage_lookup_record v_record;
3525 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3526 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3527 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3528
3529 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3530 for (entryId = 0; entryId < mm_table->count; entryId++) {
3531 if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
3532 v_record.us_vdd = mm_table->entries[entryId].vddc +
3533 mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
3534 else
3535 v_record.us_vdd = mm_table->entries[entryId].vddc +
3536 mm_table->entries[entryId].vddgfx_offset;
3537
3538 /* Add the calculated VDDGFX to the VDDGFX lookup table */
3539 mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
3540 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3541 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3542 }
3543 }
3544 return 0;
3545}
3546
3547
3548/**
3549 * Change virtual leakage voltage to actual value.
3550 *
3551 * @param hwmgr the address of the powerplay hardware manager.
3552 * @param pointer to changing voltage
3553 * @param pointer to leakage table
3554 */
3555static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
3556 uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
3557{
3558 uint32_t leakage_index;
3559
3560 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3561 for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
3562 /* if this voltage matches a leakage voltage ID */
3563 /* patch with actual leakage voltage */
3564 if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
3565 *voltage = pLeakageTable->actual_voltage[leakage_index];
3566 break;
3567 }
3568 }
3569
3570 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
3571 printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
3572}
3573
3574/**
3575 * Patch voltage lookup table by EVV leakages.
3576 *
3577 * @param hwmgr the address of the powerplay hardware manager.
3578 * @param pointer to voltage lookup table
3579 * @param pointer to leakage table
3580 * @return always 0
3581 */
3582static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
3583 phm_ppt_v1_voltage_lookup_table *lookup_table,
3584 phw_tonga_leakage_voltage *pLeakageTable)
3585{
3586 uint32_t i;
3587
3588 for (i = 0; i < lookup_table->count; i++) {
3589 tonga_patch_with_vdd_leakage(hwmgr,
3590 &lookup_table->entries[i].us_vdd, pLeakageTable);
3591 }
3592
3593 return 0;
3594}
3595
3596static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3597 phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
3598{
3599 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3600
3601 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
3602 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
3603 pptable_info->max_clock_voltage_on_dc.vddc;
3604
3605 return 0;
3606}
3607
3608static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
3609 struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
3610 uint16_t *Vddgfx)
3611{
3612 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
3613 return 0;
3614}
3615
3616int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
3617 phm_ppt_v1_voltage_lookup_table *lookup_table)
3618{
3619 uint32_t table_size, i, j;
3620 phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3621 table_size = lookup_table->count;
3622
3623 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3624 "Lookup table is empty", return -1);
3625
3626 /* Sorting voltages */
3627 for (i = 0; i < table_size - 1; i++) {
3628 for (j = i + 1; j > 0; j--) {
3629 if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
3630 tmp_voltage_lookup_record = lookup_table->entries[j-1];
3631 lookup_table->entries[j-1] = lookup_table->entries[j];
3632 lookup_table->entries[j] = tmp_voltage_lookup_record;
3633 }
3634 }
3635 }
3636
3637 return 0;
3638}
3639
3640static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3641{
3642 int result = 0;
3643 int tmp_result;
3644 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3645 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3646
3647 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3648 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3649 pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
3650 if (tmp_result != 0)
3651 result = tmp_result;
3652
3653 tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
3654 &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
3655 if (tmp_result != 0)
3656 result = tmp_result;
3657 } else {
3658 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3659 pptable_info->vddc_lookup_table, &(data->vddc_leakage));
3660 if (tmp_result != 0)
3661 result = tmp_result;
3662
3663 tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
3664 &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
3665 if (tmp_result != 0)
3666 result = tmp_result;
3667 }
3668
3669 tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3670 if (tmp_result != 0)
3671 result = tmp_result;
3672
3673 tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
3674 if (tmp_result != 0)
3675 result = tmp_result;
3676
3677 tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
3678 if (tmp_result != 0)
3679 result = tmp_result;
3680
3681 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
3682 if (tmp_result != 0)
3683 result = tmp_result;
3684
3685 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
3686 if (tmp_result != 0)
3687 result = tmp_result;
3688
3689 return result;
3690}
3691
3692int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3693{
3694 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3695 data->low_sclk_interrupt_threshold = 0;
3696
3697 return 0;
3698}
3699
3700int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
3701{
3702 int tmp_result, result = 0;
3703
3704 tmp_result = tonga_read_clock_registers(hwmgr);
3705 PP_ASSERT_WITH_CODE((0 == tmp_result),
3706 "Failed to read clock registers!", result = tmp_result);
3707
3708 tmp_result = tonga_get_memory_type(hwmgr);
3709 PP_ASSERT_WITH_CODE((0 == tmp_result),
3710 "Failed to get memory type!", result = tmp_result);
3711
3712 tmp_result = tonga_enable_acpi_power_management(hwmgr);
3713 PP_ASSERT_WITH_CODE((0 == tmp_result),
3714 "Failed to enable ACPI power management!", result = tmp_result);
3715
3716 tmp_result = tonga_init_power_gate_state(hwmgr);
3717 PP_ASSERT_WITH_CODE((0 == tmp_result),
3718 "Failed to init power gate state!", result = tmp_result);
3719
3720 tmp_result = tonga_get_mc_microcode_version(hwmgr);
3721 PP_ASSERT_WITH_CODE((0 == tmp_result),
3722 "Failed to get MC microcode version!", result = tmp_result);
3723
3724 tmp_result = tonga_init_sclk_threshold(hwmgr);
3725 PP_ASSERT_WITH_CODE((0 == tmp_result),
3726 "Failed to init sclk threshold!", result = tmp_result);
3727
3728 return result;
3729}
3730
3731/**
3732 * Enable voltage control
3733 *
3734 * @param hwmgr the address of the powerplay hardware manager.
3735 * @return always 0
3736 */
3737int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
3738{
3739 /* enable voltage control */
3740 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
3741
3742 return 0;
3743}
3744
3745/**
3746 * Checks if we want to support voltage control
3747 *
3748 * @param hwmgr the address of the powerplay hardware manager.
3749 */
3750bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
3751{
3752 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3753
3754 return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
3755}
3756
3757/*---------------------------MC----------------------------*/
3758
3759uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
3760{
3761 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
3762}
3763
3764bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
3765{
3766 bool result = 1;
3767
3768 switch (inReg) {
3769 case mmMC_SEQ_RAS_TIMING:
3770 *outReg = mmMC_SEQ_RAS_TIMING_LP;
3771 break;
3772
3773 case mmMC_SEQ_DLL_STBY:
3774 *outReg = mmMC_SEQ_DLL_STBY_LP;
3775 break;
3776
3777 case mmMC_SEQ_G5PDX_CMD0:
3778 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
3779 break;
3780
3781 case mmMC_SEQ_G5PDX_CMD1:
3782 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
3783 break;
3784
3785 case mmMC_SEQ_G5PDX_CTRL:
3786 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
3787 break;
3788
3789 case mmMC_SEQ_CAS_TIMING:
3790 *outReg = mmMC_SEQ_CAS_TIMING_LP;
3791 break;
3792
3793 case mmMC_SEQ_MISC_TIMING:
3794 *outReg = mmMC_SEQ_MISC_TIMING_LP;
3795 break;
3796
3797 case mmMC_SEQ_MISC_TIMING2:
3798 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
3799 break;
3800
3801 case mmMC_SEQ_PMG_DVS_CMD:
3802 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
3803 break;
3804
3805 case mmMC_SEQ_PMG_DVS_CTL:
3806 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
3807 break;
3808
3809 case mmMC_SEQ_RD_CTL_D0:
3810 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
3811 break;
3812
3813 case mmMC_SEQ_RD_CTL_D1:
3814 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
3815 break;
3816
3817 case mmMC_SEQ_WR_CTL_D0:
3818 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
3819 break;
3820
3821 case mmMC_SEQ_WR_CTL_D1:
3822 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
3823 break;
3824
3825 case mmMC_PMG_CMD_EMRS:
3826 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
3827 break;
3828
3829 case mmMC_PMG_CMD_MRS:
3830 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
3831 break;
3832
3833 case mmMC_PMG_CMD_MRS1:
3834 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
3835 break;
3836
3837 case mmMC_SEQ_PMG_TIMING:
3838 *outReg = mmMC_SEQ_PMG_TIMING_LP;
3839 break;
3840
3841 case mmMC_PMG_CMD_MRS2:
3842 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
3843 break;
3844
3845 case mmMC_SEQ_WR_CTL_2:
3846 *outReg = mmMC_SEQ_WR_CTL_2_LP;
3847 break;
3848
3849 default:
3850 result = 0;
3851 break;
3852 }
3853
3854 return result;
3855}
3856
3857int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
3858{
3859 uint32_t i;
3860 uint16_t address;
3861
3862 for (i = 0; i < table->last; i++) {
3863 table->mc_reg_address[i].s0 =
3864 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
3865 ? address : table->mc_reg_address[i].s1;
3866 }
3867 return 0;
3868}
3869
3870int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
3871{
3872 uint8_t i, j;
3873
3874 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3875 "Invalid VramInfo table.", return -1);
3876 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3877 "Invalid VramInfo table.", return -1);
3878
3879 for (i = 0; i < table->last; i++) {
3880 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3881 }
3882 ni_table->last = table->last;
3883
3884 for (i = 0; i < table->num_entries; i++) {
3885 ni_table->mc_reg_table_entry[i].mclk_max =
3886 table->mc_reg_table_entry[i].mclk_max;
3887 for (j = 0; j < table->last; j++) {
3888 ni_table->mc_reg_table_entry[i].mc_data[j] =
3889 table->mc_reg_table_entry[i].mc_data[j];
3890 }
3891 }
c15c8d70 3892
c82baa28 3893 ni_table->num_entries = table->num_entries;
3894
3895 return 0;
3896}
3897
3898/**
3899 * VBIOS omits some information to reduce size, we need to recover them here.
3900 * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3901 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3902 * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
3903 * 3. need to set these data for each clock range
3904 *
3905 * @param hwmgr the address of the powerplay hardware manager.
3906 * @param table the address of MCRegTable
3907 * @return always 0
3908 */
3909int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
3910{
3911 uint8_t i, j, k;
3912 uint32_t temp_reg;
3913 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3914
3915 for (i = 0, j = table->last; i < table->last; i++) {
3916 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3917 "Invalid VramInfo table.", return -1);
3918 switch (table->mc_reg_address[i].s1) {
3919 /*
3920 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3921 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3922 */
3923 case mmMC_SEQ_MISC1:
3924 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
3925 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3926 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3927 for (k = 0; k < table->num_entries; k++) {
3928 table->mc_reg_table_entry[k].mc_data[j] =
3929 ((temp_reg & 0xffff0000)) |
3930 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3931 }
3932 j++;
3933 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3934 "Invalid VramInfo table.", return -1);
3935
3936 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3937 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3938 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3939 for (k = 0; k < table->num_entries; k++) {
3940 table->mc_reg_table_entry[k].mc_data[j] =
3941 (temp_reg & 0xffff0000) |
3942 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3943
3944 if (!data->is_memory_GDDR5) {
3945 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3946 }
3947 }
3948 j++;
3949 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3950 "Invalid VramInfo table.", return -1);
3951
3952 if (!data->is_memory_GDDR5) {
3953 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3954 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3955 for (k = 0; k < table->num_entries; k++) {
3956 table->mc_reg_table_entry[k].mc_data[j] =
3957 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3958 }
3959 j++;
3960 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3961 "Invalid VramInfo table.", return -1);
3962 }
3963
3964 break;
3965
3966 case mmMC_SEQ_RESERVE_M:
3967 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3968 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3969 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3970 for (k = 0; k < table->num_entries; k++) {
3971 table->mc_reg_table_entry[k].mc_data[j] =
3972 (temp_reg & 0xffff0000) |
3973 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3974 }
3975 j++;
3976 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3977 "Invalid VramInfo table.", return -1);
3978 break;
3979
3980 default:
3981 break;
3982 }
3983
3984 }
3985
3986 table->last = j;
3987
3988 return 0;
3989}
3990
3991int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
3992{
3993 uint8_t i, j;
3994 for (i = 0; i < table->last; i++) {
3995 for (j = 1; j < table->num_entries; j++) {
3996 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3997 table->mc_reg_table_entry[j].mc_data[i]) {
3998 table->validflag |= (1<<i);
3999 break;
4000 }
4001 }
4002 }
4003
4004 return 0;
4005}
4006
4007int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
4008{
4009 int result;
4010 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4011 pp_atomctrl_mc_reg_table *table;
4012 phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
4013 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
4014
4015 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
4016
4017 if (NULL == table)
c15c8d70 4018 return -ENOMEM;
c82baa28 4019
4020 /* Program additional LP registers that are no longer programmed by VBIOS */
4021 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
4022 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
4023 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
4024 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
4025 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
4026 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
4027 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
4028 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
4029 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
4030 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
4031 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
4032 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
4033 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
4034 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
4035 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
4036 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
4037 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
4038 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
4039 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
4040 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
4041
4042 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
4043
4044 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
4045
4046 if (0 == result)
4047 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
4048
4049 if (0 == result) {
4050 tonga_set_s0_mc_reg_index(ni_table);
4051 result = tonga_set_mc_special_registers(hwmgr, ni_table);
4052 }
4053
4054 if (0 == result)
4055 tonga_set_valid_flag(ni_table);
4056
4057 kfree(table);
4058 return result;
4059}
4060
4061/*
4062* Copy one arb setting to another and then switch the active set.
4063* arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
4064*/
4065int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
4066 uint32_t arbFreqSrc, uint32_t arbFreqDest)
4067{
4068 uint32_t mc_arb_dram_timing;
4069 uint32_t mc_arb_dram_timing2;
4070 uint32_t burst_time;
4071 uint32_t mc_cg_config;
4072
4073 switch (arbFreqSrc) {
4074 case MC_CG_ARB_FREQ_F0:
4075 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
4076 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
4077 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
4078 break;
4079
4080 case MC_CG_ARB_FREQ_F1:
4081 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
4082 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
4083 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
4084 break;
4085
4086 default:
4087 return -1;
4088 }
4089
4090 switch (arbFreqDest) {
4091 case MC_CG_ARB_FREQ_F0:
4092 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
4093 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
4094 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
4095 break;
4096
4097 case MC_CG_ARB_FREQ_F1:
4098 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
4099 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
4100 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
4101 break;
4102
4103 default:
4104 return -1;
4105 }
4106
4107 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
4108 mc_cg_config |= 0x0000000F;
4109 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
4110 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
4111
4112 return 0;
4113}
4114
4115/**
4116 * Initial switch from ARB F0->F1
4117 *
4118 * @param hwmgr the address of the powerplay hardware manager.
4119 * @return always 0
4120 * This function is to be called from the SetPowerState table.
4121 */
4122int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
4123{
4124 return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4125}
4126
4127/**
4128 * Initialize the ARB DRAM timing table's index field.
4129 *
4130 * @param hwmgr the address of the powerplay hardware manager.
4131 * @return always 0
4132 */
4133int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
4134{
4135 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4136 uint32_t tmp;
4137 int result;
4138
4139 /*
4140 * This is a read-modify-write on the first byte of the ARB table.
4141 * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
4142 * This solution is ugly, but we never write the whole table only individual fields in it.
4143 * In reality this field should not be in that structure but in a soft register.
4144 */
4145 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
4146 data->arb_table_start, &tmp, data->sram_end);
4147
4148 if (0 != result)
4149 return result;
4150
4151 tmp &= 0x00FFFFFF;
4152 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
4153
4154 return tonga_write_smc_sram_dword(hwmgr->smumgr,
4155 data->arb_table_start, tmp, data->sram_end);
4156}
4157
4158int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
4159{
4160 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4161
4162 uint32_t i, j;
4163
4164 for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
4165 if (data->tonga_mc_reg_table.validflag & 1<<j) {
4166 PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
4167 "Index of mc_reg_table->address[] array out of boundary", return -1);
4168 mc_reg_table->address[i].s0 =
4169 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
4170 mc_reg_table->address[i].s1 =
4171 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
4172 i++;
4173 }
4174 }
4175
4176 mc_reg_table->last = (uint8_t)i;
4177
4178 return 0;
4179}
4180
4181/*convert register values from driver to SMC format */
4182void tonga_convert_mc_registers(
4183 const phw_tonga_mc_reg_entry * pEntry,
4184 SMU72_Discrete_MCRegisterSet *pData,
4185 uint32_t numEntries, uint32_t validflag)
4186{
4187 uint32_t i, j;
4188
4189 for (i = 0, j = 0; j < numEntries; j++) {
4190 if (validflag & 1<<j) {
4191 pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
4192 i++;
4193 }
4194 }
4195}
4196
4197/* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
4198int tonga_convert_mc_reg_table_entry_to_smc(
4199 struct pp_hwmgr *hwmgr,
4200 const uint32_t memory_clock,
4201 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
4202 )
4203{
4204 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4205 uint32_t i = 0;
4206
4207 for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
4208 if (memory_clock <=
4209 data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
4210 break;
4211 }
4212 }
4213
4214 if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
4215 --i;
4216
4217 tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
4218 mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
4219
4220 return 0;
4221}
4222
4223int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
4224 SMU72_Discrete_MCRegisters *mc_reg_table)
4225{
4226 int result = 0;
4227 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4228 int res;
4229 uint32_t i;
4230
4231 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
4232 res = tonga_convert_mc_reg_table_entry_to_smc(
4233 hwmgr,
4234 data->dpm_table.mclk_table.dpm_levels[i].value,
4235 &mc_reg_table->data[i]
4236 );
4237
4238 if (0 != res)
4239 result = res;
4240 }
4241
4242 return result;
4243}
4244
4245int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
4246{
4247 int result;
4248 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4249
4250 memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
4251 result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
4252 PP_ASSERT_WITH_CODE(0 == result,
4253 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
4254
4255 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
4256 PP_ASSERT_WITH_CODE(0 == result,
4257 "Failed to initialize MCRegTable for driver state!", return result;);
4258
4259 return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
4260 (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
4261}
4262
4263/**
4264 * Programs static screed detection parameters
4265 *
4266 * @param hwmgr the address of the powerplay hardware manager.
4267 * @return always 0
4268 */
4269int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
4270{
4271 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4272
4273 /* Set static screen threshold unit*/
4274 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4275 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
4276 data->static_screen_threshold_unit);
4277 /* Set static screen threshold*/
4278 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4279 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
4280 data->static_screen_threshold);
4281
4282 return 0;
4283}
4284
4285/**
4286 * Setup display gap for glitch free memory clock switching.
4287 *
4288 * @param hwmgr the address of the powerplay hardware manager.
4289 * @return always 0
4290 */
4291int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
4292{
4293 uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4294 CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4295
4296 display_gap = PHM_SET_FIELD(display_gap,
4297 CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
4298
4299 display_gap = PHM_SET_FIELD(display_gap,
4300 CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
4301
4302 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4303 ixCG_DISPLAY_GAP_CNTL, display_gap);
4304
4305 return 0;
4306}
4307
4308/**
4309 * Programs activity state transition voting clients
4310 *
4311 * @param hwmgr the address of the powerplay hardware manager.
4312 * @return always 0
4313 */
4314int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
4315{
4316 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4317
4318 /* Clear reset for voting clients before enabling DPM */
4319 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4320 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
4321 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4322 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
4323
4324 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4325 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
4326 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4327 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
4328 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4329 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
4330 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4331 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
4332 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4333 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
4334 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4335 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
4336 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4337 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
4338 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4339 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
4340
4341 return 0;
4342}
4343
4344
4345int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
4346{
4347 int tmp_result, result = 0;
4348
4349 tmp_result = tonga_check_for_dpm_stopped(hwmgr);
4350
4351 if (cf_tonga_voltage_control(hwmgr)) {
4352 tmp_result = tonga_enable_voltage_control(hwmgr);
4353 PP_ASSERT_WITH_CODE((0 == tmp_result),
4354 "Failed to enable voltage control!", result = tmp_result);
4355
4356 tmp_result = tonga_construct_voltage_tables(hwmgr);
4357 PP_ASSERT_WITH_CODE((0 == tmp_result),
4358 "Failed to contruct voltage tables!", result = tmp_result);
4359 }
4360
4361 tmp_result = tonga_initialize_mc_reg_table(hwmgr);
4362 PP_ASSERT_WITH_CODE((0 == tmp_result),
4363 "Failed to initialize MC reg table!", result = tmp_result);
4364
4365 tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
4366 PP_ASSERT_WITH_CODE((0 == tmp_result),
4367 "Failed to program static screen threshold parameters!", result = tmp_result);
4368
4369 tmp_result = tonga_enable_display_gap(hwmgr);
4370 PP_ASSERT_WITH_CODE((0 == tmp_result),
4371 "Failed to enable display gap!", result = tmp_result);
4372
4373 tmp_result = tonga_program_voting_clients(hwmgr);
4374 PP_ASSERT_WITH_CODE((0 == tmp_result),
4375 "Failed to program voting clients!", result = tmp_result);
4376
4377 tmp_result = tonga_process_firmware_header(hwmgr);
4378 PP_ASSERT_WITH_CODE((0 == tmp_result),
4379 "Failed to process firmware header!", result = tmp_result);
4380
4381 tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
4382 PP_ASSERT_WITH_CODE((0 == tmp_result),
4383 "Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
4384
4385 tmp_result = tonga_init_smc_table(hwmgr);
4386 PP_ASSERT_WITH_CODE((0 == tmp_result),
4387 "Failed to initialize SMC table!", result = tmp_result);
4388
4389 tmp_result = tonga_init_arb_table_index(hwmgr);
4390 PP_ASSERT_WITH_CODE((0 == tmp_result),
4391 "Failed to initialize ARB table index!", result = tmp_result);
4392
4393 tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
4394 PP_ASSERT_WITH_CODE((0 == tmp_result),
4395 "Failed to populate initialize MC Reg table!", result = tmp_result);
4396
bbb207f3
RZ		 4397 tmp_result = tonga_notify_smc_display_change(hwmgr, false);
4398 PP_ASSERT_WITH_CODE((0 == tmp_result),
4399 "Failed to notify no display!", result = tmp_result);
4400
c82baa28 4401 /* enable SCLK control */
4402 tmp_result = tonga_enable_sclk_control(hwmgr);
4403 PP_ASSERT_WITH_CODE((0 == tmp_result),
4404 "Failed to enable SCLK control!", result = tmp_result);
4405
4406 /* enable DPM */
4407 tmp_result = tonga_start_dpm(hwmgr);
4408 PP_ASSERT_WITH_CODE((0 == tmp_result),
4409 "Failed to start DPM!", result = tmp_result);
4410
4411 return result;
4412}
4413
4414int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4415{
4416 int tmp_result, result = 0;
4417
4418 tmp_result = tonga_check_for_dpm_running(hwmgr);
4419 PP_ASSERT_WITH_CODE((0 == tmp_result),
4420 "SMC is still running!", return 0);
4421
4422 tmp_result = tonga_stop_dpm(hwmgr);
4423 PP_ASSERT_WITH_CODE((0 == tmp_result),
4424 "Failed to stop DPM!", result = tmp_result);
4425
4426 tmp_result = tonga_reset_to_default(hwmgr);
4427 PP_ASSERT_WITH_CODE((0 == tmp_result),
4428 "Failed to reset to default!", result = tmp_result);
4429
4430 return result;
4431}
4432
4433int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
4434{
4435 int result;
4436
4437 result = tonga_set_boot_state(hwmgr);
4438 if (0 != result)
4439 printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
4440
4441 return result;
4442}
4443
4444int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
4445{
92dea67d 4446 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
c82baa28 4447
92dea67d
EH		 4448 if (data->soft_pp_table) {
4449 kfree(data->soft_pp_table);
4450 data->soft_pp_table = NULL;
c82baa28 4451 }
4452
92dea67d 4453 return phm_hwmgr_backend_fini(hwmgr);
c82baa28 4454}
4455
4456/**
4457 * Initializes the Volcanic Islands Hardware Manager
4458 *
4459 * @param hwmgr the address of the powerplay hardware manager.
4460 * @return 1 if success; otherwise appropriate error code.
4461 */
4462int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4463{
4464 int result = 0;
4465 SMU72_Discrete_DpmTable *table = NULL;
4466 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4467 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4468 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4469 phw_tonga_ulv_parm *ulv;
52b52a87 4470 struct cgs_system_info sys_info = {0};
c82baa28 4471
4472 PP_ASSERT_WITH_CODE((NULL != hwmgr),
4473 "Invalid Parameter!", return -1;);
4474
4475 data->dll_defaule_on = 0;
4476 data->sram_end = SMC_RAM_END;
4477
4478 data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
4479 data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
4480 data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
4481 data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
4482 data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
4483 data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
4484 data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
4485 data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
4486
4487 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
4488 data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
4489 data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
4490
4491 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4492 PHM_PlatformCaps_DisableVoltageIsland);
4493
4494 data->sclk_dpm_key_disabled = 0;
4495 data->mclk_dpm_key_disabled = 0;
4496 data->pcie_dpm_key_disabled = 0;
4497 data->pcc_monitor_enabled = 0;
4498
4499 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4500 PHM_PlatformCaps_UnTabledHardwareInterface);
4501
4502 data->gpio_debug = 0;
4503 data->engine_clock_data = 0;
4504 data->memory_clock_data = 0;
4505 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4506 PHM_PlatformCaps_DynamicPatchPowerState);
4507
4508 /* need to set voltage control types before EVV patching*/
4509 data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
4510 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4511 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4512 data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4513
3ec2cdb8 4514 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4515 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
4516 data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4517 }
4518
4519 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4520 PHM_PlatformCaps_ControlVDDGFX)) {
3ec2cdb8 4521 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4522 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
4523 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4524 }
4525 }
4526
4527 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
4528 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4529 PHM_PlatformCaps_ControlVDDGFX);
4530 }
4531
4532 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4533 PHM_PlatformCaps_EnableMVDDControl)) {
3ec2cdb8 4534 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4535 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
4536 data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4537 }
4538 }
4539
4540 if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
4541 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4542 PHM_PlatformCaps_EnableMVDDControl);
4543 }
4544
4545 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4546 PHM_PlatformCaps_ControlVDDCI)) {
3ec2cdb8 4547 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4548 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
4549 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
3ec2cdb8 4550 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4551 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
4552 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4553 }
4554
4555 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
4556 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4557 PHM_PlatformCaps_ControlVDDCI);
4558
4559 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4560 PHM_PlatformCaps_TablelessHardwareInterface);
4561
4562 if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
4563 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4564 PHM_PlatformCaps_ClockStretcher);
4565
4566 /* Initializes DPM default values*/
4567 tonga_initialize_dpm_defaults(hwmgr);
4568
4569 /* Get leakage voltage based on leakage ID.*/
4570 PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
4571 "Get EVV Voltage Failed. Abort Driver loading!", return -1);
4572
4573 tonga_complete_dependency_tables(hwmgr);
4574
4575 /* Parse pptable data read from VBIOS*/
4576 tonga_set_private_var_based_on_pptale(hwmgr);
4577
4578 /* ULV Support*/
4579 ulv = &(data->ulv);
4580 ulv->ulv_supported = 0;
4581
4582 /* Initalize Dynamic State Adjustment Rule Settings*/
4583 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
aa22ae4b
AD		 4584 if (result)
4585 printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
c82baa28 4586 data->uvd_enabled = 0;
4587
4588 table = &(data->smc_state_table);
4589
4590 /*
4591 * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
4592 * Peak Current Control feature is enabled and we should program PCC HW register
4593 */
4594 if (0 == atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
4595 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
4596 CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
4597
4598 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
4599 case 0:
4600 temp_reg = PHM_SET_FIELD(temp_reg,
4601 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
4602 break;
4603 case 1:
4604 temp_reg = PHM_SET_FIELD(temp_reg,
4605 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
4606 break;
4607 case 2:
4608 temp_reg = PHM_SET_FIELD(temp_reg,
4609 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
4610 break;
4611 case 3:
4612 temp_reg = PHM_SET_FIELD(temp_reg,
4613 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
4614 break;
4615 case 4:
4616 temp_reg = PHM_SET_FIELD(temp_reg,
4617 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
4618 break;
4619 default:
4620 printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \
4621 Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
4622 break;
4623 }
4624 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4625 ixCNB_PWRMGT_CNTL, temp_reg);
4626 }
4627
4628 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4629 PHM_PlatformCaps_EnableSMU7ThermalManagement);
4630 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4631 PHM_PlatformCaps_SMU7);
4632
4633 data->vddc_phase_shed_control = 0;
4634
3d5afb41
AD		 4635 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4636 PHM_PlatformCaps_UVDPowerGating);
f997e6f2
AD		 4637 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4638 PHM_PlatformCaps_VCEPowerGating);
52b52a87
AD		 4639 sys_info.size = sizeof(struct cgs_system_info);
4640 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
4641 result = cgs_query_system_info(hwmgr->device, &sys_info);
4642 if (!result) {
4643 if (sys_info.value & AMD_PG_SUPPORT_UVD)
4644 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4645 PHM_PlatformCaps_UVDPowerGating);
4646 if (sys_info.value & AMD_PG_SUPPORT_VCE)
4647 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4648 PHM_PlatformCaps_VCEPowerGating);
4649 }
834b694c 4650
c82baa28 4651 if (0 == result) {
4652 data->is_tlu_enabled = 0;
4653 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4654 TONGA_MAX_HARDWARE_POWERLEVELS;
4655 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
4656 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
4657
834b694c
AD		 4658 sys_info.size = sizeof(struct cgs_system_info);
4659 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
4660 result = cgs_query_system_info(hwmgr->device, &sys_info);
4661 if (result)
4662 data->pcie_gen_cap = 0x30007;
4663 else
4664 data->pcie_gen_cap = (uint32_t)sys_info.value;
4665 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
4666 data->pcie_spc_cap = 20;
4667 sys_info.size = sizeof(struct cgs_system_info);
4668 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
4669 result = cgs_query_system_info(hwmgr->device, &sys_info);
4670 if (result)
4671 data->pcie_lane_cap = 0x2f0000;
4672 else
4673 data->pcie_lane_cap = (uint32_t)sys_info.value;
c82baa28 4674 } else {
4675 /* Ignore return value in here, we are cleaning up a mess. */
4676 tonga_hwmgr_backend_fini(hwmgr);
4677 }
4678
4679 return result;
4680}
4681
4682static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
4683 enum amd_dpm_forced_level level)
4684{
4685 int ret = 0;
4686
4687 switch (level) {
4688 case AMD_DPM_FORCED_LEVEL_HIGH:
4689 ret = tonga_force_dpm_highest(hwmgr);
4690 if (ret)
4691 return ret;
4692 break;
4693 case AMD_DPM_FORCED_LEVEL_LOW:
4694 ret = tonga_force_dpm_lowest(hwmgr);
4695 if (ret)
4696 return ret;
4697 break;
4698 case AMD_DPM_FORCED_LEVEL_AUTO:
4699 ret = tonga_unforce_dpm_levels(hwmgr);
4700 if (ret)
4701 return ret;
4702 break;
4703 default:
4704 break;
4705 }
4706
4707 hwmgr->dpm_level = level;
4708 return ret;
4709}
4710
4711static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4712 struct pp_power_state *prequest_ps,
4713 const struct pp_power_state *pcurrent_ps)
4714{
4715 struct tonga_power_state *tonga_ps =
4716 cast_phw_tonga_power_state(&prequest_ps->hardware);
4717
4718 uint32_t sclk;
4719 uint32_t mclk;
4720 struct PP_Clocks minimum_clocks = {0};
4721 bool disable_mclk_switching;
4722 bool disable_mclk_switching_for_frame_lock;
4723 struct cgs_display_info info = {0};
4724 const struct phm_clock_and_voltage_limits *max_limits;
4725 uint32_t i;
4726 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4727 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4728
4729 int32_t count;
4730 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4731
4732 data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
4733
4734 PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
4735 "VI should always have 2 performance levels",
4736 );
4737
4738 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4739 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4740 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4741
4742 if (PP_PowerSource_DC == hwmgr->power_source) {
4743 for (i = 0; i < tonga_ps->performance_level_count; i++) {
4744 if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
4745 tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
4746 if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
4747 tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
4748 }
4749 }
4750
4751 tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
4752 tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
4753
4754 tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4755
4756 cgs_get_active_displays_info(hwmgr->device, &info);
4757
4758 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4759
4760 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4761
4762 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4763
4764 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4765 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4766
4767 for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
4768 if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
4769 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
4770 break;
4771 }
4772 }
4773
4774 if (count < 0)
4775 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
4776
4777 stable_pstate_mclk = max_limits->mclk;
4778
4779 minimum_clocks.engineClock = stable_pstate_sclk;
4780 minimum_clocks.memoryClock = stable_pstate_mclk;
4781 }
4782
4783 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4784 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4785
4786 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4787 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4788
4789 tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4790
4791 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4792 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
4793 "Overdrive sclk exceeds limit",
4794 hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
4795
4796 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4797 tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4798 }
4799
4800 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4801 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4802 "Overdrive mclk exceeds limit",
4803 hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4804
4805 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4806 tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4807 }
4808
4809 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4810 hwmgr->platform_descriptor.platformCaps,
4811 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4812
4813 disable_mclk_switching = (1 < info.display_count) ||
4814 disable_mclk_switching_for_frame_lock;
4815
4816 sclk = tonga_ps->performance_levels[0].engine_clock;
4817 mclk = tonga_ps->performance_levels[0].memory_clock;
4818
4819 if (disable_mclk_switching)
4820 mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
4821
4822 if (sclk < minimum_clocks.engineClock)
4823 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4824
4825 if (mclk < minimum_clocks.memoryClock)
4826 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4827
4828 tonga_ps->performance_levels[0].engine_clock = sclk;
4829 tonga_ps->performance_levels[0].memory_clock = mclk;
4830
4831 tonga_ps->performance_levels[1].engine_clock =
4832 (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
4833 tonga_ps->performance_levels[1].engine_clock :
4834 tonga_ps->performance_levels[0].engine_clock;
4835
4836 if (disable_mclk_switching) {
4837 if (mclk < tonga_ps->performance_levels[1].memory_clock)
4838 mclk = tonga_ps->performance_levels[1].memory_clock;
4839
4840 tonga_ps->performance_levels[0].memory_clock = mclk;
4841 tonga_ps->performance_levels[1].memory_clock = mclk;
4842 } else {
4843 if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
4844 tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
4845 }
4846
4847 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4848 for (i=0; i < tonga_ps->performance_level_count; i++) {
4849 tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4850 tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4851 tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4852 tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4853 }
4854 }
4855
4856 return 0;
4857}
4858
4859int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
4860{
4861 return sizeof(struct tonga_power_state);
4862}
4863
4864static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4865{
4866 struct pp_power_state *ps;
4867 struct tonga_power_state *tonga_ps;
4868
4869 if (hwmgr == NULL)
4870 return -EINVAL;
4871
4872 ps = hwmgr->request_ps;
4873
4874 if (ps == NULL)
4875 return -EINVAL;
4876
4877 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4878
4879 if (low)
4880 return tonga_ps->performance_levels[0].memory_clock;
4881 else
4882 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
4883}
4884
4885static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4886{
4887 struct pp_power_state *ps;
4888 struct tonga_power_state *tonga_ps;
4889
4890 if (hwmgr == NULL)
4891 return -EINVAL;
4892
4893 ps = hwmgr->request_ps;
4894
4895 if (ps == NULL)
4896 return -EINVAL;
4897
4898 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4899
4900 if (low)
4901 return tonga_ps->performance_levels[0].engine_clock;
4902 else
4903 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
4904}
4905
4906static uint16_t tonga_get_current_pcie_speed(
4907 struct pp_hwmgr *hwmgr)
4908{
4909 uint32_t speed_cntl = 0;
4910
4911 speed_cntl = cgs_read_ind_register(hwmgr->device,
4912 CGS_IND_REG__PCIE,
4913 ixPCIE_LC_SPEED_CNTL);
4914 return((uint16_t)PHM_GET_FIELD(speed_cntl,
4915 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4916}
4917
4918static int tonga_get_current_pcie_lane_number(
4919 struct pp_hwmgr *hwmgr)
4920{
4921 uint32_t link_width;
4922
4923 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4924 CGS_IND_REG__PCIE,
4925 PCIE_LC_LINK_WIDTH_CNTL,
4926 LC_LINK_WIDTH_RD);
4927
4928 PP_ASSERT_WITH_CODE((7 >= link_width),
4929 "Invalid PCIe lane width!", return 0);
4930
4931 return decode_pcie_lane_width(link_width);
4932}
4933
4934static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4935 struct pp_hw_power_state *hw_ps)
4936{
4937 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4938 struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
4939 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4940 uint16_t size;
4941 uint8_t frev, crev;
4942 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4943
4944 /* First retrieve the Boot clocks and VDDC from the firmware info table.
4945 * We assume here that fw_info is unchanged if this call fails.
4946 */
4947 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4948 hwmgr->device, index,
4949 &size, &frev, &crev);
4950 if (!fw_info)
4951 /* During a test, there is no firmware info table. */
4952 return 0;
4953
4954 /* Patch the state. */
4955 data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock);
4956 data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4957 data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4958 data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4959 data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4960 data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
4961 data->vbios_boot_state.pcie_lane_bootup_value =
4962 (uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
4963
4964 /* set boot power state */
4965 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4966 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4967 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4968 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4969
4970 return 0;
4971}
4972
4973static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4974 void *state, struct pp_power_state *power_state,
4975 void *pp_table, uint32_t classification_flag)
4976{
4977 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4978
4979 struct tonga_power_state *tonga_ps =
4980 (struct tonga_power_state *)(&(power_state->hardware));
4981
4982 struct tonga_performance_level *performance_level;
4983
4984 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
4985
4986 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
4987 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
4988
4989 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
4990 (ATOM_Tonga_SCLK_Dependency_Table *)
c9fe74e6 4991 (((unsigned long)powerplay_table) +
c82baa28 4992 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
4993
4994 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
4995 (ATOM_Tonga_MCLK_Dependency_Table *)
c9fe74e6 4996 (((unsigned long)powerplay_table) +
c82baa28 4997 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
4998
4999 /* The following fields are not initialized here: id orderedList allStatesList */
5000 power_state->classification.ui_label =
5001 (le16_to_cpu(state_entry->usClassification) &
5002 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
5003 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
5004 power_state->classification.flags = classification_flag;
5005 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
5006
5007 power_state->classification.temporary_state = false;
5008 power_state->classification.to_be_deleted = false;
5009
5010 power_state->validation.disallowOnDC =
5011 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
5012
5013 power_state->pcie.lanes = 0;
5014
5015 power_state->display.disableFrameModulation = false;
5016 power_state->display.limitRefreshrate = false;
5017 power_state->display.enableVariBright =
5018 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
5019
5020 power_state->validation.supportedPowerLevels = 0;
5021 power_state->uvd_clocks.VCLK = 0;
5022 power_state->uvd_clocks.DCLK = 0;
5023 power_state->temperatures.min = 0;
5024 power_state->temperatures.max = 0;
5025
5026 performance_level = &(tonga_ps->performance_levels
5027 [tonga_ps->performance_level_count++]);
5028
5029 PP_ASSERT_WITH_CODE(
5030 (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
5031 "Performance levels exceeds SMC limit!",
5032 return -1);
5033
5034 PP_ASSERT_WITH_CODE(
5035 (tonga_ps->performance_level_count <=
5036 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
5037 "Performance levels exceeds Driver limit!",
5038 return -1);
5039
5040 /* Performance levels are arranged from low to high. */
5041 performance_level->memory_clock =
5042 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
5043
5044 performance_level->engine_clock =
5045 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
5046
5047 performance_level->pcie_gen = get_pcie_gen_support(
5048 data->pcie_gen_cap,
5049 state_entry->ucPCIEGenLow);
5050
5051 performance_level->pcie_lane = get_pcie_lane_support(
5052 data->pcie_lane_cap,
5053 state_entry->ucPCIELaneHigh);
5054
5055 performance_level =
5056 &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
5057
5058 performance_level->memory_clock =
5059 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
5060
5061 performance_level->engine_clock =
5062 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
5063
5064 performance_level->pcie_gen = get_pcie_gen_support(
5065 data->pcie_gen_cap,
5066 state_entry->ucPCIEGenHigh);
5067
5068 performance_level->pcie_lane = get_pcie_lane_support(
5069 data->pcie_lane_cap,
5070 state_entry->ucPCIELaneHigh);
5071
5072 return 0;
5073}
5074
5075static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5076 unsigned long entry_index, struct pp_power_state *ps)
5077{
5078 int result;
5079 struct tonga_power_state *tonga_ps;
5080 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5081
5082 struct phm_ppt_v1_information *table_info =
5083 (struct phm_ppt_v1_information *)(hwmgr->pptable);
5084
5085 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5086 table_info->vdd_dep_on_mclk;
5087
5088 ps->hardware.magic = PhwTonga_Magic;
5089
5090 tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
5091
5092 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
5093 tonga_get_pp_table_entry_callback_func);
5094
5095 /* This is the earliest time we have all the dependency table and the VBIOS boot state
5096 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
5097 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
5098 */
5099 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5100 if (dep_mclk_table->entries[0].clk !=
5101 data->vbios_boot_state.mclk_bootup_value)
5102 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5103 "does not match VBIOS boot MCLK level");
5104 if (dep_mclk_table->entries[0].vddci !=
5105 data->vbios_boot_state.vddci_bootup_value)
5106 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5107 "does not match VBIOS boot VDDCI level");
5108 }
5109
5110 /* set DC compatible flag if this state supports DC */
5111 if (!ps->validation.disallowOnDC)
5112 tonga_ps->dc_compatible = true;
5113
5114 if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
5115 data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
5116 else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
5117 if (data->bacos.best_match == 0xffff) {
5118 /* For V.I. use boot state as base BACO state */
5119 data->bacos.best_match = PP_StateClassificationFlag_Boot;
5120 data->bacos.performance_level = tonga_ps->performance_levels[0];
5121 }
5122 }
5123
5124 tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
5125 tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
5126
5127 if (!result) {
5128 uint32_t i;
5129
5130 switch (ps->classification.ui_label) {
5131 case PP_StateUILabel_Performance:
5132 data->use_pcie_performance_levels = true;
5133
5134 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5135 if (data->pcie_gen_performance.max <
5136 tonga_ps->performance_levels[i].pcie_gen)
5137 data->pcie_gen_performance.max =
5138 tonga_ps->performance_levels[i].pcie_gen;
5139
5140 if (data->pcie_gen_performance.min >
5141 tonga_ps->performance_levels[i].pcie_gen)
5142 data->pcie_gen_performance.min =
5143 tonga_ps->performance_levels[i].pcie_gen;
5144
5145 if (data->pcie_lane_performance.max <
5146 tonga_ps->performance_levels[i].pcie_lane)
5147 data->pcie_lane_performance.max =
5148 tonga_ps->performance_levels[i].pcie_lane;
5149
5150 if (data->pcie_lane_performance.min >
5151 tonga_ps->performance_levels[i].pcie_lane)
5152 data->pcie_lane_performance.min =
5153 tonga_ps->performance_levels[i].pcie_lane;
5154 }
5155 break;
5156 case PP_StateUILabel_Battery:
5157 data->use_pcie_power_saving_levels = true;
5158
5159 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5160 if (data->pcie_gen_power_saving.max <
5161 tonga_ps->performance_levels[i].pcie_gen)
5162 data->pcie_gen_power_saving.max =
5163 tonga_ps->performance_levels[i].pcie_gen;
5164
5165 if (data->pcie_gen_power_saving.min >
5166 tonga_ps->performance_levels[i].pcie_gen)
5167 data->pcie_gen_power_saving.min =
5168 tonga_ps->performance_levels[i].pcie_gen;
5169
5170 if (data->pcie_lane_power_saving.max <
5171 tonga_ps->performance_levels[i].pcie_lane)
5172 data->pcie_lane_power_saving.max =
5173 tonga_ps->performance_levels[i].pcie_lane;
5174
5175 if (data->pcie_lane_power_saving.min >
5176 tonga_ps->performance_levels[i].pcie_lane)
5177 data->pcie_lane_power_saving.min =
5178 tonga_ps->performance_levels[i].pcie_lane;
5179 }
5180 break;
5181 default:
5182 break;
5183 }
5184 }
5185 return 0;
5186}
5187
5188static void
5189tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5190{
ab4f4b14 5191 uint32_t sclk, mclk, activity_percent;
9c5f8de6
RZ		 5192 uint32_t offset;
5193 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
c82baa28 5194
5195 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5196
5197 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5198
5199 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5200
5201 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5202 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);
9c5f8de6 5203
9c5f8de6 5204 offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
ab4f4b14
RZ		 5205 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
5206 activity_percent += 0x80;
5207 activity_percent >>= 8;
9c5f8de6 5208
ab4f4b14 5209 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
9c5f8de6 5210
d27d4941
RZ		 5211 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
5212
5213 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
c82baa28 5214}
5215
5216static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
5217{
5218 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5219 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5220 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5221 struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
5222 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5223 struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
5224 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5225 struct PP_Clocks min_clocks = {0};
5226 uint32_t i;
5227 struct cgs_display_info info = {0};
5228
5229 data->need_update_smu7_dpm_table = 0;
5230
5231 for (i = 0; i < psclk_table->count; i++) {
5232 if (sclk == psclk_table->dpm_levels[i].value)
5233 break;
5234 }
5235
5236 if (i >= psclk_table->count)
5237 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5238 else {
5239 /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
5240 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
5241 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
5242 }
5243
5244 for (i=0; i < pmclk_table->count; i++) {
5245 if (mclk == pmclk_table->dpm_levels[i].value)
5246 break;
5247 }
5248
5249 if (i >= pmclk_table->count)
5250 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5251
5252 cgs_get_active_displays_info(hwmgr->device, &info);
5253
5254 if (data->display_timing.num_existing_displays != info.display_count)
5255 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
5256
5257 return 0;
5258}
5259
5260static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
5261{
5262 uint32_t i;
5263 uint32_t sclk, max_sclk = 0;
5264 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5265 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5266
5267 for (i = 0; i < hw_ps->performance_level_count; i++) {
5268 sclk = hw_ps->performance_levels[i].engine_clock;
5269 if (max_sclk < sclk)
5270 max_sclk = sclk;
5271 }
5272
5273 for (i = 0; i < pdpm_table->sclk_table.count; i++) {
5274 if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
5275 return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
5276 pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
5277 pdpm_table->pcie_speed_table.dpm_levels[i].value);
5278 }
5279
5280 return 0;
5281}
5282
5283static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
5284{
5285 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5286 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5287 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5288 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5289
5290 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
5291 uint16_t current_link_speed;
5292
5293 if (data->force_pcie_gen == PP_PCIEGenInvalid)
5294 current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
5295 else
5296 current_link_speed = data->force_pcie_gen;
5297
5298 data->force_pcie_gen = PP_PCIEGenInvalid;
5299 data->pspp_notify_required = false;
5300 if (target_link_speed > current_link_speed) {
5301 switch(target_link_speed) {
5302 case PP_PCIEGen3:
5303 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
5304 break;
5305 data->force_pcie_gen = PP_PCIEGen2;
5306 if (current_link_speed == PP_PCIEGen2)
5307 break;
5308 case PP_PCIEGen2:
5309 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
5310 break;
5311 default:
5312 data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
5313 break;
5314 }
5315 } else {
5316 if (target_link_speed < current_link_speed)
5317 data->pspp_notify_required = true;
5318 }
5319
5320 return 0;
5321}
5322
5323static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5324{
5325 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5326
5327 if (0 == data->need_update_smu7_dpm_table)
5328 return 0;
5329
5330 if ((0 == data->sclk_dpm_key_disabled) &&
5331 (data->need_update_smu7_dpm_table &
5332 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5333 PP_ASSERT_WITH_CODE(
5334 true == tonga_is_dpm_running(hwmgr),
5335 "Trying to freeze SCLK DPM when DPM is disabled",
5336 );
5337 PP_ASSERT_WITH_CODE(
5338 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5339 PPSMC_MSG_SCLKDPM_FreezeLevel),
5340 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
5341 return -1);
5342 }
5343
5344 if ((0 == data->mclk_dpm_key_disabled) &&
5345 (data->need_update_smu7_dpm_table &
5346 DPMTABLE_OD_UPDATE_MCLK)) {
5347 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5348 "Trying to freeze MCLK DPM when DPM is disabled",
5349 );
5350 PP_ASSERT_WITH_CODE(
5351 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5352 PPSMC_MSG_MCLKDPM_FreezeLevel),
5353 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
5354 return -1);
5355 }
5356
5357 return 0;
5358}
5359
5360static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
5361{
5362 int result = 0;
5363
5364 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5365 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5366 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5367 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5368 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5369 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5370
5371 struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
5372 uint32_t dpm_count, clock_percent;
5373 uint32_t i;
5374
5375 if (0 == data->need_update_smu7_dpm_table)
5376 return 0;
5377
5378 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
5379 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
5380
5381 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5382 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5383 /* Need to do calculation based on the golden DPM table
5384 * as the Heatmap GPU Clock axis is also based on the default values
5385 */
5386 PP_ASSERT_WITH_CODE(
5387 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
5388 "Divide by 0!",
5389 return -1);
5390 dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
5391 for (i = dpm_count; i > 1; i--) {
5392 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
5393 clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
5394 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5395
5396 pdpm_table->sclk_table.dpm_levels[i].value =
5397 pgolden_dpm_table->sclk_table.dpm_levels[i].value +
5398 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5399
5400 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
5401 clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
5402 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5403
5404 pdpm_table->sclk_table.dpm_levels[i].value =
5405 pgolden_dpm_table->sclk_table.dpm_levels[i].value -
5406 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5407 } else
5408 pdpm_table->sclk_table.dpm_levels[i].value =
5409 pgolden_dpm_table->sclk_table.dpm_levels[i].value;
5410 }
5411 }
5412 }
5413
5414 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
5415 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
5416
5417 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5418 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5419
5420 PP_ASSERT_WITH_CODE(
5421 (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
5422 "Divide by 0!",
5423 return -1);
5424 dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
5425 for (i = dpm_count; i > 1; i--) {
5426 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
5427 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
5428 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5429
5430 pdpm_table->mclk_table.dpm_levels[i].value =
5431 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
5432 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5433
5434 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
5435 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
5436 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5437
5438 pdpm_table->mclk_table.dpm_levels[i].value =
5439 pgolden_dpm_table->mclk_table.dpm_levels[i].value -
5440 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5441 } else
5442 pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
5443 }
5444 }
5445 }
5446
5447 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
5448 result = tonga_populate_all_memory_levels(hwmgr);
5449 PP_ASSERT_WITH_CODE((0 == result),
5450 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
5451 return result);
5452 }
5453
5454 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
5455 /*populate MCLK dpm table to SMU7 */
5456 result = tonga_populate_all_memory_levels(hwmgr);
5457 PP_ASSERT_WITH_CODE((0 == result),
5458 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
5459 return result);
5460 }
5461
5462 return result;
5463}
5464
5465static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
5466 struct tonga_single_dpm_table * pdpm_table,
5467 uint32_t low_limit, uint32_t high_limit)
5468{
5469 uint32_t i;
5470
5471 for (i = 0; i < pdpm_table->count; i++) {
5472 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
5473 (pdpm_table->dpm_levels[i].value > high_limit))
5474 pdpm_table->dpm_levels[i].enabled = false;
5475 else
5476 pdpm_table->dpm_levels[i].enabled = true;
5477 }
5478 return 0;
5479}
5480
5481static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
5482{
5483 int result = 0;
5484 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5485 uint32_t high_limit_count;
5486
5487 PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
5488 "power state did not have any performance level",
5489 return -1);
5490
5491 high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
5492
5493 tonga_trim_single_dpm_states(hwmgr,
5494 &(data->dpm_table.sclk_table),
5495 hw_state->performance_levels[0].engine_clock,
5496 hw_state->performance_levels[high_limit_count].engine_clock);
5497
5498 tonga_trim_single_dpm_states(hwmgr,
5499 &(data->dpm_table.mclk_table),
5500 hw_state->performance_levels[0].memory_clock,
5501 hw_state->performance_levels[high_limit_count].memory_clock);
5502
5503 return result;
5504}
5505
5506static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
5507{
5508 int result;
5509 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5510 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5511 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5512
c82baa28 5513 result = tonga_trim_dpm_states(hwmgr, tonga_ps);
5514 if (0 != result)
5515 return result;
5516
5517 data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
5518 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
5519 data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
5520 if (data->uvd_enabled)
5521 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
5522
5523 data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
5524
5525 return 0;
5526}
5527
0859ed3d 5528int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
c82baa28 5529{
0859ed3d 5530 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
c82baa28 5531 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
5532 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
5533}
5534
0859ed3d
RZ		 5535int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
5536{
5537 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5538 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
5539 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
5540}
5541
5542int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
5543{
5544 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5545 uint32_t mm_boot_level_offset, mm_boot_level_value;
5546 struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5547
5548 if (!bgate) {
5549 data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
5550 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
5551 mm_boot_level_offset /= 4;
5552 mm_boot_level_offset *= 4;
5553 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5554 mm_boot_level_value &= 0x00FFFFFF;
5555 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
5556 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5557
5558 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
5559 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5560 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5561 PPSMC_MSG_UVDDPM_SetEnabledMask,
5562 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
5563 }
5564
5565 return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
5566}
5567
5568int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
c82baa28 5569{
5570 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5571 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5572 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5573 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5574
5575 uint32_t mm_boot_level_offset, mm_boot_level_value;
5576 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5577
0859ed3d 5578 if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
c82baa28 5579 data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
5580
5581 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
5582 mm_boot_level_offset /= 4;
5583 mm_boot_level_offset *= 4;
5584 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5585 mm_boot_level_value &= 0xFF00FFFF;
5586 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
5587 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5588
0859ed3d
RZ		 5589 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5590 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5591 PPSMC_MSG_VCEDPM_SetEnabledMask,
5592 (uint32_t)(1 << data->smc_state_table.VceBootLevel));
c82baa28 5593
0859ed3d
RZ		 5594 tonga_enable_disable_vce_dpm(hwmgr, true);
5595 } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
5596 tonga_enable_disable_vce_dpm(hwmgr, false);
c82baa28 5597
5598 return 0;
5599}
5600
5601static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
5602{
5603 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5604
5605 uint32_t address;
5606 int32_t result;
5607
5608 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
5609 return 0;
5610
5611
5612 memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
5613
5614 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
5615
5616 if(result != 0)
5617 return result;
5618
5619
5620 address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
5621
5622 return tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
5623 (uint8_t *)&data->mc_reg_table.data[0],
5624 sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
5625 data->sram_end);
5626}
5627
5628static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
5629{
5630 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5631
5632 if (data->need_update_smu7_dpm_table &
5633 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
5634 return tonga_program_memory_timing_parameters(hwmgr);
5635
5636 return 0;
5637}
5638
5639static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5640{
5641 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5642
5643 if (0 == data->need_update_smu7_dpm_table)
5644 return 0;
5645
5646 if ((0 == data->sclk_dpm_key_disabled) &&
5647 (data->need_update_smu7_dpm_table &
5648 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5649
5650 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5651 "Trying to Unfreeze SCLK DPM when DPM is disabled",
5652 );
5653 PP_ASSERT_WITH_CODE(
5654 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5655 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5656 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
5657 return -1);
5658 }
5659
5660 if ((0 == data->mclk_dpm_key_disabled) &&
5661 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5662
5663 PP_ASSERT_WITH_CODE(
5664 true == tonga_is_dpm_running(hwmgr),
5665 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5666 );
5667 PP_ASSERT_WITH_CODE(
5668 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5669 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5670 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
5671 return -1);
5672 }
5673
5674 data->need_update_smu7_dpm_table = 0;
5675
5676 return 0;
5677}
5678
5679static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
5680{
5681 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5682 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5683 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5684 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
5685 uint8_t request;
5686
5687 if (data->pspp_notify_required ||
5688 data->pcie_performance_request) {
5689 if (target_link_speed == PP_PCIEGen3)
5690 request = PCIE_PERF_REQ_GEN3;
5691 else if (target_link_speed == PP_PCIEGen2)
5692 request = PCIE_PERF_REQ_GEN2;
5693 else
5694 request = PCIE_PERF_REQ_GEN1;
5695
5696 if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
5697 data->pcie_performance_request = false;
5698 return 0;
5699 }
5700
5701 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
5702 if (PP_PCIEGen2 == target_link_speed)
5703 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
5704 else
5705 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
5706 }
5707 }
5708
5709 data->pcie_performance_request = false;
5710 return 0;
5711}
5712
5713static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
5714{
5715 int tmp_result, result = 0;
5716
5717 tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
5718 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
5719
5720 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5721 tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
5722 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
5723 }
5724
5725 tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
5726 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
5727
5728 tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
5729 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
5730
5731 tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
5732 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
5733
5734 tmp_result = tonga_update_vce_dpm(hwmgr, input);
5735 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
5736
5737 tmp_result = tonga_update_sclk_threshold(hwmgr);
5738 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
5739
5740 tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
5741 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
5742
5743 tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
5744 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
5745
5746 tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
5747 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
5748
5749 tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
5750 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
5751
5752 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5753 tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
5754 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
5755 }
5756
5757 return result;
5758}
5759
1e4854e9
RZ		 5760/**
5761* Set maximum target operating fan output PWM
5762*
5763* @param pHwMgr: the address of the powerplay hardware manager.
5764* @param usMaxFanPwm: max operating fan PWM in percents
5765* @return The response that came from the SMC.
5766*/
5767static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5768{
5769 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5770
5771 if (phm_is_hw_access_blocked(hwmgr))
5772 return 0;
5773
c15c8d70 5774 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1);
1e4854e9 5775}
bbb207f3
RZ		 5776
5777int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5778{
5779 uint32_t num_active_displays = 0;
5780 struct cgs_display_info info = {0};
5781 info.mode_info = NULL;
5782
5783 cgs_get_active_displays_info(hwmgr->device, &info);
5784
5785 num_active_displays = info.display_count;
5786
5787 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5788 tonga_notify_smc_display_change(hwmgr, false);
5789 else
5790 tonga_notify_smc_display_change(hwmgr, true);
5791
5792 return 0;
5793}
5794
5795/**
5796* Programs the display gap
5797*
5798* @param hwmgr the address of the powerplay hardware manager.
5799* @return always OK
5800*/
5801int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
5802{
5803 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5804 uint32_t num_active_displays = 0;
5805 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5806 uint32_t display_gap2;
5807 uint32_t pre_vbi_time_in_us;
5808 uint32_t frame_time_in_us;
5809 uint32_t ref_clock;
5810 uint32_t refresh_rate = 0;
5811 struct cgs_display_info info = {0};
5812 struct cgs_mode_info mode_info;
5813
5814 info.mode_info = &mode_info;
5815
5816 cgs_get_active_displays_info(hwmgr->device, &info);
5817 num_active_displays = info.display_count;
5818
5819 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5820 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5821
5822 ref_clock = mode_info.ref_clock;
5823 refresh_rate = mode_info.refresh_rate;
5824
5825 if(0 == refresh_rate)
5826 refresh_rate = 60;
5827
5828 frame_time_in_us = 1000000 / refresh_rate;
5829
5830 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5831 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5832
5833 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5834
5835 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
5836
5837 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
5838
5839 if (num_active_displays == 1)
5840 tonga_notify_smc_display_change(hwmgr, true);
5841
5842 return 0;
5843}
5844
5845int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5846{
5847
5848 tonga_program_display_gap(hwmgr);
5849
5850 /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
5851 return 0;
5852}
5853
1e4854e9
RZ		 5854/**
5855* Set maximum target operating fan output RPM
5856*
5857* @param pHwMgr: the address of the powerplay hardware manager.
5858* @param usMaxFanRpm: max operating fan RPM value.
5859* @return The response that came from the SMC.
5860*/
5861static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5862{
5863 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5864
5865 if (phm_is_hw_access_blocked(hwmgr))
5866 return 0;
5867
c15c8d70 5868 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1);
1e4854e9
RZ		 5869}
5870
5871uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
5872{
5873 uint32_t reference_clock;
5874 uint32_t tc;
5875 uint32_t divide;
5876
5877 ATOM_FIRMWARE_INFO *fw_info;
5878 uint16_t size;
5879 uint8_t frev, crev;
5880 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5881
5882 tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5883
5884 if (tc)
5885 return TCLK;
5886
5887 fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5888 &size, &frev, &crev);
5889
5890 if (!fw_info)
5891 return 0;
5892
dcf799e5 5893 reference_clock = le16_to_cpu(fw_info->usReferenceClock);
1e4854e9
RZ		 5894
5895 divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5896
5897 if (0 != divide)
5898 return reference_clock / 4;
5899
5900 return reference_clock;
5901}
5902
5903int tonga_dpm_set_interrupt_state(void *private_data,
5904 unsigned src_id, unsigned type,
5905 int enabled)
5906{
5907 uint32_t cg_thermal_int;
5908 struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5909
5910 if (hwmgr == NULL)
5911 return -EINVAL;
5912
5913 switch (type) {
5914 case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5915 if (enabled) {
5916 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5917 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5918 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5919 } else {
5920 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5921 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5922 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5923 }
5924 break;
5925
5926 case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5927 if (enabled) {
5928 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5929 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5930 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5931 } else {
5932 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5933 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5934 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5935 }
5936 break;
5937 default:
5938 break;
5939 }
5940 return 0;
5941}
5942
5943int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5944 const void *thermal_interrupt_info)
5945{
5946 int result;
5947 const struct pp_interrupt_registration_info *info =
5948 (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5949
5950 if (info == NULL)
5951 return -EINVAL;
5952
5953 result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5954 tonga_dpm_set_interrupt_state,
5955 info->call_back, info->context);
5956
5957 if (result)
5958 return -EINVAL;
5959
5960 result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5961 tonga_dpm_set_interrupt_state,
5962 info->call_back, info->context);
5963
5964 if (result)
5965 return -EINVAL;
5966
5967 return 0;
5968}
5969
e829ecdb
RZ		 5970bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5971{
5972 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5973 bool is_update_required = false;
5974 struct cgs_display_info info = {0,0,NULL};
5975
5976 cgs_get_active_displays_info(hwmgr->device, &info);
5977
5978 if (data->display_timing.num_existing_displays != info.display_count)
5979 is_update_required = true;
5980/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5981 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5982 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5983 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5984 is_update_required = true;
5985*/
5986 return is_update_required;
5987}
5988
5989static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
5990 const struct tonga_performance_level *pl2)
5991{
5992 return ((pl1->memory_clock == pl2->memory_clock) &&
5993 (pl1->engine_clock == pl2->engine_clock) &&
5994 (pl1->pcie_gen == pl2->pcie_gen) &&
5995 (pl1->pcie_lane == pl2->pcie_lane));
5996}
5997
5998int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5999{
6000 const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
6001 const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
6002 int i;
6003
c15c8d70 6004 if (equal == NULL || psa == NULL || psb == NULL)
e829ecdb
RZ		 6005 return -EINVAL;
6006
6007 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
6008 if (psa->performance_level_count != psb->performance_level_count) {
6009 *equal = false;
6010 return 0;
6011 }
6012
6013 for (i = 0; i < psa->performance_level_count; i++) {
6014 if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
6015 /* If we have found even one performance level pair that is different the states are different. */
6016 *equal = false;
6017 return 0;
6018 }
6019 }
6020
6021 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6022 *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
6023 *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
6024 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
6025 *equal &= (psa->acp_clk == psb->acp_clk);
6026
6027 return 0;
6028}
6029
9dcfc193
EH		 6030static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
6031{
6032 if (mode) {
6033 /* stop auto-manage */
6034 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
6035 PHM_PlatformCaps_MicrocodeFanControl))
6036 tonga_fan_ctrl_stop_smc_fan_control(hwmgr);
6037 tonga_fan_ctrl_set_static_mode(hwmgr, mode);
6038 } else
6039 /* restart auto-manage */
6040 tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr);
6041
6042 return 0;
6043}
6044
6045static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr)
6046{
6047 if (hwmgr->fan_ctrl_is_in_default_mode)
6048 return hwmgr->fan_ctrl_default_mode;
6049 else
6050 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
6051 CG_FDO_CTRL2, FDO_PWM_MODE);
6052}
6053
5d37a63d
EH		 6054static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
6055{
6056 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6057
92dea67d
EH		 6058 if (!data->soft_pp_table) {
6059 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
6060 if (!data->soft_pp_table)
6061 return -ENOMEM;
6062 memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
6063 hwmgr->soft_pp_table_size);
6064 }
6065
6066 *table = (char *)&data->soft_pp_table;
5d37a63d 6067
92dea67d 6068 return hwmgr->soft_pp_table_size;
5d37a63d
EH		 6069}
6070
6071static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
6072{
6073 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6074
92dea67d
EH		 6075 if (!data->soft_pp_table) {
6076 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
6077 if (!data->soft_pp_table)
6078 return -ENOMEM;
6079 }
6080
6081 memcpy(data->soft_pp_table, buf, size);
6082
6083 hwmgr->soft_pp_table = data->soft_pp_table;
5d37a63d 6084
92dea67d 6085 /* TODO: re-init powerplay to implement modified pptable */
5d37a63d
EH		 6086
6087 return 0;
6088}
6089
6090static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
5632708f 6091 enum pp_clock_type type, uint32_t mask)
5d37a63d
EH		 6092{
6093 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6094
6095 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
6096 return -EINVAL;
6097
6098 switch (type) {
6099 case PP_SCLK:
6100 if (!data->sclk_dpm_key_disabled)
6101 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6102 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5632708f 6103 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5d37a63d
EH		 6104 break;
6105 case PP_MCLK:
6106 if (!data->mclk_dpm_key_disabled)
6107 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6108 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5632708f 6109 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5d37a63d
EH		 6110 break;
6111 case PP_PCIE:
5632708f
EH		 6112 {
6113 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
6114 uint32_t level = 0;
6115
6116 while (tmp >>= 1)
6117 level++;
6118
5d37a63d
EH		 6119 if (!data->pcie_dpm_key_disabled)
6120 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6121 PPSMC_MSG_PCIeDPM_ForceLevel,
5632708f 6122 level);
5d37a63d 6123 break;
5632708f 6124 }
5d37a63d
EH		 6125 default:
6126 break;
6127 }
6128
6129 return 0;
6130}
6131
6132static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr,
6133 enum pp_clock_type type, char *buf)
6134{
6135 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6136 struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
6137 struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
6138 struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
6139 int i, now, size = 0;
6140 uint32_t clock, pcie_speed;
6141
6142 switch (type) {
6143 case PP_SCLK:
6144 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
6145 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6146
6147 for (i = 0; i < sclk_table->count; i++) {
6148 if (clock > sclk_table->dpm_levels[i].value)
6149 continue;
6150 break;
6151 }
6152 now = i;
6153
6154 for (i = 0; i < sclk_table->count; i++)
6155 size += sprintf(buf + size, "%d: %uMhz %s\n",
6156 i, sclk_table->dpm_levels[i].value / 100,
6157 (i == now) ? "*" : "");
6158 break;
6159 case PP_MCLK:
6160 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
6161 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6162
6163 for (i = 0; i < mclk_table->count; i++) {
6164 if (clock > mclk_table->dpm_levels[i].value)
6165 continue;
6166 break;
6167 }
6168 now = i;
6169
6170 for (i = 0; i < mclk_table->count; i++)
6171 size += sprintf(buf + size, "%d: %uMhz %s\n",
6172 i, mclk_table->dpm_levels[i].value / 100,
6173 (i == now) ? "*" : "");
6174 break;
6175 case PP_PCIE:
6176 pcie_speed = tonga_get_current_pcie_speed(hwmgr);
6177 for (i = 0; i < pcie_table->count; i++) {
6178 if (pcie_speed != pcie_table->dpm_levels[i].value)
6179 continue;
6180 break;
6181 }
6182 now = i;
6183
6184 for (i = 0; i < pcie_table->count; i++)
6185 size += sprintf(buf + size, "%d: %s %s\n", i,
6186 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
6187 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6188 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6189 (i == now) ? "*" : "");
6190 break;
6191 default:
6192 break;
6193 }
6194 return size;
6195}
6196
c82baa28 6197static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
6198 .backend_init = &tonga_hwmgr_backend_init,
6199 .backend_fini = &tonga_hwmgr_backend_fini,
6200 .asic_setup = &tonga_setup_asic_task,
6201 .dynamic_state_management_enable = &tonga_enable_dpm_tasks,
6202 .apply_state_adjust_rules = tonga_apply_state_adjust_rules,
6203 .force_dpm_level = &tonga_force_dpm_level,
6204 .power_state_set = tonga_set_power_state_tasks,
6205 .get_power_state_size = tonga_get_power_state_size,
6206 .get_mclk = tonga_dpm_get_mclk,
6207 .get_sclk = tonga_dpm_get_sclk,
6208 .patch_boot_state = tonga_dpm_patch_boot_state,
6209 .get_pp_table_entry = tonga_get_pp_table_entry,
6210 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
6211 .print_current_perforce_level = tonga_print_current_perforce_level,
0859ed3d
RZ		 6212 .powerdown_uvd = tonga_phm_powerdown_uvd,
6213 .powergate_uvd = tonga_phm_powergate_uvd,
6214 .powergate_vce = tonga_phm_powergate_vce,
6215 .disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
ce90dbd9 6216 .update_clock_gatings = tonga_phm_update_clock_gatings,
bbb207f3
RZ		 6217 .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
6218 .display_config_changed = tonga_display_configuration_changed_task,
1e4854e9
RZ		 6219 .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
6220 .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
6221 .get_temperature = tonga_thermal_get_temperature,
6222 .stop_thermal_controller = tonga_thermal_stop_thermal_controller,
6223 .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
6224 .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
6225 .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
6226 .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
6227 .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
6228 .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
6229 .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
6230 .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
e829ecdb
RZ		 6231 .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
6232 .check_states_equal = tonga_check_states_equal,
9dcfc193
EH		 6233 .set_fan_control_mode = tonga_set_fan_control_mode,
6234 .get_fan_control_mode = tonga_get_fan_control_mode,
5d37a63d
EH		 6235 .get_pp_table = tonga_get_pp_table,
6236 .set_pp_table = tonga_set_pp_table,
6237 .force_clock_level = tonga_force_clock_level,
6238 .print_clock_levels = tonga_print_clock_levels,
c82baa28 6239};
6240
6241int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
6242{
6243 tonga_hwmgr *data;
6244
6245 data = kzalloc (sizeof(tonga_hwmgr), GFP_KERNEL);
6246 if (data == NULL)
6247 return -ENOMEM;
6248 memset(data, 0x00, sizeof(tonga_hwmgr));
6249
6250 hwmgr->backend = data;
6251 hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
6252 hwmgr->pptable_func = &tonga_pptable_funcs;
1e4854e9 6253 pp_tonga_thermal_initialize(hwmgr);
c82baa28 6254 return 0;
6255}
6256
Linux 6.x block layer and io_uring tree(s)