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1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #ifndef _SMU_HELPER_H_ | |
24 | #define _SMU_HELPER_H_ | |
25 | ||
26 | struct pp_atomctrl_voltage_table; | |
27 | struct pp_hwmgr; | |
28 | struct phm_ppt_v1_voltage_lookup_table; | |
63c2f7ed RZ |
29 | struct Watermarks_t; |
30 | struct pp_wm_sets_with_clock_ranges_soc15; | |
8e686279 | 31 | |
09695ad7 RZ |
32 | uint8_t convert_to_vid(uint16_t vddc); |
33 | uint16_t convert_to_vddc(uint8_t vid); | |
34 | ||
63c2f7ed RZ |
35 | struct watermark_row_generic_t { |
36 | uint16_t MinClock; | |
37 | uint16_t MaxClock; | |
38 | uint16_t MinUclk; | |
39 | uint16_t MaxUclk; | |
40 | ||
41 | uint8_t WmSetting; | |
42 | uint8_t Padding[3]; | |
43 | }; | |
44 | ||
45 | struct watermarks { | |
46 | struct watermark_row_generic_t WatermarkRow[2][4]; | |
47 | uint32_t padding[7]; | |
48 | }; | |
49 | ||
a553c19d AD |
50 | int phm_copy_clock_limits_array( |
51 | struct pp_hwmgr *hwmgr, | |
52 | uint32_t **pptable_info_array, | |
53 | const uint32_t *pptable_array, | |
54 | uint32_t power_saving_clock_count); | |
55 | ||
56 | int phm_copy_overdrive_settings_limits_array( | |
57 | struct pp_hwmgr *hwmgr, | |
58 | uint32_t **pptable_info_array, | |
59 | const uint32_t *pptable_array, | |
60 | uint32_t od_setting_count); | |
61 | ||
8e686279 RZ |
62 | extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, |
63 | uint32_t index, | |
64 | uint32_t value, uint32_t mask); | |
65 | extern int phm_wait_for_indirect_register_unequal( | |
66 | struct pp_hwmgr *hwmgr, | |
67 | uint32_t indirect_port, uint32_t index, | |
68 | uint32_t value, uint32_t mask); | |
69 | ||
70 | ||
71 | extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr); | |
72 | extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr); | |
73 | extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr); | |
74 | ||
75 | extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table); | |
76 | extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); | |
77 | extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); | |
78 | extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table); | |
79 | extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table); | |
80 | extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max); | |
81 | extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes); | |
82 | extern int32_t phm_get_dpm_level_enable_mask_value(void *table); | |
83 | extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table, | |
84 | uint32_t voltage); | |
85 | extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage); | |
86 | extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci); | |
87 | extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); | |
88 | extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, | |
89 | uint16_t virtual_voltage_id, int32_t *sclk); | |
90 | extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); | |
91 | extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); | |
92 | extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); | |
93 | ||
94 | extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, | |
95 | uint32_t sclk, uint16_t id, uint16_t *voltage); | |
96 | ||
97 | extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size); | |
98 | ||
99 | extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, | |
100 | uint32_t value, uint32_t mask); | |
101 | ||
102 | extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, | |
103 | uint32_t indirect_port, | |
104 | uint32_t index, | |
105 | uint32_t value, | |
106 | uint32_t mask); | |
107 | ||
160b8e75 RZ |
108 | int phm_irq_process(struct amdgpu_device *adev, |
109 | struct amdgpu_irq_src *source, | |
110 | struct amdgpu_iv_entry *entry); | |
111 | ||
4d200372 | 112 | int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr); |
160b8e75 | 113 | |
b3892e2b RZ |
114 | void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, |
115 | uint8_t *frev, uint8_t *crev); | |
116 | ||
63c2f7ed RZ |
117 | int smu_get_voltage_dependency_table_ppt_v1( |
118 | const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table, | |
119 | struct phm_ppt_v1_clock_voltage_dependency_table *dep_table); | |
120 | ||
121 | int smu_set_watermarks_for_clocks_ranges(void *wt_table, | |
20582319 | 122 | struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); |
63c2f7ed | 123 | |
8e686279 RZ |
124 | #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT |
125 | #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK | |
126 | ||
127 | #define PHM_SET_FIELD(origval, reg, field, fieldval) \ | |
128 | (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ | |
129 | (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) | |
130 | ||
131 | #define PHM_GET_FIELD(value, reg, field) \ | |
132 | (((value) & PHM_FIELD_MASK(reg, field)) >> \ | |
133 | PHM_FIELD_SHIFT(reg, field)) | |
134 | ||
135 | ||
136 | /* Operations on named fields. */ | |
137 | ||
138 | #define PHM_READ_FIELD(device, reg, field) \ | |
139 | PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) | |
140 | ||
141 | #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \ | |
142 | PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
143 | reg, field) | |
144 | ||
145 | #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ | |
146 | PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
147 | reg, field) | |
148 | ||
149 | #define PHM_WRITE_FIELD(device, reg, field, fieldval) \ | |
150 | cgs_write_register(device, mm##reg, PHM_SET_FIELD( \ | |
151 | cgs_read_register(device, mm##reg), reg, field, fieldval)) | |
152 | ||
153 | #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ | |
154 | cgs_write_ind_register(device, port, ix##reg, \ | |
155 | PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
156 | reg, field, fieldval)) | |
157 | ||
158 | #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ | |
159 | cgs_write_ind_register(device, port, ix##reg, \ | |
160 | PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
161 | reg, field, fieldval)) | |
162 | ||
163 | #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ | |
164 | phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask) | |
165 | ||
166 | ||
167 | #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ | |
168 | PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
169 | ||
170 | #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ | |
171 | PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ | |
172 | << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) | |
173 | ||
174 | #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ | |
175 | phm_wait_for_indirect_register_unequal(hwmgr, \ | |
176 | mm##port##_INDEX, index, value, mask) | |
177 | ||
178 | #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ | |
179 | PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
180 | ||
181 | #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ | |
182 | PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ | |
183 | (fieldval) << PHM_FIELD_SHIFT(reg, field), \ | |
184 | PHM_FIELD_MASK(reg, field) ) | |
185 | ||
186 | ||
187 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ | |
188 | port, index, value, mask) \ | |
189 | phm_wait_for_indirect_register_unequal(hwmgr, \ | |
190 | mm##port##_INDEX_11, index, value, mask) | |
191 | ||
192 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ | |
193 | PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
194 | ||
195 | #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ | |
196 | PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ | |
197 | (fieldval) << PHM_FIELD_SHIFT(reg, field), \ | |
198 | PHM_FIELD_MASK(reg, field)) | |
199 | ||
200 | ||
201 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \ | |
202 | port, index, value, mask) \ | |
203 | phm_wait_on_indirect_register(hwmgr, \ | |
204 | mm##port##_INDEX_11, index, value, mask) | |
205 | ||
206 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ | |
207 | PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
208 | ||
209 | #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ | |
210 | PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \ | |
211 | (fieldval) << PHM_FIELD_SHIFT(reg, field), \ | |
212 | PHM_FIELD_MASK(reg, field)) | |
213 | ||
214 | #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ | |
215 | index, value, mask) \ | |
216 | phm_wait_for_register_unequal(hwmgr, \ | |
217 | index, value, mask) | |
218 | ||
219 | #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ | |
220 | PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ | |
221 | mm##reg, value, mask) | |
222 | ||
223 | #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ | |
224 | PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \ | |
225 | (fieldval) << PHM_FIELD_SHIFT(reg, field), \ | |
226 | PHM_FIELD_MASK(reg, field)) | |
227 | ||
228 | #endif /* _SMU_HELPER_H_ */ |