[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / ppatomfwctrl.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef PP_ATOMFWCTRL_H
#define PP_ATOMFWCTRL_H

#include "hwmgr.h"

typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;

#define GetIndexIntoMasterCmdTable(FieldName) \
	(((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
#define GetIndexIntoMasterDataTable(FieldName) \
	(((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))

#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32

struct pp_atomfwctrl_voltage_table_entry {
	uint16_t value;
	uint32_t  smio_low;
};

struct pp_atomfwctrl_voltage_table {
	uint32_t count;
	uint32_t mask_low;
	uint32_t phase_delay;
	uint8_t psi0_enable;
	uint8_t psi1_enable;
	uint8_t max_vid_step;
	uint8_t telemetry_offset;
	uint8_t telemetry_slope;
	struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
};

struct pp_atomfwctrl_gpio_pin_assignment {
	uint16_t us_gpio_pin_aindex;
	uint8_t uc_gpio_pin_bit_shift;
};

struct pp_atomfwctrl_clock_dividers_soc15 {
	uint32_t   ulClock;           /* the actual clock */
	uint32_t   ulDid;             /* DFS divider */
	uint32_t   ulPll_fb_mult;     /* Feedback Multiplier:  bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
	uint32_t   ulPll_ss_fbsmult;  /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
	uint16_t   usPll_ss_slew_frac;
	uint8_t    ucPll_ss_enable;
	uint8_t    ucReserve;
	uint32_t   ulReserve[2];
};

struct pp_atomfwctrl_avfs_parameters {
	uint32_t   ulMaxVddc;
	uint32_t   ulMinVddc;

	uint32_t   ulMeanNsigmaAcontant0;
	uint32_t   ulMeanNsigmaAcontant1;
	uint32_t   ulMeanNsigmaAcontant2;
	uint16_t   usMeanNsigmaDcTolSigma;
	uint16_t   usMeanNsigmaPlatformMean;
	uint16_t   usMeanNsigmaPlatformSigma;
	uint32_t   ulGbVdroopTableCksoffA0;
	uint32_t   ulGbVdroopTableCksoffA1;
	uint32_t   ulGbVdroopTableCksoffA2;
	uint32_t   ulGbVdroopTableCksonA0;
	uint32_t   ulGbVdroopTableCksonA1;
	uint32_t   ulGbVdroopTableCksonA2;

	uint32_t   ulGbFuseTableCksoffM1;
	uint32_t   ulGbFuseTableCksoffM2;
	uint32_t   ulGbFuseTableCksoffB;

	uint32_t   ulGbFuseTableCksonM1;
	uint32_t   ulGbFuseTableCksonM2;
	uint32_t   ulGbFuseTableCksonB;

	uint8_t    ucEnableGbVdroopTableCkson;
	uint8_t    ucEnableGbFuseTableCkson;
	uint16_t   usPsmAgeComfactor;

	uint32_t   ulDispclk2GfxclkM1;
	uint32_t   ulDispclk2GfxclkM2;
	uint32_t   ulDispclk2GfxclkB;
	uint32_t   ulDcefclk2GfxclkM1;
	uint32_t   ulDcefclk2GfxclkM2;
	uint32_t   ulDcefclk2GfxclkB;
	uint32_t   ulPixelclk2GfxclkM1;
	uint32_t   ulPixelclk2GfxclkM2;
	uint32_t   ulPixelclk2GfxclkB;
	uint32_t   ulPhyclk2GfxclkM1;
	uint32_t   ulPhyclk2GfxclkM2;
	uint32_t   ulPhyclk2GfxclkB;
	uint32_t   ulAcgGbVdroopTableA0;
	uint32_t   ulAcgGbVdroopTableA1;
	uint32_t   ulAcgGbVdroopTableA2;
	uint32_t   ulAcgGbFuseTableM1;
	uint32_t   ulAcgGbFuseTableM2;
	uint32_t   ulAcgGbFuseTableB;
	uint32_t   ucAcgEnableGbVdroopTable;
	uint32_t   ucAcgEnableGbFuseTable;
};

struct pp_atomfwctrl_gpio_parameters {
	uint8_t   ucAcDcGpio;
	uint8_t   ucAcDcPolarity;
	uint8_t   ucVR0HotGpio;
	uint8_t   ucVR0HotPolarity;
	uint8_t   ucVR1HotGpio;
	uint8_t   ucVR1HotPolarity;
	uint8_t   ucFwCtfGpio;
	uint8_t   ucFwCtfPolarity;
};

struct pp_atomfwctrl_bios_boot_up_values {
	uint32_t   ulRevision;
	uint32_t   ulGfxClk;
	uint32_t   ulUClk;
	uint32_t   ulSocClk;
	uint32_t   ulDCEFClk;
	uint16_t   usVddc;
	uint16_t   usVddci;
	uint16_t   usMvddc;
	uint16_t   usVddGfx;
};

int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
		uint32_t clock_type, uint32_t clock_value,
		struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
		struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);

int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
		uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
		uint8_t voltage_type, uint8_t voltage_mode);

int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
		struct pp_atomfwctrl_avfs_parameters *param);
int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
		struct pp_atomfwctrl_gpio_parameters *param);

int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
			struct pp_atomfwctrl_bios_boot_up_values *boot_values);

#endif
Commit	Line	Data
0d2c7569 EH	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef PP_ATOMFWCTRL_H
	25	#define PP_ATOMFWCTRL_H
	26
	27	#include "hwmgr.h"
	28
c5b053d2 RZ	29	typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
c5b053d2 RZ	30
0d2c7569 EH	31	#define GetIndexIntoMasterCmdTable(FieldName) \
	32	(((char)(&((struct atom_master_list_of_command_functions_v2_1)0)->FieldName)-(char*)0)/sizeof(uint16_t))
	33	#define GetIndexIntoMasterDataTable(FieldName) \
	34	(((char)(&((struct atom_master_list_of_data_tables_v2_1)0)->FieldName)-(char*)0)/sizeof(uint16_t))
	35
	36	#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
	37
	38	struct pp_atomfwctrl_voltage_table_entry {
	39	uint16_t value;
	40	uint32_t smio_low;
	41	};
	42
	43	struct pp_atomfwctrl_voltage_table {
	44	uint32_t count;
	45	uint32_t mask_low;
	46	uint32_t phase_delay;
	47	uint8_t psi0_enable;
	48	uint8_t psi1_enable;
	49	uint8_t max_vid_step;
	50	uint8_t telemetry_offset;
	51	uint8_t telemetry_slope;
	52	struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
	53	};
	54
	55	struct pp_atomfwctrl_gpio_pin_assignment {
	56	uint16_t us_gpio_pin_aindex;
	57	uint8_t uc_gpio_pin_bit_shift;
	58	};
	59
	60	struct pp_atomfwctrl_clock_dividers_soc15 {
	61	uint32_t ulClock; /* the actual clock */
	62	uint32_t ulDid; /* DFS divider */
	63	uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
	64	uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
	65	uint16_t usPll_ss_slew_frac;
	66	uint8_t ucPll_ss_enable;
	67	uint8_t ucReserve;
	68	uint32_t ulReserve[2];
	69	};
	70
	71	struct pp_atomfwctrl_avfs_parameters {
	72	uint32_t ulMaxVddc;
	73	uint32_t ulMinVddc;
6524e494	74
0d2c7569 EH	75	uint32_t ulMeanNsigmaAcontant0;
	76	uint32_t ulMeanNsigmaAcontant1;
	77	uint32_t ulMeanNsigmaAcontant2;
	78	uint16_t usMeanNsigmaDcTolSigma;
	79	uint16_t usMeanNsigmaPlatformMean;
	80	uint16_t usMeanNsigmaPlatformSigma;
	81	uint32_t ulGbVdroopTableCksoffA0;
	82	uint32_t ulGbVdroopTableCksoffA1;
	83	uint32_t ulGbVdroopTableCksoffA2;
	84	uint32_t ulGbVdroopTableCksonA0;
	85	uint32_t ulGbVdroopTableCksonA1;
	86	uint32_t ulGbVdroopTableCksonA2;
6524e494	87
0d2c7569	88	uint32_t ulGbFuseTableCksoffM1;
6524e494 RZ	89	uint32_t ulGbFuseTableCksoffM2;
	90	uint32_t ulGbFuseTableCksoffB;
	91
0d2c7569	92	uint32_t ulGbFuseTableCksonM1;
6524e494	93	uint32_t ulGbFuseTableCksonM2;
0d2c7569	94	uint32_t ulGbFuseTableCksonB;
6524e494	95
0d2c7569	96	uint8_t ucEnableGbVdroopTableCkson;
0d2c7569 EH	97	uint8_t ucEnableGbFuseTableCkson;
0d2c7569 EH	98	uint16_t usPsmAgeComfactor;
6524e494	99
0d2c7569	100	uint32_t ulDispclk2GfxclkM1;
6524e494	101	uint32_t ulDispclk2GfxclkM2;
0d2c7569 EH	102	uint32_t ulDispclk2GfxclkB;
0d2c7569 EH	103	uint32_t ulDcefclk2GfxclkM1;
6524e494	104	uint32_t ulDcefclk2GfxclkM2;
0d2c7569 EH	105	uint32_t ulDcefclk2GfxclkB;
0d2c7569 EH	106	uint32_t ulPixelclk2GfxclkM1;
6524e494	107	uint32_t ulPixelclk2GfxclkM2;
0d2c7569 EH	108	uint32_t ulPixelclk2GfxclkB;
0d2c7569 EH	109	uint32_t ulPhyclk2GfxclkM1;
6524e494	110	uint32_t ulPhyclk2GfxclkM2;
0d2c7569	111	uint32_t ulPhyclk2GfxclkB;
b7437509 RZ	112	uint32_t ulAcgGbVdroopTableA0;
	113	uint32_t ulAcgGbVdroopTableA1;
	114	uint32_t ulAcgGbVdroopTableA2;
	115	uint32_t ulAcgGbFuseTableM1;
	116	uint32_t ulAcgGbFuseTableM2;
	117	uint32_t ulAcgGbFuseTableB;
	118	uint32_t ucAcgEnableGbVdroopTable;
	119	uint32_t ucAcgEnableGbFuseTable;
0d2c7569 EH	120	};
	121
	122	struct pp_atomfwctrl_gpio_parameters {
	123	uint8_t ucAcDcGpio;
	124	uint8_t ucAcDcPolarity;
	125	uint8_t ucVR0HotGpio;
	126	uint8_t ucVR0HotPolarity;
	127	uint8_t ucVR1HotGpio;
	128	uint8_t ucVR1HotPolarity;
	129	uint8_t ucFwCtfGpio;
	130	uint8_t ucFwCtfPolarity;
	131	};
05ee3215 RZ	132
	133	struct pp_atomfwctrl_bios_boot_up_values {
	134	uint32_t ulRevision;
	135	uint32_t ulGfxClk;
	136	uint32_t ulUClk;
	137	uint32_t ulSocClk;
c5b053d2	138	uint32_t ulDCEFClk;
05ee3215 RZ	139	uint16_t usVddc;
	140	uint16_t usVddci;
	141	uint16_t usMvddc;
	142	uint16_t usVddGfx;
	143	};
	144
0d2c7569 EH	145	int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
	146	uint32_t clock_type, uint32_t clock_value,
	147	struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
	148	int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
	149	bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
	150	struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
	151
	152	int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
	153	uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
	154	bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
	155	uint8_t voltage_type, uint8_t voltage_mode);
	156
	157	int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
	158	struct pp_atomfwctrl_avfs_parameters *param);
	159	int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
	160	struct pp_atomfwctrl_gpio_parameters *param);
	161
05ee3215 RZ	162	int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
	163	struct pp_atomfwctrl_bios_boot_up_values *boot_values);
	164
0d2c7569 EH	165	#endif
0d2c7569 EH	166