[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / ppatomctrl.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef PP_ATOMVOLTAGECTRL_H
#define PP_ATOMVOLTAGECTRL_H

#include "hwmgr.h"

#define MEM_TYPE_GDDR5  0x50
#define MEM_TYPE_GDDR4  0x40
#define MEM_TYPE_GDDR3  0x30
#define MEM_TYPE_DDR2   0x20
#define MEM_TYPE_GDDR1  0x10
#define MEM_TYPE_DDR3   0xb0
#define MEM_TYPE_MASK   0xF0


/* As returned from PowerConnectorDetectionTable. */
#define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE  0x80
#define PP_ATOM_POWER_BUDGET_SHOW_WARNING       0x40
#define PP_ATOM_POWER_BUDGET_SHOW_WAIVER        0x20
#define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR    0x0F

/* New functions for Evergreen and beyond. */
#define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32

struct pp_atomctrl_clock_dividers {
	uint32_t pll_post_divider;
	uint32_t pll_feedback_divider;
	uint32_t pll_ref_divider;
	bool  enable_post_divider;
};

typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;

union pp_atomctrl_tcipll_fb_divider {
	struct {
		uint32_t ul_fb_div_frac : 14;
		uint32_t ul_fb_div : 12;
		uint32_t un_used : 6;
	};
	uint32_t ul_fb_divider;
};

typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;

struct pp_atomctrl_clock_dividers_rv730 {
	uint32_t pll_post_divider;
	pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
	uint32_t pll_ref_divider;
	bool  enable_post_divider;
	bool  enable_dithen;
	uint32_t vco_mode;
};
typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;


struct pp_atomctrl_clock_dividers_kong {
	uint32_t    pll_post_divider;
	uint32_t    real_clock;
};
typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;

struct pp_atomctrl_clock_dividers_ci {
	uint32_t    pll_post_divider;               /* post divider value */
	uint32_t    real_clock;
	pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /* Output Parameter: PLL FB divider */
	uint8_t   uc_pll_ref_div;                      /* Output Parameter: PLL ref divider */
	uint8_t   uc_pll_post_div;                      /* Output Parameter: PLL post divider */
	uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
};
typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;

struct pp_atomctrl_clock_dividers_vi {
	uint32_t    pll_post_divider;               /* post divider value */
	uint32_t    real_clock;
	pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /*Output Parameter: PLL FB divider */
	uint8_t   uc_pll_ref_div;                      /*Output Parameter: PLL ref divider */
	uint8_t   uc_pll_post_div;                     /*Output Parameter: PLL post divider */
	uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
};
typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;

struct pp_atomctrl_clock_dividers_ai {
	u16 usSclk_fcw_frac;
	u16  usSclk_fcw_int;
	u8   ucSclkPostDiv;
	u8   ucSclkVcoMode;
	u8   ucSclkPllRange;
	u8   ucSscEnable;
	u16  usSsc_fcw1_frac;
	u16  usSsc_fcw1_int;
	u16  usReserved;
	u16  usPcc_fcw_int;
	u16  usSsc_fcw_slew_frac;
	u16  usPcc_fcw_slew_frac;
};
typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;


union pp_atomctrl_s_mpll_fb_divider {
	struct {
		uint32_t cl_kf : 12;
		uint32_t clk_frac : 12;
		uint32_t un_used : 8;
	};
	uint32_t ul_fb_divider;
};
typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;

enum pp_atomctrl_spread_spectrum_mode {
	pp_atomctrl_spread_spectrum_mode_down = 0,
	pp_atomctrl_spread_spectrum_mode_center
};
typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;

struct pp_atomctrl_memory_clock_param {
	pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
	uint32_t mpll_post_divider;
	uint32_t bw_ctrl;
	uint32_t dll_speed;
	uint32_t vco_mode;
	uint32_t yclk_sel;
	uint32_t qdr;
	uint32_t half_rate;
};
typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;

struct pp_atomctrl_internal_ss_info {
	uint32_t speed_spectrum_percentage;                      /* in 1/100 percentage */
	uint32_t speed_spectrum_rate;                            /* in KHz */
	pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
};
typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;

#ifndef NUMBER_OF_M3ARB_PARAMS
#define NUMBER_OF_M3ARB_PARAMS 3
#endif

#ifndef NUMBER_OF_M3ARB_PARAM_SETS
#define NUMBER_OF_M3ARB_PARAM_SETS 10
#endif

struct pp_atomctrl_kong_system_info {
	uint32_t			ul_bootup_uma_clock;          /* in 10kHz unit */
	uint16_t			us_max_nb_voltage;            /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
	uint16_t			us_min_nb_voltage;            /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
	uint16_t			us_bootup_nb_voltage;         /* boot up NB voltage */
	uint8_t			uc_htc_tmp_lmt;               /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
	uint8_t			uc_tj_offset;                /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
	/* 0: default 1: uvd 2: fs-3d */
	uint32_t          ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
};
typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;

struct pp_atomctrl_memory_info {
	uint8_t memory_vendor;
	uint8_t memory_type;
};
typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;

#define MAX_AC_TIMING_ENTRIES 16

struct pp_atomctrl_memory_clock_range_table {
	uint8_t   num_entries;
	uint8_t   rsv[3];

	uint32_t mclk[MAX_AC_TIMING_ENTRIES];
};
typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;

struct pp_atomctrl_voltage_table_entry {
	uint16_t value;
	uint32_t smio_low;
};

typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;

struct pp_atomctrl_voltage_table {
	uint32_t count;
	uint32_t mask_low;
	uint32_t phase_delay;   /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
	pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
};

typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;

#define VBIOS_MC_REGISTER_ARRAY_SIZE           32
#define VBIOS_MAX_AC_TIMING_ENTRIES            20

struct pp_atomctrl_mc_reg_entry {
	uint32_t           mclk_max;
	uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
};
typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;

struct pp_atomctrl_mc_register_address {
	uint16_t s1;
	uint8_t  uc_pre_reg_data;
};

typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;

#define MAX_SCLK_RANGE 8

struct pp_atom_ctrl_sclk_range_table_entry{
	uint8_t  ucVco_setting;
	uint8_t  ucPostdiv;
	uint16_t usFcw_pcc;
	uint16_t usFcw_trans_upper;
	uint16_t usRcw_trans_lower;
};


struct pp_atom_ctrl_sclk_range_table{
	struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE];
};

struct pp_atomctrl_mc_reg_table {
	uint8_t                         last;                    /* number of registers */
	uint8_t                         num_entries;             /* number of AC timing entries */
	pp_atomctrl_mc_reg_entry        mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
	pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
};
typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;

struct pp_atomctrl_gpio_pin_assignment {
	uint16_t                   us_gpio_pin_aindex;
	uint8_t                    uc_gpio_pin_bit_shift;
};
typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;

struct pp_atom_ctrl__avfs_parameters {
	uint32_t  ulAVFS_meanNsigma_Acontant0;
	uint32_t  ulAVFS_meanNsigma_Acontant1;
	uint32_t  ulAVFS_meanNsigma_Acontant2;
	uint16_t usAVFS_meanNsigma_DC_tol_sigma;
	uint16_t usAVFS_meanNsigma_Platform_mean;
	uint16_t usAVFS_meanNsigma_Platform_sigma;
	uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a0;
	uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a1;
	uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a2;
	uint32_t  ulGB_VDROOP_TABLE_CKSON_a0;
	uint32_t  ulGB_VDROOP_TABLE_CKSON_a1;
	uint32_t  ulGB_VDROOP_TABLE_CKSON_a2;
	uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
	uint16_t  usAVFSGB_FUSE_TABLE_CKSOFF_m2;
	uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_b;
	uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_m1;
	uint16_t  usAVFSGB_FUSE_TABLE_CKSON_m2;
	uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_b;
	uint16_t  usMaxVoltage_0_25mv;
	uint8_t  ucEnableGB_VDROOP_TABLE_CKSOFF;
	uint8_t  ucEnableGB_VDROOP_TABLE_CKSON;
	uint8_t  ucEnableGB_FUSE_TABLE_CKSOFF;
	uint8_t  ucEnableGB_FUSE_TABLE_CKSON;
	uint16_t usPSM_Age_ComFactor;
	uint8_t  ucEnableApplyAVFS_CKS_OFF_Voltage;
	uint8_t  ucReserved;
};

extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
		uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
						 uint32_t clock_value,
						 pp_atomctrl_clock_dividers_kong *dividers);
extern int atomctrl_read_efuse(void *device, uint16_t start_index,
		uint16_t end_index, uint32_t mask, uint32_t *efuse);
extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
		uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
								uint8_t level);
extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
				uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);

extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);

#endif
Commit	Line	Data
c82baa28	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef PP_ATOMVOLTAGECTRL_H
	25	#define PP_ATOMVOLTAGECTRL_H
	26
	27	#include "hwmgr.h"
	28
	29	#define MEM_TYPE_GDDR5 0x50
	30	#define MEM_TYPE_GDDR4 0x40
	31	#define MEM_TYPE_GDDR3 0x30
	32	#define MEM_TYPE_DDR2 0x20
	33	#define MEM_TYPE_GDDR1 0x10
	34	#define MEM_TYPE_DDR3 0xb0
	35	#define MEM_TYPE_MASK 0xF0
	36
	37
	38	/* As returned from PowerConnectorDetectionTable. */
	39	#define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80
	40	#define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40
	41	#define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20
	42	#define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F
	43
	44	/* New functions for Evergreen and beyond. */
	45	#define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
	46
	47	struct pp_atomctrl_clock_dividers {
	48	uint32_t pll_post_divider;
	49	uint32_t pll_feedback_divider;
	50	uint32_t pll_ref_divider;
	51	bool enable_post_divider;
	52	};
	53
	54	typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
	55
	56	union pp_atomctrl_tcipll_fb_divider {
	57	struct {
	58	uint32_t ul_fb_div_frac : 14;
	59	uint32_t ul_fb_div : 12;
	60	uint32_t un_used : 6;
	61	};
	62	uint32_t ul_fb_divider;
	63	};
	64
65	typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
66
67	struct pp_atomctrl_clock_dividers_rv730 {
68	uint32_t pll_post_divider;
69	pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
70	uint32_t pll_ref_divider;
71	bool enable_post_divider;
72	bool enable_dithen;
73	uint32_t vco_mode;
74	};
75	typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
76
77
78	struct pp_atomctrl_clock_dividers_kong {
79	uint32_t pll_post_divider;
80	uint32_t real_clock;
81	};
82	typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
83
84	struct pp_atomctrl_clock_dividers_ci {
85	uint32_t pll_post_divider; /* post divider value */
86	uint32_t real_clock;
87	pp_atomctrl_tcipll_fb_divider ul_fb_div; /* Output Parameter: PLL FB divider */
88	uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */
89	uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */
90	uint8_t uc_pll_cntl_flag; /Output Flags: control flag /
91	};
92	typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
93
94	struct pp_atomctrl_clock_dividers_vi {
95	uint32_t pll_post_divider; /* post divider value */
96	uint32_t real_clock;
97	pp_atomctrl_tcipll_fb_divider ul_fb_div; /Output Parameter: PLL FB divider /
98	uint8_t uc_pll_ref_div; /Output Parameter: PLL ref divider /
99	uint8_t uc_pll_post_div; /Output Parameter: PLL post divider /
100	uint8_t uc_pll_cntl_flag; /Output Flags: control flag /
101	};
102	typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
103
a23eefa2 RZ	104	struct pp_atomctrl_clock_dividers_ai {
	105	u16 usSclk_fcw_frac;
	106	u16 usSclk_fcw_int;
	107	u8 ucSclkPostDiv;
	108	u8 ucSclkVcoMode;
	109	u8 ucSclkPllRange;
	110	u8 ucSscEnable;
	111	u16 usSsc_fcw1_frac;
	112	u16 usSsc_fcw1_int;
	113	u16 usReserved;
	114	u16 usPcc_fcw_int;
	115	u16 usSsc_fcw_slew_frac;
	116	u16 usPcc_fcw_slew_frac;
	117	};
	118	typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;
	119
	120
c82baa28	121	union pp_atomctrl_s_mpll_fb_divider {
	122	struct {
	123	uint32_t cl_kf : 12;
	124	uint32_t clk_frac : 12;
	125	uint32_t un_used : 8;
	126	};
	127	uint32_t ul_fb_divider;
	128	};
	129	typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
	130
	131	enum pp_atomctrl_spread_spectrum_mode {
	132	pp_atomctrl_spread_spectrum_mode_down = 0,
	133	pp_atomctrl_spread_spectrum_mode_center
	134	};
	135	typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
	136
	137	struct pp_atomctrl_memory_clock_param {
	138	pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
	139	uint32_t mpll_post_divider;
	140	uint32_t bw_ctrl;
	141	uint32_t dll_speed;
	142	uint32_t vco_mode;
	143	uint32_t yclk_sel;
	144	uint32_t qdr;
	145	uint32_t half_rate;
	146	};
	147	typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
	148
	149	struct pp_atomctrl_internal_ss_info {
	150	uint32_t speed_spectrum_percentage; /* in 1/100 percentage */
	151	uint32_t speed_spectrum_rate; /* in KHz */
	152	pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
	153	};
	154	typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
	155
	156	#ifndef NUMBER_OF_M3ARB_PARAMS
	157	#define NUMBER_OF_M3ARB_PARAMS 3
	158	#endif
	159
	160	#ifndef NUMBER_OF_M3ARB_PARAM_SETS
	161	#define NUMBER_OF_M3ARB_PARAM_SETS 10
	162	#endif
	163
	164	struct pp_atomctrl_kong_system_info {
	165	uint32_t ul_bootup_uma_clock; /* in 10kHz unit */
	166	uint16_t us_max_nb_voltage; /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
	167	uint16_t us_min_nb_voltage; /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
	168	uint16_t us_bootup_nb_voltage; /* boot up NB voltage */
	169	uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
	170	uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
	171	/* 0: default 1: uvd 2: fs-3d */
	172	uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
	173	};
	174	typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
	175
	176	struct pp_atomctrl_memory_info {
	177	uint8_t memory_vendor;
	178	uint8_t memory_type;
	179	};
	180	typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
	181
	182	#define MAX_AC_TIMING_ENTRIES 16
	183
	184	struct pp_atomctrl_memory_clock_range_table {
185	uint8_t num_entries;
186	uint8_t rsv[3];
187
188	uint32_t mclk[MAX_AC_TIMING_ENTRIES];
189	};
190	typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
191
192	struct pp_atomctrl_voltage_table_entry {
193	uint16_t value;
194	uint32_t smio_low;
195	};
196
197	typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
198
199	struct pp_atomctrl_voltage_table {
200	uint32_t count;
201	uint32_t mask_low;
202	uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
203	pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
204	};
205
206	typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
207
208	#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
209	#define VBIOS_MAX_AC_TIMING_ENTRIES 20
210
211	struct pp_atomctrl_mc_reg_entry {
212	uint32_t mclk_max;
213	uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
214	};
215	typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
216
217	struct pp_atomctrl_mc_register_address {
218	uint16_t s1;
219	uint8_t uc_pre_reg_data;
220	};
221
222	typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
223
a23eefa2 RZ	224	#define MAX_SCLK_RANGE 8
	225
	226	struct pp_atom_ctrl_sclk_range_table_entry{
	227	uint8_t ucVco_setting;
	228	uint8_t ucPostdiv;
	229	uint16_t usFcw_pcc;
	230	uint16_t usFcw_trans_upper;
	231	uint16_t usRcw_trans_lower;
	232	};
	233
	234
	235	struct pp_atom_ctrl_sclk_range_table{
	236	struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE];
	237	};
	238
c82baa28	239	struct pp_atomctrl_mc_reg_table {
	240	uint8_t last; /* number of registers */
	241	uint8_t num_entries; /* number of AC timing entries */
	242	pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
	243	pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
	244	};
	245	typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
	246
	247	struct pp_atomctrl_gpio_pin_assignment {
	248	uint16_t us_gpio_pin_aindex;
	249	uint8_t uc_gpio_pin_bit_shift;
	250	};
	251	typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
	252
432c3a3c RZ	253	struct pp_atom_ctrl__avfs_parameters {
	254	uint32_t ulAVFS_meanNsigma_Acontant0;
	255	uint32_t ulAVFS_meanNsigma_Acontant1;
	256	uint32_t ulAVFS_meanNsigma_Acontant2;
	257	uint16_t usAVFS_meanNsigma_DC_tol_sigma;
	258	uint16_t usAVFS_meanNsigma_Platform_mean;
	259	uint16_t usAVFS_meanNsigma_Platform_sigma;
	260	uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0;
	261	uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1;
	262	uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2;
	263	uint32_t ulGB_VDROOP_TABLE_CKSON_a0;
	264	uint32_t ulGB_VDROOP_TABLE_CKSON_a1;
	265	uint32_t ulGB_VDROOP_TABLE_CKSON_a2;
	266	uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
	267	uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2;
	268	uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b;
	269	uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1;
	270	uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2;
	271	uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b;
	272	uint16_t usMaxVoltage_0_25mv;
	273	uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF;
	274	uint8_t ucEnableGB_VDROOP_TABLE_CKSON;
	275	uint8_t ucEnableGB_FUSE_TABLE_CKSOFF;
	276	uint8_t ucEnableGB_FUSE_TABLE_CKSON;
	277	uint16_t usPSM_Age_ComFactor;
	278	uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage;
	279	uint8_t ucReserved;
	280	};
	281
c82baa28	282	extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment gpio_pin_assignment);
	283	extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t voltage);
	284	extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
	285	extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info ssInfo);
	286	extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info ssInfo);
	287	extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table table);
	288	extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
	289	extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
	290	extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param mpll_param, bool strobe_mode);
	291	extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi dividers);
	292	extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi dividers);
	293	extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
	294	extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table voltage_table);
3ec2cdb8 EH	295	extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
3ec2cdb8 EH	296	uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
d39d5c2c AD	297	extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
	298	uint32_t clock_value,
	299	pp_atomctrl_clock_dividers_kong *dividers);
3ec2cdb8 EH	300	extern int atomctrl_read_efuse(void *device, uint16_t start_index,
	301	uint16_t end_index, uint32_t mask, uint32_t *efuse);
	302	extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
	303	uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
a23eefa2 RZ	304	extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai dividers);
	305	extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
	306	uint8_t level);
	307	extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
	308	uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
	309	extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr hwmgr, struct pp_atom_ctrl_sclk_range_table table);
432c3a3c RZ	310
	311	extern int atomctrl_get_avfs_information(struct pp_hwmgr hwmgr, struct pp_atom_ctrl__avfs_parameters param);
	312
c82baa28	313	#endif
c82baa28	314