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drm/amd/powerplay: enable avfs feature for polaris
[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / polaris10_hwmgr.c
CommitLineData
a23eefa2
RZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
ae17c999 26#include <asm/div64.h>
a23eefa2
RZ		 27#include "linux/delay.h"
28#include "pp_acpi.h"
29#include "hwmgr.h"
2cc0c0b5
FC		 30#include "polaris10_hwmgr.h"
31#include "polaris10_powertune.h"
32#include "polaris10_dyn_defaults.h"
33#include "polaris10_smumgr.h"
a23eefa2
RZ		 34#include "pp_debug.h"
35#include "ppatomctrl.h"
36#include "atombios.h"
37#include "tonga_pptable.h"
38#include "pppcielanes.h"
39#include "amd_pcie_helpers.h"
40#include "hardwaremanager.h"
41#include "tonga_processpptables.h"
42#include "cgs_common.h"
43#include "smu74.h"
44#include "smu_ucode_xfer_vi.h"
45#include "smu74_discrete.h"
46#include "smu/smu_7_1_3_d.h"
47#include "smu/smu_7_1_3_sh_mask.h"
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50#include "oss/oss_3_0_d.h"
51#include "gca/gfx_8_0_d.h"
52#include "bif/bif_5_0_d.h"
53#include "bif/bif_5_0_sh_mask.h"
54#include "gmc/gmc_8_1_d.h"
55#include "gmc/gmc_8_1_sh_mask.h"
56#include "bif/bif_5_0_d.h"
57#include "bif/bif_5_0_sh_mask.h"
58#include "dce/dce_10_0_d.h"
59#include "dce/dce_10_0_sh_mask.h"
60
2cc0c0b5
FC		 61#include "polaris10_thermal.h"
62#include "polaris10_clockpowergating.h"
eede5262 63
a23eefa2
RZ		 64#define MC_CG_ARB_FREQ_F0 0x0a
65#define MC_CG_ARB_FREQ_F1 0x0b
66#define MC_CG_ARB_FREQ_F2 0x0c
67#define MC_CG_ARB_FREQ_F3 0x0d
68
69#define MC_CG_SEQ_DRAMCONF_S0 0x05
70#define MC_CG_SEQ_DRAMCONF_S1 0x06
71#define MC_CG_SEQ_YCLK_SUSPEND 0x04
72#define MC_CG_SEQ_YCLK_RESUME 0x0a
73
74
75#define SMC_RAM_END 0x40000
76
77#define SMC_CG_IND_START 0xc0030000
78#define SMC_CG_IND_END 0xc0040000
79
80#define VOLTAGE_SCALE 4
81#define VOLTAGE_VID_OFFSET_SCALE1 625
82#define VOLTAGE_VID_OFFSET_SCALE2 100
83
84#define VDDC_VDDCI_DELTA 200
85
86#define MEM_FREQ_LOW_LATENCY 25000
87#define MEM_FREQ_HIGH_LATENCY 80000
88
89#define MEM_LATENCY_HIGH 45
90#define MEM_LATENCY_LOW 35
91#define MEM_LATENCY_ERR 0xFFFF
92
93#define MC_SEQ_MISC0_GDDR5_SHIFT 28
94#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95#define MC_SEQ_MISC0_GDDR5_VALUE 5
96
97
98#define PCIE_BUS_CLK 10000
99#define TCLK (PCIE_BUS_CLK / 10)
100
101
909a0631
NW		 102static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
a23eefa2
RZ		 104
105/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
909a0631
NW		 106static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
107{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
a23eefa2
RZ		 109
110/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
909a0631
NW		 111static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
112{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
a23eefa2
RZ		 113
114/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
115enum DPM_EVENT_SRC {
116 DPM_EVENT_SRC_ANALOG = 0,
117 DPM_EVENT_SRC_EXTERNAL = 1,
118 DPM_EVENT_SRC_DIGITAL = 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
121};
122
909a0631 123static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
a23eefa2 124
2cc0c0b5 125struct polaris10_power_state *cast_phw_polaris10_power_state(
a23eefa2
RZ		 126 struct pp_hw_power_state *hw_ps)
127{
2cc0c0b5 128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 129 "Invalid Powerstate Type!",
130 return NULL);
131
2cc0c0b5 132 return (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 133}
134
2cc0c0b5 135const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
a23eefa2
RZ		 136 const struct pp_hw_power_state *hw_ps)
137{
2cc0c0b5 138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 139 "Invalid Powerstate Type!",
140 return NULL);
141
2cc0c0b5 142 return (const struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 143}
144
2cc0c0b5 145static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 146{
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
148 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
149 ? true : false;
150}
151
152/**
153 * Find the MC microcode version and store it in the HwMgr struct
154 *
155 * @param hwmgr the address of the powerplay hardware manager.
156 * @return always 0
157 */
158int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
159{
160 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
161
162 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
163
164 return 0;
165}
166
167uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
168{
169 uint32_t speedCntl = 0;
170
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
173 ixPCIE_LC_SPEED_CNTL);
174 return((uint16_t)PHM_GET_FIELD(speedCntl,
175 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
176}
177
178int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
179{
180 uint32_t link_width;
181
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
184 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
185
186 PP_ASSERT_WITH_CODE((7 >= link_width),
187 "Invalid PCIe lane width!", return 0);
188
189 return decode_pcie_lane_width(link_width);
190}
191
e85c7d66 192/**
193* Enable voltage control
194*
195* @param pHwMgr the address of the powerplay hardware manager.
196* @return always PP_Result_OK
197*/
2cc0c0b5 198int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
e85c7d66 199{
200 PP_ASSERT_WITH_CODE(
201 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
203 return 1;
204 );
205
206 return 0;
207}
a23eefa2
RZ		 208
209/**
210* Checks if we want to support voltage control
211*
212* @param hwmgr the address of the powerplay hardware manager.
213*/
2cc0c0b5 214static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
a23eefa2 215{
2cc0c0b5
FC		 216 const struct polaris10_hwmgr *data =
217 (const struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 218
2cc0c0b5 219 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
a23eefa2
RZ		 220}
221
222/**
223* Enable voltage control
224*
225* @param hwmgr the address of the powerplay hardware manager.
226* @return always 0
227*/
2cc0c0b5 228static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 229{
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
232 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
233
234 return 0;
235}
236
237/**
238* Create Voltage Tables.
239*
240* @param hwmgr the address of the powerplay hardware manager.
241* @return always 0
242*/
2cc0c0b5 243static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
a23eefa2 244{
2cc0c0b5 245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 246 struct phm_ppt_v1_information *table_info =
247 (struct phm_ppt_v1_information *)hwmgr->pptable;
248 int result;
249
2cc0c0b5 250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 251 result = atomctrl_get_voltage_table_v3(hwmgr,
252 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
253 &(data->mvdd_voltage_table));
254 PP_ASSERT_WITH_CODE((0 == result),
255 "Failed to retrieve MVDD table.",
256 return result);
2cc0c0b5 257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 258 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
259 table_info->vdd_dep_on_mclk);
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
262 return result;);
263 }
264
2cc0c0b5 265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 266 result = atomctrl_get_voltage_table_v3(hwmgr,
267 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
268 &(data->vddci_voltage_table));
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve VDDCI table.",
271 return result);
2cc0c0b5 272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 273 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
274 table_info->vdd_dep_on_mclk);
275 PP_ASSERT_WITH_CODE((0 == result),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
277 return result);
278 }
279
2cc0c0b5 280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 281 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
282 table_info->vddc_lookup_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
285 return result);
286 }
287
288 PP_ASSERT_WITH_CODE(
289 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
292 &(data->vddc_voltage_table)));
293
294 PP_ASSERT_WITH_CODE(
295 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
298 &(data->vddci_voltage_table)));
299
300 PP_ASSERT_WITH_CODE(
301 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
304 &(data->mvdd_voltage_table)));
305
306 return 0;
307}
308
309/**
310* Programs static screed detection parameters
311*
312* @param hwmgr the address of the powerplay hardware manager.
313* @return always 0
314*/
2cc0c0b5 315static int polaris10_program_static_screen_threshold_parameters(
a23eefa2
RZ		 316 struct pp_hwmgr *hwmgr)
317{
2cc0c0b5 318 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 319
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
322 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
323 data->static_screen_threshold_unit);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
326 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
327 data->static_screen_threshold);
328
329 return 0;
330}
331
332/**
333* Setup display gap for glitch free memory clock switching.
334*
335* @param hwmgr the address of the powerplay hardware manager.
336* @return always 0
337*/
2cc0c0b5 338static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 339{
340 uint32_t display_gap =
341 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
342 ixCG_DISPLAY_GAP_CNTL);
343
344 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
345 DISP_GAP, DISPLAY_GAP_IGNORE);
346
347 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
348 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
349
350 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
351 ixCG_DISPLAY_GAP_CNTL, display_gap);
352
353 return 0;
354}
355
356/**
357* Programs activity state transition voting clients
358*
359* @param hwmgr the address of the powerplay hardware manager.
360* @return always 0
361*/
2cc0c0b5 362static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
a23eefa2 363{
2cc0c0b5 364 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 365
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
370 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
371
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
377 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
379 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
381 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
382 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
383 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
388
389 return 0;
390}
391
392/**
393* Get the location of various tables inside the FW image.
394*
395* @param hwmgr the address of the powerplay hardware manager.
396* @return always 0
397*/
2cc0c0b5 398static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
a23eefa2 399{
2cc0c0b5
FC		 400 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
401 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
a23eefa2
RZ		 402 uint32_t tmp;
403 int result;
404 bool error = false;
405
2cc0c0b5 406 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 407 SMU7_FIRMWARE_HEADER_LOCATION +
408 offsetof(SMU74_Firmware_Header, DpmTable),
409 &tmp, data->sram_end);
410
411 if (0 == result)
412 data->dpm_table_start = tmp;
413
414 error |= (0 != result);
415
2cc0c0b5 416 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 417 SMU7_FIRMWARE_HEADER_LOCATION +
418 offsetof(SMU74_Firmware_Header, SoftRegisters),
419 &tmp, data->sram_end);
420
421 if (!result) {
422 data->soft_regs_start = tmp;
423 smu_data->soft_regs_start = tmp;
424 }
425
426 error |= (0 != result);
427
2cc0c0b5 428 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 429 SMU7_FIRMWARE_HEADER_LOCATION +
430 offsetof(SMU74_Firmware_Header, mcRegisterTable),
431 &tmp, data->sram_end);
432
433 if (!result)
434 data->mc_reg_table_start = tmp;
435
2cc0c0b5 436 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 437 SMU7_FIRMWARE_HEADER_LOCATION +
438 offsetof(SMU74_Firmware_Header, FanTable),
439 &tmp, data->sram_end);
440
441 if (!result)
442 data->fan_table_start = tmp;
443
444 error |= (0 != result);
445
2cc0c0b5 446 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 447 SMU7_FIRMWARE_HEADER_LOCATION +
448 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
449 &tmp, data->sram_end);
450
451 if (!result)
452 data->arb_table_start = tmp;
453
454 error |= (0 != result);
455
2cc0c0b5 456 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 457 SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU74_Firmware_Header, Version),
459 &tmp, data->sram_end);
460
461 if (!result)
462 hwmgr->microcode_version_info.SMC = tmp;
463
464 error |= (0 != result);
465
466 return error ? -1 : 0;
467}
468
469/* Copy one arb setting to another and then switch the active set.
470 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
471 */
2cc0c0b5 472static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 473 uint32_t arb_src, uint32_t arb_dest)
474{
475 uint32_t mc_arb_dram_timing;
476 uint32_t mc_arb_dram_timing2;
477 uint32_t burst_time;
478 uint32_t mc_cg_config;
479
480 switch (arb_src) {
481 case MC_CG_ARB_FREQ_F0:
482 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
483 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
484 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
485 break;
486 case MC_CG_ARB_FREQ_F1:
487 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
488 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
489 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
490 break;
491 default:
492 return -EINVAL;
493 }
494
495 switch (arb_dest) {
496 case MC_CG_ARB_FREQ_F0:
497 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
498 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
499 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
500 break;
501 case MC_CG_ARB_FREQ_F1:
502 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
503 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
504 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
505 break;
506 default:
507 return -EINVAL;
508 }
509
510 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
511 mc_cg_config |= 0x0000000F;
512 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
513 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
514
515 return 0;
516}
517
518/**
519* Initial switch from ARB F0->F1
520*
521* @param hwmgr the address of the powerplay hardware manager.
522* @return always 0
523* This function is to be called from the SetPowerState table.
524*/
2cc0c0b5 525static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
a23eefa2 526{
2cc0c0b5 527 return polaris10_copy_and_switch_arb_sets(hwmgr,
a23eefa2
RZ		 528 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
529}
530
2cc0c0b5 531static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
a23eefa2 532{
2cc0c0b5 533 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 534 struct phm_ppt_v1_information *table_info =
535 (struct phm_ppt_v1_information *)(hwmgr->pptable);
536 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
537 uint32_t i, max_entry;
538
539 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
540 data->use_pcie_power_saving_levels), "No pcie performance levels!",
541 return -EINVAL);
542
543 if (data->use_pcie_performance_levels &&
544 !data->use_pcie_power_saving_levels) {
545 data->pcie_gen_power_saving = data->pcie_gen_performance;
546 data->pcie_lane_power_saving = data->pcie_lane_performance;
547 } else if (!data->use_pcie_performance_levels &&
548 data->use_pcie_power_saving_levels) {
549 data->pcie_gen_performance = data->pcie_gen_power_saving;
550 data->pcie_lane_performance = data->pcie_lane_power_saving;
551 }
552
553 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
554 SMU74_MAX_LEVELS_LINK,
555 MAX_REGULAR_DPM_NUMBER);
556
557 if (pcie_table != NULL) {
558 /* max_entry is used to make sure we reserve one PCIE level
559 * for boot level (fix for A+A PSPP issue).
560 * If PCIE table from PPTable have ULV entry + 8 entries,
561 * then ignore the last entry.*/
562 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
563 SMU74_MAX_LEVELS_LINK : pcie_table->count;
564 for (i = 1; i < max_entry; i++) {
565 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
566 get_pcie_gen_support(data->pcie_gen_cap,
567 pcie_table->entries[i].gen_speed),
568 get_pcie_lane_support(data->pcie_lane_cap,
569 pcie_table->entries[i].lane_width));
570 }
571 data->dpm_table.pcie_speed_table.count = max_entry - 1;
e85c7d66 572
573 /* Setup BIF_SCLK levels */
574 for (i = 0; i < max_entry; i++)
575 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
a23eefa2
RZ		 576 } else {
577 /* Hardcode Pcie Table */
578 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
579 get_pcie_gen_support(data->pcie_gen_cap,
580 PP_Min_PCIEGen),
581 get_pcie_lane_support(data->pcie_lane_cap,
582 PP_Max_PCIELane));
583 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
584 get_pcie_gen_support(data->pcie_gen_cap,
585 PP_Min_PCIEGen),
586 get_pcie_lane_support(data->pcie_lane_cap,
587 PP_Max_PCIELane));
588 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
589 get_pcie_gen_support(data->pcie_gen_cap,
590 PP_Max_PCIEGen),
591 get_pcie_lane_support(data->pcie_lane_cap,
592 PP_Max_PCIELane));
593 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
594 get_pcie_gen_support(data->pcie_gen_cap,
595 PP_Max_PCIEGen),
596 get_pcie_lane_support(data->pcie_lane_cap,
597 PP_Max_PCIELane));
598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
599 get_pcie_gen_support(data->pcie_gen_cap,
600 PP_Max_PCIEGen),
601 get_pcie_lane_support(data->pcie_lane_cap,
602 PP_Max_PCIELane));
603 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
604 get_pcie_gen_support(data->pcie_gen_cap,
605 PP_Max_PCIEGen),
606 get_pcie_lane_support(data->pcie_lane_cap,
607 PP_Max_PCIELane));
608
609 data->dpm_table.pcie_speed_table.count = 6;
610 }
611 /* Populate last level for boot PCIE level, but do not increment count. */
612 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
613 data->dpm_table.pcie_speed_table.count,
614 get_pcie_gen_support(data->pcie_gen_cap,
615 PP_Min_PCIEGen),
616 get_pcie_lane_support(data->pcie_lane_cap,
617 PP_Max_PCIELane));
618
619 return 0;
620}
621
622/*
623 * This function is to initalize all DPM state tables
624 * for SMU7 based on the dependency table.
625 * Dynamic state patching function will then trim these
626 * state tables to the allowed range based
627 * on the power policy or external client requests,
628 * such as UVD request, etc.
629 */
2cc0c0b5 630int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
a23eefa2 631{
2cc0c0b5 632 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 633 struct phm_ppt_v1_information *table_info =
634 (struct phm_ppt_v1_information *)(hwmgr->pptable);
635 uint32_t i;
636
637 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
638 table_info->vdd_dep_on_sclk;
639 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
640 table_info->vdd_dep_on_mclk;
641
642 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
643 "SCLK dependency table is missing. This table is mandatory",
644 return -EINVAL);
645 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
646 "SCLK dependency table has to have is missing."
647 "This table is mandatory",
648 return -EINVAL);
649
650 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
651 "MCLK dependency table is missing. This table is mandatory",
652 return -EINVAL);
653 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
654 "MCLK dependency table has to have is missing."
655 "This table is mandatory",
656 return -EINVAL);
657
658 /* clear the state table to reset everything to default */
659 phm_reset_single_dpm_table(
660 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
661 phm_reset_single_dpm_table(
662 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
663
664
665 /* Initialize Sclk DPM table based on allow Sclk values */
666 data->dpm_table.sclk_table.count = 0;
667 for (i = 0; i < dep_sclk_table->count; i++) {
668 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
669 dep_sclk_table->entries[i].clk) {
670
671 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
672 dep_sclk_table->entries[i].clk;
673
674 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
675 (i == 0) ? true : false;
676 data->dpm_table.sclk_table.count++;
677 }
678 }
679
680 /* Initialize Mclk DPM table based on allow Mclk values */
681 data->dpm_table.mclk_table.count = 0;
682 for (i = 0; i < dep_mclk_table->count; i++) {
683 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
684 [data->dpm_table.mclk_table.count - 1].value !=
685 dep_mclk_table->entries[i].clk) {
686 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
687 dep_mclk_table->entries[i].clk;
688 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
689 (i == 0) ? true : false;
690 data->dpm_table.mclk_table.count++;
691 }
692 }
693
694 /* setup PCIE gen speed levels */
2cc0c0b5 695 polaris10_setup_default_pcie_table(hwmgr);
a23eefa2
RZ		 696
697 /* save a copy of the default DPM table */
698 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
2cc0c0b5 699 sizeof(struct polaris10_dpm_table));
a23eefa2
RZ		 700
701 return 0;
702}
703
704uint8_t convert_to_vid(uint16_t vddc)
705{
706 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
707}
708
709/**
710 * Mvdd table preparation for SMC.
711 *
712 * @param *hwmgr The address of the hardware manager.
713 * @param *table The SMC DPM table structure to be populated.
714 * @return 0
715 */
2cc0c0b5 716static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 717 SMU74_Discrete_DpmTable *table)
718{
2cc0c0b5 719 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 720 uint32_t count, level;
721
2cc0c0b5 722 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 723 count = data->mvdd_voltage_table.count;
724 if (count > SMU_MAX_SMIO_LEVELS)
725 count = SMU_MAX_SMIO_LEVELS;
726 for (level = 0; level < count; level++) {
727 table->SmioTable2.Pattern[level].Voltage =
728 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
729 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
730 table->SmioTable2.Pattern[level].Smio =
731 (uint8_t) level;
732 table->Smio[level] |=
733 data->mvdd_voltage_table.entries[level].smio_low;
734 }
735 table->SmioMask2 = data->vddci_voltage_table.mask_low;
736
737 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
738 }
739
740 return 0;
741}
742
2cc0c0b5 743static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 744 struct SMU74_Discrete_DpmTable *table)
745{
746 uint32_t count, level;
2cc0c0b5 747 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 748
749 count = data->vddci_voltage_table.count;
750
2cc0c0b5 751 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 752 if (count > SMU_MAX_SMIO_LEVELS)
753 count = SMU_MAX_SMIO_LEVELS;
754 for (level = 0; level < count; ++level) {
755 table->SmioTable1.Pattern[level].Voltage =
756 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
757 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
758
759 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
760 }
761 }
762
763 table->SmioMask1 = data->vddci_voltage_table.mask_low;
764
765 return 0;
766}
767
768/**
769* Preparation of vddc and vddgfx CAC tables for SMC.
770*
771* @param hwmgr the address of the hardware manager
772* @param table the SMC DPM table structure to be populated
773* @return always 0
774*/
2cc0c0b5 775static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 776 struct SMU74_Discrete_DpmTable *table)
777{
778 uint32_t count;
779 uint8_t index;
2cc0c0b5 780 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 781 struct phm_ppt_v1_information *table_info =
782 (struct phm_ppt_v1_information *)(hwmgr->pptable);
783 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
784 table_info->vddc_lookup_table;
785 /* tables is already swapped, so in order to use the value from it,
786 * we need to swap it back.
787 * We are populating vddc CAC data to BapmVddc table
788 * in split and merged mode
789 */
790 for (count = 0; count < lookup_table->count; count++) {
791 index = phm_get_voltage_index(lookup_table,
792 data->vddc_voltage_table.entries[count].value);
793 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
794 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
795 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
796 }
797
798 return 0;
799}
800
801/**
802* Preparation of voltage tables for SMC.
803*
804* @param hwmgr the address of the hardware manager
805* @param table the SMC DPM table structure to be populated
806* @return always 0
807*/
808
2cc0c0b5 809int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 810 struct SMU74_Discrete_DpmTable *table)
811{
2cc0c0b5
FC		 812 polaris10_populate_smc_vddci_table(hwmgr, table);
813 polaris10_populate_smc_mvdd_table(hwmgr, table);
814 polaris10_populate_cac_table(hwmgr, table);
a23eefa2
RZ		 815
816 return 0;
817}
818
2cc0c0b5 819static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 820 struct SMU74_Discrete_Ulv *state)
821{
2cc0c0b5 822 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 823 struct phm_ppt_v1_information *table_info =
824 (struct phm_ppt_v1_information *)(hwmgr->pptable);
825
826 state->CcPwrDynRm = 0;
827 state->CcPwrDynRm1 = 0;
828
829 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
830 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
831 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
832
833 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
834
835 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
836 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
837 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
838
839 return 0;
840}
841
2cc0c0b5 842static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 843 struct SMU74_Discrete_DpmTable *table)
844{
2cc0c0b5 845 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
a23eefa2
RZ		 846}
847
2cc0c0b5 848static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 849 struct SMU74_Discrete_DpmTable *table)
850{
2cc0c0b5
FC		 851 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
852 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 853 int i;
854
855 /* Index (dpm_table->pcie_speed_table.count)
856 * is reserved for PCIE boot level. */
857 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
858 table->LinkLevel[i].PcieGenSpeed =
859 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
860 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
861 dpm_table->pcie_speed_table.dpm_levels[i].param1);
862 table->LinkLevel[i].EnabledForActivity = 1;
863 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
864 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
865 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
866 }
867
868 data->smc_state_table.LinkLevelCount =
869 (uint8_t)dpm_table->pcie_speed_table.count;
870 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
871 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
872
873 return 0;
874}
875
2cc0c0b5 876static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 877{
878 uint32_t reference_clock, tmp;
879 struct cgs_display_info info = {0};
880 struct cgs_mode_info mode_info;
881
882 info.mode_info = &mode_info;
883
884 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
885
886 if (tmp)
887 return TCLK;
888
889 cgs_get_active_displays_info(hwmgr->device, &info);
890 reference_clock = mode_info.ref_clock;
891
892 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
893
894 if (0 != tmp)
895 return reference_clock / 4;
896
897 return reference_clock;
898}
899
900/**
901* Calculates the SCLK dividers using the provided engine clock
902*
903* @param hwmgr the address of the hardware manager
904* @param clock the engine clock to use to populate the structure
905* @param sclk the SMC SCLK structure to be populated
906*/
2cc0c0b5 907static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 908 uint32_t clock, SMU_SclkSetting *sclk_setting)
909{
2cc0c0b5 910 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 911 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
912 struct pp_atomctrl_clock_dividers_ai dividers;
913
914 uint32_t ref_clock;
915 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
916 uint8_t i;
917 int result;
918 uint64_t temp;
919
920 sclk_setting->SclkFrequency = clock;
921 /* get the engine clock dividers for this clock value */
922 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
923 if (result == 0) {
924 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
925 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
926 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
927 sclk_setting->PllRange = dividers.ucSclkPllRange;
e85c7d66 928 sclk_setting->Sclk_slew_rate = 0x400;
929 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
930 sclk_setting->Pcc_down_slew_rate = 0xffff;
a23eefa2
RZ		 931 sclk_setting->SSc_En = dividers.ucSscEnable;
932 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
933 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
e85c7d66 934 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
a23eefa2
RZ		 935 return result;
936 }
937
2cc0c0b5 938 ref_clock = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 939
940 for (i = 0; i < NUM_SCLK_RANGE; i++) {
941 if (clock > data->range_table[i].trans_lower_frequency
942 && clock <= data->range_table[i].trans_upper_frequency) {
943 sclk_setting->PllRange = i;
944 break;
945 }
946 }
947
948 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
949 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
950 temp <<= 0x10;
ae17c999
SG		 951 do_div(temp, ref_clock);
952 sclk_setting->Fcw_frac = temp & 0xffff;
a23eefa2
RZ		 953
954 pcc_target_percent = 10; /* Hardcode 10% for now. */
955 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
956 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
957
958 ss_target_percent = 2; /* Hardcode 2% for now. */
959 sclk_setting->SSc_En = 0;
960 if (ss_target_percent) {
961 sclk_setting->SSc_En = 1;
962 ss_target_freq = clock - (clock * ss_target_percent / 100);
963 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
964 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
965 temp <<= 0x10;
ae17c999
SG		 966 do_div(temp, ref_clock);
967 sclk_setting->Fcw1_frac = temp & 0xffff;
a23eefa2
RZ		 968 }
969
970 return 0;
971}
972
2cc0c0b5 973static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 974 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
975 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
976{
977 uint32_t i;
978 uint16_t vddci;
2cc0c0b5 979 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 980
981 *voltage = *mvdd = 0;
982
983 /* clock - voltage dependency table is empty table */
984 if (dep_table->count == 0)
985 return -EINVAL;
986
987 for (i = 0; i < dep_table->count; i++) {
988 /* find first sclk bigger than request */
989 if (dep_table->entries[i].clk >= clock) {
990 *voltage |= (dep_table->entries[i].vddc *
991 VOLTAGE_SCALE) << VDDC_SHIFT;
2cc0c0b5 992 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 993 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
994 VOLTAGE_SCALE) << VDDCI_SHIFT;
995 else if (dep_table->entries[i].vddci)
996 *voltage |= (dep_table->entries[i].vddci *
997 VOLTAGE_SCALE) << VDDCI_SHIFT;
998 else {
999 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000 (dep_table->entries[i].vddc -
1001 (uint16_t)data->vddc_vddci_delta));
3ff21127 1002 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
a23eefa2
RZ		 1003 }
1004
2cc0c0b5 1005 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1006 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1007 VOLTAGE_SCALE;
1008 else if (dep_table->entries[i].mvdd)
1009 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1010 VOLTAGE_SCALE;
1011
1012 *voltage |= 1 << PHASES_SHIFT;
1013 return 0;
1014 }
1015 }
1016
1017 /* sclk is bigger than max sclk in the dependence table */
1018 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1019
2cc0c0b5 1020 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 1021 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1022 VOLTAGE_SCALE) << VDDCI_SHIFT;
1023 else if (dep_table->entries[i-1].vddci) {
1024 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1025 (dep_table->entries[i].vddc -
1026 (uint16_t)data->vddc_vddci_delta));
1027 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1028 }
1029
2cc0c0b5 1030 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1031 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1032 else if (dep_table->entries[i].mvdd)
1033 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1034
1035 return 0;
1036}
1037
909a0631
NW		 1038static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1039{ {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1040 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1041 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1042 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1043 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1044 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1045 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1046 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
a23eefa2 1047
2cc0c0b5 1048static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1049{
1050 uint32_t i, ref_clk;
2cc0c0b5 1051 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1052 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1053 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1054
2cc0c0b5 1055 ref_clk = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 1056
1057 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1058 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1059 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1060 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1061 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1062
1063 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1064 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1065
1066 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1067 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1068 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1069 }
1070 return;
1071 }
1072
1073 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1074
1075 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1076 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1077
1078 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1079 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1080 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1081
1082 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1083 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1084
1085 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1086 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1087 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1088 }
1089}
1090
1091/**
1092* Populates single SMC SCLK structure using the provided engine clock
1093*
1094* @param hwmgr the address of the hardware manager
1095* @param clock the engine clock to use to populate the structure
1096* @param sclk the SMC SCLK structure to be populated
1097*/
1098
2cc0c0b5 1099static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1100 uint32_t clock, uint16_t sclk_al_threshold,
1101 struct SMU74_Discrete_GraphicsLevel *level)
1102{
1103 int result, i, temp;
1104 /* PP_Clocks minClocks; */
1105 uint32_t mvdd;
2cc0c0b5 1106 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1107 struct phm_ppt_v1_information *table_info =
1108 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1109 SMU_SclkSetting curr_sclk_setting = { 0 };
1110
2cc0c0b5 1111 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
a23eefa2
RZ		 1112
1113 /* populate graphics levels */
2cc0c0b5 1114 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1115 table_info->vdd_dep_on_sclk, clock,
1116 &level->MinVoltage, &mvdd);
1117
1118 PP_ASSERT_WITH_CODE((0 == result),
1119 "can not find VDDC voltage value for "
1120 "VDDC engine clock dependency table",
1121 return result);
1122 level->ActivityLevel = sclk_al_threshold;
1123
1124 level->CcPwrDynRm = 0;
1125 level->CcPwrDynRm1 = 0;
1126 level->EnabledForActivity = 0;
1127 level->EnabledForThrottle = 1;
1128 level->UpHyst = 10;
1129 level->DownHyst = 0;
1130 level->VoltageDownHyst = 0;
1131 level->PowerThrottle = 0;
1132
1133 /*
1134 * TODO: get minimum clocks from dal configaration
1135 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1136 */
1137 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1138
1139 /* get level->DeepSleepDivId
1140 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1142 */
859b8b6a 1143 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
2cc0c0b5 1144 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
354ef928 1145 temp = clock >> i;
a23eefa2 1146
859b8b6a 1147 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
a23eefa2
RZ		 1148 break;
1149 }
1150
1151 level->DeepSleepDivId = i;
1152
1153 /* Default to slow, highest DPM level will be
1154 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1155 */
1156 if (data->update_up_hyst)
1157 level->UpHyst = (uint8_t)data->up_hyst;
1158 if (data->update_down_hyst)
1159 level->DownHyst = (uint8_t)data->down_hyst;
1160
1161 level->SclkSetting = curr_sclk_setting;
1162
1163 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1164 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1165 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1166 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1167 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1168 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1169 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1170 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
e85c7d66 1171 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1172 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1173 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1174 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1175 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
e85c7d66 1176 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
a23eefa2
RZ		 1177 return 0;
1178}
1179
1180/**
1181* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1182*
1183* @param hwmgr the address of the hardware manager
1184*/
2cc0c0b5 1185static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1186{
2cc0c0b5
FC		 1187 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1188 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1189 struct phm_ppt_v1_information *table_info =
1190 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1191 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1192 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1193 int result = 0;
1194 uint32_t array = data->dpm_table_start +
1195 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1196 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1197 SMU74_MAX_LEVELS_GRAPHICS;
1198 struct SMU74_Discrete_GraphicsLevel *levels =
1199 data->smc_state_table.GraphicsLevel;
1200 uint32_t i, max_entry;
1201 uint8_t hightest_pcie_level_enabled = 0,
1202 lowest_pcie_level_enabled = 0,
1203 mid_pcie_level_enabled = 0,
1204 count = 0;
1205
2cc0c0b5 1206 polaris10_get_sclk_range_table(hwmgr);
a23eefa2
RZ		 1207
1208 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1209
2cc0c0b5 1210 result = polaris10_populate_single_graphic_level(hwmgr,
a23eefa2
RZ		 1211 dpm_table->sclk_table.dpm_levels[i].value,
1212 (uint16_t)data->activity_target[i],
1213 &(data->smc_state_table.GraphicsLevel[i]));
1214 if (result)
1215 return result;
1216
1217 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1218 if (i > 1)
1219 levels[i].DeepSleepDivId = 0;
1220 }
5de95e55
RZ		 1221 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1222 PHM_PlatformCaps_SPLLShutdownSupport))
1223 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
a23eefa2
RZ		 1224
1225 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1226 data->smc_state_table.GraphicsDpmLevelCount =
1227 (uint8_t)dpm_table->sclk_table.count;
1228 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1229 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1230
1231
1232 if (pcie_table != NULL) {
1233 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1234 "There must be 1 or more PCIE levels defined in PPTable.",
1235 return -EINVAL);
1236 max_entry = pcie_entry_cnt - 1;
1237 for (i = 0; i < dpm_table->sclk_table.count; i++)
1238 levels[i].pcieDpmLevel =
1239 (uint8_t) ((i < max_entry) ? i : max_entry);
1240 } else {
1241 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1242 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1243 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1244 hightest_pcie_level_enabled++;
1245
1246 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1247 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1248 (1 << lowest_pcie_level_enabled)) == 0))
1249 lowest_pcie_level_enabled++;
1250
1251 while ((count < hightest_pcie_level_enabled) &&
1252 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1253 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1254 count++;
1255
1256 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1257 hightest_pcie_level_enabled ?
1258 (lowest_pcie_level_enabled + 1 + count) :
1259 hightest_pcie_level_enabled;
1260
1261 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262 for (i = 2; i < dpm_table->sclk_table.count; i++)
1263 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1264
1265 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1267
1268 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1270 }
1271 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1272 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1273 (uint32_t)array_size, data->sram_end);
1274
1275 return result;
1276}
1277
2cc0c0b5 1278static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1279 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1280{
2cc0c0b5 1281 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1282 struct phm_ppt_v1_information *table_info =
1283 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1284 int result = 0;
1285 struct cgs_display_info info = {0, 0, NULL};
1286
1287 cgs_get_active_displays_info(hwmgr->device, &info);
1288
1289 if (table_info->vdd_dep_on_mclk) {
2cc0c0b5 1290 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1291 table_info->vdd_dep_on_mclk, clock,
1292 &mem_level->MinVoltage, &mem_level->MinMvdd);
1293 PP_ASSERT_WITH_CODE((0 == result),
1294 "can not find MinVddc voltage value from memory "
1295 "VDDC voltage dependency table", return result);
1296 }
1297
1298 mem_level->MclkFrequency = clock;
a23eefa2
RZ		 1299 mem_level->EnabledForThrottle = 1;
1300 mem_level->EnabledForActivity = 0;
1301 mem_level->UpHyst = 0;
1302 mem_level->DownHyst = 100;
1303 mem_level->VoltageDownHyst = 0;
1304 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1305 mem_level->StutterEnable = false;
a23eefa2
RZ		 1306 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1307
1308 data->display_timing.num_existing_displays = info.display_count;
1309
1310 if ((data->mclk_stutter_mode_threshold) &&
1311 (clock <= data->mclk_stutter_mode_threshold) &&
1312 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1313 STUTTER_ENABLE) & 0x1))
1314 mem_level->StutterEnable = true;
1315
1316 if (!result) {
1317 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1318 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1319 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1320 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1321 }
1322 return result;
1323}
1324
1325/**
1326* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1327*
1328* @param hwmgr the address of the hardware manager
1329*/
2cc0c0b5 1330static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1331{
2cc0c0b5
FC		 1332 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1333 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1334 int result;
1335 /* populate MCLK dpm table to SMU7 */
1336 uint32_t array = data->dpm_table_start +
1337 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1338 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1339 SMU74_MAX_LEVELS_MEMORY;
1340 struct SMU74_Discrete_MemoryLevel *levels =
1341 data->smc_state_table.MemoryLevel;
1342 uint32_t i;
1343
1344 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1345 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1346 "can not populate memory level as memory clock is zero",
1347 return -EINVAL);
2cc0c0b5 1348 result = polaris10_populate_single_memory_level(hwmgr,
a23eefa2
RZ		 1349 dpm_table->mclk_table.dpm_levels[i].value,
1350 &levels[i]);
b4c6f99e
RZ		 1351 if (i == dpm_table->mclk_table.count - 1) {
1352 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1353 levels[i].EnabledForActivity = 1;
1354 }
a23eefa2
RZ		 1355 if (result)
1356 return result;
1357 }
1358
a23eefa2
RZ		 1359 /* in order to prevent MC activity from stutter mode to push DPM up.
1360 * the UVD change complements this by putting the MCLK in
1361 * a higher state by default such that we are not effected by
1362 * up threshold or and MCLK DPM latency.
1363 */
9a3c1b34 1364 levels[0].ActivityLevel = 0x1f;
a23eefa2
RZ		 1365 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1366
1367 data->smc_state_table.MemoryDpmLevelCount =
1368 (uint8_t)dpm_table->mclk_table.count;
1369 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1370 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
a23eefa2
RZ		 1371
1372 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1373 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1374 (uint32_t)array_size, data->sram_end);
1375
1376 return result;
1377}
1378
1379/**
1380* Populates the SMC MVDD structure using the provided memory clock.
1381*
1382* @param hwmgr the address of the hardware manager
1383* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1384* @param voltage the SMC VOLTAGE structure to be populated
1385*/
2cc0c0b5 1386int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1387 uint32_t mclk, SMIO_Pattern *smio_pat)
1388{
2cc0c0b5 1389 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1390 struct phm_ppt_v1_information *table_info =
1391 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1392 uint32_t i = 0;
1393
2cc0c0b5 1394 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
a23eefa2
RZ		 1395 /* find mvdd value which clock is more than request */
1396 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1397 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1398 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1399 break;
1400 }
1401 }
1402 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1403 "MVDD Voltage is outside the supported range.",
1404 return -EINVAL);
1405 } else
1406 return -EINVAL;
1407
1408 return 0;
1409}
1410
2cc0c0b5 1411static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1412 SMU74_Discrete_DpmTable *table)
1413{
1414 int result = 0;
1415 uint32_t sclk_frequency;
2cc0c0b5 1416 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1417 struct phm_ppt_v1_information *table_info =
1418 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1419 SMIO_Pattern vol_level;
1420 uint32_t mvdd;
1421 uint16_t us_mvdd;
1422
1423 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1424
1425 if (!data->sclk_dpm_key_disabled) {
1426 /* Get MinVoltage and Frequency from DPM0,
1427 * already converted to SMC_UL */
1428 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
2cc0c0b5 1429 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1430 table_info->vdd_dep_on_sclk,
1431 table->ACPILevel.SclkFrequency,
1432 &table->ACPILevel.MinVoltage, &mvdd);
1433 PP_ASSERT_WITH_CODE((0 == result),
1434 "Cannot find ACPI VDDC voltage value "
1435 "in Clock Dependency Table", );
1436 } else {
1437 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1438 table->ACPILevel.MinVoltage =
1439 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1440 }
1441
2cc0c0b5 1442 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
a23eefa2
RZ		 1443 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1444
1445 table->ACPILevel.DeepSleepDivId = 0;
1446 table->ACPILevel.CcPwrDynRm = 0;
1447 table->ACPILevel.CcPwrDynRm1 = 0;
1448
1449 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1450 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1451 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1452 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1453
1454 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1455 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1456 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1457 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
e85c7d66 1458 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1459 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1460 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1461 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1462 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
e85c7d66 1463 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
a23eefa2
RZ		 1464
1465 if (!data->mclk_dpm_key_disabled) {
1466 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1467 table->MemoryACPILevel.MclkFrequency =
1468 data->dpm_table.mclk_table.dpm_levels[0].value;
2cc0c0b5 1469 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1470 table_info->vdd_dep_on_mclk,
1471 table->MemoryACPILevel.MclkFrequency,
1472 &table->MemoryACPILevel.MinVoltage, &mvdd);
1473 PP_ASSERT_WITH_CODE((0 == result),
1474 "Cannot find ACPI VDDCI voltage value "
1475 "in Clock Dependency Table",
1476 );
1477 } else {
1478 table->MemoryACPILevel.MclkFrequency =
1479 data->vbios_boot_state.mclk_bootup_value;
1480 table->MemoryACPILevel.MinVoltage =
1481 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1482 }
1483
1484 us_mvdd = 0;
2cc0c0b5 1485 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
a23eefa2
RZ		 1486 (data->mclk_dpm_key_disabled))
1487 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1488 else {
2cc0c0b5 1489 if (!polaris10_populate_mvdd_value(hwmgr,
a23eefa2
RZ		 1490 data->dpm_table.mclk_table.dpm_levels[0].value,
1491 &vol_level))
1492 us_mvdd = vol_level.Voltage;
1493 }
1494
2cc0c0b5 1495 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
a23eefa2
RZ		 1496 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1497 else
1498 table->MemoryACPILevel.MinMvdd = 0;
1499
1500 table->MemoryACPILevel.StutterEnable = false;
1501
1502 table->MemoryACPILevel.EnabledForThrottle = 0;
1503 table->MemoryACPILevel.EnabledForActivity = 0;
1504 table->MemoryACPILevel.UpHyst = 0;
1505 table->MemoryACPILevel.DownHyst = 100;
1506 table->MemoryACPILevel.VoltageDownHyst = 0;
1507 table->MemoryACPILevel.ActivityLevel =
1508 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1509
1510 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1511 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1512
1513 return result;
1514}
1515
2cc0c0b5 1516static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1517 SMU74_Discrete_DpmTable *table)
1518{
1519 int result = -EINVAL;
1520 uint8_t count;
1521 struct pp_atomctrl_clock_dividers_vi dividers;
1522 struct phm_ppt_v1_information *table_info =
1523 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1524 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1525 table_info->mm_dep_table;
2cc0c0b5 1526 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1527
1528 table->VceLevelCount = (uint8_t)(mm_table->count);
1529 table->VceBootLevel = 0;
1530
1531 for (count = 0; count < table->VceLevelCount; count++) {
1532 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
681ed01c 1533 table->VceLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1534 table->VceLevel[count].MinVoltage |=
1535 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1536 table->VceLevel[count].MinVoltage |=
1537 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1538 VOLTAGE_SCALE) << VDDCI_SHIFT;
1539 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1540
1541 /*retrieve divider value for VBIOS */
1542 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1543 table->VceLevel[count].Frequency, &dividers);
1544 PP_ASSERT_WITH_CODE((0 == result),
1545 "can not find divide id for VCE engine clock",
1546 return result);
1547
1548 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1549
1550 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1551 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1552 }
1553 return result;
1554}
1555
2cc0c0b5 1556static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1557 SMU74_Discrete_DpmTable *table)
1558{
1559 int result = -EINVAL;
1560 uint8_t count;
1561 struct pp_atomctrl_clock_dividers_vi dividers;
1562 struct phm_ppt_v1_information *table_info =
1563 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1564 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1565 table_info->mm_dep_table;
2cc0c0b5 1566 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1567
1568 table->SamuBootLevel = 0;
1569 table->SamuLevelCount = (uint8_t)(mm_table->count);
1570
1571 for (count = 0; count < table->SamuLevelCount; count++) {
1572 /* not sure whether we need evclk or not */
681ed01c 1573 table->SamuLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1574 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1575 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1576 VOLTAGE_SCALE) << VDDC_SHIFT;
1577 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1578 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1579 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1580
1581 /* retrieve divider value for VBIOS */
1582 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1583 table->SamuLevel[count].Frequency, &dividers);
1584 PP_ASSERT_WITH_CODE((0 == result),
1585 "can not find divide id for samu clock", return result);
1586
1587 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1588
1589 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1590 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1591 }
1592 return result;
1593}
1594
2cc0c0b5 1595static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1596 int32_t eng_clock, int32_t mem_clock,
1597 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1598{
1599 uint32_t dram_timing;
1600 uint32_t dram_timing2;
1601 uint32_t burst_time;
1602 int result;
1603
1604 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1605 eng_clock, mem_clock);
1606 PP_ASSERT_WITH_CODE(result == 0,
1607 "Error calling VBIOS to set DRAM_TIMING.", return result);
1608
1609 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1610 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1611 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1612
1613
1614 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1615 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1616 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1617
1618 return 0;
1619}
1620
2cc0c0b5 1621static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 1622{
2cc0c0b5 1623 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1624 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1625 uint32_t i, j;
1626 int result = 0;
1627
1628 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1629 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2cc0c0b5 1630 result = polaris10_populate_memory_timing_parameters(hwmgr,
a23eefa2
RZ		 1631 data->dpm_table.sclk_table.dpm_levels[i].value,
1632 data->dpm_table.mclk_table.dpm_levels[j].value,
1633 &arb_regs.entries[i][j]);
1634 if (result == 0)
1635 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1636 if (result != 0)
1637 return result;
1638 }
1639 }
1640
2cc0c0b5 1641 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 1642 hwmgr->smumgr,
1643 data->arb_table_start,
1644 (uint8_t *)&arb_regs,
1645 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1646 data->sram_end);
1647 return result;
1648}
1649
2cc0c0b5 1650static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1651 struct SMU74_Discrete_DpmTable *table)
1652{
1653 int result = -EINVAL;
1654 uint8_t count;
1655 struct pp_atomctrl_clock_dividers_vi dividers;
1656 struct phm_ppt_v1_information *table_info =
1657 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1658 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1659 table_info->mm_dep_table;
2cc0c0b5 1660 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1661
1662 table->UvdLevelCount = (uint8_t)(mm_table->count);
1663 table->UvdBootLevel = 0;
1664
1665 for (count = 0; count < table->UvdLevelCount; count++) {
681ed01c 1666 table->UvdLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1667 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1668 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1669 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1670 VOLTAGE_SCALE) << VDDC_SHIFT;
1671 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1672 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1673 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1674
1675 /* retrieve divider value for VBIOS */
1676 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1677 table->UvdLevel[count].VclkFrequency, &dividers);
1678 PP_ASSERT_WITH_CODE((0 == result),
1679 "can not find divide id for Vclk clock", return result);
1680
1681 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1682
1683 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1684 table->UvdLevel[count].DclkFrequency, &dividers);
1685 PP_ASSERT_WITH_CODE((0 == result),
1686 "can not find divide id for Dclk clock", return result);
1687
1688 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1689
1690 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1691 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1692 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1693
1694 }
1695 return result;
1696}
1697
2cc0c0b5 1698static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1699 struct SMU74_Discrete_DpmTable *table)
1700{
1701 int result = 0;
2cc0c0b5 1702 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1703
1704 table->GraphicsBootLevel = 0;
1705 table->MemoryBootLevel = 0;
1706
1707 /* find boot level from dpm table */
1708 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1709 data->vbios_boot_state.sclk_bootup_value,
1710 (uint32_t *)&(table->GraphicsBootLevel));
1711
1712 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1713 data->vbios_boot_state.mclk_bootup_value,
1714 (uint32_t *)&(table->MemoryBootLevel));
1715
1716 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1717 VOLTAGE_SCALE;
1718 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1719 VOLTAGE_SCALE;
1720 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1721 VOLTAGE_SCALE;
1722
1723 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1724 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1725 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1726
1727 return 0;
1728}
1729
1730
2cc0c0b5 1731static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
a23eefa2 1732{
2cc0c0b5 1733 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1734 struct phm_ppt_v1_information *table_info =
1735 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1736 uint8_t count, level;
1737
1738 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1739
1740 for (level = 0; level < count; level++) {
1741 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1742 data->vbios_boot_state.sclk_bootup_value) {
1743 data->smc_state_table.GraphicsBootLevel = level;
1744 break;
1745 }
1746 }
1747
1748 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1749 for (level = 0; level < count; level++) {
1750 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1751 data->vbios_boot_state.mclk_bootup_value) {
1752 data->smc_state_table.MemoryBootLevel = level;
1753 break;
1754 }
1755 }
1756
1757 return 0;
1758}
1759
2cc0c0b5 1760static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1761{
1762 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1763 volt_with_cks, value;
1764 uint16_t clock_freq_u16;
2cc0c0b5 1765 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1766 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1767 volt_offset = 0;
1768 struct phm_ppt_v1_information *table_info =
1769 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1770 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1771 table_info->vdd_dep_on_sclk;
1772
1773 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1774
1775 /* Read SMU_Eefuse to read and calculate RO and determine
1776 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1777 */
1778 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1779 ixSMU_EFUSE_0 + (146 * 4));
1780 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1781 ixSMU_EFUSE_0 + (148 * 4));
1782 efuse &= 0xFF000000;
1783 efuse = efuse >> 24;
1784 efuse2 &= 0xF;
1785
1786 if (efuse2 == 1)
1787 ro = (2300 - 1350) * efuse / 255 + 1350;
1788 else
1789 ro = (2500 - 1000) * efuse / 255 + 1000;
1790
1791 if (ro >= 1660)
1792 type = 0;
1793 else
1794 type = 1;
1795
1796 /* Populate Stretch amount */
1797 data->smc_state_table.ClockStretcherAmount = stretch_amount;
1798
1799 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1800 for (i = 0; i < sclk_table->count; i++) {
1801 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1802 sclk_table->entries[i].cks_enable << i;
1803 volt_without_cks = (uint32_t)((14041 *
1804 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1805 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1806 volt_with_cks = (uint32_t)((13946 *
1807 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1808 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1809 if (volt_without_cks >= volt_with_cks)
1810 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1811 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1812 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1813 }
1814
1815 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1816 STRETCH_ENABLE, 0x0);
1817 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1818 masterReset, 0x1);
1819 /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1820 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1821 masterReset, 0x0);
1822
1823 /* Populate CKS Lookup Table */
1824 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1825 stretch_amount2 = 0;
1826 else if (stretch_amount == 3 || stretch_amount == 4)
1827 stretch_amount2 = 1;
1828 else {
1829 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1830 PHM_PlatformCaps_ClockStretcher);
1831 PP_ASSERT_WITH_CODE(false,
1832 "Stretch Amount in PPTable not supported\n",
1833 return -EINVAL);
1834 }
1835
1836 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1837 ixPWR_CKS_CNTL);
1838 value &= 0xFFC2FF87;
1839 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2cc0c0b5 1840 polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
a23eefa2 1841 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2cc0c0b5 1842 polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
a23eefa2
RZ		 1843 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1844 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
2cc0c0b5
FC		 1845 if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1846 && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
a23eefa2 1847 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2cc0c0b5 1848 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
a23eefa2 1849 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2cc0c0b5 1850 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
a23eefa2 1851 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2cc0c0b5
FC		 1852 value |= (polaris10_clock_stretch_amount_conversion
1853 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
a23eefa2
RZ		 1854 [stretch_amount]) << 3;
1855 }
1856 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1857 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1858 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2cc0c0b5 1859 polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
a23eefa2 1860 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2cc0c0b5 1861 (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
a23eefa2
RZ		 1862
1863 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1864 ixPWR_CKS_CNTL, value);
1865
1866 /* Populate DDT Lookup Table */
1867 for (i = 0; i < 4; i++) {
1868 /* Assign the minimum and maximum VID stored
1869 * in the last row of Clock Stretcher Voltage Table.
1870 */
1871 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
2cc0c0b5 1872 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
a23eefa2 1873 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
2cc0c0b5 1874 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
a23eefa2
RZ		 1875 /* Loop through each SCLK and check the frequency
1876 * to see if it lies within the frequency for clock stretcher.
1877 */
1878 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1879 cks_setting = 0;
1880 clock_freq = PP_SMC_TO_HOST_UL(
1881 data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1882 /* Check the allowed frequency against the sclk level[j].
1883 * Sclk's endianness has already been converted,
1884 * and it's in 10Khz unit,
1885 * as opposed to Data table, which is in Mhz unit.
1886 */
2cc0c0b5 1887 if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
a23eefa2 1888 cks_setting |= 0x2;
2cc0c0b5 1889 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
a23eefa2
RZ		 1890 cks_setting |= 0x1;
1891 }
1892 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1893 |= cks_setting << (j * 2);
1894 }
1895 CONVERT_FROM_HOST_TO_SMC_US(
1896 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1897 }
1898
1899 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1900 value &= 0xFFFFFFFE;
1901 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1902
1903 return 0;
1904}
1905
1906/**
1907* Populates the SMC VRConfig field in DPM table.
1908*
1909* @param hwmgr the address of the hardware manager
1910* @param table the SMC DPM table structure to be populated
1911* @return always 0
1912*/
2cc0c0b5 1913static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1914 struct SMU74_Discrete_DpmTable *table)
1915{
2cc0c0b5 1916 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1917 uint16_t config;
1918
1919 config = VR_MERGED_WITH_VDDC;
1920 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1921
1922 /* Set Vddc Voltage Controller */
2cc0c0b5 1923 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 1924 config = VR_SVI2_PLANE_1;
1925 table->VRConfig |= config;
1926 } else {
1927 PP_ASSERT_WITH_CODE(false,
1928 "VDDC should be on SVI2 control in merged mode!",
1929 );
1930 }
1931 /* Set Vddci Voltage Controller */
2cc0c0b5 1932 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 1933 config = VR_SVI2_PLANE_2; /* only in merged mode */
1934 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2cc0c0b5 1935 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 1936 config = VR_SMIO_PATTERN_1;
1937 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1938 } else {
1939 config = VR_STATIC_VOLTAGE;
1940 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1941 }
1942 /* Set Mvdd Voltage Controller */
2cc0c0b5 1943 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 1944 config = VR_SVI2_PLANE_2;
1945 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2cc0c0b5 1946 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 1947 config = VR_SMIO_PATTERN_2;
1948 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1949 } else {
1950 config = VR_STATIC_VOLTAGE;
1951 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1952 }
1953
1954 return 0;
1955}
1956
432c3a3c
RZ		 1957
1958int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1959{
1960 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1961 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1962 int result = 0;
1963 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1964 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1965 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1966 uint32_t tmp, i;
1967 struct pp_smumgr *smumgr = hwmgr->smumgr;
1968 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1969
1970 struct phm_ppt_v1_information *table_info =
1971 (struct phm_ppt_v1_information *)hwmgr->pptable;
1972 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1973 table_info->vdd_dep_on_sclk;
1974
1975
1976 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1977 return result;
1978
1979 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1980
1981 if (0 == result) {
1982 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1983 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1984 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1985 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1986 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1987 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1988 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1989 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1990 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1991 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1992 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1993 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1994 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1995 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1996 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1997 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1998 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1999 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
2000 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
2001 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
2002 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
2003 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
2004 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
2005 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
2006
2007 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
2008 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
2009 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
2010 }
2011
2012 result = polaris10_read_smc_sram_dword(smumgr,
2013 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
2014 &tmp, data->sram_end);
2015
2016 polaris10_copy_bytes_to_smc(smumgr,
2017 tmp,
2018 (uint8_t *)&AVFS_meanNsigma,
2019 sizeof(AVFS_meanNsigma_t),
2020 data->sram_end);
2021
2022 result = polaris10_read_smc_sram_dword(smumgr,
2023 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
2024 &tmp, data->sram_end);
2025 polaris10_copy_bytes_to_smc(smumgr,
2026 tmp,
2027 (uint8_t *)&AVFS_SclkOffset,
2028 sizeof(AVFS_Sclk_Offset_t),
2029 data->sram_end);
2030
2031 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2032 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2033 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2034 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2035 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2036 }
2037 return result;
2038}
2039
2040
a23eefa2
RZ		 2041/**
2042* Initializes the SMC table and uploads it
2043*
2044* @param hwmgr the address of the powerplay hardware manager.
2045* @return always 0
2046*/
2cc0c0b5 2047static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2048{
2049 int result;
2cc0c0b5 2050 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2051 struct phm_ppt_v1_information *table_info =
2052 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2053 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2cc0c0b5 2054 const struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 2055 uint8_t i;
2056 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
e85c7d66 2057 pp_atomctrl_clock_dividers_vi dividers;
a23eefa2 2058
2cc0c0b5 2059 result = polaris10_setup_default_dpm_tables(hwmgr);
a23eefa2
RZ		 2060 PP_ASSERT_WITH_CODE(0 == result,
2061 "Failed to setup default DPM tables!", return result);
2062
2cc0c0b5
FC		 2063 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2064 polaris10_populate_smc_voltage_tables(hwmgr, table);
a23eefa2 2065
681ed01c 2066 table->SystemFlags = 0;
a23eefa2
RZ		 2067 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2068 PHM_PlatformCaps_AutomaticDCTransition))
2069 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2070
2071 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2072 PHM_PlatformCaps_StepVddc))
2073 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2074
2075 if (data->is_memory_gddr5)
2076 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2077
2078 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2cc0c0b5 2079 result = polaris10_populate_ulv_state(hwmgr, table);
a23eefa2
RZ		 2080 PP_ASSERT_WITH_CODE(0 == result,
2081 "Failed to initialize ULV state!", return result);
2082 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2cc0c0b5 2083 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
a23eefa2
RZ		 2084 }
2085
2cc0c0b5 2086 result = polaris10_populate_smc_link_level(hwmgr, table);
a23eefa2
RZ		 2087 PP_ASSERT_WITH_CODE(0 == result,
2088 "Failed to initialize Link Level!", return result);
2089
2cc0c0b5 2090 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 2091 PP_ASSERT_WITH_CODE(0 == result,
2092 "Failed to initialize Graphics Level!", return result);
2093
2cc0c0b5 2094 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 2095 PP_ASSERT_WITH_CODE(0 == result,
2096 "Failed to initialize Memory Level!", return result);
2097
2cc0c0b5 2098 result = polaris10_populate_smc_acpi_level(hwmgr, table);
a23eefa2
RZ		 2099 PP_ASSERT_WITH_CODE(0 == result,
2100 "Failed to initialize ACPI Level!", return result);
2101
2cc0c0b5 2102 result = polaris10_populate_smc_vce_level(hwmgr, table);
a23eefa2
RZ		 2103 PP_ASSERT_WITH_CODE(0 == result,
2104 "Failed to initialize VCE Level!", return result);
2105
2cc0c0b5 2106 result = polaris10_populate_smc_samu_level(hwmgr, table);
a23eefa2
RZ		 2107 PP_ASSERT_WITH_CODE(0 == result,
2108 "Failed to initialize SAMU Level!", return result);
2109
2110 /* Since only the initial state is completely set up at this point
2111 * (the other states are just copies of the boot state) we only
2112 * need to populate the ARB settings for the initial state.
2113 */
2cc0c0b5 2114 result = polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 2115 PP_ASSERT_WITH_CODE(0 == result,
2116 "Failed to Write ARB settings for the initial state.", return result);
2117
2cc0c0b5 2118 result = polaris10_populate_smc_uvd_level(hwmgr, table);
a23eefa2
RZ		 2119 PP_ASSERT_WITH_CODE(0 == result,
2120 "Failed to initialize UVD Level!", return result);
2121
2cc0c0b5 2122 result = polaris10_populate_smc_boot_level(hwmgr, table);
a23eefa2
RZ		 2123 PP_ASSERT_WITH_CODE(0 == result,
2124 "Failed to initialize Boot Level!", return result);
2125
2cc0c0b5 2126 result = polaris10_populate_smc_initailial_state(hwmgr);
a23eefa2
RZ		 2127 PP_ASSERT_WITH_CODE(0 == result,
2128 "Failed to initialize Boot State!", return result);
2129
2cc0c0b5 2130 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
a23eefa2
RZ		 2131 PP_ASSERT_WITH_CODE(0 == result,
2132 "Failed to populate BAPM Parameters!", return result);
2133
2134 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2135 PHM_PlatformCaps_ClockStretcher)) {
2cc0c0b5 2136 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
a23eefa2
RZ		 2137 PP_ASSERT_WITH_CODE(0 == result,
2138 "Failed to populate Clock Stretcher Data Table!",
2139 return result);
2140 }
432c3a3c
RZ		 2141
2142 result = polaris10_populate_avfs_parameters(hwmgr);
2143 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2144
9ab9cf05 2145 table->CurrSclkPllRange = 0xff;
a23eefa2
RZ		 2146 table->GraphicsVoltageChangeEnable = 1;
2147 table->GraphicsThermThrottleEnable = 1;
2148 table->GraphicsInterval = 1;
2149 table->VoltageInterval = 1;
2150 table->ThermalInterval = 1;
2151 table->TemperatureLimitHigh =
2152 table_info->cac_dtp_table->usTargetOperatingTemp *
2cc0c0b5 2153 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2154 table->TemperatureLimitLow =
2155 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2cc0c0b5 2156 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2157 table->MemoryVoltageChangeEnable = 1;
2158 table->MemoryInterval = 1;
2159 table->VoltageResponseTime = 0;
2160 table->PhaseResponseTime = 0;
2161 table->MemoryThermThrottleEnable = 1;
2162 table->PCIeBootLinkLevel = 0;
2163 table->PCIeGenInterval = 1;
681ed01c 2164 table->VRConfig = 0;
a23eefa2 2165
2cc0c0b5 2166 result = polaris10_populate_vr_config(hwmgr, table);
a23eefa2
RZ		 2167 PP_ASSERT_WITH_CODE(0 == result,
2168 "Failed to populate VRConfig setting!", return result);
2169
2170 table->ThermGpio = 17;
2171 table->SclkStepSize = 0x4000;
2172
2173 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2174 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2175 } else {
2cc0c0b5 2176 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2177 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2178 PHM_PlatformCaps_RegulatorHot);
2179 }
2180
2181 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2182 &gpio_pin)) {
2183 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2184 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2185 PHM_PlatformCaps_AutomaticDCTransition);
2186 } else {
2cc0c0b5 2187 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2188 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2189 PHM_PlatformCaps_AutomaticDCTransition);
2190 }
2191
2192 /* Thermal Output GPIO */
2193 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2194 &gpio_pin)) {
2195 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2196 PHM_PlatformCaps_ThermalOutGPIO);
2197
2198 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2199
2200 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2201 * since VBIOS will program this register to set 'inactive state',
2202 * driver can then determine 'active state' from this and
2203 * program SMU with correct polarity
2204 */
2205 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2206 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2207 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2208
2209 /* if required, combine VRHot/PCC with thermal out GPIO */
2210 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2211 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2212 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2213 } else {
2214 table->ThermOutGpio = 17;
2215 table->ThermOutPolarity = 1;
2216 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2217 }
2218
e85c7d66 2219 /* Populate BIF_SCLK levels into SMC DPM table */
2220 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2221 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2222 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2223
2224 if (i == 0)
2225 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2226 else
2227 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2228 }
2229
a23eefa2
RZ		 2230 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2231 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2232
2233 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2234 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2235 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2236 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2237 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
9ab9cf05 2238 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
a23eefa2
RZ		 2239 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2240 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2241 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2242 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2243
2244 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2cc0c0b5 2245 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
a23eefa2
RZ		 2246 data->dpm_table_start +
2247 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2248 (uint8_t *)&(table->SystemFlags),
2249 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2250 data->sram_end);
2251 PP_ASSERT_WITH_CODE(0 == result,
2252 "Failed to upload dpm data to SMC memory!", return result);
2253
2254 return 0;
2255}
2256
2257/**
2258* Initialize the ARB DRAM timing table's index field.
2259*
2260* @param hwmgr the address of the powerplay hardware manager.
2261* @return always 0
2262*/
2cc0c0b5 2263static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
a23eefa2 2264{
2cc0c0b5 2265 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2266 uint32_t tmp;
2267 int result;
2268
2269 /* This is a read-modify-write on the first byte of the ARB table.
2270 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2271 * is the field 'current'.
2272 * This solution is ugly, but we never write the whole table only
2273 * individual fields in it.
2274 * In reality this field should not be in that structure
2275 * but in a soft register.
2276 */
2cc0c0b5 2277 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2278 data->arb_table_start, &tmp, data->sram_end);
2279
2280 if (result)
2281 return result;
2282
2283 tmp &= 0x00FFFFFF;
2284 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2285
2cc0c0b5 2286 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2287 data->arb_table_start, tmp, data->sram_end);
2288}
2289
2cc0c0b5 2290static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2291{
2292 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2293 PHM_PlatformCaps_RegulatorHot))
2294 return smum_send_msg_to_smc(hwmgr->smumgr,
2295 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2296
2297 return 0;
2298}
2299
2cc0c0b5 2300static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2301{
2302 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2303 SCLK_PWRMGT_OFF, 0);
2304 return 0;
2305}
2306
2cc0c0b5 2307static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
a23eefa2 2308{
2cc0c0b5
FC		 2309 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2310 struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 2311
2312 if (ulv->ulv_supported)
2313 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2314
2315 return 0;
2316}
2317
2cc0c0b5 2318static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2319{
2320 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2321 PHM_PlatformCaps_SclkDeepSleep)) {
2322 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2323 PP_ASSERT_WITH_CODE(false,
2324 "Attempt to enable Master Deep Sleep switch failed!",
2325 return -1);
2326 } else {
2327 if (smum_send_msg_to_smc(hwmgr->smumgr,
2328 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2329 PP_ASSERT_WITH_CODE(false,
2330 "Attempt to disable Master Deep Sleep switch failed!",
2331 return -1);
2332 }
2333 }
2334
2335 return 0;
2336}
2337
2cc0c0b5 2338static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2339{
2cc0c0b5 2340 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
40787ef2
RZ		 2341 uint32_t soft_register_value = 0;
2342 uint32_t handshake_disables_offset = data->soft_regs_start
2343 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
a23eefa2
RZ		 2344
2345 /* enable SCLK dpm */
2346 if (!data->sclk_dpm_key_disabled)
2347 PP_ASSERT_WITH_CODE(
2348 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2349 "Failed to enable SCLK DPM during DPM Start Function!",
2350 return -1);
2351
2352 /* enable MCLK dpm */
2353 if (0 == data->mclk_dpm_key_disabled) {
40787ef2
RZ		 2354/* Disable UVD - SMU handshake for MCLK. */
2355 soft_register_value = cgs_read_ind_register(hwmgr->device,
2356 CGS_IND_REG__SMC, handshake_disables_offset);
2357 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2358 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2359 handshake_disables_offset, soft_register_value);
a23eefa2
RZ		 2360
2361 PP_ASSERT_WITH_CODE(
2362 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2363 PPSMC_MSG_MCLKDPM_Enable)),
2364 "Failed to enable MCLK DPM during DPM Start Function!",
2365 return -1);
2366
a23eefa2
RZ		 2367 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2368
2369 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2370 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2371 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2372 udelay(10);
2373 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2375 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2376 }
2377
2378 return 0;
2379}
2380
2cc0c0b5 2381static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2382{
2cc0c0b5 2383 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2384
2385 /*enable general power management */
2386
2387 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2388 GLOBAL_PWRMGT_EN, 1);
2389
2390 /* enable sclk deep sleep */
2391
2392 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2393 DYNAMIC_PM_EN, 1);
2394
2395 /* prepare for PCIE DPM */
2396
2397 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2398 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2399 VoltageChangeTimeout), 0x1000);
2400 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2401 SWRST_COMMAND_1, RESETLC, 0x0);
e85c7d66 2402/*
a23eefa2
RZ		 2403 PP_ASSERT_WITH_CODE(
2404 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2405 PPSMC_MSG_Voltage_Cntl_Enable)),
2406 "Failed to enable voltage DPM during DPM Start Function!",
2407 return -1);
e85c7d66 2408*/
a23eefa2 2409
2cc0c0b5 2410 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
a23eefa2
RZ		 2411 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2412 return -1;
2413 }
2414
2415 /* enable PCIE dpm */
2416 if (0 == data->pcie_dpm_key_disabled) {
2417 PP_ASSERT_WITH_CODE(
2418 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2419 PPSMC_MSG_PCIeDPM_Enable)),
2420 "Failed to enable pcie DPM during DPM Start Function!",
2421 return -1);
2422 }
2423
c8c67448
EH		 2424 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2425 PHM_PlatformCaps_Falcon_QuickTransition)) {
2426 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2427 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2428 "Failed to enable AC DC GPIO Interrupt!",
2429 );
2430 }
a23eefa2
RZ		 2431
2432 return 0;
2433}
2434
2cc0c0b5 2435static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
a23eefa2
RZ		 2436{
2437 bool protection;
2438 enum DPM_EVENT_SRC src;
2439
2440 switch (sources) {
2441 default:
2442 printk(KERN_ERR "Unknown throttling event sources.");
2443 /* fall through */
2444 case 0:
2445 protection = false;
2446 /* src is unused */
2447 break;
2448 case (1 << PHM_AutoThrottleSource_Thermal):
2449 protection = true;
2450 src = DPM_EVENT_SRC_DIGITAL;
2451 break;
2452 case (1 << PHM_AutoThrottleSource_External):
2453 protection = true;
2454 src = DPM_EVENT_SRC_EXTERNAL;
2455 break;
2456 case (1 << PHM_AutoThrottleSource_External) |
2457 (1 << PHM_AutoThrottleSource_Thermal):
2458 protection = true;
2459 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2460 break;
2461 }
2462 /* Order matters - don't enable thermal protection for the wrong source. */
2463 if (protection) {
2464 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2465 DPM_EVENT_SRC, src);
2466 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2467 THERMAL_PROTECTION_DIS,
f0911de8 2468 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
a23eefa2
RZ		 2469 PHM_PlatformCaps_ThermalController));
2470 } else
2471 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2472 THERMAL_PROTECTION_DIS, 1);
2473}
2474
2cc0c0b5 2475static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 2476 PHM_AutoThrottleSource source)
2477{
2cc0c0b5 2478 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2479
2480 if (!(data->active_auto_throttle_sources & (1 << source))) {
2481 data->active_auto_throttle_sources |= 1 << source;
2cc0c0b5 2482 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
a23eefa2
RZ		 2483 }
2484 return 0;
2485}
2486
2cc0c0b5 2487static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
a23eefa2 2488{
2cc0c0b5 2489 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
a23eefa2
RZ		 2490}
2491
2cc0c0b5 2492int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
a23eefa2 2493{
2cc0c0b5 2494 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2495 data->pcie_performance_request = true;
2496
2497 return 0;
2498}
2499
2cc0c0b5 2500int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2501{
2502 int tmp_result, result = 0;
2cc0c0b5 2503 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
a23eefa2
RZ		 2504 PP_ASSERT_WITH_CODE(result == 0,
2505 "DPM is already running right now, no need to enable DPM!",
2506 return 0);
2507
2cc0c0b5
FC		 2508 if (polaris10_voltage_control(hwmgr)) {
2509 tmp_result = polaris10_enable_voltage_control(hwmgr);
a23eefa2
RZ		 2510 PP_ASSERT_WITH_CODE(tmp_result == 0,
2511 "Failed to enable voltage control!",
2512 result = tmp_result);
2513
2cc0c0b5 2514 tmp_result = polaris10_construct_voltage_tables(hwmgr);
a23eefa2
RZ		 2515 PP_ASSERT_WITH_CODE((0 == tmp_result),
2516 "Failed to contruct voltage tables!",
2517 result = tmp_result);
2518 }
2519
2520 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2521 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2522 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2523 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2524
2525 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2526 PHM_PlatformCaps_ThermalController))
2527 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2528 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2529
2cc0c0b5 2530 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
a23eefa2
RZ		 2531 PP_ASSERT_WITH_CODE((0 == tmp_result),
2532 "Failed to program static screen threshold parameters!",
2533 result = tmp_result);
2534
2cc0c0b5 2535 tmp_result = polaris10_enable_display_gap(hwmgr);
a23eefa2
RZ		 2536 PP_ASSERT_WITH_CODE((0 == tmp_result),
2537 "Failed to enable display gap!", result = tmp_result);
2538
2cc0c0b5 2539 tmp_result = polaris10_program_voting_clients(hwmgr);
a23eefa2
RZ		 2540 PP_ASSERT_WITH_CODE((0 == tmp_result),
2541 "Failed to program voting clients!", result = tmp_result);
2542
2cc0c0b5 2543 tmp_result = polaris10_process_firmware_header(hwmgr);
a23eefa2
RZ		 2544 PP_ASSERT_WITH_CODE((0 == tmp_result),
2545 "Failed to process firmware header!", result = tmp_result);
2546
2cc0c0b5 2547 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
a23eefa2
RZ		 2548 PP_ASSERT_WITH_CODE((0 == tmp_result),
2549 "Failed to initialize switch from ArbF0 to F1!",
2550 result = tmp_result);
2551
2cc0c0b5 2552 tmp_result = polaris10_init_smc_table(hwmgr);
a23eefa2
RZ		 2553 PP_ASSERT_WITH_CODE((0 == tmp_result),
2554 "Failed to initialize SMC table!", result = tmp_result);
2555
2cc0c0b5 2556 tmp_result = polaris10_init_arb_table_index(hwmgr);
a23eefa2
RZ		 2557 PP_ASSERT_WITH_CODE((0 == tmp_result),
2558 "Failed to initialize ARB table index!", result = tmp_result);
2559
2cc0c0b5 2560 tmp_result = polaris10_populate_pm_fuses(hwmgr);
a23eefa2
RZ		 2561 PP_ASSERT_WITH_CODE((0 == tmp_result),
2562 "Failed to populate PM fuses!", result = tmp_result);
2563
2cc0c0b5 2564 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
a23eefa2
RZ		 2565 PP_ASSERT_WITH_CODE((0 == tmp_result),
2566 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2567
2cc0c0b5 2568 tmp_result = polaris10_enable_sclk_control(hwmgr);
a23eefa2
RZ		 2569 PP_ASSERT_WITH_CODE((0 == tmp_result),
2570 "Failed to enable SCLK control!", result = tmp_result);
2571
2cc0c0b5 2572 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
e85c7d66 2573 PP_ASSERT_WITH_CODE((0 == tmp_result),
2574 "Failed to enable voltage control!", result = tmp_result);
2575
2cc0c0b5 2576 tmp_result = polaris10_enable_ulv(hwmgr);
a23eefa2
RZ		 2577 PP_ASSERT_WITH_CODE((0 == tmp_result),
2578 "Failed to enable ULV!", result = tmp_result);
2579
2cc0c0b5 2580 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
a23eefa2
RZ		 2581 PP_ASSERT_WITH_CODE((0 == tmp_result),
2582 "Failed to enable deep sleep master switch!", result = tmp_result);
2583
2cc0c0b5 2584 tmp_result = polaris10_start_dpm(hwmgr);
a23eefa2
RZ		 2585 PP_ASSERT_WITH_CODE((0 == tmp_result),
2586 "Failed to start DPM!", result = tmp_result);
2587
2cc0c0b5 2588 tmp_result = polaris10_enable_smc_cac(hwmgr);
a23eefa2
RZ		 2589 PP_ASSERT_WITH_CODE((0 == tmp_result),
2590 "Failed to enable SMC CAC!", result = tmp_result);
2591
2cc0c0b5 2592 tmp_result = polaris10_enable_power_containment(hwmgr);
a23eefa2
RZ		 2593 PP_ASSERT_WITH_CODE((0 == tmp_result),
2594 "Failed to enable power containment!", result = tmp_result);
2595
2cc0c0b5 2596 tmp_result = polaris10_power_control_set_level(hwmgr);
a23eefa2
RZ		 2597 PP_ASSERT_WITH_CODE((0 == tmp_result),
2598 "Failed to power control set level!", result = tmp_result);
2599
2cc0c0b5 2600 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
a23eefa2
RZ		 2601 PP_ASSERT_WITH_CODE((0 == tmp_result),
2602 "Failed to enable thermal auto throttle!", result = tmp_result);
2603
2cc0c0b5 2604 tmp_result = polaris10_pcie_performance_request(hwmgr);
a23eefa2 2605 PP_ASSERT_WITH_CODE((0 == tmp_result),
5f88567c 2606 "pcie performance request failed!", result = tmp_result);
a23eefa2
RZ		 2607
2608 return result;
2609}
2610
2cc0c0b5 2611int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2612{
2613
2614 return 0;
2615}
2616
2cc0c0b5 2617int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2618{
2619
2620 return 0;
2621}
2622
2cc0c0b5 2623int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
a23eefa2 2624{
a72d5604
EH		 2625 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2626
2627 if (data->soft_pp_table) {
2628 kfree(data->soft_pp_table);
2629 data->soft_pp_table = NULL;
2630 }
2631
a23eefa2
RZ		 2632 return phm_hwmgr_backend_fini(hwmgr);
2633}
2634
2cc0c0b5 2635int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
a23eefa2 2636{
2cc0c0b5 2637 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2638
2639 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2640 PHM_PlatformCaps_SclkDeepSleep);
2641
f0911de8
RZ		 2642 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2643 PHM_PlatformCaps_DynamicPatchPowerState);
2644
2cc0c0b5 2645 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2646 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2647 PHM_PlatformCaps_EnableMVDDControl);
2648
2cc0c0b5 2649 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2650 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2651 PHM_PlatformCaps_ControlVDDCI);
2652
2653 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2654 PHM_PlatformCaps_TablelessHardwareInterface);
2655
2656 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2657 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2658
2659 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2660 PHM_PlatformCaps_DynamicPowerManagement);
2661
f0911de8
RZ		 2662 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2663 PHM_PlatformCaps_UnTabledHardwareInterface);
2664
a23eefa2
RZ		 2665 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2666 PHM_PlatformCaps_TablelessHardwareInterface);
2667
2668 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2669 PHM_PlatformCaps_SMC);
2670
2671 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2672 PHM_PlatformCaps_NonABMSupportInPPLib);
2673
2674 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2675 PHM_PlatformCaps_DynamicUVDState);
2676
a23eefa2 2677 /* power tune caps Assume disabled */
a23eefa2
RZ		 2678 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2679 PHM_PlatformCaps_SQRamping);
2680 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2681 PHM_PlatformCaps_DBRamping);
2682 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2683 PHM_PlatformCaps_TDRamping);
2684 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2685 PHM_PlatformCaps_TCPRamping);
2686
f0911de8
RZ		 2687 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2688 PHM_PlatformCaps_PowerContainment);
2689 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2690 PHM_PlatformCaps_CAC);
2691
2692 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2693 PHM_PlatformCaps_RegulatorHot);
2694
2695 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2696 PHM_PlatformCaps_AutomaticDCTransition);
2697
2698 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2699 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2700
2701 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2702 PHM_PlatformCaps_FanSpeedInTableIsRPM);
919e334d 2703
5de95e55
RZ		 2704 if (hwmgr->chip_id == CHIP_POLARIS11)
2705 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2706 PHM_PlatformCaps_SPLLShutdownSupport);
a23eefa2
RZ		 2707 return 0;
2708}
2709
2cc0c0b5 2710static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
a23eefa2 2711{
2cc0c0b5 2712 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 2713
2cc0c0b5 2714 polaris10_initialize_power_tune_defaults(hwmgr);
a23eefa2
RZ		 2715
2716 data->pcie_gen_performance.max = PP_PCIEGen1;
2717 data->pcie_gen_performance.min = PP_PCIEGen3;
2718 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2719 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2720 data->pcie_lane_performance.max = 0;
2721 data->pcie_lane_performance.min = 16;
2722 data->pcie_lane_power_saving.max = 0;
2723 data->pcie_lane_power_saving.min = 16;
2724}
2725
2726/**
2727* Get Leakage VDDC based on leakage ID.
2728*
2729* @param hwmgr the address of the powerplay hardware manager.
2730* @return always 0
2731*/
2cc0c0b5 2732static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
a23eefa2 2733{
2cc0c0b5 2734 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2735 uint16_t vv_id;
2736 uint16_t vddc = 0;
2737 uint16_t i, j;
2738 uint32_t sclk = 0;
2739 struct phm_ppt_v1_information *table_info =
2740 (struct phm_ppt_v1_information *)hwmgr->pptable;
2741 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2742 table_info->vdd_dep_on_sclk;
2743 int result;
2744
2cc0c0b5 2745 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
a23eefa2
RZ		 2746 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2747 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2748 table_info->vddc_lookup_table, vv_id, &sclk)) {
2749 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2750 PHM_PlatformCaps_ClockStretcher)) {
2751 for (j = 1; j < sclk_table->count; j++) {
2752 if (sclk_table->entries[j].clk == sclk &&
2753 sclk_table->entries[j].cks_enable == 0) {
2754 sclk += 5000;
2755 break;
2756 }
2757 }
2758 }
2759
2760
2761 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2762 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2763 "Error retrieving EVV voltage value!",
2764 continue);
2765
2766
2767 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2768 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2769 "Invalid VDDC value", result = -EINVAL;);
2770
2771 /* the voltage should not be zero nor equal to leakage ID */
2772 if (vddc != 0 && vddc != vv_id) {
2773 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2774 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2775 data->vddc_leakage.count++;
2776 }
2777 }
2778 }
2779
2780 return 0;
2781}
2782
2783/**
2784 * Change virtual leakage voltage to actual value.
2785 *
2786 * @param hwmgr the address of the powerplay hardware manager.
2787 * @param pointer to changing voltage
2788 * @param pointer to leakage table
2789 */
2cc0c0b5
FC		 2790static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2791 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2792{
2793 uint32_t index;
2794
2795 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2796 for (index = 0; index < leakage_table->count; index++) {
2797 /* if this voltage matches a leakage voltage ID */
2798 /* patch with actual leakage voltage */
2799 if (leakage_table->leakage_id[index] == *voltage) {
2800 *voltage = leakage_table->actual_voltage[index];
2801 break;
2802 }
2803 }
2804
2805 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2806 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2807}
2808
2809/**
2810* Patch voltage lookup table by EVV leakages.
2811*
2812* @param hwmgr the address of the powerplay hardware manager.
2813* @param pointer to voltage lookup table
2814* @param pointer to leakage table
2815* @return always 0
2816*/
2cc0c0b5 2817static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
a23eefa2 2818 phm_ppt_v1_voltage_lookup_table *lookup_table,
2cc0c0b5 2819 struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2820{
2821 uint32_t i;
2822
2823 for (i = 0; i < lookup_table->count; i++)
2cc0c0b5 2824 polaris10_patch_with_vdd_leakage(hwmgr,
a23eefa2
RZ		 2825 &lookup_table->entries[i].us_vdd, leakage_table);
2826
2827 return 0;
2828}
2829
2cc0c0b5
FC		 2830static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2831 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
a23eefa2
RZ		 2832 uint16_t *vddc)
2833{
2834 struct phm_ppt_v1_information *table_info =
2835 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2cc0c0b5 2836 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
a23eefa2
RZ		 2837 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2838 table_info->max_clock_voltage_on_dc.vddc;
2839 return 0;
2840}
2841
2cc0c0b5 2842static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
a23eefa2
RZ		 2843 struct pp_hwmgr *hwmgr)
2844{
2845 uint8_t entryId;
2846 uint8_t voltageId;
2847 struct phm_ppt_v1_information *table_info =
2848 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2849
2850 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2851 table_info->vdd_dep_on_sclk;
2852 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2853 table_info->vdd_dep_on_mclk;
2854 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2855 table_info->mm_dep_table;
2856
2857 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2858 voltageId = sclk_table->entries[entryId].vddInd;
2859 sclk_table->entries[entryId].vddc =
2860 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2861 }
2862
2863 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2864 voltageId = mclk_table->entries[entryId].vddInd;
2865 mclk_table->entries[entryId].vddc =
2866 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2867 }
2868
2869 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2870 voltageId = mm_table->entries[entryId].vddcInd;
2871 mm_table->entries[entryId].vddc =
2872 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2873 }
2874
2875 return 0;
2876
2877}
2878
2cc0c0b5 2879static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2880{
2881 /* Need to determine if we need calculated voltage. */
2882 return 0;
2883}
2884
2cc0c0b5 2885static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2886{
2887 /* Need to determine if we need calculated voltage from mm table. */
2888 return 0;
2889}
2890
2cc0c0b5 2891static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 2892 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2893{
2894 uint32_t table_size, i, j;
2895 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2896 table_size = lookup_table->count;
2897
2898 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2899 "Lookup table is empty", return -EINVAL);
2900
2901 /* Sorting voltages */
2902 for (i = 0; i < table_size - 1; i++) {
2903 for (j = i + 1; j > 0; j--) {
2904 if (lookup_table->entries[j].us_vdd <
2905 lookup_table->entries[j - 1].us_vdd) {
2906 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2907 lookup_table->entries[j - 1] = lookup_table->entries[j];
2908 lookup_table->entries[j] = tmp_voltage_lookup_record;
2909 }
2910 }
2911 }
2912
2913 return 0;
2914}
2915
2cc0c0b5 2916static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2917{
2918 int result = 0;
2919 int tmp_result;
2cc0c0b5 2920 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2921 struct phm_ppt_v1_information *table_info =
2922 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2923
2cc0c0b5 2924 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
a23eefa2
RZ		 2925 table_info->vddc_lookup_table, &(data->vddc_leakage));
2926 if (tmp_result)
2927 result = tmp_result;
2928
2cc0c0b5 2929 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
a23eefa2
RZ		 2930 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2931 if (tmp_result)
2932 result = tmp_result;
2933
2cc0c0b5 2934 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
a23eefa2
RZ		 2935 if (tmp_result)
2936 result = tmp_result;
2937
2cc0c0b5 2938 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
a23eefa2
RZ		 2939 if (tmp_result)
2940 result = tmp_result;
2941
2cc0c0b5 2942 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
a23eefa2
RZ		 2943 if (tmp_result)
2944 result = tmp_result;
2945
2cc0c0b5 2946 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
a23eefa2
RZ		 2947 if (tmp_result)
2948 result = tmp_result;
2949
2950 return result;
2951}
2952
2cc0c0b5 2953static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2954{
2955 struct phm_ppt_v1_information *table_info =
2956 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2957
2958 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2959 table_info->vdd_dep_on_sclk;
2960 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2961 table_info->vdd_dep_on_mclk;
2962
2963 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
edf600da 2964 "VDD dependency on SCLK table is missing. \
a23eefa2
RZ		 2965 This table is mandatory", return -EINVAL);
2966 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
edf600da 2967 "VDD dependency on SCLK table has to have is missing. \
a23eefa2
RZ		 2968 This table is mandatory", return -EINVAL);
2969
2970 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
edf600da 2971 "VDD dependency on MCLK table is missing. \
a23eefa2
RZ		 2972 This table is mandatory", return -EINVAL);
2973 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2974 "VDD dependency on MCLK table has to have is missing. \
2975 This table is mandatory", return -EINVAL);
2976
2977 table_info->max_clock_voltage_on_ac.sclk =
2978 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2979 table_info->max_clock_voltage_on_ac.mclk =
2980 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2981 table_info->max_clock_voltage_on_ac.vddc =
2982 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2983 table_info->max_clock_voltage_on_ac.vddci =
2984 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2985
f0911de8
RZ		 2986 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2987 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2988 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2989 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2990
a23eefa2
RZ		 2991 return 0;
2992}
2993
2cc0c0b5 2994int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
a23eefa2 2995{
2cc0c0b5 2996 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2997 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2998 uint32_t temp_reg;
2999 int result;
f0911de8
RZ		 3000 struct phm_ppt_v1_information *table_info =
3001 (struct phm_ppt_v1_information *)(hwmgr->pptable);
a23eefa2
RZ		 3002
3003 data->dll_default_on = false;
3004 data->sram_end = SMC_RAM_END;
7d367c2a 3005 data->mclk_dpm0_activity_target = 0xa;
a23eefa2 3006 data->disable_dpm_mask = 0xFF;
2cc0c0b5
FC		 3007 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3008 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3009 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3010 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3011 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3012 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3013 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3014 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3015 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3016 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3017
3018 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3019 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3020 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3021 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3022 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3023 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3024 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3025 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
a23eefa2
RZ		 3026
3027 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3028
2cc0c0b5 3029 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
a23eefa2
RZ		 3030
3031 /* need to set voltage control types before EVV patching */
2cc0c0b5
FC		 3032 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3033 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3034 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
a23eefa2 3035
919e334d
RZ		 3036 data->enable_tdc_limit_feature = true;
3037 data->enable_pkg_pwr_tracking_feature = true;
a2fb4934 3038 data->force_pcie_gen = PP_PCIEGenInvalid;
9a3c1b34 3039 data->mclk_stutter_mode_threshold = 40000;
919e334d 3040
a23eefa2
RZ		 3041 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3042 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 3043 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2 3044
a23eefa2
RZ		 3045 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3046 PHM_PlatformCaps_EnableMVDDControl)) {
3047 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3048 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 3049 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 3050 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3051 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 3052 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 3053 }
3054
3055 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3056 PHM_PlatformCaps_ControlVDDCI)) {
3057 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3058 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 3059 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 3060 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3061 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2cc0c0b5 3062 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 3063 }
3064
2cc0c0b5 3065 polaris10_set_features_platform_caps(hwmgr);
a23eefa2 3066
2cc0c0b5 3067 polaris10_init_dpm_defaults(hwmgr);
a23eefa2
RZ		 3068
3069 /* Get leakage voltage based on leakage ID. */
2cc0c0b5 3070 result = polaris10_get_evv_voltages(hwmgr);
a23eefa2
RZ		 3071
3072 if (result) {
3073 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
3074 return -1;
3075 }
3076
2cc0c0b5
FC		 3077 polaris10_complete_dependency_tables(hwmgr);
3078 polaris10_set_private_data_based_on_pptable(hwmgr);
a23eefa2
RZ		 3079
3080 /* Initalize Dynamic State Adjustment Rule Settings */
3081 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3082
3083 if (0 == result) {
3084 struct cgs_system_info sys_info = {0};
3085
3086 data->is_tlu_enabled = 0;
3087
3088 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2cc0c0b5 3089 POLARIS10_MAX_HARDWARE_POWERLEVELS;
a23eefa2
RZ		 3090 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3091 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
f0911de8 3092
a23eefa2
RZ		 3093
3094 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3095 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3096 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3097 case 0:
3098 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3099 break;
3100 case 1:
3101 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3102 break;
3103 case 2:
3104 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3105 break;
3106 case 3:
3107 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3108 break;
3109 case 4:
3110 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3111 break;
3112 default:
3113 PP_ASSERT_WITH_CODE(0,
3114 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3115 );
3116 break;
3117 }
3118 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3119 }
3120
f0911de8
RZ		 3121 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3122 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3123 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3124 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3125
3126 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3127 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3128
3129 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3130
3131 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3132
3133 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3134 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3135
3136 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3137
3138 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3139 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3140
3141 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3142 table_info->cac_dtp_table->usOperatingTempStep = 1;
3143 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3144
3145 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3146 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3147
3148 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3149 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3150
3151 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3152 table_info->cac_dtp_table->usOperatingTempMinLimit;
3153
3154 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3155 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3156
3157 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3158 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3159
3160 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3161 table_info->cac_dtp_table->usOperatingTempStep;
3162
3163 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3164 table_info->cac_dtp_table->usTargetOperatingTemp;
3165 }
3166
a23eefa2
RZ		 3167 sys_info.size = sizeof(struct cgs_system_info);
3168 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3169 result = cgs_query_system_info(hwmgr->device, &sys_info);
3170 if (result)
3171 data->pcie_gen_cap = 0x30007;
3172 else
3173 data->pcie_gen_cap = (uint32_t)sys_info.value;
3174 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3175 data->pcie_spc_cap = 20;
3176 sys_info.size = sizeof(struct cgs_system_info);
3177 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3178 result = cgs_query_system_info(hwmgr->device, &sys_info);
3179 if (result)
3180 data->pcie_lane_cap = 0x2f0000;
3181 else
3182 data->pcie_lane_cap = (uint32_t)sys_info.value;
f0911de8
RZ		 3183
3184 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3185/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3186 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3187 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
a23eefa2
RZ		 3188 } else {
3189 /* Ignore return value in here, we are cleaning up a mess. */
2cc0c0b5 3190 polaris10_hwmgr_backend_fini(hwmgr);
a23eefa2
RZ		 3191 }
3192
3193 return 0;
3194}
3195
2cc0c0b5 3196static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
a23eefa2 3197{
2cc0c0b5 3198 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3199 uint32_t level, tmp;
3200
3201 if (!data->pcie_dpm_key_disabled) {
3202 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3203 level = 0;
3204 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3205 while (tmp >>= 1)
3206 level++;
3207
3208 if (level)
3209 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3210 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3211 }
3212 }
3213
3214 if (!data->sclk_dpm_key_disabled) {
3215 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3216 level = 0;
3217 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3218 while (tmp >>= 1)
3219 level++;
3220
3221 if (level)
3222 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3223 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3224 (1 << level));
3225 }
3226 }
3227
3228 if (!data->mclk_dpm_key_disabled) {
3229 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3230 level = 0;
3231 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3232 while (tmp >>= 1)
3233 level++;
3234
3235 if (level)
3236 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3237 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3238 (1 << level));
3239 }
3240 }
3241
3242 return 0;
3243}
3244
2cc0c0b5 3245static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
a23eefa2 3246{
2cc0c0b5 3247 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3248
3249 phm_apply_dal_min_voltage_request(hwmgr);
3250
3251 if (!data->sclk_dpm_key_disabled) {
3252 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3253 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3254 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3255 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3256 }
3257
3258 if (!data->mclk_dpm_key_disabled) {
3259 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3260 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3261 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3262 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3263 }
3264
3265 return 0;
3266}
3267
2cc0c0b5 3268static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
a23eefa2 3269{
2cc0c0b5 3270 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 3271
2cc0c0b5 3272 if (!polaris10_is_dpm_running(hwmgr))
a23eefa2
RZ		 3273 return -EINVAL;
3274
3275 if (!data->pcie_dpm_key_disabled) {
3276 smum_send_msg_to_smc(hwmgr->smumgr,
3277 PPSMC_MSG_PCIeDPM_UnForceLevel);
3278 }
3279
2cc0c0b5 3280 return polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 3281}
3282
2cc0c0b5 3283static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
a23eefa2 3284{
2cc0c0b5
FC		 3285 struct polaris10_hwmgr *data =
3286 (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3287 uint32_t level;
3288
3289 if (!data->sclk_dpm_key_disabled)
3290 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3291 level = phm_get_lowest_enabled_level(hwmgr,
3292 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3293 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3294 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3295 (1 << level));
3296
3297 }
2043f43e 3298
a23eefa2
RZ		 3299 if (!data->mclk_dpm_key_disabled) {
3300 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3301 level = phm_get_lowest_enabled_level(hwmgr,
3302 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3303 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3304 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3305 (1 << level));
3306 }
3307 }
2043f43e 3308
a23eefa2
RZ		 3309 if (!data->pcie_dpm_key_disabled) {
3310 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3311 level = phm_get_lowest_enabled_level(hwmgr,
3312 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3313 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3314 PPSMC_MSG_PCIeDPM_ForceLevel,
3315 (level));
3316 }
3317 }
3318
3319 return 0;
3320
3321}
2cc0c0b5 3322static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3323 enum amd_dpm_forced_level level)
3324{
3325 int ret = 0;
3326
3327 switch (level) {
3328 case AMD_DPM_FORCED_LEVEL_HIGH:
2cc0c0b5 3329 ret = polaris10_force_dpm_highest(hwmgr);
a23eefa2
RZ		 3330 if (ret)
3331 return ret;
3332 break;
3333 case AMD_DPM_FORCED_LEVEL_LOW:
2cc0c0b5 3334 ret = polaris10_force_dpm_lowest(hwmgr);
a23eefa2
RZ		 3335 if (ret)
3336 return ret;
3337 break;
3338 case AMD_DPM_FORCED_LEVEL_AUTO:
2cc0c0b5 3339 ret = polaris10_unforce_dpm_levels(hwmgr);
a23eefa2
RZ		 3340 if (ret)
3341 return ret;
3342 break;
3343 default:
3344 break;
3345 }
3346
3347 hwmgr->dpm_level = level;
3348
3349 return ret;
3350}
3351
2cc0c0b5 3352static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
a23eefa2 3353{
2cc0c0b5 3354 return sizeof(struct polaris10_power_state);
a23eefa2
RZ		 3355}
3356
3357
2cc0c0b5 3358static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3359 struct pp_power_state *request_ps,
3360 const struct pp_power_state *current_ps)
3361{
3362
2cc0c0b5
FC		 3363 struct polaris10_power_state *polaris10_ps =
3364 cast_phw_polaris10_power_state(&request_ps->hardware);
a23eefa2
RZ		 3365 uint32_t sclk;
3366 uint32_t mclk;
3367 struct PP_Clocks minimum_clocks = {0};
3368 bool disable_mclk_switching;
3369 bool disable_mclk_switching_for_frame_lock;
3370 struct cgs_display_info info = {0};
3371 const struct phm_clock_and_voltage_limits *max_limits;
3372 uint32_t i;
2cc0c0b5 3373 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3374 struct phm_ppt_v1_information *table_info =
3375 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3376 int32_t count;
3377 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3378
3379 data->battery_state = (PP_StateUILabel_Battery ==
3380 request_ps->classification.ui_label);
3381
2cc0c0b5 3382 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
a23eefa2
RZ		 3383 "VI should always have 2 performance levels",
3384 );
3385
3386 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3387 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3388 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3389
3390 /* Cap clock DPM tables at DC MAX if it is in DC. */
3391 if (PP_PowerSource_DC == hwmgr->power_source) {
2cc0c0b5
FC		 3392 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3393 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3394 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3395 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3396 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
a23eefa2
RZ		 3397 }
3398 }
3399
2cc0c0b5
FC		 3400 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3401 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
a23eefa2
RZ		 3402
3403 cgs_get_active_displays_info(hwmgr->device, &info);
3404
3405 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3406
3407 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3408
3409 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3410 PHM_PlatformCaps_StablePState)) {
3411 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3412 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3413
3414 for (count = table_info->vdd_dep_on_sclk->count - 1;
3415 count >= 0; count--) {
3416 if (stable_pstate_sclk >=
3417 table_info->vdd_dep_on_sclk->entries[count].clk) {
3418 stable_pstate_sclk =
3419 table_info->vdd_dep_on_sclk->entries[count].clk;
3420 break;
3421 }
3422 }
3423
3424 if (count < 0)
3425 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3426
3427 stable_pstate_mclk = max_limits->mclk;
3428
3429 minimum_clocks.engineClock = stable_pstate_sclk;
3430 minimum_clocks.memoryClock = stable_pstate_mclk;
3431 }
3432
3433 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3434 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3435
3436 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3437 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3438
2cc0c0b5 3439 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
a23eefa2
RZ		 3440
3441 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3442 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3443 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3444 "Overdrive sclk exceeds limit",
3445 hwmgr->gfx_arbiter.sclk_over_drive =
3446 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3447
3448 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
2cc0c0b5 3449 polaris10_ps->performance_levels[1].engine_clock =
a23eefa2
RZ		 3450 hwmgr->gfx_arbiter.sclk_over_drive;
3451 }
3452
3453 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3454 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3455 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3456 "Overdrive mclk exceeds limit",
3457 hwmgr->gfx_arbiter.mclk_over_drive =
3458 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3459
3460 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
2cc0c0b5 3461 polaris10_ps->performance_levels[1].memory_clock =
a23eefa2
RZ		 3462 hwmgr->gfx_arbiter.mclk_over_drive;
3463 }
3464
3465 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3466 hwmgr->platform_descriptor.platformCaps,
3467 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3468
3469 disable_mclk_switching = (1 < info.display_count) ||
3470 disable_mclk_switching_for_frame_lock;
3471
2cc0c0b5
FC		 3472 sclk = polaris10_ps->performance_levels[0].engine_clock;
3473 mclk = polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3474
3475 if (disable_mclk_switching)
2cc0c0b5
FC		 3476 mclk = polaris10_ps->performance_levels
3477 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 3478
3479 if (sclk < minimum_clocks.engineClock)
3480 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3481 max_limits->sclk : minimum_clocks.engineClock;
3482
3483 if (mclk < minimum_clocks.memoryClock)
3484 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3485 max_limits->mclk : minimum_clocks.memoryClock;
3486
2cc0c0b5
FC		 3487 polaris10_ps->performance_levels[0].engine_clock = sclk;
3488 polaris10_ps->performance_levels[0].memory_clock = mclk;
a23eefa2 3489
2cc0c0b5
FC		 3490 polaris10_ps->performance_levels[1].engine_clock =
3491 (polaris10_ps->performance_levels[1].engine_clock >=
3492 polaris10_ps->performance_levels[0].engine_clock) ?
3493 polaris10_ps->performance_levels[1].engine_clock :
3494 polaris10_ps->performance_levels[0].engine_clock;
a23eefa2
RZ		 3495
3496 if (disable_mclk_switching) {
2cc0c0b5
FC		 3497 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3498 mclk = polaris10_ps->performance_levels[1].memory_clock;
a23eefa2 3499
2cc0c0b5
FC		 3500 polaris10_ps->performance_levels[0].memory_clock = mclk;
3501 polaris10_ps->performance_levels[1].memory_clock = mclk;
a23eefa2 3502 } else {
2cc0c0b5
FC		 3503 if (polaris10_ps->performance_levels[1].memory_clock <
3504 polaris10_ps->performance_levels[0].memory_clock)
3505 polaris10_ps->performance_levels[1].memory_clock =
3506 polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3507 }
3508
3509 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3510 PHM_PlatformCaps_StablePState)) {
2cc0c0b5
FC		 3511 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3512 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3513 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3514 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3515 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
a23eefa2
RZ		 3516 }
3517 }
3518 return 0;
3519}
3520
3521
2cc0c0b5 3522static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3523{
3524 struct pp_power_state *ps;
2cc0c0b5 3525 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3526
3527 if (hwmgr == NULL)
3528 return -EINVAL;
3529
3530 ps = hwmgr->request_ps;
3531
3532 if (ps == NULL)
3533 return -EINVAL;
3534
2cc0c0b5 3535 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3536
3537 if (low)
2cc0c0b5 3538 return polaris10_ps->performance_levels[0].memory_clock;
a23eefa2 3539 else
2cc0c0b5
FC		 3540 return polaris10_ps->performance_levels
3541 [polaris10_ps->performance_level_count-1].memory_clock;
a23eefa2
RZ		 3542}
3543
2cc0c0b5 3544static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3545{
3546 struct pp_power_state *ps;
2cc0c0b5 3547 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3548
3549 if (hwmgr == NULL)
3550 return -EINVAL;
3551
3552 ps = hwmgr->request_ps;
3553
3554 if (ps == NULL)
3555 return -EINVAL;
3556
2cc0c0b5 3557 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3558
3559 if (low)
2cc0c0b5 3560 return polaris10_ps->performance_levels[0].engine_clock;
a23eefa2 3561 else
2cc0c0b5
FC		 3562 return polaris10_ps->performance_levels
3563 [polaris10_ps->performance_level_count-1].engine_clock;
a23eefa2
RZ		 3564}
3565
2cc0c0b5 3566static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3567 struct pp_hw_power_state *hw_ps)
3568{
2cc0c0b5
FC		 3569 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3570 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 3571 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3572 uint16_t size;
3573 uint8_t frev, crev;
3574 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3575
3576 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3577 * We assume here that fw_info is unchanged if this call fails.
3578 */
3579 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3580 hwmgr->device, index,
3581 &size, &frev, &crev);
3582 if (!fw_info)
3583 /* During a test, there is no firmware info table. */
3584 return 0;
3585
3586 /* Patch the state. */
3587 data->vbios_boot_state.sclk_bootup_value =
3588 le32_to_cpu(fw_info->ulDefaultEngineClock);
3589 data->vbios_boot_state.mclk_bootup_value =
3590 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3591 data->vbios_boot_state.mvdd_bootup_value =
3592 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3593 data->vbios_boot_state.vddc_bootup_value =
3594 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3595 data->vbios_boot_state.vddci_bootup_value =
3596 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3597 data->vbios_boot_state.pcie_gen_bootup_value =
3598 phm_get_current_pcie_speed(hwmgr);
3599
3600 data->vbios_boot_state.pcie_lane_bootup_value =
3601 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3602
3603 /* set boot power state */
3604 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3605 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3606 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3607 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3608
3609 return 0;
3610}
3611
2cc0c0b5 3612static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3613 void *state, struct pp_power_state *power_state,
3614 void *pp_table, uint32_t classification_flag)
3615{
2cc0c0b5
FC		 3616 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3617 struct polaris10_power_state *polaris10_power_state =
3618 (struct polaris10_power_state *)(&(power_state->hardware));
3619 struct polaris10_performance_level *performance_level;
a23eefa2
RZ		 3620 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3621 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3622 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3ff21127
RZ		 3623 PPTable_Generic_SubTable_Header *sclk_dep_table =
3624 (PPTable_Generic_SubTable_Header *)
a23eefa2
RZ		 3625 (((unsigned long)powerplay_table) +
3626 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3ff21127 3627
a23eefa2
RZ		 3628 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3629 (ATOM_Tonga_MCLK_Dependency_Table *)
3630 (((unsigned long)powerplay_table) +
3631 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3632
3633 /* The following fields are not initialized here: id orderedList allStatesList */
3634 power_state->classification.ui_label =
3635 (le16_to_cpu(state_entry->usClassification) &
3636 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3637 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3638 power_state->classification.flags = classification_flag;
3639 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3640
3641 power_state->classification.temporary_state = false;
3642 power_state->classification.to_be_deleted = false;
3643
3644 power_state->validation.disallowOnDC =
3645 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3646 ATOM_Tonga_DISALLOW_ON_DC));
3647
3648 power_state->pcie.lanes = 0;
3649
3650 power_state->display.disableFrameModulation = false;
3651 power_state->display.limitRefreshrate = false;
3652 power_state->display.enableVariBright =
3653 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3654 ATOM_Tonga_ENABLE_VARIBRIGHT));
3655
3656 power_state->validation.supportedPowerLevels = 0;
3657 power_state->uvd_clocks.VCLK = 0;
3658 power_state->uvd_clocks.DCLK = 0;
3659 power_state->temperatures.min = 0;
3660 power_state->temperatures.max = 0;
3661
2cc0c0b5
FC		 3662 performance_level = &(polaris10_power_state->performance_levels
3663 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3664
3665 PP_ASSERT_WITH_CODE(
2cc0c0b5 3666 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
a23eefa2
RZ		 3667 "Performance levels exceeds SMC limit!",
3668 return -1);
3669
3670 PP_ASSERT_WITH_CODE(
2cc0c0b5 3671 (polaris10_power_state->performance_level_count <=
a23eefa2
RZ		 3672 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3673 "Performance levels exceeds Driver limit!",
3674 return -1);
3675
3676 /* Performance levels are arranged from low to high. */
3677 performance_level->memory_clock = mclk_dep_table->entries
3678 [state_entry->ucMemoryClockIndexLow].ulMclk;
3ff21127
RZ		 3679 if (sclk_dep_table->ucRevId == 0)
3680 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3681 [state_entry->ucEngineClockIndexLow].ulSclk;
3682 else if (sclk_dep_table->ucRevId == 1)
3683 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
a23eefa2
RZ		 3684 [state_entry->ucEngineClockIndexLow].ulSclk;
3685 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3686 state_entry->ucPCIEGenLow);
3687 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3688 state_entry->ucPCIELaneHigh);
3689
2cc0c0b5
FC		 3690 performance_level = &(polaris10_power_state->performance_levels
3691 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3692 performance_level->memory_clock = mclk_dep_table->entries
3693 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3ff21127
RZ		 3694
3695 if (sclk_dep_table->ucRevId == 0)
3696 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3697 [state_entry->ucEngineClockIndexHigh].ulSclk;
3698 else if (sclk_dep_table->ucRevId == 1)
3699 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
a23eefa2 3700 [state_entry->ucEngineClockIndexHigh].ulSclk;
3ff21127 3701
a23eefa2
RZ		 3702 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3703 state_entry->ucPCIEGenHigh);
3704 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3705 state_entry->ucPCIELaneHigh);
3706
3707 return 0;
3708}
3709
2cc0c0b5 3710static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3711 unsigned long entry_index, struct pp_power_state *state)
3712{
3713 int result;
2cc0c0b5
FC		 3714 struct polaris10_power_state *ps;
3715 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3716 struct phm_ppt_v1_information *table_info =
3717 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3718 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3719 table_info->vdd_dep_on_mclk;
3720
3721 state->hardware.magic = PHM_VIslands_Magic;
3722
2cc0c0b5 3723 ps = (struct polaris10_power_state *)(&state->hardware);
a23eefa2
RZ		 3724
3725 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
2cc0c0b5 3726 polaris10_get_pp_table_entry_callback_func);
a23eefa2
RZ		 3727
3728 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3729 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3730 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3731 */
3732 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3733 if (dep_mclk_table->entries[0].clk !=
3734 data->vbios_boot_state.mclk_bootup_value)
3735 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3736 "does not match VBIOS boot MCLK level");
3737 if (dep_mclk_table->entries[0].vddci !=
3738 data->vbios_boot_state.vddci_bootup_value)
3739 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3740 "does not match VBIOS boot VDDCI level");
3741 }
3742
3743 /* set DC compatible flag if this state supports DC */
3744 if (!state->validation.disallowOnDC)
3745 ps->dc_compatible = true;
3746
3747 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3748 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3749
3750 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3751 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3752
3753 if (!result) {
3754 uint32_t i;
3755
3756 switch (state->classification.ui_label) {
3757 case PP_StateUILabel_Performance:
3758 data->use_pcie_performance_levels = true;
a23eefa2
RZ		 3759 for (i = 0; i < ps->performance_level_count; i++) {
3760 if (data->pcie_gen_performance.max <
3761 ps->performance_levels[i].pcie_gen)
3762 data->pcie_gen_performance.max =
3763 ps->performance_levels[i].pcie_gen;
3764
3765 if (data->pcie_gen_performance.min >
3766 ps->performance_levels[i].pcie_gen)
3767 data->pcie_gen_performance.min =
3768 ps->performance_levels[i].pcie_gen;
3769
3770 if (data->pcie_lane_performance.max <
3771 ps->performance_levels[i].pcie_lane)
3772 data->pcie_lane_performance.max =
3773 ps->performance_levels[i].pcie_lane;
a23eefa2
RZ		 3774 if (data->pcie_lane_performance.min >
3775 ps->performance_levels[i].pcie_lane)
3776 data->pcie_lane_performance.min =
3777 ps->performance_levels[i].pcie_lane;
3778 }
3779 break;
3780 case PP_StateUILabel_Battery:
3781 data->use_pcie_power_saving_levels = true;
3782
3783 for (i = 0; i < ps->performance_level_count; i++) {
3784 if (data->pcie_gen_power_saving.max <
3785 ps->performance_levels[i].pcie_gen)
3786 data->pcie_gen_power_saving.max =
3787 ps->performance_levels[i].pcie_gen;
3788
3789 if (data->pcie_gen_power_saving.min >
3790 ps->performance_levels[i].pcie_gen)
3791 data->pcie_gen_power_saving.min =
3792 ps->performance_levels[i].pcie_gen;
3793
3794 if (data->pcie_lane_power_saving.max <
3795 ps->performance_levels[i].pcie_lane)
3796 data->pcie_lane_power_saving.max =
3797 ps->performance_levels[i].pcie_lane;
3798
3799 if (data->pcie_lane_power_saving.min >
3800 ps->performance_levels[i].pcie_lane)
3801 data->pcie_lane_power_saving.min =
3802 ps->performance_levels[i].pcie_lane;
3803 }
3804 break;
3805 default:
3806 break;
3807 }
3808 }
3809 return 0;
3810}
3811
3812static void
2cc0c0b5 3813polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
a23eefa2 3814{
b2d96143
RZ		 3815 uint32_t sclk, mclk, activity_percent;
3816 uint32_t offset;
3817 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3818
3819 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3820
3821 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3822
3823 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3824
3825 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3826 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3827 mclk / 100, sclk / 100);
b2d96143
RZ		 3828
3829 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3830 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3831 activity_percent += 0x80;
3832 activity_percent >>= 8;
3833
3834 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3835
3836 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3837
3838 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
a23eefa2
RZ		 3839}
3840
2cc0c0b5 3841static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 3842{
3843 const struct phm_set_power_state_input *states =
3844 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3845 const struct polaris10_power_state *polaris10_ps =
3846 cast_const_phw_polaris10_power_state(states->pnew_state);
3847 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3848 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3849 uint32_t sclk = polaris10_ps->performance_levels
3850 [polaris10_ps->performance_level_count - 1].engine_clock;
3851 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3852 uint32_t mclk = polaris10_ps->performance_levels
3853 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 3854 struct PP_Clocks min_clocks = {0};
3855 uint32_t i;
3856 struct cgs_display_info info = {0};
3857
3858 data->need_update_smu7_dpm_table = 0;
3859
3860 for (i = 0; i < sclk_table->count; i++) {
3861 if (sclk == sclk_table->dpm_levels[i].value)
3862 break;
3863 }
3864
3865 if (i >= sclk_table->count)
3866 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3867 else {
3868 /* TODO: Check SCLK in DAL's minimum clocks
3869 * in case DeepSleep divider update is required.
3870 */
2cc0c0b5
FC		 3871 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3872 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3873 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 3874 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3875 }
3876
3877 for (i = 0; i < mclk_table->count; i++) {
3878 if (mclk == mclk_table->dpm_levels[i].value)
3879 break;
3880 }
3881
3882 if (i >= mclk_table->count)
3883 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3884
3885 cgs_get_active_displays_info(hwmgr->device, &info);
3886
3887 if (data->display_timing.num_existing_displays != info.display_count)
3888 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3889
3890 return 0;
3891}
3892
2cc0c0b5
FC		 3893static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3894 const struct polaris10_power_state *polaris10_ps)
a23eefa2
RZ		 3895{
3896 uint32_t i;
3897 uint32_t sclk, max_sclk = 0;
2cc0c0b5
FC		 3898 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3899 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2 3900
2cc0c0b5
FC		 3901 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3902 sclk = polaris10_ps->performance_levels[i].engine_clock;
a23eefa2
RZ		 3903 if (max_sclk < sclk)
3904 max_sclk = sclk;
3905 }
3906
3907 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3908 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3909 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3910 dpm_table->pcie_speed_table.dpm_levels
3911 [dpm_table->pcie_speed_table.count - 1].value :
3912 dpm_table->pcie_speed_table.dpm_levels[i].value);
3913 }
3914
3915 return 0;
3916}
3917
2cc0c0b5 3918static int polaris10_request_link_speed_change_before_state_change(
a23eefa2
RZ		 3919 struct pp_hwmgr *hwmgr, const void *input)
3920{
3921 const struct phm_set_power_state_input *states =
3922 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3923 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3924 const struct polaris10_power_state *polaris10_nps =
3925 cast_const_phw_polaris10_power_state(states->pnew_state);
3926 const struct polaris10_power_state *polaris10_cps =
3927 cast_const_phw_polaris10_power_state(states->pcurrent_state);
a23eefa2 3928
2cc0c0b5 3929 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
a23eefa2
RZ		 3930 uint16_t current_link_speed;
3931
3932 if (data->force_pcie_gen == PP_PCIEGenInvalid)
2cc0c0b5 3933 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
a23eefa2
RZ		 3934 else
3935 current_link_speed = data->force_pcie_gen;
3936
3937 data->force_pcie_gen = PP_PCIEGenInvalid;
3938 data->pspp_notify_required = false;
3939
3940 if (target_link_speed > current_link_speed) {
3941 switch (target_link_speed) {
3942 case PP_PCIEGen3:
3943 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3944 break;
3945 data->force_pcie_gen = PP_PCIEGen2;
3946 if (current_link_speed == PP_PCIEGen2)
3947 break;
3948 case PP_PCIEGen2:
3949 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3950 break;
3951 default:
3952 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3953 break;
3954 }
3955 } else {
3956 if (target_link_speed < current_link_speed)
3957 data->pspp_notify_required = true;
3958 }
3959
3960 return 0;
3961}
3962
2cc0c0b5 3963static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 3964{
2cc0c0b5 3965 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3966
3967 if (0 == data->need_update_smu7_dpm_table)
3968 return 0;
3969
3970 if ((0 == data->sclk_dpm_key_disabled) &&
3971 (data->need_update_smu7_dpm_table &
3972 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
2cc0c0b5 3973 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 3974 "Trying to freeze SCLK DPM when DPM is disabled",
3975 );
3976 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3977 PPSMC_MSG_SCLKDPM_FreezeLevel),
3978 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3979 return -1);
3980 }
3981
3982 if ((0 == data->mclk_dpm_key_disabled) &&
3983 (data->need_update_smu7_dpm_table &
3984 DPMTABLE_OD_UPDATE_MCLK)) {
2cc0c0b5 3985 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 3986 "Trying to freeze MCLK DPM when DPM is disabled",
3987 );
3988 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3989 PPSMC_MSG_MCLKDPM_FreezeLevel),
3990 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3991 return -1);
3992 }
3993
3994 return 0;
3995}
3996
2cc0c0b5 3997static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
a23eefa2
RZ		 3998 struct pp_hwmgr *hwmgr, const void *input)
3999{
4000 int result = 0;
4001 const struct phm_set_power_state_input *states =
4002 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4003 const struct polaris10_power_state *polaris10_ps =
4004 cast_const_phw_polaris10_power_state(states->pnew_state);
4005 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4006 uint32_t sclk = polaris10_ps->performance_levels
4007 [polaris10_ps->performance_level_count - 1].engine_clock;
4008 uint32_t mclk = polaris10_ps->performance_levels
4009 [polaris10_ps->performance_level_count - 1].memory_clock;
4010 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4011
4012 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
a23eefa2
RZ		 4013 uint32_t dpm_count, clock_percent;
4014 uint32_t i;
4015
4016 if (0 == data->need_update_smu7_dpm_table)
4017 return 0;
4018
4019 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4020 dpm_table->sclk_table.dpm_levels
4021 [dpm_table->sclk_table.count - 1].value = sclk;
4022
4023 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4024 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4025 /* Need to do calculation based on the golden DPM table
4026 * as the Heatmap GPU Clock axis is also based on the default values
4027 */
4028 PP_ASSERT_WITH_CODE(
4029 (golden_dpm_table->sclk_table.dpm_levels
4030 [golden_dpm_table->sclk_table.count - 1].value != 0),
4031 "Divide by 0!",
4032 return -1);
4033 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4034
4035 for (i = dpm_count; i > 1; i--) {
4036 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4037 clock_percent =
4038 ((sclk
4039 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4040 ) * 100)
4041 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4042
4043 dpm_table->sclk_table.dpm_levels[i].value =
4044 golden_dpm_table->sclk_table.dpm_levels[i].value +
4045 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4046 clock_percent)/100;
4047
4048 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4049 clock_percent =
4050 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4051 - sclk) * 100)
4052 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4053
4054 dpm_table->sclk_table.dpm_levels[i].value =
4055 golden_dpm_table->sclk_table.dpm_levels[i].value -
4056 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4057 clock_percent) / 100;
4058 } else
4059 dpm_table->sclk_table.dpm_levels[i].value =
4060 golden_dpm_table->sclk_table.dpm_levels[i].value;
4061 }
4062 }
4063 }
4064
4065 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4066 dpm_table->mclk_table.dpm_levels
4067 [dpm_table->mclk_table.count - 1].value = mclk;
4068
4069 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4070 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4071
4072 PP_ASSERT_WITH_CODE(
4073 (golden_dpm_table->mclk_table.dpm_levels
4074 [golden_dpm_table->mclk_table.count-1].value != 0),
4075 "Divide by 0!",
4076 return -1);
4077 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4078 for (i = dpm_count; i > 1; i--) {
4079 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4080 clock_percent = ((mclk -
4081 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4082 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4083
4084 dpm_table->mclk_table.dpm_levels[i].value =
4085 golden_dpm_table->mclk_table.dpm_levels[i].value +
4086 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4087 clock_percent) / 100;
4088
4089 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4090 clock_percent = (
4091 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4092 * 100)
4093 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4094
4095 dpm_table->mclk_table.dpm_levels[i].value =
4096 golden_dpm_table->mclk_table.dpm_levels[i].value -
4097 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4098 clock_percent) / 100;
4099 } else
4100 dpm_table->mclk_table.dpm_levels[i].value =
4101 golden_dpm_table->mclk_table.dpm_levels[i].value;
4102 }
4103 }
4104 }
4105
4106 if (data->need_update_smu7_dpm_table &
4107 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
2cc0c0b5 4108 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 4109 PP_ASSERT_WITH_CODE((0 == result),
4110 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4111 return result);
4112 }
4113
4114 if (data->need_update_smu7_dpm_table &
4115 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4116 /*populate MCLK dpm table to SMU7 */
2cc0c0b5 4117 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 4118 PP_ASSERT_WITH_CODE((0 == result),
4119 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4120 return result);
4121 }
4122
4123 return result;
4124}
4125
2cc0c0b5
FC		 4126static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4127 struct polaris10_single_dpm_table *dpm_table,
a23eefa2
RZ		 4128 uint32_t low_limit, uint32_t high_limit)
4129{
4130 uint32_t i;
a23eefa2
RZ		 4131
4132 for (i = 0; i < dpm_table->count; i++) {
4133 if ((dpm_table->dpm_levels[i].value < low_limit)
4134 || (dpm_table->dpm_levels[i].value > high_limit))
4135 dpm_table->dpm_levels[i].enabled = false;
a23eefa2
RZ		 4136 else
4137 dpm_table->dpm_levels[i].enabled = true;
4138 }
4139
4140 return 0;
4141}
4142
2cc0c0b5
FC		 4143static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4144 const struct polaris10_power_state *polaris10_ps)
a23eefa2
RZ		 4145{
4146 int result = 0;
2cc0c0b5 4147 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4148 uint32_t high_limit_count;
4149
2cc0c0b5 4150 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
a23eefa2
RZ		 4151 "power state did not have any performance level",
4152 return -1);
4153
2cc0c0b5 4154 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
a23eefa2 4155
2cc0c0b5 4156 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4157 &(data->dpm_table.sclk_table),
2cc0c0b5
FC		 4158 polaris10_ps->performance_levels[0].engine_clock,
4159 polaris10_ps->performance_levels[high_limit_count].engine_clock);
a23eefa2 4160
2cc0c0b5 4161 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4162 &(data->dpm_table.mclk_table),
2cc0c0b5
FC		 4163 polaris10_ps->performance_levels[0].memory_clock,
4164 polaris10_ps->performance_levels[high_limit_count].memory_clock);
a23eefa2
RZ		 4165
4166 return result;
4167}
4168
2cc0c0b5 4169static int polaris10_generate_dpm_level_enable_mask(
a23eefa2
RZ		 4170 struct pp_hwmgr *hwmgr, const void *input)
4171{
4172 int result;
4173 const struct phm_set_power_state_input *states =
4174 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4175 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4176 const struct polaris10_power_state *polaris10_ps =
4177 cast_const_phw_polaris10_power_state(states->pnew_state);
a23eefa2 4178
2cc0c0b5 4179 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
a23eefa2
RZ		 4180 if (result)
4181 return result;
4182
4183 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4184 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4185 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4186 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4187 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4188 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4189
4190 return 0;
4191}
4192
2cc0c0b5 4193int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
a23eefa2
RZ		 4194{
4195 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
92c6d645
EH		 4196 PPSMC_MSG_UVDDPM_Enable :
4197 PPSMC_MSG_UVDDPM_Disable);
4198}
4199
2cc0c0b5 4200int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4201{
4202 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
a23eefa2
RZ		 4203 PPSMC_MSG_VCEDPM_Enable :
4204 PPSMC_MSG_VCEDPM_Disable);
4205}
4206
2cc0c0b5 4207int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4208{
4209 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4210 PPSMC_MSG_SAMUDPM_Enable :
4211 PPSMC_MSG_SAMUDPM_Disable);
4212}
4213
2cc0c0b5 4214int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4215{
2cc0c0b5 4216 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645
EH		 4217 uint32_t mm_boot_level_offset, mm_boot_level_value;
4218 struct phm_ppt_v1_information *table_info =
4219 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4220
4221 if (!bgate) {
4222 data->smc_state_table.UvdBootLevel = 0;
4223 if (table_info->mm_dep_table->count > 0)
4224 data->smc_state_table.UvdBootLevel =
4225 (uint8_t) (table_info->mm_dep_table->count - 1);
4226 mm_boot_level_offset = data->dpm_table_start +
4227 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4228 mm_boot_level_offset /= 4;
4229 mm_boot_level_offset *= 4;
4230 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4231 CGS_IND_REG__SMC, mm_boot_level_offset);
4232 mm_boot_level_value &= 0x00FFFFFF;
4233 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4234 cgs_write_ind_register(hwmgr->device,
4235 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4236
4237 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4238 PHM_PlatformCaps_UVDDPM) ||
4239 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4240 PHM_PlatformCaps_StablePState))
4241 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4242 PPSMC_MSG_UVDDPM_SetEnabledMask,
4243 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4244 }
4245
2cc0c0b5 4246 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
92c6d645
EH		 4247}
4248
2cc0c0b5 4249static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4250{
4251 const struct phm_set_power_state_input *states =
4252 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4253 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4254 const struct polaris10_power_state *polaris10_nps =
4255 cast_const_phw_polaris10_power_state(states->pnew_state);
4256 const struct polaris10_power_state *polaris10_cps =
4257 cast_const_phw_polaris10_power_state(states->pcurrent_state);
a23eefa2
RZ		 4258
4259 uint32_t mm_boot_level_offset, mm_boot_level_value;
4260 struct phm_ppt_v1_information *table_info =
4261 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4262
2cc0c0b5
FC		 4263 if (polaris10_nps->vce_clks.evclk > 0 &&
4264 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
a23eefa2
RZ		 4265
4266 data->smc_state_table.VceBootLevel =
4267 (uint8_t) (table_info->mm_dep_table->count - 1);
4268
4269 mm_boot_level_offset = data->dpm_table_start +
4270 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4271 mm_boot_level_offset /= 4;
4272 mm_boot_level_offset *= 4;
4273 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4274 CGS_IND_REG__SMC, mm_boot_level_offset);
4275 mm_boot_level_value &= 0xFF00FFFF;
4276 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4277 cgs_write_ind_register(hwmgr->device,
4278 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4279
4280 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4281 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4282 PPSMC_MSG_VCEDPM_SetEnabledMask,
4283 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4284
2cc0c0b5
FC		 4285 polaris10_enable_disable_vce_dpm(hwmgr, true);
4286 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4287 polaris10_cps != NULL &&
4288 polaris10_cps->vce_clks.evclk > 0)
4289 polaris10_enable_disable_vce_dpm(hwmgr, false);
a23eefa2
RZ		 4290 }
4291
4292 return 0;
4293}
4294
2cc0c0b5 4295int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4296{
2cc0c0b5 4297 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645 4298 uint32_t mm_boot_level_offset, mm_boot_level_value;
92c6d645
EH		 4299
4300 if (!bgate) {
871fd840 4301 data->smc_state_table.SamuBootLevel = 0;
92c6d645
EH		 4302 mm_boot_level_offset = data->dpm_table_start +
4303 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4304 mm_boot_level_offset /= 4;
4305 mm_boot_level_offset *= 4;
4306 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4307 CGS_IND_REG__SMC, mm_boot_level_offset);
4308 mm_boot_level_value &= 0xFFFFFF00;
4309 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4310 cgs_write_ind_register(hwmgr->device,
4311 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4312
4313 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4314 PHM_PlatformCaps_StablePState))
4315 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4316 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4317 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4318 }
4319
2cc0c0b5 4320 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
92c6d645
EH		 4321}
4322
2cc0c0b5 4323static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4324{
2cc0c0b5 4325 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4326
4327 int result = 0;
4328 uint32_t low_sclk_interrupt_threshold = 0;
4329
4330 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4331 PHM_PlatformCaps_SclkThrottleLowNotification)
4332 && (hwmgr->gfx_arbiter.sclk_threshold !=
4333 data->low_sclk_interrupt_threshold)) {
4334 data->low_sclk_interrupt_threshold =
4335 hwmgr->gfx_arbiter.sclk_threshold;
4336 low_sclk_interrupt_threshold =
4337 data->low_sclk_interrupt_threshold;
4338
4339 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4340
2cc0c0b5 4341 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 4342 hwmgr->smumgr,
4343 data->dpm_table_start +
4344 offsetof(SMU74_Discrete_DpmTable,
4345 LowSclkInterruptThreshold),
4346 (uint8_t *)&low_sclk_interrupt_threshold,
4347 sizeof(uint32_t),
4348 data->sram_end);
4349 }
4350
4351 return result;
4352}
4353
2cc0c0b5 4354static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 4355{
2cc0c0b5 4356 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4357
4358 if (data->need_update_smu7_dpm_table &
4359 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2cc0c0b5 4360 return polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 4361
4362 return 0;
4363}
4364
2cc0c0b5 4365static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 4366{
2cc0c0b5 4367 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4368
4369 if (0 == data->need_update_smu7_dpm_table)
4370 return 0;
4371
4372 if ((0 == data->sclk_dpm_key_disabled) &&
4373 (data->need_update_smu7_dpm_table &
4374 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4375
2cc0c0b5 4376 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 4377 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4378 );
4379 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4380 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4381 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4382 return -1);
4383 }
4384
4385 if ((0 == data->mclk_dpm_key_disabled) &&
4386 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4387
2cc0c0b5 4388 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 4389 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4390 );
4391 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4392 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4393 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4394 return -1);
4395 }
4396
4397 data->need_update_smu7_dpm_table = 0;
4398
4399 return 0;
4400}
4401
2cc0c0b5 4402static int polaris10_notify_link_speed_change_after_state_change(
a23eefa2
RZ		 4403 struct pp_hwmgr *hwmgr, const void *input)
4404{
4405 const struct phm_set_power_state_input *states =
4406 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4407 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4408 const struct polaris10_power_state *polaris10_ps =
4409 cast_const_phw_polaris10_power_state(states->pnew_state);
4410 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
a23eefa2
RZ		 4411 uint8_t request;
4412
4413 if (data->pspp_notify_required) {
4414 if (target_link_speed == PP_PCIEGen3)
4415 request = PCIE_PERF_REQ_GEN3;
4416 else if (target_link_speed == PP_PCIEGen2)
4417 request = PCIE_PERF_REQ_GEN2;
4418 else
4419 request = PCIE_PERF_REQ_GEN1;
4420
4421 if (request == PCIE_PERF_REQ_GEN1 &&
4422 phm_get_current_pcie_speed(hwmgr) > 0)
4423 return 0;
4424
4425 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4426 if (PP_PCIEGen2 == target_link_speed)
4427 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4428 else
4429 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4430 }
4431 }
4432
4433 return 0;
4434}
4435
2cc0c0b5 4436static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4437{
4438 int tmp_result, result = 0;
2cc0c0b5 4439 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 4440
2cc0c0b5 4441 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
a23eefa2
RZ		 4442 PP_ASSERT_WITH_CODE((0 == tmp_result),
4443 "Failed to find DPM states clocks in DPM table!",
4444 result = tmp_result);
4445
4446 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4447 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4448 tmp_result =
2cc0c0b5 4449 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
a23eefa2
RZ		 4450 PP_ASSERT_WITH_CODE((0 == tmp_result),
4451 "Failed to request link speed change before state change!",
4452 result = tmp_result);
4453 }
4454
2cc0c0b5 4455 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4456 PP_ASSERT_WITH_CODE((0 == tmp_result),
4457 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4458
2cc0c0b5 4459 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
a23eefa2
RZ		 4460 PP_ASSERT_WITH_CODE((0 == tmp_result),
4461 "Failed to populate and upload SCLK MCLK DPM levels!",
4462 result = tmp_result);
4463
2cc0c0b5 4464 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
a23eefa2
RZ		 4465 PP_ASSERT_WITH_CODE((0 == tmp_result),
4466 "Failed to generate DPM level enabled mask!",
4467 result = tmp_result);
4468
2cc0c0b5 4469 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
a23eefa2
RZ		 4470 PP_ASSERT_WITH_CODE((0 == tmp_result),
4471 "Failed to update VCE DPM!",
4472 result = tmp_result);
4473
2cc0c0b5 4474 tmp_result = polaris10_update_sclk_threshold(hwmgr);
a23eefa2
RZ		 4475 PP_ASSERT_WITH_CODE((0 == tmp_result),
4476 "Failed to update SCLK threshold!",
4477 result = tmp_result);
4478
2cc0c0b5 4479 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
a23eefa2
RZ		 4480 PP_ASSERT_WITH_CODE((0 == tmp_result),
4481 "Failed to program memory timing parameters!",
4482 result = tmp_result);
4483
2cc0c0b5 4484 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4485 PP_ASSERT_WITH_CODE((0 == tmp_result),
4486 "Failed to unfreeze SCLK MCLK DPM!",
4487 result = tmp_result);
4488
2cc0c0b5 4489 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 4490 PP_ASSERT_WITH_CODE((0 == tmp_result),
4491 "Failed to upload DPM level enabled mask!",
4492 result = tmp_result);
4493
4494 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4495 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4496 tmp_result =
2cc0c0b5 4497 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
a23eefa2
RZ		 4498 PP_ASSERT_WITH_CODE((0 == tmp_result),
4499 "Failed to notify link speed change after state change!",
4500 result = tmp_result);
4501 }
4502 data->apply_optimized_settings = false;
4503 return result;
4504}
4505
2cc0c0b5 4506static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
a23eefa2 4507{
eede5262
EH		 4508 hwmgr->thermal_controller.
4509 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
a23eefa2 4510
eede5262 4511 if (phm_is_hw_access_blocked(hwmgr))
a23eefa2 4512 return 0;
eede5262
EH		 4513
4514 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4515 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
a23eefa2
RZ		 4516}
4517
2cc0c0b5 4518int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
a23eefa2
RZ		 4519{
4520 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4521
4522 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4523}
4524
2cc0c0b5 4525int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4526{
4527 uint32_t num_active_displays = 0;
4528 struct cgs_display_info info = {0};
4529 info.mode_info = NULL;
4530
4531 cgs_get_active_displays_info(hwmgr->device, &info);
4532
4533 num_active_displays = info.display_count;
4534
4535 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
2cc0c0b5 4536 polaris10_notify_smc_display_change(hwmgr, false);
a23eefa2 4537 else
2cc0c0b5 4538 polaris10_notify_smc_display_change(hwmgr, true);
a23eefa2
RZ		 4539
4540 return 0;
4541}
4542
4543/**
4544* Programs the display gap
4545*
4546* @param hwmgr the address of the powerplay hardware manager.
4547* @return always OK
4548*/
2cc0c0b5 4549int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2 4550{
2cc0c0b5 4551 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4552 uint32_t num_active_displays = 0;
4553 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4554 uint32_t display_gap2;
4555 uint32_t pre_vbi_time_in_us;
4556 uint32_t frame_time_in_us;
4557 uint32_t ref_clock;
4558 uint32_t refresh_rate = 0;
4559 struct cgs_display_info info = {0};
4560 struct cgs_mode_info mode_info;
4561
4562 info.mode_info = &mode_info;
4563
4564 cgs_get_active_displays_info(hwmgr->device, &info);
4565 num_active_displays = info.display_count;
4566
4567 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4568 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4569
4570 ref_clock = mode_info.ref_clock;
4571 refresh_rate = mode_info.refresh_rate;
4572
4573 if (0 == refresh_rate)
4574 refresh_rate = 60;
4575
4576 frame_time_in_us = 1000000 / refresh_rate;
4577
4578 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4579 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4580
4581 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4582
4583 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4584
4585 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4586
2cc0c0b5 4587 polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
a23eefa2
RZ		 4588
4589 return 0;
4590}
4591
4592
2cc0c0b5 4593int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
a23eefa2 4594{
2cc0c0b5 4595 return polaris10_program_display_gap(hwmgr);
a23eefa2
RZ		 4596}
4597
4598/**
4599* Set maximum target operating fan output RPM
4600*
4601* @param hwmgr: the address of the powerplay hardware manager.
4602* @param usMaxFanRpm: max operating fan RPM value.
4603* @return The response that came from the SMC.
4604*/
2cc0c0b5 4605static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
a23eefa2 4606{
eede5262
EH		 4607 hwmgr->thermal_controller.
4608 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4609
4610 if (phm_is_hw_access_blocked(hwmgr))
4611 return 0;
4612
4613 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4614 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
a23eefa2
RZ		 4615}
4616
2cc0c0b5 4617int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 4618 const void *thermal_interrupt_info)
4619{
4620 return 0;
4621}
4622
2cc0c0b5 4623bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
a23eefa2 4624{
2cc0c0b5 4625 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4626 bool is_update_required = false;
4627 struct cgs_display_info info = {0, 0, NULL};
4628
4629 cgs_get_active_displays_info(hwmgr->device, &info);
4630
4631 if (data->display_timing.num_existing_displays != info.display_count)
4632 is_update_required = true;
4633/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4634 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4635 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
2cc0c0b5
FC		 4636 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4637 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4638 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 4639 is_update_required = true;
4640*/
4641 return is_update_required;
4642}
4643
2cc0c0b5
FC		 4644static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4645 const struct polaris10_performance_level *pl2)
a23eefa2
RZ		 4646{
4647 return ((pl1->memory_clock == pl2->memory_clock) &&
4648 (pl1->engine_clock == pl2->engine_clock) &&
4649 (pl1->pcie_gen == pl2->pcie_gen) &&
4650 (pl1->pcie_lane == pl2->pcie_lane));
4651}
4652
2cc0c0b5 4653int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
a23eefa2 4654{
2cc0c0b5
FC		 4655 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4656 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
a23eefa2
RZ		 4657 int i;
4658
4659 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4660 return -EINVAL;
4661
4662 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4663 if (psa->performance_level_count != psb->performance_level_count) {
4664 *equal = false;
4665 return 0;
4666 }
4667
4668 for (i = 0; i < psa->performance_level_count; i++) {
2cc0c0b5 4669 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
a23eefa2
RZ		 4670 /* If we have found even one performance level pair that is different the states are different. */
4671 *equal = false;
4672 return 0;
4673 }
4674 }
4675
4676 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4677 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4678 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4679 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4680
4681 return 0;
4682}
4683
2cc0c0b5 4684int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
a23eefa2 4685{
2cc0c0b5 4686 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4687
4688 uint32_t vbios_version;
4689
4690 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4691
4692 phm_get_mc_microcode_version(hwmgr);
4693 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4694 /* Full version of MC ucode has already been loaded. */
4695 if (vbios_version == 0) {
4696 data->need_long_memory_training = false;
4697 return 0;
4698 }
4699
4700 data->need_long_memory_training = true;
4701
4702/*
edf600da 4703 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
a23eefa2
RZ		 4704 pfd = &tonga_mcmeFirmware;
4705 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
2cc0c0b5 4706 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
a23eefa2
RZ		 4707 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4708 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4709*/
4710 return 0;
4711}
4712
4713/**
4714 * Read clock related registers.
4715 *
4716 * @param hwmgr the address of the powerplay hardware manager.
4717 * @return always 0
4718 */
2cc0c0b5 4719static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
a23eefa2 4720{
2cc0c0b5 4721 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4722
4723 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4724 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4725 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4726
4727 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4728 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4729 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4730
4731 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4732 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4733 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4734
4735 return 0;
4736}
4737
4738/**
4739 * Find out if memory is GDDR5.
4740 *
4741 * @param hwmgr the address of the powerplay hardware manager.
4742 * @return always 0
4743 */
2cc0c0b5 4744static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
a23eefa2 4745{
2cc0c0b5 4746 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4747 uint32_t temp;
4748
4749 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4750
4751 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4752 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4753 MC_SEQ_MISC0_GDDR5_SHIFT));
4754
4755 return 0;
4756}
4757
4758/**
4759 * Enables Dynamic Power Management by SMC
4760 *
4761 * @param hwmgr the address of the powerplay hardware manager.
4762 * @return always 0
4763 */
2cc0c0b5 4764static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4765{
4766 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4767 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4768
4769 return 0;
4770}
4771
4772/**
4773 * Initialize PowerGating States for different engines
4774 *
4775 * @param hwmgr the address of the powerplay hardware manager.
4776 * @return always 0
4777 */
2cc0c0b5 4778static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
a23eefa2 4779{
2cc0c0b5 4780 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4781
4782 data->uvd_power_gated = false;
4783 data->vce_power_gated = false;
4784 data->samu_power_gated = false;
4785
4786 return 0;
4787}
4788
2cc0c0b5 4789static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4790{
2cc0c0b5 4791 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4792 data->low_sclk_interrupt_threshold = 0;
4793
4794 return 0;
4795}
4796
2cc0c0b5 4797int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4798{
4799 int tmp_result, result = 0;
4800
2cc0c0b5 4801 polaris10_upload_mc_firmware(hwmgr);
a23eefa2 4802
2cc0c0b5 4803 tmp_result = polaris10_read_clock_registers(hwmgr);
a23eefa2
RZ		 4804 PP_ASSERT_WITH_CODE((0 == tmp_result),
4805 "Failed to read clock registers!", result = tmp_result);
4806
2cc0c0b5 4807 tmp_result = polaris10_get_memory_type(hwmgr);
a23eefa2
RZ		 4808 PP_ASSERT_WITH_CODE((0 == tmp_result),
4809 "Failed to get memory type!", result = tmp_result);
4810
2cc0c0b5 4811 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
a23eefa2
RZ		 4812 PP_ASSERT_WITH_CODE((0 == tmp_result),
4813 "Failed to enable ACPI power management!", result = tmp_result);
4814
2cc0c0b5 4815 tmp_result = polaris10_init_power_gate_state(hwmgr);
a23eefa2
RZ		 4816 PP_ASSERT_WITH_CODE((0 == tmp_result),
4817 "Failed to init power gate state!", result = tmp_result);
4818
4819 tmp_result = phm_get_mc_microcode_version(hwmgr);
4820 PP_ASSERT_WITH_CODE((0 == tmp_result),
4821 "Failed to get MC microcode version!", result = tmp_result);
4822
2cc0c0b5 4823 tmp_result = polaris10_init_sclk_threshold(hwmgr);
a23eefa2
RZ		 4824 PP_ASSERT_WITH_CODE((0 == tmp_result),
4825 "Failed to init sclk threshold!", result = tmp_result);
4826
4827 return result;
4828}
4829
2cc0c0b5
FC		 4830static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4831{
4832 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4833
a72d5604 4834 if (!data->soft_pp_table) {
c688c641
MFW		 4835 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4836 hwmgr->soft_pp_table_size,
4837 GFP_KERNEL);
a72d5604
EH		 4838 if (!data->soft_pp_table)
4839 return -ENOMEM;
a72d5604 4840 }
2cc0c0b5 4841
a72d5604
EH		 4842 *table = (char *)&data->soft_pp_table;
4843
4844 return hwmgr->soft_pp_table_size;
2cc0c0b5
FC		 4845}
4846
4847static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4848{
4849 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4850
a72d5604
EH		 4851 if (!data->soft_pp_table) {
4852 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4853 if (!data->soft_pp_table)
4854 return -ENOMEM;
4855 }
4856
4857 memcpy(data->soft_pp_table, buf, size);
4858
4859 hwmgr->soft_pp_table = data->soft_pp_table;
2cc0c0b5 4860
a72d5604 4861 /* TODO: re-init powerplay to implement modified pptable */
2cc0c0b5
FC		 4862
4863 return 0;
4864}
4865
4866static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
5632708f 4867 enum pp_clock_type type, uint32_t mask)
2cc0c0b5
FC		 4868{
4869 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4870
4871 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4872 return -EINVAL;
4873
4874 switch (type) {
4875 case PP_SCLK:
4876 if (!data->sclk_dpm_key_disabled)
4877 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4878 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5632708f 4879 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
2cc0c0b5
FC		 4880 break;
4881 case PP_MCLK:
4882 if (!data->mclk_dpm_key_disabled)
4883 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4884 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5632708f 4885 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
2cc0c0b5
FC		 4886 break;
4887 case PP_PCIE:
5632708f
EH		 4888 {
4889 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4890 uint32_t level = 0;
4891
4892 while (tmp >>= 1)
4893 level++;
4894
2cc0c0b5
FC		 4895 if (!data->pcie_dpm_key_disabled)
4896 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4897 PPSMC_MSG_PCIeDPM_ForceLevel,
5632708f 4898 level);
2cc0c0b5 4899 break;
5632708f 4900 }
2cc0c0b5
FC		 4901 default:
4902 break;
4903 }
4904
4905 return 0;
4906}
4907
4908static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4909{
4910 uint32_t speedCntl = 0;
4911
4912 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4913 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4914 ixPCIE_LC_SPEED_CNTL);
4915 return((uint16_t)PHM_GET_FIELD(speedCntl,
4916 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4917}
4918
4919static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4920 enum pp_clock_type type, char *buf)
4921{
4922 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4923 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4924 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4925 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4926 int i, now, size = 0;
4927 uint32_t clock, pcie_speed;
4928
4929 switch (type) {
4930 case PP_SCLK:
4931 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4932 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4933
4934 for (i = 0; i < sclk_table->count; i++) {
4935 if (clock > sclk_table->dpm_levels[i].value)
4936 continue;
4937 break;
4938 }
4939 now = i;
4940
4941 for (i = 0; i < sclk_table->count; i++)
4942 size += sprintf(buf + size, "%d: %uMhz %s\n",
4943 i, sclk_table->dpm_levels[i].value / 100,
4944 (i == now) ? "*" : "");
4945 break;
4946 case PP_MCLK:
4947 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4948 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4949
4950 for (i = 0; i < mclk_table->count; i++) {
4951 if (clock > mclk_table->dpm_levels[i].value)
4952 continue;
4953 break;
4954 }
4955 now = i;
4956
4957 for (i = 0; i < mclk_table->count; i++)
4958 size += sprintf(buf + size, "%d: %uMhz %s\n",
4959 i, mclk_table->dpm_levels[i].value / 100,
4960 (i == now) ? "*" : "");
4961 break;
4962 case PP_PCIE:
4963 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4964 for (i = 0; i < pcie_table->count; i++) {
4965 if (pcie_speed != pcie_table->dpm_levels[i].value)
4966 continue;
4967 break;
4968 }
4969 now = i;
4970
4971 for (i = 0; i < pcie_table->count; i++)
4972 size += sprintf(buf + size, "%d: %s %s\n", i,
4973 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4974 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4975 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4976 (i == now) ? "*" : "");
4977 break;
4978 default:
4979 break;
4980 }
4981 return size;
4982}
4983
9e26bbb3
RZ		 4984static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4985{
4986 if (mode) {
4987 /* stop auto-manage */
4988 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4989 PHM_PlatformCaps_MicrocodeFanControl))
4990 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4991 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4992 } else
4993 /* restart auto-manage */
4994 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4995
4996 return 0;
4997}
4998
4999static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5000{
5001 if (hwmgr->fan_ctrl_is_in_default_mode)
5002 return hwmgr->fan_ctrl_default_mode;
5003 else
5004 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5005 CG_FDO_CTRL2, FDO_PWM_MODE);
5006}
5007
2cc0c0b5
FC		 5008static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5009 .backend_init = &polaris10_hwmgr_backend_init,
5010 .backend_fini = &polaris10_hwmgr_backend_fini,
5011 .asic_setup = &polaris10_setup_asic_task,
5012 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5013 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5014 .force_dpm_level = &polaris10_force_dpm_level,
5015 .power_state_set = polaris10_set_power_state_tasks,
5016 .get_power_state_size = polaris10_get_power_state_size,
5017 .get_mclk = polaris10_dpm_get_mclk,
5018 .get_sclk = polaris10_dpm_get_sclk,
5019 .patch_boot_state = polaris10_dpm_patch_boot_state,
5020 .get_pp_table_entry = polaris10_get_pp_table_entry,
a23eefa2 5021 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
2cc0c0b5
FC		 5022 .print_current_perforce_level = polaris10_print_current_perforce_level,
5023 .powerdown_uvd = polaris10_phm_powerdown_uvd,
5024 .powergate_uvd = polaris10_phm_powergate_uvd,
5025 .powergate_vce = polaris10_phm_powergate_vce,
5026 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5027 .update_clock_gatings = polaris10_phm_update_clock_gatings,
5028 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5029 .display_config_changed = polaris10_display_configuration_changed_task,
5030 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5031 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5032 .get_temperature = polaris10_thermal_get_temperature,
5033 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5034 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5035 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5036 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5037 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5038 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5039 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5040 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5041 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5042 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5043 .check_states_equal = polaris10_check_states_equal,
9e26bbb3
RZ		 5044 .set_fan_control_mode = polaris10_set_fan_control_mode,
5045 .get_fan_control_mode = polaris10_get_fan_control_mode,
2cc0c0b5
FC		 5046 .get_pp_table = polaris10_get_pp_table,
5047 .set_pp_table = polaris10_set_pp_table,
5048 .force_clock_level = polaris10_force_clock_level,
5049 .print_clock_levels = polaris10_print_clock_levels,
5050 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
a23eefa2
RZ		 5051};
5052
2cc0c0b5 5053int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
a23eefa2 5054{
2cc0c0b5 5055 struct polaris10_hwmgr *data;
a23eefa2 5056
2cc0c0b5 5057 data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
a23eefa2
RZ		 5058 if (data == NULL)
5059 return -ENOMEM;
5060
5061 hwmgr->backend = data;
2cc0c0b5 5062 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
a23eefa2 5063 hwmgr->pptable_func = &tonga_pptable_funcs;
2cc0c0b5 5064 pp_polaris10_thermal_initialize(hwmgr);
a23eefa2
RZ		 5065
5066 return 0;
5067}
Linux 6.x block layer and io_uring tree(s)