[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / hardwaremanager.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/errno.h>
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "power_state.h"
#include "pp_acpi.h"
#include "amd_acpi.h"
#include "amd_powerplay.h"

#define PHM_FUNC_CHECK(hw) \
	do {							\
		if ((hw) == NULL || (hw)->hwmgr_func == NULL)	\
			return -EINVAL;				\
	} while (0)

void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);

	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
}

bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
{
	return hwmgr->block_hw_access;
}

int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
{
	hwmgr->block_hw_access = block;
	return 0;
}

int phm_setup_asic(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->asic_setup)
			return hwmgr->hwmgr_func->asic_setup(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_set_power_state(struct pp_hwmgr *hwmgr,
		    const struct pp_hw_power_state *pcurrent_state,
		    const struct pp_hw_power_state *pnew_power_state)
{
	struct phm_set_power_state_input states;

	PHM_FUNC_CHECK(hwmgr);

	states.pcurrent_state = pcurrent_state;
	states.pnew_state = pnew_power_state;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_state_set)
			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	}

	return 0;
}

int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
			return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr,
				&(hwmgr->enable_dynamic_state_management),
				NULL, NULL);
	}
	return 0;
}

int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
		return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);

	return 0;
}

int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				   struct pp_power_state *adjusted_ps,
			     const struct pp_power_state *current_ps)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
		return hwmgr->hwmgr_func->apply_state_adjust_rules(
									hwmgr,
								 adjusted_ps,
								 current_ps);
	return 0;
}

int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	return 0;
}

int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	return 0;
}

int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->powergate_vce != NULL)
		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	return 0;
}

int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	}
	return 0;
}

int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->display_config_changed)
			hwmgr->hwmgr_func->display_config_changed(hwmgr);
	} else
		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
	return 0;
}

int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface))
		if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);

	return 0;
}

int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
}

int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
}

/**
* Initializes the thermal controller subsystem.
*
* @param    pHwMgr  the address of the powerplay hardware manager.
* @param    pTemperatureRange the address of the structure holding the temperature range.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
*/
int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
{

	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
}


bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
}


int phm_check_states_equal(struct pp_hwmgr *hwmgr,
				 const struct pp_hw_power_state *pstate1,
				 const struct pp_hw_power_state *pstate2,
				 bool *equal)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->check_states_equal == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
}

int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
		    const struct amd_pp_display_configuration *display_config)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
		return -EINVAL;

	hwmgr->display_config = *display_config;
	/* to do pass other display configuration in furture */

	if (hwmgr->hwmgr_func->store_cc6_data)
		hwmgr->hwmgr_func->store_cc6_data(hwmgr,
				display_config->cpu_pstate_separation_time,
				display_config->cpu_cc6_disable,
				display_config->cpu_pstate_disable,
				display_config->nb_pstate_switch_disable);

	return 0;
}

int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
		struct amd_pp_dal_clock_info *info)
{
	PHM_FUNC_CHECK(hwmgr);

	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
}

int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);

	return 0;
}
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/errno.h>
	24	#include "hwmgr.h"
	25	#include "hardwaremanager.h"
28a18bab	26	#include "power_state.h"
3bace359 JZ	27	#include "pp_acpi.h"
3bace359 JZ	28	#include "amd_acpi.h"
7fb72a1f	29	#include "amd_powerplay.h"
3bace359	30
88b8dcbe RZ	31	#define PHM_FUNC_CHECK(hw) \
	32	do { \
	33	if ((hw) == NULL \|\| (hw)->hwmgr_func == NULL) \
	34	return -EINVAL; \
	35	} while (0)
	36
3bace359 JZ	37	void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
	38	{
	39	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	40	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	41	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	42	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	43	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	44	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	45	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	46	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	47	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	48	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
	49
	50	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	51	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	52	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
	53
	54	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	55
	56	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	57	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
	58
	59	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
	60
	61	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
	62	acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
	63	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	64	}
	65
28a18bab RZ	66	bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
	67	{
	68	return hwmgr->block_hw_access;
	69	}
	70
	71	int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
	72	{
	73	hwmgr->block_hw_access = block;
	74	return 0;
	75	}
	76
3bace359 JZ	77	int phm_setup_asic(struct pp_hwmgr *hwmgr)
3bace359 JZ	78	{
88b8dcbe RZ	79	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	80
3bace359 JZ	81	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	82	PHM_PlatformCaps_TablelessHardwareInterface)) {
	83	if (NULL != hwmgr->hwmgr_func->asic_setup)
	84	return hwmgr->hwmgr_func->asic_setup(hwmgr);
	85	} else {
28a18bab	86	return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
3bace359 JZ	87	NULL, NULL);
	88	}
	89
	90	return 0;
	91	}
	92
28a18bab RZ	93	int phm_set_power_state(struct pp_hwmgr *hwmgr,
	94	const struct pp_hw_power_state *pcurrent_state,
	95	const struct pp_hw_power_state *pnew_power_state)
	96	{
	97	struct phm_set_power_state_input states;
	98
88b8dcbe RZ	99	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	100
28a18bab RZ	101	states.pcurrent_state = pcurrent_state;
	102	states.pnew_state = pnew_power_state;
	103
	104	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	105	PHM_PlatformCaps_TablelessHardwareInterface)) {
	106	if (NULL != hwmgr->hwmgr_func->power_state_set)
	107	return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	108	} else {
	109	return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	110	}
	111
	112	return 0;
	113	}
	114
3bace359 JZ	115	int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
3bace359 JZ	116	{
88b8dcbe RZ	117	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	118
3bace359 JZ	119	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	120	PHM_PlatformCaps_TablelessHardwareInterface)) {
	121	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
	122	return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	123	} else {
28a18bab	124	return phm_dispatch_table(hwmgr,
3bace359 JZ	125	&(hwmgr->enable_dynamic_state_management),
	126	NULL, NULL);
	127	}
	128	return 0;
	129	}
28a18bab RZ	130
	131	int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
	132	{
88b8dcbe RZ	133	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	134
28a18bab RZ	135	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
	136	return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
	137
	138	return 0;
	139	}
	140
	141	int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
	142	struct pp_power_state *adjusted_ps,
	143	const struct pp_power_state *current_ps)
	144	{
88b8dcbe RZ	145	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	146
28a18bab RZ	147	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
	148	return hwmgr->hwmgr_func->apply_state_adjust_rules(
	149	hwmgr,
	150	adjusted_ps,
	151	current_ps);
	152	return 0;
	153	}
	154
	155	int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
	156	{
88b8dcbe RZ	157	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	158
28a18bab RZ	159	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
	160	return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	161	return 0;
	162	}
	163
	164	int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
	165	{
88b8dcbe RZ	166	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	167
28a18bab RZ	168	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
	169	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	170	return 0;
	171	}
	172
	173	int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
	174	{
88b8dcbe RZ	175	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	176
28a18bab RZ	177	if (hwmgr->hwmgr_func->powergate_vce != NULL)
	178	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	179	return 0;
	180	}
	181
	182	int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
	183	{
88b8dcbe RZ	184	PHM_FUNC_CHECK(hwmgr);
88b8dcbe RZ	185
28a18bab RZ	186	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	187	PHM_PlatformCaps_TablelessHardwareInterface)) {
	188	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
	189	return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	190	} else {
	191	return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	192	}
	193	return 0;
	194	}
6f3bf747 RZ	195
	196	int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
	197	{
88b8dcbe	198	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	199
	200	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	201	PHM_PlatformCaps_TablelessHardwareInterface)) {
	202	if (NULL != hwmgr->hwmgr_func->display_config_changed)
	203	hwmgr->hwmgr_func->display_config_changed(hwmgr);
	204	} else
	205	return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
73afe621	206	return 0;
6f3bf747 RZ	207	}
	208
	209	int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
	210	{
88b8dcbe	211	PHM_FUNC_CHECK(hwmgr);
6f3bf747 RZ	212
	213	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	214	PHM_PlatformCaps_TablelessHardwareInterface))
eafbbd98	215	if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
6f3bf747 RZ	216	hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
6f3bf747 RZ	217
73afe621	218	return 0;
6f3bf747	219	}
fba4eef5 RZ	220
	221	int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
	222	{
88b8dcbe RZ	223	PHM_FUNC_CHECK(hwmgr);
	224
	225	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
fba4eef5 RZ	226	return -EINVAL;
	227
	228	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
	229	}
	230
	231	int phm_register_thermal_interrupt(struct pp_hwmgr hwmgr, const void info)
	232	{
88b8dcbe RZ	233	PHM_FUNC_CHECK(hwmgr);
	234
	235	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
fba4eef5 RZ	236	return -EINVAL;
	237
	238	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
	239	}
	240
	241	/**
	242	* Initializes the thermal controller subsystem.
	243	*
	244	* @param pHwMgr the address of the powerplay hardware manager.
	245	* @param pTemperatureRange the address of the structure holding the temperature range.
	246	* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
	247	*/
	248	int phm_start_thermal_controller(struct pp_hwmgr hwmgr, struct PP_TemperatureRange temperature_range)
	249	{
	250
	251	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
	252	}
09b4c872 RZ	253
	254
	255	bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
	256	{
88b8dcbe RZ	257	PHM_FUNC_CHECK(hwmgr);
	258
	259	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
09b4c872 RZ	260	return -EINVAL;
	261
	262	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
	263	}
	264
	265
	266	int phm_check_states_equal(struct pp_hwmgr *hwmgr,
	267	const struct pp_hw_power_state *pstate1,
	268	const struct pp_hw_power_state *pstate2,
	269	bool *equal)
	270	{
88b8dcbe RZ	271	PHM_FUNC_CHECK(hwmgr);
	272
	273	if (hwmgr->hwmgr_func->check_states_equal == NULL)
09b4c872 RZ	274	return -EINVAL;
	275
	276	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
	277	}
7fb72a1f RZ	278
	279	int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
	280	const struct amd_pp_display_configuration *display_config)
	281	{
88b8dcbe	282	PHM_FUNC_CHECK(hwmgr);
14f63411	283
88b8dcbe	284	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
7fb72a1f RZ	285	return -EINVAL;
7fb72a1f RZ	286
14f63411	287	hwmgr->display_config = *display_config;
7fb72a1f	288	/* to do pass other display configuration in furture */
7fb72a1f	289
14f63411 EY	290	if (hwmgr->hwmgr_func->store_cc6_data)
	291	hwmgr->hwmgr_func->store_cc6_data(hwmgr,
	292	display_config->cpu_pstate_separation_time,
	293	display_config->cpu_cc6_disable,
	294	display_config->cpu_pstate_disable,
	295	display_config->nb_pstate_switch_disable);
	296
	297	return 0;
7fb72a1f	298	}
73afe621	299
c4dd206b	300	int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
88b8dcbe	301	struct amd_pp_dal_clock_info *info)
c4dd206b	302	{
88b8dcbe RZ	303	PHM_FUNC_CHECK(hwmgr);
	304
	305	if (info == NULL \|\| hwmgr->hwmgr_func->get_dal_power_level == NULL)
c4dd206b VP	306	return -EINVAL;
c4dd206b VP	307
1c9a9082	308	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
c4dd206b VP	309	}
c4dd206b VP	310
73afe621 RZ	311	int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
73afe621 RZ	312	{
88b8dcbe RZ	313	PHM_FUNC_CHECK(hwmgr);
	314
	315	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
73afe621 RZ	316	return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
	317
	318	return 0;
	319	}
	320