[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / hardwaremanager.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/errno.h>
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "power_state.h"
#include "pp_acpi.h"
#include "amd_acpi.h"
#include "amd_powerplay.h"

void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);

	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
}

bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
{
	return hwmgr->block_hw_access;
}

int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
{
	hwmgr->block_hw_access = block;
	return 0;
}

int phm_setup_asic(struct pp_hwmgr *hwmgr)
{
	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->asic_setup)
			return hwmgr->hwmgr_func->asic_setup(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
					  NULL, NULL);
	}

	return 0;
}

int phm_set_power_state(struct pp_hwmgr *hwmgr,
		    const struct pp_hw_power_state *pcurrent_state,
		    const struct pp_hw_power_state *pnew_power_state)
{
	struct phm_set_power_state_input states;

	states.pcurrent_state = pcurrent_state;
	states.pnew_state = pnew_power_state;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->power_state_set)
			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	}

	return 0;
}

int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
			return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr,
				&(hwmgr->enable_dynamic_state_management),
				NULL, NULL);
	}
	return 0;
}

int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
{
	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
		return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);

	return 0;
}

int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				   struct pp_power_state *adjusted_ps,
			     const struct pp_power_state *current_ps)
{
	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
		return hwmgr->hwmgr_func->apply_state_adjust_rules(
									hwmgr,
								 adjusted_ps,
								 current_ps);
	return 0;
}

int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	return 0;
}

int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
{
	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	return 0;
}

int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
{
	if (hwmgr->hwmgr_func->powergate_vce != NULL)
		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	return 0;
}

int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	} else {
		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	}
	return 0;
}

int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
	if (hwmgr == NULL)
		return -EINVAL;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->display_config_changed)
			hwmgr->hwmgr_func->display_config_changed(hwmgr);
	} else
		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
	return 0;
}

int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
	if (hwmgr == NULL)
		return -EINVAL;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
				 PHM_PlatformCaps_TablelessHardwareInterface))
		if (NULL != hwmgr->hwmgr_func->display_config_changed)
			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);

	return 0;
}

int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
{
	if (hwmgr == NULL || hwmgr->hwmgr_func->stop_thermal_controller == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
}

int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
{
	if (hwmgr == NULL || hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
}

/**
* Initializes the thermal controller subsystem.
*
* @param    pHwMgr  the address of the powerplay hardware manager.
* @param    pTemperatureRange the address of the structure holding the temperature range.
* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
*/
int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
{

	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
}


bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{
	if (hwmgr == NULL || hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
}


int phm_check_states_equal(struct pp_hwmgr *hwmgr,
				 const struct pp_hw_power_state *pstate1,
				 const struct pp_hw_power_state *pstate2,
				 bool *equal)
{
	if (hwmgr == NULL || hwmgr->hwmgr_func->check_states_equal == NULL)
		return -EINVAL;

	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
}

int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
		    const struct amd_pp_display_configuration *display_config)
{
	if (hwmgr == NULL || hwmgr->hwmgr_func->store_cc6_data == NULL)
		return -EINVAL;

	/* to do pass other display configuration in furture */
	return hwmgr->hwmgr_func->store_cc6_data(hwmgr,
					display_config->cpu_pstate_separation_time,
					display_config->cpu_cc6_disable,
					display_config->cpu_pstate_disable,
					display_config->nb_pstate_switch_disable);

}

int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
	if (hwmgr != NULL && hwmgr->hwmgr_func->set_cpu_power_state != NULL)
		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);

	return 0;
}
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/errno.h>
	24	#include "hwmgr.h"
	25	#include "hardwaremanager.h"
28a18bab	26	#include "power_state.h"
3bace359 JZ	27	#include "pp_acpi.h"
3bace359 JZ	28	#include "amd_acpi.h"
7fb72a1f	29	#include "amd_powerplay.h"
3bace359 JZ	30
	31	void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
	32	{
	33	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
	34	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
	35	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
	36	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
	37	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
	38	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
	39	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
	40	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
	41	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
	42	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
	43
	44	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
	45	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
	46	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
	47
	48	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	49
	50	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
	51	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
	52
	53	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
	54
	55	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
	56	acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
	57	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
	58	}
	59
28a18bab RZ	60	bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
	61	{
	62	return hwmgr->block_hw_access;
	63	}
	64
	65	int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
	66	{
	67	hwmgr->block_hw_access = block;
	68	return 0;
	69	}
	70
3bace359 JZ	71	int phm_setup_asic(struct pp_hwmgr *hwmgr)
	72	{
	73	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	74	PHM_PlatformCaps_TablelessHardwareInterface)) {
	75	if (NULL != hwmgr->hwmgr_func->asic_setup)
	76	return hwmgr->hwmgr_func->asic_setup(hwmgr);
	77	} else {
28a18bab	78	return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
3bace359 JZ	79	NULL, NULL);
	80	}
	81
	82	return 0;
	83	}
	84
28a18bab RZ	85	int phm_set_power_state(struct pp_hwmgr *hwmgr,
	86	const struct pp_hw_power_state *pcurrent_state,
	87	const struct pp_hw_power_state *pnew_power_state)
	88	{
	89	struct phm_set_power_state_input states;
	90
	91	states.pcurrent_state = pcurrent_state;
	92	states.pnew_state = pnew_power_state;
	93
	94	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	95	PHM_PlatformCaps_TablelessHardwareInterface)) {
	96	if (NULL != hwmgr->hwmgr_func->power_state_set)
	97	return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
	98	} else {
	99	return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
	100	}
	101
	102	return 0;
	103	}
	104
3bace359 JZ	105	int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
	106	{
	107	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	108	PHM_PlatformCaps_TablelessHardwareInterface)) {
	109	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
	110	return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
	111	} else {
28a18bab	112	return phm_dispatch_table(hwmgr,
3bace359 JZ	113	&(hwmgr->enable_dynamic_state_management),
	114	NULL, NULL);
	115	}
	116	return 0;
	117	}
28a18bab RZ	118
	119	int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
	120	{
	121	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
	122	return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
	123
	124	return 0;
	125	}
	126
	127	int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
	128	struct pp_power_state *adjusted_ps,
	129	const struct pp_power_state *current_ps)
	130	{
	131	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
	132	return hwmgr->hwmgr_func->apply_state_adjust_rules(
	133	hwmgr,
	134	adjusted_ps,
	135	current_ps);
	136	return 0;
	137	}
	138
	139	int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
	140	{
	141	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
	142	return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
	143	return 0;
	144	}
	145
	146	int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
	147	{
	148	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
	149	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
	150	return 0;
	151	}
	152
	153	int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
	154	{
	155	if (hwmgr->hwmgr_func->powergate_vce != NULL)
	156	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
	157	return 0;
	158	}
	159
	160	int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
	161	{
	162	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	163	PHM_PlatformCaps_TablelessHardwareInterface)) {
	164	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
	165	return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
	166	} else {
	167	return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
	168	}
	169	return 0;
	170	}
6f3bf747 RZ	171
	172	int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
	173	{
	174	if (hwmgr == NULL)
	175	return -EINVAL;
	176
	177	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	178	PHM_PlatformCaps_TablelessHardwareInterface)) {
	179	if (NULL != hwmgr->hwmgr_func->display_config_changed)
	180	hwmgr->hwmgr_func->display_config_changed(hwmgr);
	181	} else
	182	return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
73afe621	183	return 0;
6f3bf747 RZ	184	}
	185
	186	int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
	187	{
	188	if (hwmgr == NULL)
	189	return -EINVAL;
	190
	191	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	192	PHM_PlatformCaps_TablelessHardwareInterface))
	193	if (NULL != hwmgr->hwmgr_func->display_config_changed)
	194	hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
	195
73afe621	196	return 0;
6f3bf747	197	}
fba4eef5 RZ	198
	199	int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
	200	{
	201	if (hwmgr == NULL \|\| hwmgr->hwmgr_func->stop_thermal_controller == NULL)
	202	return -EINVAL;
	203
	204	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
	205	}
	206
	207	int phm_register_thermal_interrupt(struct pp_hwmgr hwmgr, const void info)
	208	{
	209	if (hwmgr == NULL \|\| hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
	210	return -EINVAL;
	211
	212	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
	213	}
	214
	215	/**
	216	* Initializes the thermal controller subsystem.
	217	*
	218	* @param pHwMgr the address of the powerplay hardware manager.
	219	* @param pTemperatureRange the address of the structure holding the temperature range.
	220	* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
	221	*/
	222	int phm_start_thermal_controller(struct pp_hwmgr hwmgr, struct PP_TemperatureRange temperature_range)
	223	{
	224
	225	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
	226	}
09b4c872 RZ	227
	228
	229	bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
	230	{
	231	if (hwmgr == NULL \|\| hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
	232	return -EINVAL;
	233
	234	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
	235	}
	236
	237
	238	int phm_check_states_equal(struct pp_hwmgr *hwmgr,
	239	const struct pp_hw_power_state *pstate1,
	240	const struct pp_hw_power_state *pstate2,
	241	bool *equal)
	242	{
	243	if (hwmgr == NULL \|\| hwmgr->hwmgr_func->check_states_equal == NULL)
	244	return -EINVAL;
	245
	246	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
	247	}
7fb72a1f RZ	248
	249	int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
	250	const struct amd_pp_display_configuration *display_config)
	251	{
	252	if (hwmgr == NULL \|\| hwmgr->hwmgr_func->store_cc6_data == NULL)
	253	return -EINVAL;
	254
	255	/* to do pass other display configuration in furture */
	256	return hwmgr->hwmgr_func->store_cc6_data(hwmgr,
	257	display_config->cpu_pstate_separation_time,
	258	display_config->cpu_cc6_disable,
	259	display_config->cpu_pstate_disable,
	260	display_config->nb_pstate_switch_disable);
	261
	262	}
73afe621 RZ	263
	264	int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
	265	{
	266	if (hwmgr != NULL && hwmgr->hwmgr_func->set_cpu_power_state != NULL)
	267	return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
	268
	269	return 0;
	270	}
	271