drm/tegra: Fix window[0] base address corruption
[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / fiji_powertune.h
CommitLineData
aabcb7c1
EH
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef FIJI_POWERTUNE_H
24#define FIJI_POWERTUNE_H
25
26enum fiji_pt_config_reg_type {
27 FIJI_CONFIGREG_MMR = 0,
28 FIJI_CONFIGREG_SMC_IND,
29 FIJI_CONFIGREG_DIDT_IND,
30 FIJI_CONFIGREG_CACHE,
31 FIJI_CONFIGREG_MAX
32};
33
34/* PowerContainment Features */
35#define POWERCONTAINMENT_FEATURE_DTE 0x00000001
36#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
37#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
38
5e037834
RZ
39#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0
40#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6
41#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0
42#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6
43#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0
44#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6
45#define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK 0xe0000000
46#define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001d
47#define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK 0xe0000000
48#define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001d
49#define DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK 0xe0000000
50#define DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001d
51
aabcb7c1
EH
52struct fiji_pt_config_reg {
53 uint32_t offset;
54 uint32_t mask;
55 uint32_t shift;
56 uint32_t value;
57 enum fiji_pt_config_reg_type type;
58};
59
60struct fiji_pt_defaults
61{
62 uint8_t SviLoadLineEn;
63 uint8_t SviLoadLineVddC;
64 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
65 uint8_t TDC_MAWt;
66 uint8_t TdcWaterfallCtl;
67 uint8_t DTEAmbientTempBase;
68};
69
70void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
71int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
72int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr);
73int fiji_enable_smc_cac(struct pp_hwmgr *hwmgr);
55d74fc9 74int fiji_disable_smc_cac(struct pp_hwmgr *hwmgr);
aabcb7c1 75int fiji_enable_power_containment(struct pp_hwmgr *hwmgr);
55d74fc9 76int fiji_disable_power_containment(struct pp_hwmgr *hwmgr);
aabcb7c1
EH
77int fiji_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
78int fiji_power_control_set_level(struct pp_hwmgr *hwmgr);
79
80#endif /* FIJI_POWERTUNE_H */
81