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Merge tag 'drm-intel-next-fixes-2016-07-25' of git://anongit.freedesktop.org/drm...
[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / hwmgr / fiji_hwmgr.h
CommitLineData
aabcb7c1
EH		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _FIJI_HWMGR_H_
25#define _FIJI_HWMGR_H_
26
27#include "hwmgr.h"
28#include "smu73.h"
29#include "smu73_discrete.h"
30#include "ppatomctrl.h"
31#include "fiji_ppsmc.h"
1445abf0 32#include "pp_endian.h"
aabcb7c1
EH		 33
34#define FIJI_MAX_HARDWARE_POWERLEVELS 2
35#define FIJI_AT_DFLT 30
36
37#define FIJI_VOLTAGE_CONTROL_NONE 0x0
38#define FIJI_VOLTAGE_CONTROL_BY_GPIO 0x1
39#define FIJI_VOLTAGE_CONTROL_BY_SVID2 0x2
40#define FIJI_VOLTAGE_CONTROL_MERGED 0x3
41
42#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
43#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
44#define DPMTABLE_UPDATE_SCLK 0x00000004
45#define DPMTABLE_UPDATE_MCLK 0x00000008
46
47struct fiji_performance_level {
48 uint32_t memory_clock;
49 uint32_t engine_clock;
50 uint16_t pcie_gen;
51 uint16_t pcie_lane;
52};
53
54struct fiji_uvd_clocks {
55 uint32_t vclk;
56 uint32_t dclk;
57};
58
59struct fiji_vce_clocks {
60 uint32_t evclk;
61 uint32_t ecclk;
62};
63
64struct fiji_power_state {
65 uint32_t magic;
66 struct fiji_uvd_clocks uvd_clks;
67 struct fiji_vce_clocks vce_clks;
68 uint32_t sam_clk;
69 uint32_t acp_clk;
70 uint16_t performance_level_count;
71 bool dc_compatible;
72 uint32_t sclk_threshold;
73 struct fiji_performance_level performance_levels[FIJI_MAX_HARDWARE_POWERLEVELS];
74};
75
76struct fiji_dpm_level {
77 bool enabled;
78 uint32_t value;
79 uint32_t param1;
80};
81
82#define FIJI_MAX_DEEPSLEEP_DIVIDER_ID 5
83#define MAX_REGULAR_DPM_NUMBER 8
84#define FIJI_MINIMUM_ENGINE_CLOCK 2500
85
86struct fiji_single_dpm_table {
87 uint32_t count;
88 struct fiji_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
89};
90
91struct fiji_dpm_table {
92 struct fiji_single_dpm_table sclk_table;
93 struct fiji_single_dpm_table mclk_table;
94 struct fiji_single_dpm_table pcie_speed_table;
95 struct fiji_single_dpm_table vddc_table;
96 struct fiji_single_dpm_table vddci_table;
97 struct fiji_single_dpm_table mvdd_table;
98};
99
100struct fiji_clock_registers {
101 uint32_t vCG_SPLL_FUNC_CNTL;
102 uint32_t vCG_SPLL_FUNC_CNTL_2;
103 uint32_t vCG_SPLL_FUNC_CNTL_3;
104 uint32_t vCG_SPLL_FUNC_CNTL_4;
105 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
106 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
107 uint32_t vDLL_CNTL;
108 uint32_t vMCLK_PWRMGT_CNTL;
109 uint32_t vMPLL_AD_FUNC_CNTL;
110 uint32_t vMPLL_DQ_FUNC_CNTL;
111 uint32_t vMPLL_FUNC_CNTL;
112 uint32_t vMPLL_FUNC_CNTL_1;
113 uint32_t vMPLL_FUNC_CNTL_2;
114 uint32_t vMPLL_SS1;
115 uint32_t vMPLL_SS2;
116};
117
118struct fiji_voltage_smio_registers {
119 uint32_t vS0_VID_LOWER_SMIO_CNTL;
120};
121
122#define FIJI_MAX_LEAKAGE_COUNT 8
123struct fiji_leakage_voltage {
124 uint16_t count;
125 uint16_t leakage_id[FIJI_MAX_LEAKAGE_COUNT];
126 uint16_t actual_voltage[FIJI_MAX_LEAKAGE_COUNT];
127};
128
129struct fiji_vbios_boot_state {
130 uint16_t mvdd_bootup_value;
131 uint16_t vddc_bootup_value;
132 uint16_t vddci_bootup_value;
133 uint32_t sclk_bootup_value;
134 uint32_t mclk_bootup_value;
135 uint16_t pcie_gen_bootup_value;
136 uint16_t pcie_lane_bootup_value;
137};
138
139struct fiji_bacos {
140 uint32_t best_match;
141 uint32_t baco_flags;
142 struct fiji_performance_level performance_level;
143};
144
145/* Ultra Low Voltage parameter structure */
146struct fiji_ulv_parm {
147 bool ulv_supported;
148 uint32_t cg_ulv_parameter;
149 uint32_t ulv_volt_change_delay;
150 struct fiji_performance_level ulv_power_level;
151};
152
153struct fiji_display_timing {
154 uint32_t min_clock_in_sr;
155 uint32_t num_existing_displays;
156};
157
158struct fiji_dpmlevel_enable_mask {
159 uint32_t uvd_dpm_enable_mask;
160 uint32_t vce_dpm_enable_mask;
161 uint32_t acp_dpm_enable_mask;
162 uint32_t samu_dpm_enable_mask;
163 uint32_t sclk_dpm_enable_mask;
164 uint32_t mclk_dpm_enable_mask;
165 uint32_t pcie_dpm_enable_mask;
166};
167
168struct fiji_pcie_perf_range {
169 uint16_t max;
170 uint16_t min;
171};
172
173struct fiji_hwmgr {
174 struct fiji_dpm_table dpm_table;
175 struct fiji_dpm_table golden_dpm_table;
176
177 uint32_t voting_rights_clients0;
178 uint32_t voting_rights_clients1;
179 uint32_t voting_rights_clients2;
180 uint32_t voting_rights_clients3;
181 uint32_t voting_rights_clients4;
182 uint32_t voting_rights_clients5;
183 uint32_t voting_rights_clients6;
184 uint32_t voting_rights_clients7;
185 uint32_t static_screen_threshold_unit;
186 uint32_t static_screen_threshold;
187 uint32_t voltage_control;
188 uint32_t vddc_vddci_delta;
189
190 uint32_t active_auto_throttle_sources;
191
192 struct fiji_clock_registers clock_registers;
193 struct fiji_voltage_smio_registers voltage_smio_registers;
194
195 bool is_memory_gddr5;
196 uint16_t acpi_vddc;
197 bool pspp_notify_required;
198 uint16_t force_pcie_gen;
199 uint16_t acpi_pcie_gen;
200 uint32_t pcie_gen_cap;
201 uint32_t pcie_lane_cap;
202 uint32_t pcie_spc_cap;
203 struct fiji_leakage_voltage vddc_leakage;
204 struct fiji_leakage_voltage Vddci_leakage;
205
206 uint32_t mvdd_control;
207 uint32_t vddc_mask_low;
208 uint32_t mvdd_mask_low;
209 uint16_t max_vddc_in_pptable;
210 uint16_t min_vddc_in_pptable;
211 uint16_t max_vddci_in_pptable;
212 uint16_t min_vddci_in_pptable;
213 uint32_t mclk_strobe_mode_threshold;
214 uint32_t mclk_stutter_mode_threshold;
215 uint32_t mclk_edc_enable_threshold;
216 uint32_t mclk_edcwr_enable_threshold;
217 bool is_uvd_enabled;
218 struct fiji_vbios_boot_state vbios_boot_state;
219
220 bool battery_state;
221 bool is_tlu_enabled;
222
223 /* ---- SMC SRAM Address of firmware header tables ---- */
224 uint32_t sram_end;
225 uint32_t dpm_table_start;
226 uint32_t soft_regs_start;
227 uint32_t mc_reg_table_start;
228 uint32_t fan_table_start;
229 uint32_t arb_table_start;
230 struct SMU73_Discrete_DpmTable smc_state_table;
231 struct SMU73_Discrete_Ulv ulv_setting;
232
233 /* ---- Stuff originally coming from Evergreen ---- */
234 uint32_t vddci_control;
235 struct pp_atomctrl_voltage_table vddc_voltage_table;
236 struct pp_atomctrl_voltage_table vddci_voltage_table;
237 struct pp_atomctrl_voltage_table mvdd_voltage_table;
238
239 uint32_t mgcg_cgtt_local2;
240 uint32_t mgcg_cgtt_local3;
241 uint32_t gpio_debug;
242 uint32_t mc_micro_code_feature;
243 uint32_t highest_mclk;
244 uint16_t acpi_vddci;
245 uint8_t mvdd_high_index;
246 uint8_t mvdd_low_index;
247 bool dll_default_on;
248 bool performance_request_registered;
249
250 /* ---- Low Power Features ---- */
251 struct fiji_bacos bacos;
252 struct fiji_ulv_parm ulv;
253
254 /* ---- CAC Stuff ---- */
255 uint32_t cac_table_start;
256 bool cac_configuration_required;
257 bool driver_calculate_cac_leakage;
258 bool cac_enabled;
259
260 /* ---- DPM2 Parameters ---- */
261 uint32_t power_containment_features;
262 bool enable_dte_feature;
263 bool enable_tdc_limit_feature;
264 bool enable_pkg_pwr_tracking_feature;
265 bool disable_uvd_power_tune_feature;
f498d9ed 266 const struct fiji_pt_defaults *power_tune_defaults;
aabcb7c1
EH		 267 struct SMU73_Discrete_PmFuses power_tune_table;
268 uint32_t dte_tj_offset;
269 uint32_t fast_watermark_threshold;
270
271 /* ---- Phase Shedding ---- */
272 bool vddc_phase_shed_control;
273
274 /* ---- DI/DT ---- */
275 struct fiji_display_timing display_timing;
276
277 /* ---- Thermal Temperature Setting ---- */
278 struct fiji_dpmlevel_enable_mask dpm_level_enable_mask;
279 uint32_t need_update_smu7_dpm_table;
280 uint32_t sclk_dpm_key_disabled;
281 uint32_t mclk_dpm_key_disabled;
282 uint32_t pcie_dpm_key_disabled;
283 uint32_t min_engine_clocks;
284 struct fiji_pcie_perf_range pcie_gen_performance;
285 struct fiji_pcie_perf_range pcie_lane_performance;
286 struct fiji_pcie_perf_range pcie_gen_power_saving;
287 struct fiji_pcie_perf_range pcie_lane_power_saving;
288 bool use_pcie_performance_levels;
289 bool use_pcie_power_saving_levels;
290 uint32_t activity_target[SMU73_MAX_LEVELS_GRAPHICS];
291 uint32_t mclk_activity_target;
292 uint32_t mclk_dpm0_activity_target;
293 uint32_t low_sclk_interrupt_threshold;
294 uint32_t last_mclk_dpm_enable_mask;
295 bool uvd_enabled;
296
297 /* ---- Power Gating States ---- */
298 bool uvd_power_gated;
299 bool vce_power_gated;
300 bool samu_power_gated;
301 bool acp_power_gated;
302 bool pg_acp_init;
303 bool frtc_enabled;
304 bool frtc_status_changed;
305};
306
307/* To convert to Q8.8 format for firmware */
308#define FIJI_Q88_FORMAT_CONVERSION_UNIT 256
309
310enum Fiji_I2CLineID {
311 Fiji_I2CLineID_DDC1 = 0x90,
312 Fiji_I2CLineID_DDC2 = 0x91,
313 Fiji_I2CLineID_DDC3 = 0x92,
314 Fiji_I2CLineID_DDC4 = 0x93,
315 Fiji_I2CLineID_DDC5 = 0x94,
316 Fiji_I2CLineID_DDC6 = 0x95,
317 Fiji_I2CLineID_SCLSDA = 0x96,
318 Fiji_I2CLineID_DDCVGA = 0x97
319};
320
321#define Fiji_I2C_DDC1DATA 0
322#define Fiji_I2C_DDC1CLK 1
323#define Fiji_I2C_DDC2DATA 2
324#define Fiji_I2C_DDC2CLK 3
325#define Fiji_I2C_DDC3DATA 4
326#define Fiji_I2C_DDC3CLK 5
327#define Fiji_I2C_SDA 40
328#define Fiji_I2C_SCL 41
329#define Fiji_I2C_DDC4DATA 65
330#define Fiji_I2C_DDC4CLK 66
331#define Fiji_I2C_DDC5DATA 0x48
332#define Fiji_I2C_DDC5CLK 0x49
333#define Fiji_I2C_DDC6DATA 0x4a
334#define Fiji_I2C_DDC6CLK 0x4b
335#define Fiji_I2C_DDCVGADATA 0x4c
336#define Fiji_I2C_DDCVGACLK 0x4d
337
338#define FIJI_UNUSED_GPIO_PIN 0x7F
339
340extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
aabcb7c1 341extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
ea617bc9
EH		 342extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
343extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
91c4c981
EH		 344int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
345int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
346int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
347int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
348int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
aabcb7c1 349
aabcb7c1 350#endif /* _FIJI_HWMGR_H_ */
Linux 6.x block layer and io_uring tree(s)