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drm/amd/powerplay: sort the call flow on temperature ranges retrieving
[linux-2.6-block.git] / drivers / gpu / drm / amd / powerplay / arcturus_ppt.c
CommitLineData
6fba5906
CG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
6fba5906
CG		 24#include <linux/firmware.h>
25#include "amdgpu.h"
26#include "amdgpu_smu.h"
18c1d3ce 27#include "smu_internal.h"
6fba5906
CG		 28#include "atomfirmware.h"
29#include "amdgpu_atomfirmware.h"
30#include "smu_v11_0.h"
31#include "smu11_driver_if_arcturus.h"
32#include "soc15_common.h"
33#include "atom.h"
34#include "power_state.h"
35#include "arcturus_ppt.h"
a94235af 36#include "smu_v11_0_pptable.h"
6fba5906 37#include "arcturus_ppsmc.h"
49e78c82 38#include "nbio/nbio_7_4_offset.h"
6fba5906 39#include "nbio/nbio_7_4_sh_mask.h"
947c127b
LG		 40#include "thm/thm_11_0_2_offset.h"
41#include "thm/thm_11_0_2_sh_mask.h"
0525f297 42#include "amdgpu_xgmi.h"
d1a84427
AG		 43#include <linux/i2c.h>
44#include <linux/pci.h>
45#include "amdgpu_ras.h"
46
55084d7f
EQ		 47/*
48 * DO NOT use these for err/warn/info/debug messages.
49 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
50 * They are more MGPU friendly.
51 */
52#undef pr_err
53#undef pr_warn
54#undef pr_info
55#undef pr_debug
56
9015d60c 57#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
6fba5906 58
d4f3c0b3
WS		 59#define MSG_MAP(msg, index, valid_in_vf) \
60 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
55bf7e62
EQ		 61#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
62 [smu_feature] = {1, (arcturus_feature)}
6fba5906 63
a94235af
EQ		 64#define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
65#define SMU_FEATURES_LOW_SHIFT 0
66#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
67#define SMU_FEATURES_HIGH_SHIFT 32
68
3f513bae
CG		 69#define SMC_DPM_FEATURE ( \
70 FEATURE_DPM_PREFETCHER_MASK | \
71 FEATURE_DPM_GFXCLK_MASK | \
72 FEATURE_DPM_UCLK_MASK | \
73 FEATURE_DPM_SOCCLK_MASK | \
74 FEATURE_DPM_MP0CLK_MASK | \
75 FEATURE_DPM_FCLK_MASK | \
76 FEATURE_DPM_XGMI_MASK)
77
1f23cadb
EQ		 78/* possible frequency drift (1Mhz) */
79#define EPSILON 1
80
d4f3c0b3
WS		 81static struct smu_11_0_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
82 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
83 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
84 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
85 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
86 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
87 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
88 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
89 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
90 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
91 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
92 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
93 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0),
94 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0),
95 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
96 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
97 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
98 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
99 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
100 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
101 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
102 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
103 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
104 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
105 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
106 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
107 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
108 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
109 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
110 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
111 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
112 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
113 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
114 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
115 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
116 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0),
117 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
118 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
119 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
120 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
121 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0),
122 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0),
123 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0),
124 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0),
125 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
126 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
127 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
128 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0),
129 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0),
130 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
131 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
132 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
133 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
134 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
135 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
136 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0),
137 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
138 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
139 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
bce9ff0e
KR		 140 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1),
141 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1),
6fba5906
CG		 142};
143
a94235af
EQ		 144static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
145 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
146 CLK_MAP(SCLK, PPCLK_GFXCLK),
147 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
148 CLK_MAP(FCLK, PPCLK_FCLK),
149 CLK_MAP(UCLK, PPCLK_UCLK),
150 CLK_MAP(MCLK, PPCLK_UCLK),
151 CLK_MAP(DCLK, PPCLK_DCLK),
152 CLK_MAP(VCLK, PPCLK_VCLK),
153};
154
155static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
156 FEA_MAP(DPM_PREFETCHER),
157 FEA_MAP(DPM_GFXCLK),
158 FEA_MAP(DPM_UCLK),
159 FEA_MAP(DPM_SOCCLK),
55bf7e62 160 FEA_MAP(DPM_FCLK),
a94235af 161 FEA_MAP(DPM_MP0CLK),
57be797c 162 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
a94235af
EQ		 163 FEA_MAP(DS_GFXCLK),
164 FEA_MAP(DS_SOCCLK),
165 FEA_MAP(DS_LCLK),
55bf7e62 166 FEA_MAP(DS_FCLK),
a94235af
EQ		 167 FEA_MAP(DS_UCLK),
168 FEA_MAP(GFX_ULV),
55bf7e62 169 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
a94235af 170 FEA_MAP(RSMU_SMN_CG),
57be797c 171 FEA_MAP(WAFL_CG),
a94235af
EQ		 172 FEA_MAP(PPT),
173 FEA_MAP(TDC),
174 FEA_MAP(APCC_PLUS),
175 FEA_MAP(VR0HOT),
176 FEA_MAP(VR1HOT),
177 FEA_MAP(FW_CTF),
178 FEA_MAP(FAN_CONTROL),
179 FEA_MAP(THERMAL),
180 FEA_MAP(OUT_OF_BAND_MONITOR),
181 FEA_MAP(TEMP_DEPENDENT_VMIN),
182};
183
184static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
185 TAB_MAP(PPTABLE),
186 TAB_MAP(AVFS),
187 TAB_MAP(AVFS_PSM_DEBUG),
188 TAB_MAP(AVFS_FUSE_OVERRIDE),
189 TAB_MAP(PMSTATUSLOG),
190 TAB_MAP(SMU_METRICS),
191 TAB_MAP(DRIVER_SMU_CONFIG),
192 TAB_MAP(OVERDRIVE),
d1a84427 193 TAB_MAP(I2C_COMMANDS),
18d7ab98 194 TAB_MAP(ACTIVITY_MONITOR_COEFF),
a94235af
EQ		 195};
196
197static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
198 PWR_MAP(AC),
199 PWR_MAP(DC),
200};
201
202static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
61696312 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
a94235af
EQ		 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
208};
209
6fba5906
CG		 210static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
211{
d4f3c0b3 212 struct smu_11_0_msg_mapping mapping;
6fba5906
CG		 213
214 if (index >= SMU_MSG_MAX_COUNT)
215 return -EINVAL;
216
7e01a2ec 217 mapping = arcturus_message_map[index];
790ef68a 218 if (!(mapping.valid_mapping))
6fba5906
CG		 219 return -EINVAL;
220
4ea5081c
WS		 221 if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)
222 return -EACCES;
223
7e01a2ec 224 return mapping.map_to;
6fba5906
CG		 225}
226
a94235af
EQ		 227static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
228{
229 struct smu_11_0_cmn2aisc_mapping mapping;
230
231 if (index >= SMU_CLK_COUNT)
232 return -EINVAL;
233
234 mapping = arcturus_clk_map[index];
235 if (!(mapping.valid_mapping)) {
d9811cfc 236 dev_warn(smc->adev->dev, "Unsupported SMU clk: %d\n", index);
a94235af
EQ		 237 return -EINVAL;
238 }
239
240 return mapping.map_to;
241}
242
243static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
244{
245 struct smu_11_0_cmn2aisc_mapping mapping;
246
247 if (index >= SMU_FEATURE_COUNT)
248 return -EINVAL;
249
250 mapping = arcturus_feature_mask_map[index];
251 if (!(mapping.valid_mapping)) {
a94235af
EQ		 252 return -EINVAL;
253 }
254
255 return mapping.map_to;
256}
257
258static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
259{
260 struct smu_11_0_cmn2aisc_mapping mapping;
261
262 if (index >= SMU_TABLE_COUNT)
263 return -EINVAL;
264
265 mapping = arcturus_table_map[index];
266 if (!(mapping.valid_mapping)) {
d9811cfc 267 dev_warn(smc->adev->dev, "Unsupported SMU table: %d\n", index);
a94235af
EQ		 268 return -EINVAL;
269 }
270
271 return mapping.map_to;
272}
273
274static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
275{
276 struct smu_11_0_cmn2aisc_mapping mapping;
277
278 if (index >= SMU_POWER_SOURCE_COUNT)
279 return -EINVAL;
280
281 mapping = arcturus_pwr_src_map[index];
282 if (!(mapping.valid_mapping)) {
d9811cfc 283 dev_warn(smc->adev->dev, "Unsupported SMU power source: %d\n", index);
a94235af
EQ		 284 return -EINVAL;
285 }
286
287 return mapping.map_to;
288}
289
a94235af
EQ		 290static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
291{
292 struct smu_11_0_cmn2aisc_mapping mapping;
293
294 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
295 return -EINVAL;
296
297 mapping = arcturus_workload_map[profile];
ebcef76b 298 if (!(mapping.valid_mapping))
a94235af 299 return -EINVAL;
a94235af
EQ		 300
301 return mapping.map_to;
302}
303
304static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
305{
832a7062
EQ		 306 struct smu_table_context *smu_table = &smu->smu_table;
307
a94235af
EQ		 308 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
309 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
310
311 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
312 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
313
314 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
315 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
316
d1a84427
AG		 317 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
318 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
319
18d7ab98
EQ		 320 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
321 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
322 AMDGPU_GEM_DOMAIN_VRAM);
323
832a7062
EQ		 324 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
325 if (!smu_table->metrics_table)
326 return -ENOMEM;
327 smu_table->metrics_time = 0;
328
a94235af
EQ		 329 return 0;
330}
331
332static int arcturus_allocate_dpm_context(struct smu_context *smu)
333{
334 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
335
3a86d7f6 336 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
a94235af
EQ		 337 GFP_KERNEL);
338 if (!smu_dpm->dpm_context)
339 return -ENOMEM;
3a86d7f6 340 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
a94235af
EQ		 341
342 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
343 GFP_KERNEL);
344 if (!smu_dpm->dpm_current_power_state)
345 return -ENOMEM;
346
347 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
348 GFP_KERNEL);
349 if (!smu_dpm->dpm_request_power_state)
350 return -ENOMEM;
351
352 return 0;
353}
354
a94235af
EQ		 355static int
356arcturus_get_allowed_feature_mask(struct smu_context *smu,
357 uint32_t *feature_mask, uint32_t num)
358{
359 if (num > 2)
360 return -EINVAL;
361
59de58f8
EQ		 362 /* pptable will handle the features to enable */
363 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
a94235af
EQ		 364
365 return 0;
366}
367
a94235af
EQ		 368static int arcturus_set_default_dpm_table(struct smu_context *smu)
369{
3a86d7f6
EQ		 370 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
371 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
372 struct smu_11_0_dpm_table *dpm_table = NULL;
373 int ret = 0;
a94235af 374
3a86d7f6
EQ		 375 /* socclk dpm table setup */
376 dpm_table = &dpm_context->dpm_tables.soc_table;
8a856ced 377 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
3a86d7f6
EQ		 378 ret = smu_v11_0_set_single_dpm_table(smu,
379 SMU_SOCCLK,
380 dpm_table);
381 if (ret)
a94235af 382 return ret;
3a86d7f6
EQ		 383 dpm_table->is_fine_grained =
384 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
a94235af 385 } else {
3a86d7f6
EQ		 386 dpm_table->count = 1;
387 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
388 dpm_table->dpm_levels[0].enabled = true;
389 dpm_table->min = dpm_table->dpm_levels[0].value;
390 dpm_table->max = dpm_table->dpm_levels[0].value;
a94235af 391 }
a94235af 392
3a86d7f6
EQ		 393 /* gfxclk dpm table setup */
394 dpm_table = &dpm_context->dpm_tables.gfx_table;
8a856ced 395 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
3a86d7f6
EQ		 396 ret = smu_v11_0_set_single_dpm_table(smu,
397 SMU_GFXCLK,
398 dpm_table);
399 if (ret)
a94235af 400 return ret;
3a86d7f6
EQ		 401 dpm_table->is_fine_grained =
402 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
a94235af 403 } else {
3a86d7f6
EQ		 404 dpm_table->count = 1;
405 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
406 dpm_table->dpm_levels[0].enabled = true;
407 dpm_table->min = dpm_table->dpm_levels[0].value;
408 dpm_table->max = dpm_table->dpm_levels[0].value;
a94235af 409 }
a94235af 410
3a86d7f6
EQ		 411 /* memclk dpm table setup */
412 dpm_table = &dpm_context->dpm_tables.uclk_table;
8a856ced 413 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
3a86d7f6
EQ		 414 ret = smu_v11_0_set_single_dpm_table(smu,
415 SMU_UCLK,
416 dpm_table);
417 if (ret)
a94235af 418 return ret;
3a86d7f6
EQ		 419 dpm_table->is_fine_grained =
420 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
a94235af 421 } else {
3a86d7f6
EQ		 422 dpm_table->count = 1;
423 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
424 dpm_table->dpm_levels[0].enabled = true;
425 dpm_table->min = dpm_table->dpm_levels[0].value;
426 dpm_table->max = dpm_table->dpm_levels[0].value;
a94235af 427 }
a94235af 428
3a86d7f6
EQ		 429 /* fclk dpm table setup */
430 dpm_table = &dpm_context->dpm_tables.fclk_table;
8a856ced 431 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
3a86d7f6
EQ		 432 ret = smu_v11_0_set_single_dpm_table(smu,
433 SMU_FCLK,
434 dpm_table);
435 if (ret)
a94235af 436 return ret;
3a86d7f6
EQ		 437 dpm_table->is_fine_grained =
438 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
a94235af 439 } else {
3a86d7f6
EQ		 440 dpm_table->count = 1;
441 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
442 dpm_table->dpm_levels[0].enabled = true;
443 dpm_table->min = dpm_table->dpm_levels[0].value;
444 dpm_table->max = dpm_table->dpm_levels[0].value;
a94235af 445 }
a94235af
EQ		 446
447 return 0;
448}
449
450static int arcturus_check_powerplay_table(struct smu_context *smu)
451{
4a13b4ce
EQ		 452 struct smu_table_context *table_context = &smu->smu_table;
453 struct smu_11_0_powerplay_table *powerplay_table =
454 table_context->power_play_table;
455 struct smu_baco_context *smu_baco = &smu->smu_baco;
456
457 mutex_lock(&smu_baco->mutex);
458 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
459 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
460 smu_baco->platform_support = true;
461 mutex_unlock(&smu_baco->mutex);
462
463 table_context->thermal_controller_type =
464 powerplay_table->thermal_controller_type;
465
a94235af
EQ		 466 return 0;
467}
468
469static int arcturus_store_powerplay_table(struct smu_context *smu)
470{
a94235af 471 struct smu_table_context *table_context = &smu->smu_table;
4a13b4ce
EQ		 472 struct smu_11_0_powerplay_table *powerplay_table =
473 table_context->power_play_table;
a94235af
EQ		 474
475 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
476 sizeof(PPTable_t));
477
4a13b4ce 478 return 0;
a94235af
EQ		 479}
480
481static int arcturus_append_powerplay_table(struct smu_context *smu)
482{
483 struct smu_table_context *table_context = &smu->smu_table;
484 PPTable_t *smc_pptable = table_context->driver_pptable;
485 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
486 int index, ret;
487
488 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
489 smc_dpm_info);
490
491 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
492 (uint8_t **)&smc_dpm_table);
493 if (ret)
494 return ret;
495
d9811cfc 496 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
a94235af
EQ		 497 smc_dpm_table->table_header.format_revision,
498 smc_dpm_table->table_header.content_revision);
499
500 if ((smc_dpm_table->table_header.format_revision == 4) &&
501 (smc_dpm_table->table_header.content_revision == 6))
502 memcpy(&smc_pptable->MaxVoltageStepGfx,
503 &smc_dpm_table->maxvoltagestepgfx,
504 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
505
506 return 0;
507}
508
4a13b4ce
EQ		 509static int arcturus_setup_pptable(struct smu_context *smu)
510{
511 int ret = 0;
512
513 ret = smu_v11_0_setup_pptable(smu);
514 if (ret)
515 return ret;
516
517 ret = arcturus_store_powerplay_table(smu);
518 if (ret)
519 return ret;
520
521 ret = arcturus_append_powerplay_table(smu);
522 if (ret)
523 return ret;
524
525 ret = arcturus_check_powerplay_table(smu);
526 if (ret)
527 return ret;
528
529 return ret;
530}
531
04c572a0 532static int arcturus_run_btc(struct smu_context *smu)
a94235af 533{
04c572a0
EQ		 534 int ret = 0;
535
1c58267c 536 ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
04c572a0 537 if (ret) {
d9811cfc 538 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
04c572a0
EQ		 539 return ret;
540 }
541
1c58267c 542 return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
a94235af
EQ		 543}
544
545static int arcturus_populate_umd_state_clk(struct smu_context *smu)
546{
62cc9dd1
EQ		 547 struct smu_11_0_dpm_context *dpm_context =
548 smu->smu_dpm.dpm_context;
549 struct smu_11_0_dpm_table *gfx_table =
550 &dpm_context->dpm_tables.gfx_table;
551 struct smu_11_0_dpm_table *mem_table =
552 &dpm_context->dpm_tables.uclk_table;
553 struct smu_11_0_dpm_table *soc_table =
554 &dpm_context->dpm_tables.soc_table;
555 struct smu_umd_pstate_table *pstate_table =
556 &smu->pstate_table;
557
558 pstate_table->gfxclk_pstate.min = gfx_table->min;
559 pstate_table->gfxclk_pstate.peak = gfx_table->max;
560
561 pstate_table->uclk_pstate.min = mem_table->min;
562 pstate_table->uclk_pstate.peak = mem_table->max;
563
564 pstate_table->socclk_pstate.min = soc_table->min;
565 pstate_table->socclk_pstate.peak = soc_table->max;
a94235af
EQ		 566
567 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
62cc9dd1
EQ		 568 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
569 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
570 pstate_table->gfxclk_pstate.standard =
571 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
572 pstate_table->uclk_pstate.standard =
573 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
574 pstate_table->socclk_pstate.standard =
575 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
576 } else {
577 pstate_table->gfxclk_pstate.standard =
578 pstate_table->gfxclk_pstate.min;
579 pstate_table->uclk_pstate.standard =
580 pstate_table->uclk_pstate.min;
581 pstate_table->socclk_pstate.standard =
582 pstate_table->socclk_pstate.min;
a94235af
EQ		 583 }
584
a94235af
EQ		 585 return 0;
586}
587
588static int arcturus_get_clk_table(struct smu_context *smu,
589 struct pp_clock_levels_with_latency *clocks,
3a86d7f6 590 struct smu_11_0_dpm_table *dpm_table)
a94235af
EQ		 591{
592 int i, count;
593
594 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
595 clocks->num_levels = count;
596
597 for (i = 0; i < count; i++) {
598 clocks->data[i].clocks_in_khz =
599 dpm_table->dpm_levels[i].value * 1000;
600 clocks->data[i].latency_in_us = 0;
601 }
602
603 return 0;
604}
605
1f23cadb
EQ		 606static int arcturus_freqs_in_same_level(int32_t frequency1,
607 int32_t frequency2)
608{
609 return (abs(frequency1 - frequency2) <= EPSILON);
610}
611
5e6dc8fe
EQ		 612static int arcturus_get_smu_metrics_data(struct smu_context *smu,
613 MetricsMember_t member,
614 uint32_t *value)
615{
616 struct smu_table_context *smu_table= &smu->smu_table;
617 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
618 int ret = 0;
619
620 mutex_lock(&smu->metrics_lock);
621
622 if (!smu_table->metrics_time ||
623 time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
624 ret = smu_update_table(smu,
625 SMU_TABLE_SMU_METRICS,
626 0,
627 smu_table->metrics_table,
628 false);
629 if (ret) {
630 dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
631 mutex_unlock(&smu->metrics_lock);
632 return ret;
633 }
634 smu_table->metrics_time = jiffies;
635 }
636
637 switch (member) {
638 case METRICS_CURR_GFXCLK:
639 *value = metrics->CurrClock[PPCLK_GFXCLK];
640 break;
641 case METRICS_CURR_SOCCLK:
642 *value = metrics->CurrClock[PPCLK_SOCCLK];
643 break;
644 case METRICS_CURR_UCLK:
645 *value = metrics->CurrClock[PPCLK_UCLK];
646 break;
647 case METRICS_CURR_VCLK:
648 *value = metrics->CurrClock[PPCLK_VCLK];
649 break;
650 case METRICS_CURR_DCLK:
651 *value = metrics->CurrClock[PPCLK_DCLK];
652 break;
653 case METRICS_CURR_FCLK:
654 *value = metrics->CurrClock[PPCLK_FCLK];
655 break;
656 case METRICS_AVERAGE_GFXCLK:
657 *value = metrics->AverageGfxclkFrequency;
658 break;
659 case METRICS_AVERAGE_SOCCLK:
660 *value = metrics->AverageSocclkFrequency;
661 break;
662 case METRICS_AVERAGE_UCLK:
663 *value = metrics->AverageUclkFrequency;
664 break;
665 case METRICS_AVERAGE_VCLK:
666 *value = metrics->AverageVclkFrequency;
667 break;
668 case METRICS_AVERAGE_DCLK:
669 *value = metrics->AverageDclkFrequency;
670 break;
671 case METRICS_AVERAGE_GFXACTIVITY:
672 *value = metrics->AverageGfxActivity;
673 break;
674 case METRICS_AVERAGE_MEMACTIVITY:
675 *value = metrics->AverageUclkActivity;
676 break;
677 case METRICS_AVERAGE_VCNACTIVITY:
678 *value = metrics->VcnActivityPercentage;
679 break;
680 case METRICS_AVERAGE_SOCKETPOWER:
681 *value = metrics->AverageSocketPower << 8;
682 break;
683 case METRICS_TEMPERATURE_EDGE:
684 *value = metrics->TemperatureEdge *
685 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
686 break;
687 case METRICS_TEMPERATURE_HOTSPOT:
688 *value = metrics->TemperatureHotspot *
689 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
690 break;
691 case METRICS_TEMPERATURE_MEM:
692 *value = metrics->TemperatureHBM *
693 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
694 break;
695 case METRICS_TEMPERATURE_VRGFX:
696 *value = metrics->TemperatureVrGfx *
697 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
698 break;
699 case METRICS_TEMPERATURE_VRSOC:
700 *value = metrics->TemperatureVrSoc *
701 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
702 break;
703 case METRICS_TEMPERATURE_VRMEM:
704 *value = metrics->TemperatureVrMem *
705 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
706 break;
707 case METRICS_THROTTLER_STATUS:
708 *value = metrics->ThrottlerStatus;
709 break;
710 case METRICS_CURR_FANSPEED:
711 *value = metrics->CurrFanSpeed;
712 break;
713 default:
714 *value = UINT_MAX;
715 break;
716 }
717
718 mutex_unlock(&smu->metrics_lock);
719
720 return ret;
721}
722
723static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
724 enum smu_clk_type clk_type,
725 uint32_t *value)
726{
727 MetricsMember_t member_type;
728 int clk_id = 0;
729
730 if (!value)
731 return -EINVAL;
732
733 clk_id = smu_clk_get_index(smu, clk_type);
734 if (clk_id < 0)
735 return -EINVAL;
736
737 switch (clk_id) {
738 case PPCLK_GFXCLK:
739 /*
740 * CurrClock[clk_id] can provide accurate
741 * output only when the dpm feature is enabled.
742 * We can use Average_* for dpm disabled case.
743 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
744 */
745 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
746 member_type = METRICS_CURR_GFXCLK;
747 else
748 member_type = METRICS_AVERAGE_GFXCLK;
749 break;
750 case PPCLK_UCLK:
751 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
752 member_type = METRICS_CURR_UCLK;
753 else
754 member_type = METRICS_AVERAGE_UCLK;
755 break;
756 case PPCLK_SOCCLK:
757 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
758 member_type = METRICS_CURR_SOCCLK;
759 else
760 member_type = METRICS_AVERAGE_SOCCLK;
761 break;
762 case PPCLK_VCLK:
763 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
764 member_type = METRICS_CURR_VCLK;
765 else
766 member_type = METRICS_AVERAGE_VCLK;
767 break;
768 case PPCLK_DCLK:
769 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
770 member_type = METRICS_CURR_DCLK;
771 else
772 member_type = METRICS_AVERAGE_DCLK;
773 break;
774 case PPCLK_FCLK:
775 member_type = METRICS_CURR_FCLK;
776 break;
777 default:
778 return -EINVAL;
779 }
780
781 return arcturus_get_smu_metrics_data(smu,
782 member_type,
783 value);
784}
785
a94235af
EQ		 786static int arcturus_print_clk_levels(struct smu_context *smu,
787 enum smu_clk_type type, char *buf)
788{
789 int i, now, size = 0;
790 int ret = 0;
791 struct pp_clock_levels_with_latency clocks;
3a86d7f6 792 struct smu_11_0_dpm_table *single_dpm_table;
a94235af 793 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
3a86d7f6 794 struct smu_11_0_dpm_context *dpm_context = NULL;
a94235af 795
30c296e1
JC		 796 if (amdgpu_ras_intr_triggered())
797 return snprintf(buf, PAGE_SIZE, "unavailable\n");
798
3a86d7f6 799 dpm_context = smu_dpm->dpm_context;
a94235af
EQ		 800
801 switch (type) {
802 case SMU_SCLK:
5e6dc8fe 803 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
a94235af 804 if (ret) {
d9811cfc 805 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
a94235af
EQ		 806 return ret;
807 }
808
3a86d7f6 809 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
a94235af
EQ		 810 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
811 if (ret) {
d9811cfc 812 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
a94235af
EQ		 813 return ret;
814 }
815
59e038d0
EQ		 816 /*
817 * For DPM disabled case, there will be only one clock level.
818 * And it's safe to assume that is always the current clock.
819 */
a94235af
EQ		 820 for (i = 0; i < clocks.num_levels; i++)
821 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
822 clocks.data[i].clocks_in_khz / 1000,
59e038d0
EQ		 823 (clocks.num_levels == 1) ? "*" :
824 (arcturus_freqs_in_same_level(
1f23cadb 825 clocks.data[i].clocks_in_khz / 1000,
5e6dc8fe 826 now) ? "*" : ""));
a94235af
EQ		 827 break;
828
829 case SMU_MCLK:
5e6dc8fe 830 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
a94235af 831 if (ret) {
d9811cfc 832 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
a94235af
EQ		 833 return ret;
834 }
835
3a86d7f6 836 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
a94235af
EQ		 837 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
838 if (ret) {
d9811cfc 839 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
a94235af
EQ		 840 return ret;
841 }
842
843 for (i = 0; i < clocks.num_levels; i++)
844 size += sprintf(buf + size, "%d: %uMhz %s\n",
845 i, clocks.data[i].clocks_in_khz / 1000,
59e038d0
EQ		 846 (clocks.num_levels == 1) ? "*" :
847 (arcturus_freqs_in_same_level(
1f23cadb 848 clocks.data[i].clocks_in_khz / 1000,
5e6dc8fe 849 now) ? "*" : ""));
a94235af
EQ		 850 break;
851
852 case SMU_SOCCLK:
5e6dc8fe 853 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
a94235af 854 if (ret) {
d9811cfc 855 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
a94235af
EQ		 856 return ret;
857 }
858
3a86d7f6 859 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
a94235af
EQ		 860 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
861 if (ret) {
d9811cfc 862 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
a94235af
EQ		 863 return ret;
864 }
865
866 for (i = 0; i < clocks.num_levels; i++)
867 size += sprintf(buf + size, "%d: %uMhz %s\n",
868 i, clocks.data[i].clocks_in_khz / 1000,
59e038d0
EQ		 869 (clocks.num_levels == 1) ? "*" :
870 (arcturus_freqs_in_same_level(
1f23cadb 871 clocks.data[i].clocks_in_khz / 1000,
5e6dc8fe 872 now) ? "*" : ""));
a94235af
EQ		 873 break;
874
875 case SMU_FCLK:
5e6dc8fe 876 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
a94235af 877 if (ret) {
d9811cfc 878 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
a94235af
EQ		 879 return ret;
880 }
881
3a86d7f6 882 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1f23cadb
EQ		 883 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
884 if (ret) {
d9811cfc 885 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
1f23cadb
EQ		 886 return ret;
887 }
888
a94235af
EQ		 889 for (i = 0; i < single_dpm_table->count; i++)
890 size += sprintf(buf + size, "%d: %uMhz %s\n",
891 i, single_dpm_table->dpm_levels[i].value,
59e038d0
EQ		 892 (clocks.num_levels == 1) ? "*" :
893 (arcturus_freqs_in_same_level(
1f23cadb 894 clocks.data[i].clocks_in_khz / 1000,
5e6dc8fe 895 now) ? "*" : ""));
a94235af
EQ		 896 break;
897
898 default:
899 break;
900 }
901
902 return size;
903}
904
3a86d7f6
EQ		 905static int arcturus_upload_dpm_level(struct smu_context *smu,
906 bool max,
907 uint32_t feature_mask,
908 uint32_t level)
a94235af 909{
3a86d7f6 910 struct smu_11_0_dpm_context *dpm_context =
60d435b7 911 smu->smu_dpm.dpm_context;
a94235af
EQ		 912 uint32_t freq;
913 int ret = 0;
914
60d435b7 915 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
a94235af 916 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
3a86d7f6 917 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
a94235af
EQ		 918 ret = smu_send_smc_msg_with_param(smu,
919 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1c58267c
MC		 920 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
921 NULL);
a94235af 922 if (ret) {
d9811cfc 923 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
a94235af
EQ		 924 max ? "max" : "min");
925 return ret;
926 }
927 }
928
60d435b7
EQ		 929 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
930 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
3a86d7f6 931 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
60d435b7
EQ		 932 ret = smu_send_smc_msg_with_param(smu,
933 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1c58267c
MC		 934 (PPCLK_UCLK << 16) | (freq & 0xffff),
935 NULL);
60d435b7 936 if (ret) {
d9811cfc 937 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
60d435b7
EQ		 938 max ? "max" : "min");
939 return ret;
940 }
941 }
942
943 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
944 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
3a86d7f6 945 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
60d435b7
EQ		 946 ret = smu_send_smc_msg_with_param(smu,
947 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1c58267c
MC		 948 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
949 NULL);
60d435b7 950 if (ret) {
d9811cfc 951 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
60d435b7
EQ		 952 max ? "max" : "min");
953 return ret;
954 }
955 }
956
a94235af
EQ		 957 return ret;
958}
959
960static int arcturus_force_clk_levels(struct smu_context *smu,
961 enum smu_clk_type type, uint32_t mask)
962{
3a86d7f6
EQ		 963 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
964 struct smu_11_0_dpm_table *single_dpm_table = NULL;
a94235af 965 uint32_t soft_min_level, soft_max_level;
1744fb23 966 uint32_t smu_version;
a94235af
EQ		 967 int ret = 0;
968
1744fb23
EQ		 969 ret = smu_get_smc_version(smu, NULL, &smu_version);
970 if (ret) {
d9811cfc 971 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1744fb23
EQ		 972 return ret;
973 }
974
975 if (smu_version >= 0x361200) {
d9811cfc 976 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1744fb23
EQ		 977 "54.18 and onwards SMU firmwares\n");
978 return -EOPNOTSUPP;
979 }
980
a94235af
EQ		 981 soft_min_level = mask ? (ffs(mask) - 1) : 0;
982 soft_max_level = mask ? (fls(mask) - 1) : 0;
983
a94235af
EQ		 984 switch (type) {
985 case SMU_SCLK:
3a86d7f6 986 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
a94235af 987 if (soft_max_level >= single_dpm_table->count) {
d9811cfc 988 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
a94235af
EQ		 989 soft_max_level, single_dpm_table->count - 1);
990 ret = -EINVAL;
991 break;
992 }
993
3a86d7f6
EQ		 994 ret = arcturus_upload_dpm_level(smu,
995 false,
996 FEATURE_DPM_GFXCLK_MASK,
997 soft_min_level);
a94235af 998 if (ret) {
d9811cfc 999 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
a94235af
EQ		 1000 break;
1001 }
1002
3a86d7f6
EQ		 1003 ret = arcturus_upload_dpm_level(smu,
1004 true,
1005 FEATURE_DPM_GFXCLK_MASK,
1006 soft_max_level);
a94235af 1007 if (ret)
d9811cfc 1008 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
a94235af
EQ		 1009
1010 break;
1011
1012 case SMU_MCLK:
a94235af 1013 case SMU_SOCCLK:
a94235af 1014 case SMU_FCLK:
0525f297
EQ		 1015 /*
1016 * Should not arrive here since Arcturus does not
1017 * support mclk/socclk/fclk softmin/softmax settings
1018 */
1019 ret = -EINVAL;
a94235af
EQ		 1020 break;
1021
1022 default:
1023 break;
1024 }
1025
a94235af
EQ		 1026 return ret;
1027}
1028
a94235af
EQ		 1029static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1030 struct smu_temperature_range *range)
1031{
e02e4d51
EQ		 1032 struct smu_table_context *table_context = &smu->smu_table;
1033 struct smu_11_0_powerplay_table *powerplay_table =
1034 table_context->power_play_table;
a94235af
EQ		 1035 PPTable_t *pptable = smu->smu_table.driver_pptable;
1036
1037 if (!range)
1038 return -EINVAL;
1039
0540eced
EQ		 1040 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1041
a94235af
EQ		 1042 range->max = pptable->TedgeLimit *
1043 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1044 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1045 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1046 range->hotspot_crit_max = pptable->ThotspotLimit *
1047 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1048 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1049 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1050 range->mem_crit_max = pptable->TmemLimit *
1051 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
cbf3f132 1052 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
a94235af 1053 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
e02e4d51 1054 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
a94235af 1055
a94235af
EQ		 1056 return 0;
1057}
1058
ba74c8bf
EQ		 1059static int arcturus_get_current_activity_percent(struct smu_context *smu,
1060 enum amd_pp_sensors sensor,
1061 uint32_t *value)
1062{
ba74c8bf
EQ		 1063 int ret = 0;
1064
1065 if (!value)
1066 return -EINVAL;
1067
ba74c8bf
EQ		 1068 switch (sensor) {
1069 case AMDGPU_PP_SENSOR_GPU_LOAD:
48219126
EQ		 1070 ret = arcturus_get_smu_metrics_data(smu,
1071 METRICS_AVERAGE_GFXACTIVITY,
1072 value);
ba74c8bf
EQ		 1073 break;
1074 case AMDGPU_PP_SENSOR_MEM_LOAD:
48219126
EQ		 1075 ret = arcturus_get_smu_metrics_data(smu,
1076 METRICS_AVERAGE_MEMACTIVITY,
1077 value);
ba74c8bf
EQ		 1078 break;
1079 default:
d9811cfc 1080 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
ba74c8bf
EQ		 1081 return -EINVAL;
1082 }
1083
48219126 1084 return ret;
ba74c8bf
EQ		 1085}
1086
1087static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
1088{
ba74c8bf
EQ		 1089 if (!value)
1090 return -EINVAL;
1091
48219126
EQ		 1092 return arcturus_get_smu_metrics_data(smu,
1093 METRICS_AVERAGE_SOCKETPOWER,
1094 value);
ba74c8bf
EQ		 1095}
1096
1097static int arcturus_thermal_get_temperature(struct smu_context *smu,
1098 enum amd_pp_sensors sensor,
1099 uint32_t *value)
1100{
ba74c8bf
EQ		 1101 int ret = 0;
1102
1103 if (!value)
1104 return -EINVAL;
1105
ba74c8bf
EQ		 1106 switch (sensor) {
1107 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
48219126
EQ		 1108 ret = arcturus_get_smu_metrics_data(smu,
1109 METRICS_TEMPERATURE_HOTSPOT,
1110 value);
ba74c8bf
EQ		 1111 break;
1112 case AMDGPU_PP_SENSOR_EDGE_TEMP:
48219126
EQ		 1113 ret = arcturus_get_smu_metrics_data(smu,
1114 METRICS_TEMPERATURE_EDGE,
1115 value);
ba74c8bf
EQ		 1116 break;
1117 case AMDGPU_PP_SENSOR_MEM_TEMP:
48219126
EQ		 1118 ret = arcturus_get_smu_metrics_data(smu,
1119 METRICS_TEMPERATURE_MEM,
1120 value);
ba74c8bf
EQ		 1121 break;
1122 default:
d9811cfc 1123 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
ba74c8bf
EQ		 1124 return -EINVAL;
1125 }
1126
48219126 1127 return ret;
ba74c8bf
EQ		 1128}
1129
1130static int arcturus_read_sensor(struct smu_context *smu,
1131 enum amd_pp_sensors sensor,
1132 void *data, uint32_t *size)
1133{
1134 struct smu_table_context *table_context = &smu->smu_table;
1135 PPTable_t *pptable = table_context->driver_pptable;
1136 int ret = 0;
1137
30c296e1
JC		 1138 if (amdgpu_ras_intr_triggered())
1139 return 0;
1140
97442140
KW		 1141 if (!data || !size)
1142 return -EINVAL;
1143
95f71bfa 1144 mutex_lock(&smu->sensor_lock);
ba74c8bf
EQ		 1145 switch (sensor) {
1146 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1147 *(uint32_t *)data = pptable->FanMaximumRpm;
1148 *size = 4;
1149 break;
1150 case AMDGPU_PP_SENSOR_MEM_LOAD:
1151 case AMDGPU_PP_SENSOR_GPU_LOAD:
1152 ret = arcturus_get_current_activity_percent(smu,
1153 sensor,
1154 (uint32_t *)data);
1155 *size = 4;
1156 break;
1157 case AMDGPU_PP_SENSOR_GPU_POWER:
1158 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1159 *size = 4;
1160 break;
1161 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1162 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1163 case AMDGPU_PP_SENSOR_MEM_TEMP:
1164 ret = arcturus_thermal_get_temperature(smu, sensor,
1165 (uint32_t *)data);
1166 *size = 4;
1167 break;
e0f9e936
EQ		 1168 case AMDGPU_PP_SENSOR_GFX_MCLK:
1169 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1170 /* the output clock frequency in 10K unit */
1171 *(uint32_t *)data *= 100;
1172 *size = 4;
1173 break;
1174 case AMDGPU_PP_SENSOR_GFX_SCLK:
1175 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1176 *(uint32_t *)data *= 100;
1177 *size = 4;
1178 break;
b2febc99
EQ		 1179 case AMDGPU_PP_SENSOR_VDDGFX:
1180 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1181 *size = 4;
1182 break;
ba74c8bf 1183 default:
b2febc99
EQ		 1184 ret = -EOPNOTSUPP;
1185 break;
ba74c8bf 1186 }
95f71bfa 1187 mutex_unlock(&smu->sensor_lock);
ba74c8bf
EQ		 1188
1189 return ret;
1190}
1191
d427cf8f
EQ		 1192static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1193 uint32_t *speed)
1194{
d427cf8f
EQ		 1195 if (!speed)
1196 return -EINVAL;
1197
48219126
EQ		 1198 return arcturus_get_smu_metrics_data(smu,
1199 METRICS_CURR_FANSPEED,
1200 speed);
d427cf8f
EQ		 1201}
1202
1203static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1204 uint32_t *speed)
1205{
1206 PPTable_t *pptable = smu->smu_table.driver_pptable;
1207 uint32_t percent, current_rpm;
1208 int ret = 0;
1209
1210 if (!speed)
1211 return -EINVAL;
1212
1213 ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1214 if (ret)
1215 return ret;
1216
1217 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1218 *speed = percent > 100 ? 100 : percent;
1219
1220 return ret;
1221}
1222
a141b4e3 1223static int arcturus_get_power_limit(struct smu_context *smu)
b4af964e 1224{
1e239fdd
EQ		 1225 struct smu_11_0_powerplay_table *powerplay_table =
1226 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
b4af964e 1227 PPTable_t *pptable = smu->smu_table.driver_pptable;
1e239fdd
EQ		 1228 uint32_t power_limit, od_percent;
1229
1230 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1231 /* the last hope to figure out the ppt limit */
1232 if (!pptable) {
1233 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1234 return -EINVAL;
b4af964e 1235 }
1e239fdd
EQ		 1236 power_limit =
1237 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1238 }
1239 smu->current_power_limit = power_limit;
b4af964e 1240
1e239fdd
EQ		 1241 if (smu->od_enabled) {
1242 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1243
1244 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1245
1246 power_limit *= (100 + od_percent);
1247 power_limit /= 100;
b4af964e 1248 }
1e239fdd 1249 smu->max_power_limit = power_limit;
b4af964e 1250
b4af964e
EQ		 1251 return 0;
1252}
1253
7aa3f675
EQ		 1254static int arcturus_get_power_profile_mode(struct smu_context *smu,
1255 char *buf)
1256{
18d7ab98 1257 DpmActivityMonitorCoeffInt_t activity_monitor;
7aa3f675
EQ		 1258 static const char *profile_name[] = {
1259 "BOOTUP_DEFAULT",
1260 "3D_FULL_SCREEN",
1261 "POWER_SAVING",
1262 "VIDEO",
1263 "VR",
1264 "COMPUTE",
1265 "CUSTOM"};
80c5a807 1266 static const char *title[] = {
18d7ab98
EQ		 1267 "PROFILE_INDEX(NAME)",
1268 "CLOCK_TYPE(NAME)",
1269 "FPS",
1270 "UseRlcBusy",
1271 "MinActiveFreqType",
1272 "MinActiveFreq",
1273 "BoosterFreqType",
1274 "BoosterFreq",
1275 "PD_Data_limit_c",
1276 "PD_Data_error_coeff",
1277 "PD_Data_error_rate_coeff"};
7aa3f675
EQ		 1278 uint32_t i, size = 0;
1279 int16_t workload_type = 0;
18d7ab98
EQ		 1280 int result = 0;
1281 uint32_t smu_version;
7aa3f675 1282
18d7ab98 1283 if (!buf)
7aa3f675
EQ		 1284 return -EINVAL;
1285
18d7ab98
EQ		 1286 result = smu_get_smc_version(smu, NULL, &smu_version);
1287 if (result)
1288 return result;
1289
41fb666d 1290 if (smu_version >= 0x360d00)
18d7ab98
EQ		 1291 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1292 title[0], title[1], title[2], title[3], title[4], title[5],
1293 title[6], title[7], title[8], title[9], title[10]);
1294 else
1295 size += sprintf(buf + size, "%16s\n",
80c5a807
AD		 1296 title[0]);
1297
7aa3f675
EQ		 1298 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1299 /*
1300 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1301 * Not all profile modes are supported on arcturus.
1302 */
1303 workload_type = smu_workload_get_type(smu, i);
1304 if (workload_type < 0)
1305 continue;
1306
41fb666d 1307 if (smu_version >= 0x360d00) {
18d7ab98
EQ		 1308 result = smu_update_table(smu,
1309 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1310 workload_type,
1311 (void *)(&activity_monitor),
1312 false);
1313 if (result) {
d9811cfc 1314 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
18d7ab98
EQ		 1315 return result;
1316 }
1317 }
1318
7aa3f675
EQ		 1319 size += sprintf(buf + size, "%2d %14s%s\n",
1320 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
18d7ab98 1321
41fb666d 1322 if (smu_version >= 0x360d00) {
18d7ab98
EQ		 1323 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1324 " ",
1325 0,
1326 "GFXCLK",
1327 activity_monitor.Gfx_FPS,
1328 activity_monitor.Gfx_UseRlcBusy,
1329 activity_monitor.Gfx_MinActiveFreqType,
1330 activity_monitor.Gfx_MinActiveFreq,
1331 activity_monitor.Gfx_BoosterFreqType,
1332 activity_monitor.Gfx_BoosterFreq,
1333 activity_monitor.Gfx_PD_Data_limit_c,
1334 activity_monitor.Gfx_PD_Data_error_coeff,
1335 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1336
1337 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1338 " ",
1339 1,
1340 "UCLK",
1341 activity_monitor.Mem_FPS,
1342 activity_monitor.Mem_UseRlcBusy,
1343 activity_monitor.Mem_MinActiveFreqType,
1344 activity_monitor.Mem_MinActiveFreq,
1345 activity_monitor.Mem_BoosterFreqType,
1346 activity_monitor.Mem_BoosterFreq,
1347 activity_monitor.Mem_PD_Data_limit_c,
1348 activity_monitor.Mem_PD_Data_error_coeff,
1349 activity_monitor.Mem_PD_Data_error_rate_coeff);
1350 }
7aa3f675
EQ		 1351 }
1352
1353 return size;
1354}
1355
1356static int arcturus_set_power_profile_mode(struct smu_context *smu,
1357 long *input,
1358 uint32_t size)
1359{
18d7ab98 1360 DpmActivityMonitorCoeffInt_t activity_monitor;
7aa3f675
EQ		 1361 int workload_type = 0;
1362 uint32_t profile_mode = input[size];
1363 int ret = 0;
18d7ab98 1364 uint32_t smu_version;
7aa3f675
EQ		 1365
1366 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1367 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
7aa3f675
EQ		 1368 return -EINVAL;
1369 }
1370
18d7ab98
EQ		 1371 ret = smu_get_smc_version(smu, NULL, &smu_version);
1372 if (ret)
1373 return ret;
1374
1375 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1376 (smu_version >=0x360d00)) {
1377 ret = smu_update_table(smu,
1378 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1379 WORKLOAD_PPLIB_CUSTOM_BIT,
1380 (void *)(&activity_monitor),
1381 false);
1382 if (ret) {
d9811cfc 1383 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
18d7ab98
EQ		 1384 return ret;
1385 }
1386
1387 switch (input[0]) {
1388 case 0: /* Gfxclk */
1389 activity_monitor.Gfx_FPS = input[1];
1390 activity_monitor.Gfx_UseRlcBusy = input[2];
1391 activity_monitor.Gfx_MinActiveFreqType = input[3];
1392 activity_monitor.Gfx_MinActiveFreq = input[4];
1393 activity_monitor.Gfx_BoosterFreqType = input[5];
1394 activity_monitor.Gfx_BoosterFreq = input[6];
1395 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1396 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1397 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1398 break;
1399 case 1: /* Uclk */
1400 activity_monitor.Mem_FPS = input[1];
1401 activity_monitor.Mem_UseRlcBusy = input[2];
1402 activity_monitor.Mem_MinActiveFreqType = input[3];
1403 activity_monitor.Mem_MinActiveFreq = input[4];
1404 activity_monitor.Mem_BoosterFreqType = input[5];
1405 activity_monitor.Mem_BoosterFreq = input[6];
1406 activity_monitor.Mem_PD_Data_limit_c = input[7];
1407 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1408 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1409 break;
1410 }
1411
1412 ret = smu_update_table(smu,
1413 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1414 WORKLOAD_PPLIB_CUSTOM_BIT,
1415 (void *)(&activity_monitor),
1416 true);
1417 if (ret) {
d9811cfc 1418 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
18d7ab98
EQ		 1419 return ret;
1420 }
1421 }
1422
7aa3f675
EQ		 1423 /*
1424 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1425 * Not all profile modes are supported on arcturus.
1426 */
1427 workload_type = smu_workload_get_type(smu, profile_mode);
1428 if (workload_type < 0) {
d9811cfc 1429 dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
7aa3f675
EQ		 1430 return -EINVAL;
1431 }
1432
1433 ret = smu_send_smc_msg_with_param(smu,
1434 SMU_MSG_SetWorkloadMask,
1c58267c
MC		 1435 1 << workload_type,
1436 NULL);
7aa3f675 1437 if (ret) {
d9811cfc 1438 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
7aa3f675
EQ		 1439 return ret;
1440 }
1441
1442 smu->power_profile_mode = profile_mode;
1443
1444 return 0;
1445}
1446
1744fb23
EQ		 1447static int arcturus_set_performance_level(struct smu_context *smu,
1448 enum amd_dpm_forced_level level)
1449{
1450 uint32_t smu_version;
1451 int ret;
1452
1453 ret = smu_get_smc_version(smu, NULL, &smu_version);
1454 if (ret) {
d9811cfc 1455 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1744fb23
EQ		 1456 return ret;
1457 }
1458
1459 switch (level) {
1460 case AMD_DPM_FORCED_LEVEL_HIGH:
1461 case AMD_DPM_FORCED_LEVEL_LOW:
1462 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1463 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1464 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1465 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1466 if (smu_version >= 0x361200) {
d9811cfc 1467 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1744fb23
EQ		 1468 "54.18 and onwards SMU firmwares\n");
1469 return -EOPNOTSUPP;
1470 }
1471 break;
1472 default:
1473 break;
1474 }
1475
1476 return smu_v11_0_set_performance_level(smu, level);
1477}
1478
a94235af
EQ		 1479static void arcturus_dump_pptable(struct smu_context *smu)
1480{
1481 struct smu_table_context *table_context = &smu->smu_table;
1482 PPTable_t *pptable = table_context->driver_pptable;
1483 int i;
1484
d9811cfc 1485 dev_info(smu->adev->dev, "Dumped PPTable:\n");
a94235af 1486
d9811cfc 1487 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
a94235af 1488
d9811cfc
EQ		 1489 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1490 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
a94235af
EQ		 1491
1492 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 1493 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1494 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
a94235af
EQ		 1495 }
1496
d9811cfc
EQ		 1497 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1498 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1499 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1500 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
a94235af 1501
d9811cfc
EQ		 1502 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1503 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1504 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1505 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1506 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1507 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1508 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
a94235af 1509
d9811cfc
EQ		 1510 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1511 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
a94235af 1512
d9811cfc 1513 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
a94235af 1514
d9811cfc
EQ		 1515 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1516 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
a94235af 1517
d9811cfc
EQ		 1518 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1519 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1520 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1521 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
a94235af 1522
d9811cfc
EQ		 1523 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1524 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1525 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1526 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
a94235af 1527
d9811cfc
EQ		 1528 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1529 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
a94235af 1530
d9811cfc 1531 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
a94235af
EQ		 1532 " .VoltageMode = 0x%02x\n"
1533 " .SnapToDiscrete = 0x%02x\n"
1534 " .NumDiscreteLevels = 0x%02x\n"
1535 " .padding = 0x%02x\n"
1536 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1537 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1538 " .SsFmin = 0x%04x\n"
1539 " .Padding_16 = 0x%04x\n",
1540 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1541 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1542 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1543 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1544 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1545 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1546 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1547 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1548 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1549 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1550 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1551
d9811cfc 1552 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
a94235af
EQ		 1553 " .VoltageMode = 0x%02x\n"
1554 " .SnapToDiscrete = 0x%02x\n"
1555 " .NumDiscreteLevels = 0x%02x\n"
1556 " .padding = 0x%02x\n"
1557 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1558 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1559 " .SsFmin = 0x%04x\n"
1560 " .Padding_16 = 0x%04x\n",
1561 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1562 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1563 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1564 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1565 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1566 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1567 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1568 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1569 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1570 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1571 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1572
d9811cfc 1573 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
a94235af
EQ		 1574 " .VoltageMode = 0x%02x\n"
1575 " .SnapToDiscrete = 0x%02x\n"
1576 " .NumDiscreteLevels = 0x%02x\n"
1577 " .padding = 0x%02x\n"
1578 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1579 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1580 " .SsFmin = 0x%04x\n"
1581 " .Padding_16 = 0x%04x\n",
1582 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1583 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1584 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1585 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1586 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1587 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1588 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1589 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1590 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1591 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1592 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1593
d9811cfc 1594 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
a94235af
EQ		 1595 " .VoltageMode = 0x%02x\n"
1596 " .SnapToDiscrete = 0x%02x\n"
1597 " .NumDiscreteLevels = 0x%02x\n"
1598 " .padding = 0x%02x\n"
1599 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1600 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1601 " .SsFmin = 0x%04x\n"
1602 " .Padding_16 = 0x%04x\n",
1603 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1604 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1605 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1606 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1607 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1608 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1609 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1610 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1611 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1612 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1613 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1614
d9811cfc 1615 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
a94235af
EQ		 1616 " .VoltageMode = 0x%02x\n"
1617 " .SnapToDiscrete = 0x%02x\n"
1618 " .NumDiscreteLevels = 0x%02x\n"
1619 " .padding = 0x%02x\n"
1620 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1621 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1622 " .SsFmin = 0x%04x\n"
1623 " .Padding_16 = 0x%04x\n",
1624 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1625 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1626 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1627 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1628 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1629 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1630 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1631 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1632 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1633 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1634 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1635
d9811cfc 1636 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
a94235af
EQ		 1637 " .VoltageMode = 0x%02x\n"
1638 " .SnapToDiscrete = 0x%02x\n"
1639 " .NumDiscreteLevels = 0x%02x\n"
1640 " .padding = 0x%02x\n"
1641 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1642 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1643 " .SsFmin = 0x%04x\n"
1644 " .Padding_16 = 0x%04x\n",
1645 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1646 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1647 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1648 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1649 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1650 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1651 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1652 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1653 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1654 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1655 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1656
1657
d9811cfc 1658 dev_info(smu->adev->dev, "FreqTableGfx\n");
a94235af 1659 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 1660 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
a94235af 1661
d9811cfc 1662 dev_info(smu->adev->dev, "FreqTableVclk\n");
a94235af 1663 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 1664 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
a94235af 1665
d9811cfc 1666 dev_info(smu->adev->dev, "FreqTableDclk\n");
a94235af 1667 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 1668 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
a94235af 1669
d9811cfc 1670 dev_info(smu->adev->dev, "FreqTableSocclk\n");
a94235af 1671 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 1672 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
a94235af 1673
d9811cfc 1674 dev_info(smu->adev->dev, "FreqTableUclk\n");
a94235af 1675 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 1676 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
a94235af 1677
d9811cfc 1678 dev_info(smu->adev->dev, "FreqTableFclk\n");
a94235af 1679 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc 1680 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
a94235af 1681
d9811cfc 1682 dev_info(smu->adev->dev, "Mp0clkFreq\n");
a94235af 1683 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 1684 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
a94235af 1685
d9811cfc 1686 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
a94235af 1687 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc
EQ		 1688 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1689
1690 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1691 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1692 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1693 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1694 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1695 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1696 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1697 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1698 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1699
1700 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1701 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1702 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1703 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1704
1705 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1706 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1707
1708 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1709 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1710 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1711 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1712 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1713 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1714
1715 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1716 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1717 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1718 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1719 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1720 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1721 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1722 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1723 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1724
1725 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1726 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1727 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1728 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1729
1730 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1731 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1732 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1733 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1734
1735 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1736 pptable->dBtcGbGfxPll.a,
1737 pptable->dBtcGbGfxPll.b,
1738 pptable->dBtcGbGfxPll.c);
d9811cfc 1739 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1740 pptable->dBtcGbGfxAfll.a,
1741 pptable->dBtcGbGfxAfll.b,
1742 pptable->dBtcGbGfxAfll.c);
d9811cfc 1743 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1744 pptable->dBtcGbSoc.a,
1745 pptable->dBtcGbSoc.b,
1746 pptable->dBtcGbSoc.c);
1747
d9811cfc 1748 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
a94235af
EQ		 1749 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1750 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 1751 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
a94235af
EQ		 1752 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1753 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1754
d9811cfc 1755 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1756 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1757 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1758 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 1759 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1760 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1761 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1762 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1763
d9811cfc
EQ		 1764 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1765 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
a94235af 1766
d9811cfc
EQ		 1767 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1768 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1769 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1770 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
a94235af 1771
d9811cfc
EQ		 1772 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1773 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1774 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1775 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
a94235af 1776
d9811cfc
EQ		 1777 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1778 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
a94235af 1779
d9811cfc 1780 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
a94235af 1781 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 1782 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1783 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1784 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1785
1786 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1787 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1788 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1789 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1790 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1791 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1792 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1793 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1794
1795 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1796 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1797 pptable->ReservedEquation0.a,
1798 pptable->ReservedEquation0.b,
1799 pptable->ReservedEquation0.c);
d9811cfc 1800 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1801 pptable->ReservedEquation1.a,
1802 pptable->ReservedEquation1.b,
1803 pptable->ReservedEquation1.c);
d9811cfc 1804 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1805 pptable->ReservedEquation2.a,
1806 pptable->ReservedEquation2.b,
1807 pptable->ReservedEquation2.c);
d9811cfc 1808 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
a94235af
EQ		 1809 pptable->ReservedEquation3.a,
1810 pptable->ReservedEquation3.b,
1811 pptable->ReservedEquation3.c);
1812
d9811cfc
EQ		 1813 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1814 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
a94235af 1815
d9811cfc
EQ		 1816 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1817 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1818 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
a94235af 1819
d9811cfc
EQ		 1820 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1821 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
a94235af 1822
d9811cfc
EQ		 1823 dev_info(smu->adev->dev, "Board Parameters:\n");
1824 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1825 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
a94235af 1826
d9811cfc
EQ		 1827 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1828 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1829 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1830 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
a94235af 1831
d9811cfc
EQ		 1832 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1833 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
a94235af 1834
d9811cfc
EQ		 1835 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1836 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1837 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
a94235af 1838
d9811cfc
EQ		 1839 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1840 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1841 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
a94235af 1842
d9811cfc
EQ		 1843 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1844 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1845 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
a94235af 1846
d9811cfc
EQ		 1847 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1848 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1849 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
a94235af 1850
d9811cfc
EQ		 1851 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1852 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1853 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1854 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
a94235af 1855
d9811cfc
EQ		 1856 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1857 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1858 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
a94235af 1859
d9811cfc
EQ		 1860 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1861 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1862 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
a94235af 1863
d9811cfc
EQ		 1864 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1865 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1866 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
a94235af 1867
d9811cfc
EQ		 1868 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1869 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1870 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
a94235af
EQ		 1871
1872 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 1873 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1874 dev_info(smu->adev->dev, " .Enabled = %d\n",
a94235af 1875 pptable->I2cControllers[i].Enabled);
d9811cfc 1876 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
a94235af 1877 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 1878 dev_info(smu->adev->dev, " .ControllerPort = %d\n",
a94235af 1879 pptable->I2cControllers[i].ControllerPort);
d9811cfc 1880 dev_info(smu->adev->dev, " .ControllerName = %d\n",
a94235af 1881 pptable->I2cControllers[i].ControllerName);
d9811cfc 1882 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n",
a94235af 1883 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 1884 dev_info(smu->adev->dev, " .I2cProtocol = %d\n",
a94235af 1885 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 1886 dev_info(smu->adev->dev, " .Speed = %d\n",
a94235af
EQ		 1887 pptable->I2cControllers[i].Speed);
1888 }
1889
d9811cfc
EQ		 1890 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1891 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
a94235af 1892
d9811cfc 1893 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
a94235af 1894
d9811cfc 1895 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
a94235af 1896 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 1897 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1898 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
a94235af 1899 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 1900 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1901 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
a94235af 1902 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 1903 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1904 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
a94235af 1905 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc 1906 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
a94235af
EQ		 1907
1908}
1909
3f513bae
CG		 1910static bool arcturus_is_dpm_running(struct smu_context *smu)
1911{
1912 int ret = 0;
1913 uint32_t feature_mask[2];
1914 unsigned long feature_enabled;
1915 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1916 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1917 ((uint64_t)feature_mask[1] << 32));
1918 return !!(feature_enabled & SMC_DPM_FEATURE);
1919}
1920
f6b4b4a1 1921static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
5bcc9240
EQ		 1922{
1923 struct smu_power_context *smu_power = &smu->smu_power;
1924 struct smu_power_gate *power_gate = &smu_power->power_gate;
1925 int ret = 0;
1926
1927 if (enable) {
1928 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1929 ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1930 if (ret) {
d9811cfc 1931 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
5bcc9240
EQ		 1932 return ret;
1933 }
1934 }
1935 power_gate->vcn_gated = false;
1936 } else {
1937 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1938 ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1939 if (ret) {
d9811cfc 1940 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
5bcc9240
EQ		 1941 return ret;
1942 }
1943 }
1944 power_gate->vcn_gated = true;
1945 }
1946
1947 return ret;
1948}
1949
d1a84427
AG		 1950static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t *req, bool write,
1951 uint8_t address, uint32_t numbytes,
1952 uint8_t *data)
1953{
1954 int i;
1955
1956 BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
1957
1958 req->I2CcontrollerPort = 0;
1959 req->I2CSpeed = 2;
1960 req->SlaveAddress = address;
1961 req->NumCmds = numbytes;
1962
1963 for (i = 0; i < numbytes; i++) {
1964 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
1965
1966 /* First 2 bytes are always write for lower 2b EEPROM address */
1967 if (i < 2)
1968 cmd->Cmd = 1;
1969 else
1970 cmd->Cmd = write;
1971
1972
1973 /* Add RESTART for read after address filled */
1974 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1975
1976 /* Add STOP in the end */
1977 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1978
1979 /* Fill with data regardless if read or write to simplify code */
1980 cmd->RegisterAddr = data[i];
1981 }
1982}
1983
1984static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
1985 uint8_t address,
1986 uint8_t *data,
1987 uint32_t numbytes)
1988{
1989 uint32_t i, ret = 0;
1990 SwI2cRequest_t req;
1991 struct amdgpu_device *adev = to_amdgpu_device(control);
1992 struct smu_table_context *smu_table = &adev->smu.smu_table;
ce0d0ec3 1993 struct smu_table *table = &smu_table->driver_table;
d1a84427
AG		 1994
1995 memset(&req, 0, sizeof(req));
1996 arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
1997
1998 mutex_lock(&adev->smu.mutex);
1999 /* Now read data starting with that address */
2000 ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2001 true);
2002 mutex_unlock(&adev->smu.mutex);
2003
2004 if (!ret) {
2005 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2006
2007 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
2008 for (i = 0; i < numbytes; i++)
2009 data[i] = res->SwI2cCmds[i].Data;
2010
d9811cfc 2011 dev_dbg(adev->dev, "arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
d1a84427
AG		 2012 (uint16_t)address, numbytes);
2013
2014 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2015 8, 1, data, numbytes, false);
2016 } else
d9811cfc 2017 dev_err(adev->dev, "arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
d1a84427
AG		 2018
2019 return ret;
2020}
2021
2022static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
2023 uint8_t address,
2024 uint8_t *data,
2025 uint32_t numbytes)
2026{
2027 uint32_t ret;
2028 SwI2cRequest_t req;
2029 struct amdgpu_device *adev = to_amdgpu_device(control);
2030
2031 memset(&req, 0, sizeof(req));
2032 arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
2033
2034 mutex_lock(&adev->smu.mutex);
2035 ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2036 mutex_unlock(&adev->smu.mutex);
2037
2038 if (!ret) {
d9811cfc 2039 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
d1a84427
AG		 2040 (uint16_t)address, numbytes);
2041
2042 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2043 8, 1, data, numbytes, false);
2044 /*
2045 * According to EEPROM spec there is a MAX of 10 ms required for
2046 * EEPROM to flush internal RX buffer after STOP was issued at the
2047 * end of write transaction. During this time the EEPROM will not be
2048 * responsive to any more commands - so wait a bit more.
2049 */
2050 msleep(10);
2051
2052 } else
d9811cfc 2053 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
d1a84427
AG		 2054
2055 return ret;
2056}
2057
2058static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
2059 struct i2c_msg *msgs, int num)
2060{
2061 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2062 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2063
2064 for (i = 0; i < num; i++) {
2065 /*
2066 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2067 * once and hence the data needs to be spliced into chunks and sent each
2068 * chunk separately
2069 */
2070 data_size = msgs[i].len - 2;
2071 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2072 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2073 data_ptr = msgs[i].buf + 2;
2074
2075 for (j = 0; j < data_size / data_chunk_size; j++) {
2076 /* Insert the EEPROM dest addess, bits 0-15 */
2077 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2078 data_chunk[1] = (next_eeprom_addr & 0xff);
2079
2080 if (msgs[i].flags & I2C_M_RD) {
2081 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2082 (uint8_t)msgs[i].addr,
2083 data_chunk, MAX_SW_I2C_COMMANDS);
2084
2085 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2086 } else {
2087
2088 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2089
2090 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2091 (uint8_t)msgs[i].addr,
2092 data_chunk, MAX_SW_I2C_COMMANDS);
2093 }
2094
2095 if (ret) {
2096 num = -EIO;
2097 goto fail;
2098 }
2099
2100 next_eeprom_addr += data_chunk_size;
2101 data_ptr += data_chunk_size;
2102 }
2103
2104 if (data_size % data_chunk_size) {
2105 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2106 data_chunk[1] = (next_eeprom_addr & 0xff);
2107
2108 if (msgs[i].flags & I2C_M_RD) {
2109 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2110 (uint8_t)msgs[i].addr,
2111 data_chunk, (data_size % data_chunk_size) + 2);
2112
2113 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2114 } else {
2115 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2116
2117 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2118 (uint8_t)msgs[i].addr,
2119 data_chunk, (data_size % data_chunk_size) + 2);
2120 }
2121
2122 if (ret) {
2123 num = -EIO;
2124 goto fail;
2125 }
2126 }
2127 }
2128
2129fail:
2130 return num;
2131}
2132
2133static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2134{
2135 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2136}
2137
2138
2139static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2140 .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2141 .functionality = arcturus_i2c_eeprom_i2c_func,
2142};
2143
2cdc9c20
WS		 2144static bool arcturus_i2c_adapter_is_added(struct i2c_adapter *control)
2145{
2146 struct amdgpu_device *adev = to_amdgpu_device(control);
2147
2148 return control->dev.parent == &adev->pdev->dev;
2149}
2150
1fc87b45 2151static int arcturus_i2c_eeprom_control_init(struct smu_context *smu, struct i2c_adapter *control)
d1a84427
AG		 2152{
2153 struct amdgpu_device *adev = to_amdgpu_device(control);
2154 int res;
2155
2cdc9c20
WS		 2156 /* smu_i2c_eeprom_init may be called twice in sriov */
2157 if (arcturus_i2c_adapter_is_added(control))
2158 return 0;
2159
d1a84427
AG		 2160 control->owner = THIS_MODULE;
2161 control->class = I2C_CLASS_SPD;
2162 control->dev.parent = &adev->pdev->dev;
2163 control->algo = &arcturus_i2c_eeprom_i2c_algo;
9015d60c 2164 snprintf(control->name, sizeof(control->name), "AMDGPU EEPROM");
d1a84427
AG		 2165
2166 res = i2c_add_adapter(control);
2167 if (res)
2168 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2169
2170 return res;
2171}
2172
1fc87b45 2173static void arcturus_i2c_eeprom_control_fini(struct smu_context *smu, struct i2c_adapter *control)
d1a84427 2174{
2cdc9c20
WS		 2175 if (!arcturus_i2c_adapter_is_added(control))
2176 return;
2177
d1a84427
AG		 2178 i2c_del_adapter(control);
2179}
2180
81a16241
KR		 2181static void arcturus_get_unique_id(struct smu_context *smu)
2182{
2183 struct amdgpu_device *adev = smu->adev;
c0732ba1 2184 uint32_t top32 = 0, bottom32 = 0, smu_version;
81a16241
KR		 2185 uint64_t id;
2186
2187 if (smu_get_smc_version(smu, NULL, &smu_version)) {
d9811cfc 2188 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
81a16241
KR		 2189 return;
2190 }
2191
2192 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2193 if (smu_version < 0x361700) {
d9811cfc 2194 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
81a16241
KR		 2195 return;
2196 }
2197
2198 /* Get the SN to turn into a Unique ID */
2199 smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2200 smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2201
2202 id = ((uint64_t)bottom32 << 32) | top32;
2203 adev->unique_id = id;
2204 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2205 * 16-digit HEX string for convenience and backwards-compatibility
2206 */
8df1a28f 2207 sprintf(adev->serial, "%llx", id);
81a16241
KR		 2208}
2209
49e78c82
EQ		 2210static bool arcturus_is_baco_supported(struct smu_context *smu)
2211{
2212 struct amdgpu_device *adev = smu->adev;
2213 uint32_t val;
2214
feb000fd 2215 if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
49e78c82
EQ		 2216 return false;
2217
2218 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2219 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2220}
2221
7af8bc50
HZ		 2222static int arcturus_set_df_cstate(struct smu_context *smu,
2223 enum pp_df_cstate state)
2224{
2225 uint32_t smu_version;
2226 int ret;
2227
2228 ret = smu_get_smc_version(smu, NULL, &smu_version);
2229 if (ret) {
d9811cfc 2230 dev_err(smu->adev->dev, "Failed to get smu version!\n");
7af8bc50
HZ		 2231 return ret;
2232 }
2233
2234 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2235 if (smu_version < 0x360F00) {
d9811cfc 2236 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
7af8bc50
HZ		 2237 return -EINVAL;
2238 }
2239
1c58267c 2240 return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
7af8bc50
HZ		 2241}
2242
ab9c2112
JC		 2243static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2244{
2245 uint32_t smu_version;
2246 int ret;
2247
2248 ret = smu_get_smc_version(smu, NULL, &smu_version);
2249 if (ret) {
d9811cfc 2250 dev_err(smu->adev->dev, "Failed to get smu version!\n");
ab9c2112
JC		 2251 return ret;
2252 }
2253
b7f0656a
JC		 2254 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2255 if (smu_version < 0x00361700) {
d9811cfc 2256 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
ab9c2112
JC		 2257 return -EINVAL;
2258 }
2259
2260 if (en)
2261 return smu_send_smc_msg_with_param(smu,
2262 SMU_MSG_GmiPwrDnControl,
2263 1,
2264 NULL);
2265
2266 return smu_send_smc_msg_with_param(smu,
2267 SMU_MSG_GmiPwrDnControl,
2268 0,
2269 NULL);
2270}
2271
8c0bba64
EQ		 2272static const struct throttling_logging_label {
2273 uint32_t feature_mask;
2274 const char *label;
2275} logging_label[] = {
2276 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2277 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2278 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2279 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2280 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2281 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2282 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2283};
2284static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2285{
2286 int throttler_idx, throtting_events = 0, buf_idx = 0;
2287 struct amdgpu_device *adev = smu->adev;
48219126 2288 uint32_t throttler_status;
8c0bba64
EQ		 2289 char log_buf[256];
2290
48219126
EQ		 2291 arcturus_get_smu_metrics_data(smu,
2292 METRICS_THROTTLER_STATUS,
2293 &throttler_status);
8c0bba64
EQ		 2294
2295 memset(log_buf, 0, sizeof(log_buf));
2296 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2297 throttler_idx++) {
48219126 2298 if (throttler_status & logging_label[throttler_idx].feature_mask) {
8c0bba64
EQ		 2299 throtting_events++;
2300 buf_idx += snprintf(log_buf + buf_idx,
2301 sizeof(log_buf) - buf_idx,
2302 "%s%s",
2303 throtting_events > 1 ? " and " : "",
2304 logging_label[throttler_idx].label);
2305 if (buf_idx >= sizeof(log_buf)) {
d9811cfc 2306 dev_err(adev->dev, "buffer overflow!\n");
8c0bba64
EQ		 2307 log_buf[sizeof(log_buf) - 1] = '\0';
2308 break;
2309 }
2310 }
2311 }
2312
2313 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2314 log_buf);
2315}
2316
947c127b
LG		 2317static int arcturus_set_thermal_range(struct smu_context *smu,
2318 struct smu_temperature_range range)
2319{
2320 struct amdgpu_device *adev = smu->adev;
2321 int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
2322 int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
2323 uint32_t val;
2324 struct smu_table_context *table_context = &smu->smu_table;
2325 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
2326
2327 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
2328 range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
2329 high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);
2330
2331 if (low > high)
2332 return -EINVAL;
2333
2334 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
2335 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
2336 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
2337 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
2338 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
2339 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
2340 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
2341 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
2342
2343 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
2344
2345 return 0;
2346}
2347
6fba5906 2348static const struct pptable_funcs arcturus_ppt_funcs = {
a94235af 2349 /* translate smu index into arcturus specific index */
6fba5906 2350 .get_smu_msg_index = arcturus_get_smu_msg_index,
a94235af
EQ		 2351 .get_smu_clk_index = arcturus_get_smu_clk_index,
2352 .get_smu_feature_index = arcturus_get_smu_feature_index,
2353 .get_smu_table_index = arcturus_get_smu_table_index,
2354 .get_smu_power_index= arcturus_get_pwr_src_index,
2355 .get_workload_type = arcturus_get_workload_type,
2356 /* internal structurs allocations */
2357 .tables_init = arcturus_tables_init,
2358 .alloc_dpm_context = arcturus_allocate_dpm_context,
a94235af
EQ		 2359 /* init dpm */
2360 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2361 /* btc */
04c572a0 2362 .run_btc = arcturus_run_btc,
a94235af
EQ		 2363 /* dpm/clk tables */
2364 .set_default_dpm_table = arcturus_set_default_dpm_table,
2365 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2366 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2367 .print_clk_levels = arcturus_print_clk_levels,
2368 .force_clk_levels = arcturus_force_clk_levels,
ba74c8bf 2369 .read_sensor = arcturus_read_sensor,
d427cf8f
EQ		 2370 .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2371 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
7aa3f675
EQ		 2372 .get_power_profile_mode = arcturus_get_power_profile_mode,
2373 .set_power_profile_mode = arcturus_set_power_profile_mode,
1744fb23 2374 .set_performance_level = arcturus_set_performance_level,
a94235af
EQ		 2375 /* debug (internal used) */
2376 .dump_pptable = arcturus_dump_pptable,
b4af964e 2377 .get_power_limit = arcturus_get_power_limit,
3f513bae 2378 .is_dpm_running = arcturus_is_dpm_running,
f6b4b4a1 2379 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
d1a84427
AG		 2380 .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2381 .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
81a16241 2382 .get_unique_id = arcturus_get_unique_id,
6c45e480
EQ		 2383 .init_microcode = smu_v11_0_init_microcode,
2384 .load_microcode = smu_v11_0_load_microcode,
6f47116e 2385 .fini_microcode = smu_v11_0_fini_microcode,
6c45e480
EQ		 2386 .init_smc_tables = smu_v11_0_init_smc_tables,
2387 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2388 .init_power = smu_v11_0_init_power,
2389 .fini_power = smu_v11_0_fini_power,
2390 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce
EQ		 2391 /* pptable related */
2392 .setup_pptable = arcturus_setup_pptable,
6c45e480 2393 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
6c45e480
EQ		 2394 .check_fw_version = smu_v11_0_check_fw_version,
2395 .write_pptable = smu_v11_0_write_pptable,
ce0d0ec3 2396 .set_driver_table_location = smu_v11_0_set_driver_table_location,
6c45e480
EQ		 2397 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2398 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2399 .system_features_control = smu_v11_0_system_features_control,
6c45e480 2400 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
31157341 2401 .init_display_count = NULL,
6c45e480
EQ		 2402 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2403 .get_enabled_mask = smu_v11_0_get_enabled_mask,
31157341 2404 .notify_display_change = NULL,
6c45e480 2405 .set_power_limit = smu_v11_0_set_power_limit,
6c45e480 2406 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
22f1e0e8
EQ		 2407 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2408 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 2409 .set_min_dcef_deep_sleep = NULL,
6c45e480
EQ		 2410 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2411 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2412 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2413 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2414 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2415 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2416 .gfx_off_control = smu_v11_0_gfx_off_control,
2417 .register_irq_handler = smu_v11_0_register_irq_handler,
2418 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2419 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
49e78c82 2420 .baco_is_support= arcturus_is_baco_supported,
6c45e480
EQ		 2421 .baco_get_state = smu_v11_0_baco_get_state,
2422 .baco_set_state = smu_v11_0_baco_set_state,
11520f27
AD		 2423 .baco_enter = smu_v11_0_baco_enter,
2424 .baco_exit = smu_v11_0_baco_exit,
6c45e480
EQ		 2425 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2426 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
7af8bc50 2427 .set_df_cstate = arcturus_set_df_cstate,
ab9c2112 2428 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
8c0bba64 2429 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
947c127b 2430 .set_thermal_range = arcturus_set_thermal_range,
6fba5906
CG		 2431};
2432
2433void arcturus_set_ppt_funcs(struct smu_context *smu)
2434{
2435 smu->ppt_funcs = &arcturus_ppt_funcs;
6fba5906 2436}
Linux 6.x block layer and io_uring tree(s)