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drm/amd/amdgpu implement tdr advanced mode
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu13 / smu_v13_0.c
CommitLineData
c05d1c40
KW		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/reboot.h>
27
28#define SMU_13_0_PARTIAL_PPTABLE
29#define SWSMU_CODE_LAYER_L3
30
31#include "amdgpu.h"
32#include "amdgpu_smu.h"
33#include "atomfirmware.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_atombios.h"
36#include "smu_v13_0.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "amdgpu_ras.h"
40#include "smu_cmn.h"
41
42#include "asic_reg/thm/thm_13_0_2_offset.h"
43#include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44#include "asic_reg/mp/mp_13_0_2_offset.h"
45#include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46#include "asic_reg/smuio/smuio_13_0_2_offset.h"
47#include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49/*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54#undef pr_err
55#undef pr_warn
56#undef pr_info
57#undef pr_debug
58
59MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60
61#define SMU13_VOLTAGE_SCALE 4
62
63#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
64
65#define LINK_WIDTH_MAX 6
66#define LINK_SPEED_MAX 3
67
68#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
69#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
70#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
71#define smnPCIE_LC_SPEED_CNTL 0x11140290
72#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
73#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
74
dd67d7a6
AD		 75static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
76static const int link_speed[] = {25, 50, 80, 160};
c05d1c40
KW		 77
78int smu_v13_0_init_microcode(struct smu_context *smu)
79{
80 struct amdgpu_device *adev = smu->adev;
81 const char *chip_name;
82 char fw_name[30];
83 int err = 0;
84 const struct smc_firmware_header_v1_0 *hdr;
85 const struct common_firmware_header *header;
86 struct amdgpu_firmware_info *ucode = NULL;
87
88 switch (adev->asic_type) {
89 case CHIP_ALDEBARAN:
90 chip_name = "aldebaran";
91 break;
92 default:
93 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
94 return -EINVAL;
95 }
96
97 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
98
99 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
100 if (err)
101 goto out;
102 err = amdgpu_ucode_validate(adev->pm.fw);
103 if (err)
104 goto out;
105
106 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
107 amdgpu_ucode_print_smc_hdr(&hdr->header);
108 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
109
110 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
111 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
112 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
113 ucode->fw = adev->pm.fw;
114 header = (const struct common_firmware_header *)ucode->fw->data;
115 adev->firmware.fw_size +=
116 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
117 }
118
119out:
120 if (err) {
121 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
122 fw_name);
123 release_firmware(adev->pm.fw);
124 adev->pm.fw = NULL;
125 }
126 return err;
127}
128
129void smu_v13_0_fini_microcode(struct smu_context *smu)
130{
131 struct amdgpu_device *adev = smu->adev;
132
133 release_firmware(adev->pm.fw);
134 adev->pm.fw = NULL;
135 adev->pm.fw_version = 0;
136}
137
138int smu_v13_0_load_microcode(struct smu_context *smu)
139{
140#if 0
141 struct amdgpu_device *adev = smu->adev;
142 const uint32_t *src;
143 const struct smc_firmware_header_v1_0 *hdr;
144 uint32_t addr_start = MP1_SRAM;
145 uint32_t i;
146 uint32_t smc_fw_size;
147 uint32_t mp1_fw_flags;
148
149 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
150 src = (const uint32_t *)(adev->pm.fw->data +
151 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
152 smc_fw_size = hdr->header.ucode_size_bytes;
153
154 for (i = 1; i < smc_fw_size/4 - 1; i++) {
155 WREG32_PCIE(addr_start, src[i]);
156 addr_start += 4;
157 }
158
159 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
160 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
161 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
162 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
163
164 for (i = 0; i < adev->usec_timeout; i++) {
165 mp1_fw_flags = RREG32_PCIE(MP1_Public |
166 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
167 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
168 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
169 break;
170 udelay(1);
171 }
172
173 if (i == adev->usec_timeout)
174 return -ETIME;
175#endif
176 return 0;
177}
178
179int smu_v13_0_check_fw_status(struct smu_context *smu)
180{
181 struct amdgpu_device *adev = smu->adev;
182 uint32_t mp1_fw_flags;
183
184 mp1_fw_flags = RREG32_PCIE(MP1_Public |
185 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
186
187 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
188 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
189 return 0;
190
191 return -EIO;
192}
193
194int smu_v13_0_check_fw_version(struct smu_context *smu)
195{
196 uint32_t if_version = 0xff, smu_version = 0xff;
197 uint16_t smu_major;
198 uint8_t smu_minor, smu_debug;
199 int ret = 0;
200
201 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
202 if (ret)
203 return ret;
204
205 smu_major = (smu_version >> 16) & 0xffff;
206 smu_minor = (smu_version >> 8) & 0xff;
207 smu_debug = (smu_version >> 0) & 0xff;
208
209 switch (smu->adev->asic_type) {
210 case CHIP_ALDEBARAN:
211 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
212 break;
213 default:
214 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
215 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
216 break;
217 }
218
f1adbe03
LL		 219 dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
220 smu_version, smu_major, smu_minor, smu_debug);
221
c05d1c40
KW		 222 /*
223 * 1. if_version mismatch is not critical as our fw is designed
224 * to be backward compatible.
225 * 2. New fw usually brings some optimizations. But that's visible
226 * only on the paired driver.
227 * Considering above, we just leave user a warning message instead
228 * of halt driver loading.
229 */
230 if (if_version != smu->smc_driver_if_version) {
231 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
232 "smu fw version = 0x%08x (%d.%d.%d)\n",
233 smu->smc_driver_if_version, if_version,
234 smu_version, smu_major, smu_minor, smu_debug);
235 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
236 }
237
238 return ret;
239}
240
241static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
242 uint32_t *size, uint32_t pptable_id)
243{
244 struct amdgpu_device *adev = smu->adev;
245 const struct smc_firmware_header_v2_1 *v2_1;
246 struct smc_soft_pptable_entry *entries;
247 uint32_t pptable_count = 0;
248 int i = 0;
249
250 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
251 entries = (struct smc_soft_pptable_entry *)
252 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
253 pptable_count = le32_to_cpu(v2_1->pptable_count);
254 for (i = 0; i < pptable_count; i++) {
255 if (le32_to_cpu(entries[i].id) == pptable_id) {
256 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
257 *size = le32_to_cpu(entries[i].ppt_size_bytes);
258 break;
259 }
260 }
261
262 if (i == pptable_count)
263 return -EINVAL;
264
265 return 0;
266}
267
268int smu_v13_0_setup_pptable(struct smu_context *smu)
269{
270 struct amdgpu_device *adev = smu->adev;
271 const struct smc_firmware_header_v1_0 *hdr;
272 int ret, index;
273 uint32_t size = 0;
274 uint16_t atom_table_size;
275 uint8_t frev, crev;
276 void *table;
277 uint16_t version_major, version_minor;
278
f1adbe03
LL		 279 /* temporarily hardcode to use vbios pptable */
280 smu->smu_table.boot_values.pp_table_id = 0;
281
282 if (amdgpu_smu_pptable_id >= 0) {
283 smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id;
284 dev_info(adev->dev, "override pptable id %d\n", amdgpu_smu_pptable_id);
285 }
c05d1c40
KW		 286
287 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
288 version_major = le16_to_cpu(hdr->header.header_version_major);
289 version_minor = le16_to_cpu(hdr->header.header_version_minor);
290 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
291 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
292 switch (version_minor) {
293 case 1:
294 ret = smu_v13_0_set_pptable_v2_1(smu, &table, &size,
295 smu->smu_table.boot_values.pp_table_id);
296 break;
297 default:
298 ret = -EINVAL;
299 break;
300 }
301 if (ret)
302 return ret;
303
304 } else {
305 dev_info(adev->dev, "use vbios provided pptable\n");
306 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
307 powerplayinfo);
308
309 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
310 (uint8_t **)&table);
311 if (ret)
312 return ret;
313 size = atom_table_size;
314 }
315
316 if (!smu->smu_table.power_play_table)
317 smu->smu_table.power_play_table = table;
318 if (!smu->smu_table.power_play_table_size)
319 smu->smu_table.power_play_table_size = size;
320
321 return 0;
322}
323
324int smu_v13_0_init_smc_tables(struct smu_context *smu)
325{
326 struct smu_table_context *smu_table = &smu->smu_table;
327 struct smu_table *tables = smu_table->tables;
328 int ret = 0;
329
330 smu_table->driver_pptable =
331 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
332 if (!smu_table->driver_pptable) {
333 ret = -ENOMEM;
334 goto err0_out;
335 }
336
337 smu_table->max_sustainable_clocks =
338 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
339 if (!smu_table->max_sustainable_clocks) {
340 ret = -ENOMEM;
341 goto err1_out;
342 }
343
344 /* Aldebaran does not support OVERDRIVE */
345 if (tables[SMU_TABLE_OVERDRIVE].size) {
346 smu_table->overdrive_table =
347 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
348 if (!smu_table->overdrive_table) {
349 ret = -ENOMEM;
350 goto err2_out;
351 }
352
353 smu_table->boot_overdrive_table =
354 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
355 if (!smu_table->boot_overdrive_table) {
356 ret = -ENOMEM;
357 goto err3_out;
358 }
359 }
360
361 return 0;
362
363err3_out:
364 kfree(smu_table->overdrive_table);
365err2_out:
366 kfree(smu_table->max_sustainable_clocks);
367err1_out:
368 kfree(smu_table->driver_pptable);
369err0_out:
370 return ret;
371}
372
373int smu_v13_0_fini_smc_tables(struct smu_context *smu)
374{
375 struct smu_table_context *smu_table = &smu->smu_table;
376 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
377
378 kfree(smu_table->gpu_metrics_table);
379 kfree(smu_table->boot_overdrive_table);
380 kfree(smu_table->overdrive_table);
381 kfree(smu_table->max_sustainable_clocks);
382 kfree(smu_table->driver_pptable);
383 smu_table->gpu_metrics_table = NULL;
384 smu_table->boot_overdrive_table = NULL;
385 smu_table->overdrive_table = NULL;
386 smu_table->max_sustainable_clocks = NULL;
387 smu_table->driver_pptable = NULL;
388 kfree(smu_table->hardcode_pptable);
389 smu_table->hardcode_pptable = NULL;
390
391 kfree(smu_table->metrics_table);
392 kfree(smu_table->watermarks_table);
393 smu_table->metrics_table = NULL;
394 smu_table->watermarks_table = NULL;
395 smu_table->metrics_time = 0;
396
397 kfree(smu_dpm->dpm_context);
398 kfree(smu_dpm->golden_dpm_context);
399 kfree(smu_dpm->dpm_current_power_state);
400 kfree(smu_dpm->dpm_request_power_state);
401 smu_dpm->dpm_context = NULL;
402 smu_dpm->golden_dpm_context = NULL;
403 smu_dpm->dpm_context_size = 0;
404 smu_dpm->dpm_current_power_state = NULL;
405 smu_dpm->dpm_request_power_state = NULL;
406
407 return 0;
408}
409
410int smu_v13_0_init_power(struct smu_context *smu)
411{
412 struct smu_power_context *smu_power = &smu->smu_power;
413
414 if (smu_power->power_context || smu_power->power_context_size != 0)
415 return -EINVAL;
416
417 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
418 GFP_KERNEL);
419 if (!smu_power->power_context)
420 return -ENOMEM;
421 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
422
423 return 0;
424}
425
426int smu_v13_0_fini_power(struct smu_context *smu)
427{
428 struct smu_power_context *smu_power = &smu->smu_power;
429
430 if (!smu_power->power_context || smu_power->power_context_size == 0)
431 return -EINVAL;
432
433 kfree(smu_power->power_context);
434 smu_power->power_context = NULL;
435 smu_power->power_context_size = 0;
436
437 return 0;
438}
439
440static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
441 uint8_t clk_id,
442 uint8_t syspll_id,
443 uint32_t *clk_freq)
444{
445 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
446 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
447 int ret, index;
448
449 input.clk_id = clk_id;
450 input.syspll_id = syspll_id;
451 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
452 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
453 getsmuclockinfo);
454
455 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
456 (uint32_t *)&input);
457 if (ret)
458 return -EINVAL;
459
460 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
461 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
462
463 return 0;
464}
465
466int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
467{
468 int ret, index;
469 uint16_t size;
470 uint8_t frev, crev;
471 struct atom_common_table_header *header;
3d01361c 472 struct atom_firmware_info_v3_4 *v_3_4;
c05d1c40
KW		 473 struct atom_firmware_info_v3_3 *v_3_3;
474 struct atom_firmware_info_v3_1 *v_3_1;
475
476 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
477 firmwareinfo);
478
479 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
480 (uint8_t **)&header);
481 if (ret)
482 return ret;
483
484 if (header->format_revision != 3) {
485 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
486 return -EINVAL;
487 }
488
489 switch (header->content_revision) {
490 case 0:
491 case 1:
492 case 2:
493 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
494 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
495 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
496 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
497 smu->smu_table.boot_values.socclk = 0;
498 smu->smu_table.boot_values.dcefclk = 0;
499 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
500 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
501 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
502 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
503 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
504 smu->smu_table.boot_values.pp_table_id = 0;
505 break;
506 case 3:
c05d1c40
KW		 507 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
508 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
509 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
510 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
511 smu->smu_table.boot_values.socclk = 0;
512 smu->smu_table.boot_values.dcefclk = 0;
513 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
514 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
515 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
516 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
517 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
518 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
e5a83213 519 break;
3d01361c
FX		 520 case 4:
521 default:
522 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
523 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
524 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
525 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
526 smu->smu_table.boot_values.socclk = 0;
527 smu->smu_table.boot_values.dcefclk = 0;
528 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
529 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
530 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
531 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
532 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
533 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
e5a83213 534 break;
c05d1c40
KW		 535 }
536
537 smu->smu_table.boot_values.format_revision = header->format_revision;
538 smu->smu_table.boot_values.content_revision = header->content_revision;
539
540 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
541 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
542 (uint8_t)0,
543 &smu->smu_table.boot_values.socclk);
544
545 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
546 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
547 (uint8_t)0,
548 &smu->smu_table.boot_values.dcefclk);
549
550 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
551 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
552 (uint8_t)0,
553 &smu->smu_table.boot_values.eclk);
554
555 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
556 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
557 (uint8_t)0,
558 &smu->smu_table.boot_values.vclk);
559
560 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
561 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
562 (uint8_t)0,
563 &smu->smu_table.boot_values.dclk);
564
565 if ((smu->smu_table.boot_values.format_revision == 3) &&
566 (smu->smu_table.boot_values.content_revision >= 2))
567 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
568 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
569 (uint8_t)SMU11_SYSPLL1_2_ID,
570 &smu->smu_table.boot_values.fclk);
571
572 return 0;
573}
574
f1adbe03 575
c05d1c40
KW		 576int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
577{
578 struct smu_table_context *smu_table = &smu->smu_table;
579 struct smu_table *memory_pool = &smu_table->memory_pool;
580 int ret = 0;
581 uint64_t address;
582 uint32_t address_low, address_high;
583
584 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
585 return ret;
586
c05d1c40
KW		 587 address = memory_pool->mc_address;
588 address_high = (uint32_t)upper_32_bits(address);
589 address_low = (uint32_t)lower_32_bits(address);
590
591 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
592 address_high, NULL);
593 if (ret)
594 return ret;
595 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
596 address_low, NULL);
597 if (ret)
598 return ret;
599 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
600 (uint32_t)memory_pool->size, NULL);
601 if (ret)
602 return ret;
603
604 return ret;
605}
606
607int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
608{
609 int ret;
610
611 ret = smu_cmn_send_smc_msg_with_param(smu,
612 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
613 if (ret)
614 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
615
616 return ret;
617}
618
619int smu_v13_0_set_driver_table_location(struct smu_context *smu)
620{
621 struct smu_table *driver_table = &smu->smu_table.driver_table;
622 int ret = 0;
623
624 if (driver_table->mc_address) {
625 ret = smu_cmn_send_smc_msg_with_param(smu,
626 SMU_MSG_SetDriverDramAddrHigh,
627 upper_32_bits(driver_table->mc_address),
628 NULL);
629 if (!ret)
630 ret = smu_cmn_send_smc_msg_with_param(smu,
631 SMU_MSG_SetDriverDramAddrLow,
632 lower_32_bits(driver_table->mc_address),
633 NULL);
634 }
635
636 return ret;
637}
638
639int smu_v13_0_set_tool_table_location(struct smu_context *smu)
640{
641 int ret = 0;
642 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
643
644 if (tool_table->mc_address) {
645 ret = smu_cmn_send_smc_msg_with_param(smu,
646 SMU_MSG_SetToolsDramAddrHigh,
647 upper_32_bits(tool_table->mc_address),
648 NULL);
649 if (!ret)
650 ret = smu_cmn_send_smc_msg_with_param(smu,
651 SMU_MSG_SetToolsDramAddrLow,
652 lower_32_bits(tool_table->mc_address),
653 NULL);
654 }
655
656 return ret;
657}
658
659int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
660{
661 int ret = 0;
662
663 if (!smu->pm_enabled)
664 return ret;
665
666 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
667
668 return ret;
669}
670
671
672int smu_v13_0_set_allowed_mask(struct smu_context *smu)
673{
674 struct smu_feature *feature = &smu->smu_feature;
675 int ret = 0;
676 uint32_t feature_mask[2];
677
678 mutex_lock(&feature->mutex);
679 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
680 goto failed;
681
682 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
683
684 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
685 feature_mask[1], NULL);
686 if (ret)
687 goto failed;
688
689 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
690 feature_mask[0], NULL);
691 if (ret)
692 goto failed;
693
694failed:
695 mutex_unlock(&feature->mutex);
696 return ret;
697}
698
699int smu_v13_0_system_features_control(struct smu_context *smu,
700 bool en)
701{
702 struct smu_feature *feature = &smu->smu_feature;
703 uint32_t feature_mask[2];
704 int ret = 0;
705
706 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
707 SMU_MSG_DisableAllSmuFeatures), NULL);
708 if (ret)
709 return ret;
710
711 bitmap_zero(feature->enabled, feature->feature_num);
712 bitmap_zero(feature->supported, feature->feature_num);
713
714 if (en) {
715 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
716 if (ret)
717 return ret;
718
719 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
720 feature->feature_num);
721 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
722 feature->feature_num);
723 }
724
725 return ret;
726}
727
728int smu_v13_0_notify_display_change(struct smu_context *smu)
729{
730 int ret = 0;
731
732 if (!smu->pm_enabled)
733 return ret;
734
735 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
736 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
737 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
738
739 return ret;
740}
741
742 static int
743smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
744 enum smu_clk_type clock_select)
745{
746 int ret = 0;
747 int clk_id;
748
749 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
750 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
751 return 0;
752
753 clk_id = smu_cmn_to_asic_specific_index(smu,
754 CMN2ASIC_MAPPING_CLK,
755 clock_select);
756 if (clk_id < 0)
757 return -EINVAL;
758
759 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
760 clk_id << 16, clock);
761 if (ret) {
762 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
763 return ret;
764 }
765
766 if (*clock != 0)
767 return 0;
768
769 /* if DC limit is zero, return AC limit */
770 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
771 clk_id << 16, clock);
772 if (ret) {
773 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
774 return ret;
775 }
776
777 return 0;
778}
779
780int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
781{
782 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
783 smu->smu_table.max_sustainable_clocks;
784 int ret = 0;
785
786 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
787 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
788 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
789 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
790 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
791 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
792
793 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
794 ret = smu_v13_0_get_max_sustainable_clock(smu,
795 &(max_sustainable_clocks->uclock),
796 SMU_UCLK);
797 if (ret) {
798 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
799 __func__);
800 return ret;
801 }
802 }
803
804 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
805 ret = smu_v13_0_get_max_sustainable_clock(smu,
806 &(max_sustainable_clocks->soc_clock),
807 SMU_SOCCLK);
808 if (ret) {
809 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
810 __func__);
811 return ret;
812 }
813 }
814
815 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
816 ret = smu_v13_0_get_max_sustainable_clock(smu,
817 &(max_sustainable_clocks->dcef_clock),
818 SMU_DCEFCLK);
819 if (ret) {
820 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
821 __func__);
822 return ret;
823 }
824
825 ret = smu_v13_0_get_max_sustainable_clock(smu,
826 &(max_sustainable_clocks->display_clock),
827 SMU_DISPCLK);
828 if (ret) {
829 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
830 __func__);
831 return ret;
832 }
833 ret = smu_v13_0_get_max_sustainable_clock(smu,
834 &(max_sustainable_clocks->phy_clock),
835 SMU_PHYCLK);
836 if (ret) {
837 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
838 __func__);
839 return ret;
840 }
841 ret = smu_v13_0_get_max_sustainable_clock(smu,
842 &(max_sustainable_clocks->pixel_clock),
843 SMU_PIXCLK);
844 if (ret) {
845 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
846 __func__);
847 return ret;
848 }
849 }
850
851 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
852 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
853
854 return 0;
855}
856
857int smu_v13_0_get_current_power_limit(struct smu_context *smu,
858 uint32_t *power_limit)
859{
860 int power_src;
861 int ret = 0;
862
863 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
864 return -EINVAL;
865
866 power_src = smu_cmn_to_asic_specific_index(smu,
867 CMN2ASIC_MAPPING_PWR,
868 smu->adev->pm.ac_power ?
869 SMU_POWER_SOURCE_AC :
870 SMU_POWER_SOURCE_DC);
871 if (power_src < 0)
872 return -EINVAL;
873
874 ret = smu_cmn_send_smc_msg_with_param(smu,
875 SMU_MSG_GetPptLimit,
876 power_src << 16,
877 power_limit);
878 if (ret)
879 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
880
881 return ret;
882}
883
884int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n)
885{
886 int ret = 0;
887
888 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
889 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
890 return -EOPNOTSUPP;
891 }
892
893 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
894 if (ret) {
895 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
896 return ret;
897 }
898
899 smu->current_power_limit = n;
900
901 return 0;
902}
903
904int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
905{
906 if (smu->smu_table.thermal_controller_type)
907 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
908
909 return 0;
910}
911
912int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
913{
914 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
915}
916
917static uint16_t convert_to_vddc(uint8_t vid)
918{
919 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
920}
921
922int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
923{
924 struct amdgpu_device *adev = smu->adev;
925 uint32_t vdd = 0, val_vid = 0;
926
927 if (!value)
928 return -EINVAL;
929 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
930 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
931 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
932
933 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
934
935 *value = vdd;
936
937 return 0;
938
939}
940
941int
942smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
943 struct pp_display_clock_request
944 *clock_req)
945{
946 enum amd_pp_clock_type clk_type = clock_req->clock_type;
947 int ret = 0;
948 enum smu_clk_type clk_select = 0;
949 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
950
951 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
952 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
953 switch (clk_type) {
954 case amd_pp_dcef_clock:
955 clk_select = SMU_DCEFCLK;
956 break;
957 case amd_pp_disp_clock:
958 clk_select = SMU_DISPCLK;
959 break;
960 case amd_pp_pixel_clock:
961 clk_select = SMU_PIXCLK;
962 break;
963 case amd_pp_phy_clock:
964 clk_select = SMU_PHYCLK;
965 break;
966 case amd_pp_mem_clock:
967 clk_select = SMU_UCLK;
968 break;
969 default:
970 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
971 ret = -EINVAL;
972 break;
973 }
974
975 if (ret)
976 goto failed;
977
978 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
979 return 0;
980
981 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
982
983 if(clk_select == SMU_UCLK)
984 smu->hard_min_uclk_req_from_dal = clk_freq;
985 }
986
987failed:
988 return ret;
989}
990
991uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
992{
993 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
994 return AMD_FAN_CTRL_MANUAL;
995 else
996 return AMD_FAN_CTRL_AUTO;
997}
998
999 static int
1000smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1001{
1002 int ret = 0;
1003
1004 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1005 return 0;
1006
1007 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1008 if (ret)
1009 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1010 __func__, (auto_fan_control ? "Start" : "Stop"));
1011
1012 return ret;
1013}
1014
1015 static int
1016smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1017{
1018 struct amdgpu_device *adev = smu->adev;
1019
1020 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1021 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1022 CG_FDO_CTRL2, TMIN, 0));
1023 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1024 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1025 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1026
1027 return 0;
1028}
1029
1030 int
1031smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1032{
1033 struct amdgpu_device *adev = smu->adev;
1034 uint32_t duty100, duty;
1035 uint64_t tmp64;
1036
1037 if (speed > 100)
1038 speed = 100;
1039
1040 if (smu_v13_0_auto_fan_control(smu, 0))
1041 return -EINVAL;
1042
1043 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1044 CG_FDO_CTRL1, FMAX_DUTY100);
1045 if (!duty100)
1046 return -EINVAL;
1047
1048 tmp64 = (uint64_t)speed * duty100;
1049 do_div(tmp64, 100);
1050 duty = (uint32_t)tmp64;
1051
1052 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1053 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1054 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1055
1056 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1057}
1058
1059 int
1060smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1061 uint32_t mode)
1062{
1063 int ret = 0;
1064
1065 switch (mode) {
1066 case AMD_FAN_CTRL_NONE:
1067 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1068 break;
1069 case AMD_FAN_CTRL_MANUAL:
1070 ret = smu_v13_0_auto_fan_control(smu, 0);
1071 break;
1072 case AMD_FAN_CTRL_AUTO:
1073 ret = smu_v13_0_auto_fan_control(smu, 1);
1074 break;
1075 default:
1076 break;
1077 }
1078
1079 if (ret) {
1080 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1081 return -EINVAL;
1082 }
1083
1084 return ret;
1085}
1086
1087int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1088 uint32_t speed)
1089{
1090 struct amdgpu_device *adev = smu->adev;
1091 int ret;
1092 uint32_t tach_period, crystal_clock_freq;
1093
1094 if (!speed)
1095 return -EINVAL;
1096
1097 ret = smu_v13_0_auto_fan_control(smu, 0);
1098 if (ret)
1099 return ret;
1100
1101 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1102 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1103 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1104 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1105 CG_TACH_CTRL, TARGET_PERIOD,
1106 tach_period));
1107
1108 ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1109
1110 return ret;
1111}
1112
1113int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1114 uint32_t pstate)
1115{
1116 int ret = 0;
1117 ret = smu_cmn_send_smc_msg_with_param(smu,
1118 SMU_MSG_SetXgmiMode,
1119 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1120 NULL);
1121 return ret;
1122}
1123
1124static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1125 struct amdgpu_irq_src *source,
1126 unsigned tyep,
1127 enum amdgpu_interrupt_state state)
1128{
1129 struct smu_context *smu = &adev->smu;
1130 uint32_t low, high;
1131 uint32_t val = 0;
1132
1133 switch (state) {
1134 case AMDGPU_IRQ_STATE_DISABLE:
1135 /* For THM irqs */
1136 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1137 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1138 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1139 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1140
1141 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1142
1143 /* For MP1 SW irqs */
1144 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1145 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1146 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1147
1148 break;
1149 case AMDGPU_IRQ_STATE_ENABLE:
1150 /* For THM irqs */
1151 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1152 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1153 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1154 smu->thermal_range.software_shutdown_temp);
1155
1156 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1157 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1158 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1159 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1160 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1161 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1162 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1163 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1164 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1165
1166 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1167 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1168 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1169 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1170
1171 /* For MP1 SW irqs */
1172 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1173 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1174 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1175 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1176
1177 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1178 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1179 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1180
1181 break;
1182 default:
1183 break;
1184 }
1185
1186 return 0;
1187}
1188
1189static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1190{
1191 return smu_cmn_send_smc_msg(smu,
1192 SMU_MSG_ReenableAcDcInterrupt,
1193 NULL);
1194}
1195
1196#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1197#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1198#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1199
1200static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1201 struct amdgpu_irq_src *source,
1202 struct amdgpu_iv_entry *entry)
1203{
1204 struct smu_context *smu = &adev->smu;
1205 uint32_t client_id = entry->client_id;
1206 uint32_t src_id = entry->src_id;
1207 /*
1208 * ctxid is used to distinguish different
1209 * events for SMCToHost interrupt.
1210 */
1211 uint32_t ctxid = entry->src_data[0];
1212 uint32_t data;
1213
1214 if (client_id == SOC15_IH_CLIENTID_THM) {
1215 switch (src_id) {
1216 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1217 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1218 /*
1219 * SW CTF just occurred.
1220 * Try to do a graceful shutdown to prevent further damage.
1221 */
1222 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1223 orderly_poweroff(true);
1224 break;
1225 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1226 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1227 break;
1228 default:
1229 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1230 src_id);
1231 break;
1232 }
1233 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1234 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1235 /*
1236 * HW CTF just occurred. Shutdown to prevent further damage.
1237 */
1238 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1239 orderly_poweroff(true);
1240 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1241 if (src_id == 0xfe) {
1242 /* ACK SMUToHost interrupt */
1243 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1244 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1245 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1246
1247 switch (ctxid) {
1248 case 0x3:
1249 dev_dbg(adev->dev, "Switched to AC mode!\n");
1250 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1251 break;
1252 case 0x4:
1253 dev_dbg(adev->dev, "Switched to DC mode!\n");
1254 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1255 break;
1256 case 0x7:
1257 /*
1258 * Increment the throttle interrupt counter
1259 */
1260 atomic64_inc(&smu->throttle_int_counter);
1261
1262 if (!atomic_read(&adev->throttling_logging_enabled))
1263 return 0;
1264
1265 if (__ratelimit(&adev->throttling_logging_rs))
1266 schedule_work(&smu->throttling_logging_work);
1267
1268 break;
1269 }
1270 }
1271 }
1272
1273 return 0;
1274}
1275
1276static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1277{
1278 .set = smu_v13_0_set_irq_state,
1279 .process = smu_v13_0_irq_process,
1280};
1281
1282int smu_v13_0_register_irq_handler(struct smu_context *smu)
1283{
1284 struct amdgpu_device *adev = smu->adev;
1285 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1286 int ret = 0;
1287
1288 irq_src->num_types = 1;
1289 irq_src->funcs = &smu_v13_0_irq_funcs;
1290
1291 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1292 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1293 irq_src);
1294 if (ret)
1295 return ret;
1296
1297 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1298 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1299 irq_src);
1300 if (ret)
1301 return ret;
1302
1303 /* Register CTF(GPIO_19) interrupt */
1304 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1305 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1306 irq_src);
1307 if (ret)
1308 return ret;
1309
1310 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1311 0xfe,
1312 irq_src);
1313 if (ret)
1314 return ret;
1315
1316 return ret;
1317}
1318
1319int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1320 struct pp_smu_nv_clock_table *max_clocks)
1321{
1322 struct smu_table_context *table_context = &smu->smu_table;
1323 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1324
1325 if (!max_clocks || !table_context->max_sustainable_clocks)
1326 return -EINVAL;
1327
1328 sustainable_clocks = table_context->max_sustainable_clocks;
1329
1330 max_clocks->dcfClockInKhz =
1331 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1332 max_clocks->displayClockInKhz =
1333 (unsigned int) sustainable_clocks->display_clock * 1000;
1334 max_clocks->phyClockInKhz =
1335 (unsigned int) sustainable_clocks->phy_clock * 1000;
1336 max_clocks->pixelClockInKhz =
1337 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1338 max_clocks->uClockInKhz =
1339 (unsigned int) sustainable_clocks->uclock * 1000;
1340 max_clocks->socClockInKhz =
1341 (unsigned int) sustainable_clocks->soc_clock * 1000;
1342 max_clocks->dscClockInKhz = 0;
1343 max_clocks->dppClockInKhz = 0;
1344 max_clocks->fabricClockInKhz = 0;
1345
1346 return 0;
1347}
1348
1349int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1350{
1351 int ret = 0;
1352
1353 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1354
1355 return ret;
1356}
1357
1358int smu_v13_0_mode1_reset(struct smu_context *smu)
1359{
5c03e584 1360 u32 smu_version;
c05d1c40 1361 int ret = 0;
5c03e584
FX		 1362 /*
1363 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1364 */
1365 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1366 if (smu_version < 0x00440700)
1367 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1368 else
1369 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
c05d1c40 1370
c05d1c40
KW		 1371 if (!ret)
1372 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1373
1374 return ret;
1375}
1376
5c03e584
FX		 1377int smu_v13_0_mode2_reset(struct smu_context *smu)
1378{
1379 u32 smu_version;
1380 int ret = 0;
1381 struct amdgpu_device *adev = smu->adev;
1382 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1383 if (smu_version >= 0x00440700)
1384 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
1385 else
1386 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", smu_version);
1387 /*TODO: mode2 reset wait time should be shorter, will modify it later*/
1388 if (!ret)
1389 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1390 return ret;
1391}
1392
c05d1c40
KW		 1393int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1394 uint32_t *min, uint32_t *max)
1395{
1396 int ret = 0, clk_id = 0;
1397 uint32_t param = 0;
1398 uint32_t clock_limit;
1399
1400 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1401 switch (clk_type) {
1402 case SMU_MCLK:
1403 case SMU_UCLK:
1404 clock_limit = smu->smu_table.boot_values.uclk;
1405 break;
1406 case SMU_GFXCLK:
1407 case SMU_SCLK:
1408 clock_limit = smu->smu_table.boot_values.gfxclk;
1409 break;
1410 case SMU_SOCCLK:
1411 clock_limit = smu->smu_table.boot_values.socclk;
1412 break;
1413 default:
1414 clock_limit = 0;
1415 break;
1416 }
1417
1418 /* clock in Mhz unit */
1419 if (min)
1420 *min = clock_limit / 100;
1421 if (max)
1422 *max = clock_limit / 100;
1423
1424 return 0;
1425 }
1426
1427 clk_id = smu_cmn_to_asic_specific_index(smu,
1428 CMN2ASIC_MAPPING_CLK,
1429 clk_type);
1430 if (clk_id < 0) {
1431 ret = -EINVAL;
1432 goto failed;
1433 }
1434 param = (clk_id & 0xffff) << 16;
1435
1436 if (max) {
1437 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1438 if (ret)
1439 goto failed;
1440 }
1441
1442 if (min) {
1443 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1444 if (ret)
1445 goto failed;
1446 }
1447
1448failed:
1449 return ret;
1450}
1451
1452int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1453 enum smu_clk_type clk_type,
1454 uint32_t min,
1455 uint32_t max)
1456{
1457 struct amdgpu_device *adev = smu->adev;
1458 int ret = 0, clk_id = 0;
1459 uint32_t param;
1460
1461 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1462 return 0;
1463
1464 clk_id = smu_cmn_to_asic_specific_index(smu,
1465 CMN2ASIC_MAPPING_CLK,
1466 clk_type);
1467 if (clk_id < 0)
1468 return clk_id;
1469
1470 if (clk_type == SMU_GFXCLK)
1471 amdgpu_gfx_off_ctrl(adev, false);
1472
1473 if (max > 0) {
1474 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1475 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1476 param, NULL);
1477 if (ret)
1478 goto out;
1479 }
1480
1481 if (min > 0) {
1482 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1483 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1484 param, NULL);
1485 if (ret)
1486 goto out;
1487 }
1488
1489out:
1490 if (clk_type == SMU_GFXCLK)
1491 amdgpu_gfx_off_ctrl(adev, true);
1492
1493 return ret;
1494}
1495
1496int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1497 enum smu_clk_type clk_type,
1498 uint32_t min,
1499 uint32_t max)
1500{
1501 int ret = 0, clk_id = 0;
1502 uint32_t param;
1503
1504 if (min <= 0 && max <= 0)
1505 return -EINVAL;
1506
1507 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1508 return 0;
1509
1510 clk_id = smu_cmn_to_asic_specific_index(smu,
1511 CMN2ASIC_MAPPING_CLK,
1512 clk_type);
1513 if (clk_id < 0)
1514 return clk_id;
1515
1516 if (max > 0) {
1517 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1518 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1519 param, NULL);
1520 if (ret)
1521 return ret;
1522 }
1523
1524 if (min > 0) {
1525 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1526 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1527 param, NULL);
1528 if (ret)
1529 return ret;
1530 }
1531
1532 return ret;
1533}
1534
1535int smu_v13_0_set_performance_level(struct smu_context *smu,
1536 enum amd_dpm_forced_level level)
1537{
1538 struct smu_13_0_dpm_context *dpm_context =
1539 smu->smu_dpm.dpm_context;
1540 struct smu_13_0_dpm_table *gfx_table =
1541 &dpm_context->dpm_tables.gfx_table;
1542 struct smu_13_0_dpm_table *mem_table =
1543 &dpm_context->dpm_tables.uclk_table;
1544 struct smu_13_0_dpm_table *soc_table =
1545 &dpm_context->dpm_tables.soc_table;
1546 struct smu_umd_pstate_table *pstate_table =
1547 &smu->pstate_table;
1548 struct amdgpu_device *adev = smu->adev;
1549 uint32_t sclk_min = 0, sclk_max = 0;
1550 uint32_t mclk_min = 0, mclk_max = 0;
1551 uint32_t socclk_min = 0, socclk_max = 0;
1552 int ret = 0;
1553
1554 switch (level) {
1555 case AMD_DPM_FORCED_LEVEL_HIGH:
1556 sclk_min = sclk_max = gfx_table->max;
1557 mclk_min = mclk_max = mem_table->max;
1558 socclk_min = socclk_max = soc_table->max;
1559 break;
1560 case AMD_DPM_FORCED_LEVEL_LOW:
1561 sclk_min = sclk_max = gfx_table->min;
1562 mclk_min = mclk_max = mem_table->min;
1563 socclk_min = socclk_max = soc_table->min;
1564 break;
1565 case AMD_DPM_FORCED_LEVEL_AUTO:
1566 sclk_min = gfx_table->min;
1567 sclk_max = gfx_table->max;
1568 mclk_min = mem_table->min;
1569 mclk_max = mem_table->max;
1570 socclk_min = soc_table->min;
1571 socclk_max = soc_table->max;
1572 break;
1573 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1574 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1575 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1576 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1577 break;
1578 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1579 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1580 break;
1581 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1582 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1583 break;
1584 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1585 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1586 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1587 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1588 break;
1589 case AMD_DPM_FORCED_LEVEL_MANUAL:
1590 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1591 return 0;
1592 default:
1593 dev_err(adev->dev, "Invalid performance level %d\n", level);
1594 return -EINVAL;
1595 }
1596
1597 mclk_min = mclk_max = 0;
1598 socclk_min = socclk_max = 0;
1599
1600 if (sclk_min && sclk_max) {
1601 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1602 SMU_GFXCLK,
1603 sclk_min,
1604 sclk_max);
1605 if (ret)
1606 return ret;
1607 }
1608
1609 if (mclk_min && mclk_max) {
1610 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1611 SMU_MCLK,
1612 mclk_min,
1613 mclk_max);
1614 if (ret)
1615 return ret;
1616 }
1617
1618 if (socclk_min && socclk_max) {
1619 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1620 SMU_SOCCLK,
1621 socclk_min,
1622 socclk_max);
1623 if (ret)
1624 return ret;
1625 }
1626
1627 return ret;
1628}
1629
1630int smu_v13_0_set_power_source(struct smu_context *smu,
1631 enum smu_power_src_type power_src)
1632{
1633 int pwr_source;
1634
1635 pwr_source = smu_cmn_to_asic_specific_index(smu,
1636 CMN2ASIC_MAPPING_PWR,
1637 (uint32_t)power_src);
1638 if (pwr_source < 0)
1639 return -EINVAL;
1640
1641 return smu_cmn_send_smc_msg_with_param(smu,
1642 SMU_MSG_NotifyPowerSource,
1643 pwr_source,
1644 NULL);
1645}
1646
1647int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1648 enum smu_clk_type clk_type,
1649 uint16_t level,
1650 uint32_t *value)
1651{
1652 int ret = 0, clk_id = 0;
1653 uint32_t param;
1654
1655 if (!value)
1656 return -EINVAL;
1657
1658 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1659 return 0;
1660
1661 clk_id = smu_cmn_to_asic_specific_index(smu,
1662 CMN2ASIC_MAPPING_CLK,
1663 clk_type);
1664 if (clk_id < 0)
1665 return clk_id;
1666
1667 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1668
1669 ret = smu_cmn_send_smc_msg_with_param(smu,
1670 SMU_MSG_GetDpmFreqByIndex,
1671 param,
1672 value);
1673 if (ret)
1674 return ret;
1675
1676 /*
1677 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1678 * now, we un-support it
1679 */
1680 *value = *value & 0x7fffffff;
1681
1682 return ret;
1683}
1684
1685int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1686 enum smu_clk_type clk_type,
1687 uint32_t *value)
1688{
1689 return smu_v13_0_get_dpm_freq_by_index(smu,
1690 clk_type,
1691 0xff,
1692 value);
1693}
1694
1695int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1696 enum smu_clk_type clk_type,
1697 struct smu_13_0_dpm_table *single_dpm_table)
1698{
1699 int ret = 0;
1700 uint32_t clk;
1701 int i;
1702
1703 ret = smu_v13_0_get_dpm_level_count(smu,
1704 clk_type,
1705 &single_dpm_table->count);
1706 if (ret) {
1707 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1708 return ret;
1709 }
1710
1711 for (i = 0; i < single_dpm_table->count; i++) {
1712 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1713 clk_type,
1714 i,
1715 &clk);
1716 if (ret) {
1717 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1718 return ret;
1719 }
1720
1721 single_dpm_table->dpm_levels[i].value = clk;
1722 single_dpm_table->dpm_levels[i].enabled = true;
1723
1724 if (i == 0)
1725 single_dpm_table->min = clk;
1726 else if (i == single_dpm_table->count - 1)
1727 single_dpm_table->max = clk;
1728 }
1729
1730 return 0;
1731}
1732
1733int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1734 enum smu_clk_type clk_type,
1735 uint32_t *min_value,
1736 uint32_t *max_value)
1737{
1738 uint32_t level_count = 0;
1739 int ret = 0;
1740
1741 if (!min_value && !max_value)
1742 return -EINVAL;
1743
1744 if (min_value) {
1745 /* by default, level 0 clock value as min value */
1746 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1747 clk_type,
1748 0,
1749 min_value);
1750 if (ret)
1751 return ret;
1752 }
1753
1754 if (max_value) {
1755 ret = smu_v13_0_get_dpm_level_count(smu,
1756 clk_type,
1757 &level_count);
1758 if (ret)
1759 return ret;
1760
1761 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1762 clk_type,
1763 level_count - 1,
1764 max_value);
1765 if (ret)
1766 return ret;
1767 }
1768
1769 return ret;
1770}
1771
1772int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1773{
1774 struct amdgpu_device *adev = smu->adev;
1775
1776 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1777 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1778 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1779}
1780
1781int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1782{
1783 uint32_t width_level;
1784
1785 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1786 if (width_level > LINK_WIDTH_MAX)
1787 width_level = 0;
1788
1789 return link_width[width_level];
1790}
1791
1792int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1793{
1794 struct amdgpu_device *adev = smu->adev;
1795
1796 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1797 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1798 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1799}
1800
1801int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1802{
1803 uint32_t speed_level;
1804
1805 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1806 if (speed_level > LINK_SPEED_MAX)
1807 speed_level = 0;
1808
1809 return link_speed[speed_level];
1810}
1811
Linux 6.x block layer and io_uring tree(s)