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drm/amd/smu: add smu v13_0 header files
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu13 / smu_v13_0.c
CommitLineData
c05d1c40
KW		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/reboot.h>
27
28#define SMU_13_0_PARTIAL_PPTABLE
29#define SWSMU_CODE_LAYER_L3
30
31#include "amdgpu.h"
32#include "amdgpu_smu.h"
33#include "atomfirmware.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_atombios.h"
36#include "smu_v13_0.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "amdgpu_ras.h"
40#include "smu_cmn.h"
41
42#include "asic_reg/thm/thm_13_0_2_offset.h"
43#include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44#include "asic_reg/mp/mp_13_0_2_offset.h"
45#include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46#include "asic_reg/smuio/smuio_13_0_2_offset.h"
47#include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49/*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54#undef pr_err
55#undef pr_warn
56#undef pr_info
57#undef pr_debug
58
59MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60
61#define SMU13_VOLTAGE_SCALE 4
62
c05d1c40
KW		 63#define LINK_WIDTH_MAX 6
64#define LINK_SPEED_MAX 3
65
66#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
67#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
68#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
69#define smnPCIE_LC_SPEED_CNTL 0x11140290
70#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
71#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
72
dd67d7a6
AD		 73static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
74static const int link_speed[] = {25, 50, 80, 160};
c05d1c40
KW		 75
76int smu_v13_0_init_microcode(struct smu_context *smu)
77{
78 struct amdgpu_device *adev = smu->adev;
79 const char *chip_name;
80 char fw_name[30];
81 int err = 0;
82 const struct smc_firmware_header_v1_0 *hdr;
83 const struct common_firmware_header *header;
84 struct amdgpu_firmware_info *ucode = NULL;
85
4a1cac25
KW		 86 /* doesn't need to load smu firmware in IOV mode */
87 if (amdgpu_sriov_vf(adev))
88 return 0;
89
1d789535 90 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9 91 case IP_VERSION(13, 0, 2):
c05d1c40
KW		 92 chip_name = "aldebaran";
93 break;
94 default:
61b396b9 95 dev_err(adev->dev, "Unsupported IP version 0x%x\n",
1d789535 96 adev->ip_versions[MP1_HWIP][0]);
c05d1c40
KW		 97 return -EINVAL;
98 }
99
100 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
101
102 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
103 if (err)
104 goto out;
105 err = amdgpu_ucode_validate(adev->pm.fw);
106 if (err)
107 goto out;
108
109 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
110 amdgpu_ucode_print_smc_hdr(&hdr->header);
111 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
112
113 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
114 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
115 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
116 ucode->fw = adev->pm.fw;
117 header = (const struct common_firmware_header *)ucode->fw->data;
118 adev->firmware.fw_size +=
119 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
120 }
121
122out:
123 if (err) {
124 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
125 fw_name);
126 release_firmware(adev->pm.fw);
127 adev->pm.fw = NULL;
128 }
129 return err;
130}
131
132void smu_v13_0_fini_microcode(struct smu_context *smu)
133{
134 struct amdgpu_device *adev = smu->adev;
135
136 release_firmware(adev->pm.fw);
137 adev->pm.fw = NULL;
138 adev->pm.fw_version = 0;
139}
140
141int smu_v13_0_load_microcode(struct smu_context *smu)
142{
143#if 0
144 struct amdgpu_device *adev = smu->adev;
145 const uint32_t *src;
146 const struct smc_firmware_header_v1_0 *hdr;
147 uint32_t addr_start = MP1_SRAM;
148 uint32_t i;
149 uint32_t smc_fw_size;
150 uint32_t mp1_fw_flags;
151
152 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
153 src = (const uint32_t *)(adev->pm.fw->data +
154 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
155 smc_fw_size = hdr->header.ucode_size_bytes;
156
157 for (i = 1; i < smc_fw_size/4 - 1; i++) {
158 WREG32_PCIE(addr_start, src[i]);
159 addr_start += 4;
160 }
161
162 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
163 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
164 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
165 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
166
167 for (i = 0; i < adev->usec_timeout; i++) {
168 mp1_fw_flags = RREG32_PCIE(MP1_Public |
169 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
170 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
171 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
172 break;
173 udelay(1);
174 }
175
176 if (i == adev->usec_timeout)
177 return -ETIME;
178#endif
179 return 0;
180}
181
182int smu_v13_0_check_fw_status(struct smu_context *smu)
183{
184 struct amdgpu_device *adev = smu->adev;
185 uint32_t mp1_fw_flags;
186
187 mp1_fw_flags = RREG32_PCIE(MP1_Public |
188 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
189
190 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
191 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
192 return 0;
193
194 return -EIO;
195}
196
197int smu_v13_0_check_fw_version(struct smu_context *smu)
198{
6f072a84 199 struct amdgpu_device *adev = smu->adev;
c05d1c40 200 uint32_t if_version = 0xff, smu_version = 0xff;
82890466 201 uint8_t smu_program, smu_major, smu_minor, smu_debug;
c05d1c40
KW		 202 int ret = 0;
203
204 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
205 if (ret)
206 return ret;
207
82890466
ML		 208 smu_program = (smu_version >> 24) & 0xff;
209 smu_major = (smu_version >> 16) & 0xff;
c05d1c40
KW		 210 smu_minor = (smu_version >> 8) & 0xff;
211 smu_debug = (smu_version >> 0) & 0xff;
6f072a84
ML		 212 if (smu->is_apu)
213 adev->pm.fw_version = smu_version;
c05d1c40 214
9f952378 215 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9 216 case IP_VERSION(13, 0, 2):
c05d1c40
KW		 217 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
218 break;
61b396b9
AD		 219 case IP_VERSION(13, 0, 1):
220 case IP_VERSION(13, 0, 3):
db090ff8 221 case IP_VERSION(13, 0, 8):
21cf0293
XH		 222 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
223 break;
068ea8bd
YZ		 224 case IP_VERSION(13, 0, 5):
225 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
226 break;
c05d1c40 227 default:
9f952378
ML		 228 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
229 adev->ip_versions[MP1_HWIP][0]);
c05d1c40
KW		 230 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
231 break;
232 }
233
0ff76b53
ML		 234 /* only for dGPU w/ SMU13*/
235 if (adev->pm.fw)
82890466
ML		 236 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
237 smu_program, smu_version, smu_major, smu_minor, smu_debug);
0ff76b53 238
c05d1c40
KW		 239 /*
240 * 1. if_version mismatch is not critical as our fw is designed
241 * to be backward compatible.
242 * 2. New fw usually brings some optimizations. But that's visible
243 * only on the paired driver.
244 * Considering above, we just leave user a warning message instead
245 * of halt driver loading.
246 */
247 if (if_version != smu->smc_driver_if_version) {
9f952378 248 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
82890466 249 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
c05d1c40 250 smu->smc_driver_if_version, if_version,
82890466 251 smu_program, smu_version, smu_major, smu_minor, smu_debug);
9f952378 252 dev_warn(adev->dev, "SMU driver if version not matched\n");
c05d1c40
KW		 253 }
254
255 return ret;
256}
257
258static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
259 uint32_t *size, uint32_t pptable_id)
260{
261 struct amdgpu_device *adev = smu->adev;
262 const struct smc_firmware_header_v2_1 *v2_1;
263 struct smc_soft_pptable_entry *entries;
264 uint32_t pptable_count = 0;
265 int i = 0;
266
267 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
268 entries = (struct smc_soft_pptable_entry *)
269 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
270 pptable_count = le32_to_cpu(v2_1->pptable_count);
271 for (i = 0; i < pptable_count; i++) {
272 if (le32_to_cpu(entries[i].id) == pptable_id) {
273 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
274 *size = le32_to_cpu(entries[i].ppt_size_bytes);
275 break;
276 }
277 }
278
279 if (i == pptable_count)
280 return -EINVAL;
281
282 return 0;
283}
284
4a1cac25 285static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
c05d1c40
KW		 286{
287 struct amdgpu_device *adev = smu->adev;
c05d1c40
KW		 288 uint16_t atom_table_size;
289 uint8_t frev, crev;
4a1cac25 290 int ret, index;
c05d1c40 291
4a1cac25
KW		 292 dev_info(adev->dev, "use vbios provided pptable\n");
293 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
294 powerplayinfo);
f1adbe03 295
4a1cac25
KW		 296 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
297 (uint8_t **)table);
298 if (ret)
299 return ret;
300
301 if (size)
302 *size = atom_table_size;
303
304 return 0;
305}
306
307static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
308 uint32_t pptable_id)
309{
310 const struct smc_firmware_header_v1_0 *hdr;
311 struct amdgpu_device *adev = smu->adev;
312 uint16_t version_major, version_minor;
313 int ret;
c05d1c40
KW		 314
315 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
4a1cac25
KW		 316 if (!hdr)
317 return -EINVAL;
318
319 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
320
c05d1c40
KW		 321 version_major = le16_to_cpu(hdr->header.header_version_major);
322 version_minor = le16_to_cpu(hdr->header.header_version_minor);
4a1cac25 323 if (version_major != 2) {
c94126c4 324 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
4a1cac25
KW		 325 version_major, version_minor);
326 return -EINVAL;
327 }
328
329 switch (version_minor) {
330 case 1:
331 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
332 break;
333 default:
334 ret = -EINVAL;
335 break;
336 }
337
338 return ret;
339}
340
341int smu_v13_0_setup_pptable(struct smu_context *smu)
342{
343 struct amdgpu_device *adev = smu->adev;
344 uint32_t size = 0, pptable_id = 0;
345 void *table;
346 int ret = 0;
c05d1c40 347
4a1cac25
KW		 348 /* override pptable_id from driver parameter */
349 if (amdgpu_smu_pptable_id >= 0) {
350 pptable_id = amdgpu_smu_pptable_id;
351 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
c05d1c40 352 } else {
4a1cac25 353 pptable_id = smu->smu_table.boot_values.pp_table_id;
c05d1c40
KW		 354 }
355
4a1cac25
KW		 356 /* force using vbios pptable in sriov mode */
357 if (amdgpu_sriov_vf(adev) || !pptable_id)
358 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
359 else
360 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
361
362 if (ret)
363 return ret;
364
c05d1c40
KW		 365 if (!smu->smu_table.power_play_table)
366 smu->smu_table.power_play_table = table;
367 if (!smu->smu_table.power_play_table_size)
368 smu->smu_table.power_play_table_size = size;
369
370 return 0;
371}
372
373int smu_v13_0_init_smc_tables(struct smu_context *smu)
374{
375 struct smu_table_context *smu_table = &smu->smu_table;
376 struct smu_table *tables = smu_table->tables;
377 int ret = 0;
378
379 smu_table->driver_pptable =
380 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
381 if (!smu_table->driver_pptable) {
382 ret = -ENOMEM;
383 goto err0_out;
384 }
385
386 smu_table->max_sustainable_clocks =
387 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
388 if (!smu_table->max_sustainable_clocks) {
389 ret = -ENOMEM;
390 goto err1_out;
391 }
392
393 /* Aldebaran does not support OVERDRIVE */
394 if (tables[SMU_TABLE_OVERDRIVE].size) {
395 smu_table->overdrive_table =
396 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
397 if (!smu_table->overdrive_table) {
398 ret = -ENOMEM;
399 goto err2_out;
400 }
401
402 smu_table->boot_overdrive_table =
403 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
404 if (!smu_table->boot_overdrive_table) {
405 ret = -ENOMEM;
406 goto err3_out;
407 }
408 }
409
410 return 0;
411
412err3_out:
413 kfree(smu_table->overdrive_table);
414err2_out:
415 kfree(smu_table->max_sustainable_clocks);
416err1_out:
417 kfree(smu_table->driver_pptable);
418err0_out:
419 return ret;
420}
421
422int smu_v13_0_fini_smc_tables(struct smu_context *smu)
423{
424 struct smu_table_context *smu_table = &smu->smu_table;
425 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
426
427 kfree(smu_table->gpu_metrics_table);
428 kfree(smu_table->boot_overdrive_table);
429 kfree(smu_table->overdrive_table);
430 kfree(smu_table->max_sustainable_clocks);
431 kfree(smu_table->driver_pptable);
432 smu_table->gpu_metrics_table = NULL;
433 smu_table->boot_overdrive_table = NULL;
434 smu_table->overdrive_table = NULL;
435 smu_table->max_sustainable_clocks = NULL;
436 smu_table->driver_pptable = NULL;
437 kfree(smu_table->hardcode_pptable);
438 smu_table->hardcode_pptable = NULL;
439
edd79420 440 kfree(smu_table->ecc_table);
c05d1c40
KW		 441 kfree(smu_table->metrics_table);
442 kfree(smu_table->watermarks_table);
edd79420 443 smu_table->ecc_table = NULL;
c05d1c40
KW		 444 smu_table->metrics_table = NULL;
445 smu_table->watermarks_table = NULL;
446 smu_table->metrics_time = 0;
447
448 kfree(smu_dpm->dpm_context);
449 kfree(smu_dpm->golden_dpm_context);
450 kfree(smu_dpm->dpm_current_power_state);
451 kfree(smu_dpm->dpm_request_power_state);
452 smu_dpm->dpm_context = NULL;
453 smu_dpm->golden_dpm_context = NULL;
454 smu_dpm->dpm_context_size = 0;
455 smu_dpm->dpm_current_power_state = NULL;
456 smu_dpm->dpm_request_power_state = NULL;
457
458 return 0;
459}
460
461int smu_v13_0_init_power(struct smu_context *smu)
462{
463 struct smu_power_context *smu_power = &smu->smu_power;
464
465 if (smu_power->power_context || smu_power->power_context_size != 0)
466 return -EINVAL;
467
468 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
469 GFP_KERNEL);
470 if (!smu_power->power_context)
471 return -ENOMEM;
472 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
473
474 return 0;
475}
476
477int smu_v13_0_fini_power(struct smu_context *smu)
478{
479 struct smu_power_context *smu_power = &smu->smu_power;
480
481 if (!smu_power->power_context || smu_power->power_context_size == 0)
482 return -EINVAL;
483
484 kfree(smu_power->power_context);
485 smu_power->power_context = NULL;
486 smu_power->power_context_size = 0;
487
488 return 0;
489}
490
c05d1c40
KW		 491int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
492{
493 int ret, index;
494 uint16_t size;
495 uint8_t frev, crev;
496 struct atom_common_table_header *header;
3d01361c 497 struct atom_firmware_info_v3_4 *v_3_4;
c05d1c40
KW		 498 struct atom_firmware_info_v3_3 *v_3_3;
499 struct atom_firmware_info_v3_1 *v_3_1;
593a54f1
EQ		 500 struct atom_smu_info_v3_6 *smu_info_v3_6;
501 struct atom_smu_info_v4_0 *smu_info_v4_0;
c05d1c40
KW		 502
503 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
504 firmwareinfo);
505
506 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
507 (uint8_t **)&header);
508 if (ret)
509 return ret;
510
511 if (header->format_revision != 3) {
512 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
513 return -EINVAL;
514 }
515
516 switch (header->content_revision) {
517 case 0:
518 case 1:
519 case 2:
520 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
521 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
522 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
523 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
524 smu->smu_table.boot_values.socclk = 0;
525 smu->smu_table.boot_values.dcefclk = 0;
526 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
527 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
528 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
529 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
530 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
531 smu->smu_table.boot_values.pp_table_id = 0;
532 break;
533 case 3:
c05d1c40
KW		 534 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
535 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
536 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
537 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
538 smu->smu_table.boot_values.socclk = 0;
539 smu->smu_table.boot_values.dcefclk = 0;
540 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
541 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
542 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
543 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
544 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
545 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
e5a83213 546 break;
3d01361c
FX		 547 case 4:
548 default:
549 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
550 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
551 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
552 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
553 smu->smu_table.boot_values.socclk = 0;
554 smu->smu_table.boot_values.dcefclk = 0;
555 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
556 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
557 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
558 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
559 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
560 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
e5a83213 561 break;
c05d1c40
KW		 562 }
563
564 smu->smu_table.boot_values.format_revision = header->format_revision;
565 smu->smu_table.boot_values.content_revision = header->content_revision;
566
593a54f1
EQ		 567 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
568 smu_info);
569 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
570 (uint8_t **)&header)) {
571 if ((frev == 3) && (crev == 6)) {
572 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
573
574 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
575 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
576 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
577 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
578 } else if ((frev == 4) && (crev == 0)) {
579 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
580
581 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
582 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
583 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
584 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
585 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
586 } else {
587 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
588 (uint32_t)frev, (uint32_t)crev);
589 }
590 }
c05d1c40
KW		 591
592 return 0;
593}
594
f1adbe03 595
c05d1c40
KW		 596int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
597{
598 struct smu_table_context *smu_table = &smu->smu_table;
599 struct smu_table *memory_pool = &smu_table->memory_pool;
600 int ret = 0;
601 uint64_t address;
602 uint32_t address_low, address_high;
603
604 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
605 return ret;
606
c05d1c40
KW		 607 address = memory_pool->mc_address;
608 address_high = (uint32_t)upper_32_bits(address);
609 address_low = (uint32_t)lower_32_bits(address);
610
611 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
612 address_high, NULL);
613 if (ret)
614 return ret;
615 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
616 address_low, NULL);
617 if (ret)
618 return ret;
619 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
620 (uint32_t)memory_pool->size, NULL);
621 if (ret)
622 return ret;
623
624 return ret;
625}
626
627int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
628{
629 int ret;
630
631 ret = smu_cmn_send_smc_msg_with_param(smu,
632 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
633 if (ret)
634 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
635
636 return ret;
637}
638
639int smu_v13_0_set_driver_table_location(struct smu_context *smu)
640{
641 struct smu_table *driver_table = &smu->smu_table.driver_table;
642 int ret = 0;
643
644 if (driver_table->mc_address) {
645 ret = smu_cmn_send_smc_msg_with_param(smu,
646 SMU_MSG_SetDriverDramAddrHigh,
647 upper_32_bits(driver_table->mc_address),
648 NULL);
649 if (!ret)
650 ret = smu_cmn_send_smc_msg_with_param(smu,
651 SMU_MSG_SetDriverDramAddrLow,
652 lower_32_bits(driver_table->mc_address),
653 NULL);
654 }
655
656 return ret;
657}
658
659int smu_v13_0_set_tool_table_location(struct smu_context *smu)
660{
661 int ret = 0;
662 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
663
664 if (tool_table->mc_address) {
665 ret = smu_cmn_send_smc_msg_with_param(smu,
666 SMU_MSG_SetToolsDramAddrHigh,
667 upper_32_bits(tool_table->mc_address),
668 NULL);
669 if (!ret)
670 ret = smu_cmn_send_smc_msg_with_param(smu,
671 SMU_MSG_SetToolsDramAddrLow,
672 lower_32_bits(tool_table->mc_address),
673 NULL);
674 }
675
676 return ret;
677}
678
679int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
680{
681 int ret = 0;
682
683 if (!smu->pm_enabled)
684 return ret;
685
686 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
687
688 return ret;
689}
690
691
692int smu_v13_0_set_allowed_mask(struct smu_context *smu)
693{
694 struct smu_feature *feature = &smu->smu_feature;
695 int ret = 0;
696 uint32_t feature_mask[2];
697
1f2cf08a
EQ		 698 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
699 feature->feature_num < 64)
700 return -EINVAL;
c05d1c40
KW		 701
702 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
703
704 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
705 feature_mask[1], NULL);
706 if (ret)
1f2cf08a 707 return ret;
c05d1c40 708
1f2cf08a
EQ		 709 return smu_cmn_send_smc_msg_with_param(smu,
710 SMU_MSG_SetAllowedFeaturesMaskLow,
711 feature_mask[0],
712 NULL);
c05d1c40
KW		 713}
714
21cf0293
XH		 715int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
716{
717 int ret = 0;
718 struct amdgpu_device *adev = smu->adev;
719
1d789535 720 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9
AD		 721 case IP_VERSION(13, 0, 1):
722 case IP_VERSION(13, 0, 3):
111aeed2 723 case IP_VERSION(13, 0, 5):
d7709eb6 724 case IP_VERSION(13, 0, 8):
21cf0293
XH		 725 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
726 return 0;
727 if (enable)
728 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
729 else
730 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
731 break;
732 default:
733 break;
734 }
735
736 return ret;
737}
738
c05d1c40
KW		 739int smu_v13_0_system_features_control(struct smu_context *smu,
740 bool en)
741{
3c6591e9
EQ		 742 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
743 SMU_MSG_DisableAllSmuFeatures), NULL);
c05d1c40
KW		 744}
745
746int smu_v13_0_notify_display_change(struct smu_context *smu)
747{
748 int ret = 0;
749
750 if (!smu->pm_enabled)
751 return ret;
752
753 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
754 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
755 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
756
757 return ret;
758}
759
760 static int
761smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
762 enum smu_clk_type clock_select)
763{
764 int ret = 0;
765 int clk_id;
766
767 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
768 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
769 return 0;
770
771 clk_id = smu_cmn_to_asic_specific_index(smu,
772 CMN2ASIC_MAPPING_CLK,
773 clock_select);
774 if (clk_id < 0)
775 return -EINVAL;
776
777 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
778 clk_id << 16, clock);
779 if (ret) {
780 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
781 return ret;
782 }
783
784 if (*clock != 0)
785 return 0;
786
787 /* if DC limit is zero, return AC limit */
788 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
789 clk_id << 16, clock);
790 if (ret) {
791 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
792 return ret;
793 }
794
795 return 0;
796}
797
798int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
799{
800 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
801 smu->smu_table.max_sustainable_clocks;
802 int ret = 0;
803
804 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
805 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
806 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
807 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
808 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
809 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
810
811 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
812 ret = smu_v13_0_get_max_sustainable_clock(smu,
813 &(max_sustainable_clocks->uclock),
814 SMU_UCLK);
815 if (ret) {
816 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
817 __func__);
818 return ret;
819 }
820 }
821
822 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
823 ret = smu_v13_0_get_max_sustainable_clock(smu,
824 &(max_sustainable_clocks->soc_clock),
825 SMU_SOCCLK);
826 if (ret) {
827 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
828 __func__);
829 return ret;
830 }
831 }
832
833 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
834 ret = smu_v13_0_get_max_sustainable_clock(smu,
835 &(max_sustainable_clocks->dcef_clock),
836 SMU_DCEFCLK);
837 if (ret) {
838 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
839 __func__);
840 return ret;
841 }
842
843 ret = smu_v13_0_get_max_sustainable_clock(smu,
844 &(max_sustainable_clocks->display_clock),
845 SMU_DISPCLK);
846 if (ret) {
847 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
848 __func__);
849 return ret;
850 }
851 ret = smu_v13_0_get_max_sustainable_clock(smu,
852 &(max_sustainable_clocks->phy_clock),
853 SMU_PHYCLK);
854 if (ret) {
855 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
856 __func__);
857 return ret;
858 }
859 ret = smu_v13_0_get_max_sustainable_clock(smu,
860 &(max_sustainable_clocks->pixel_clock),
861 SMU_PIXCLK);
862 if (ret) {
863 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
864 __func__);
865 return ret;
866 }
867 }
868
869 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
870 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
871
872 return 0;
873}
874
875int smu_v13_0_get_current_power_limit(struct smu_context *smu,
876 uint32_t *power_limit)
877{
878 int power_src;
879 int ret = 0;
880
881 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
882 return -EINVAL;
883
884 power_src = smu_cmn_to_asic_specific_index(smu,
885 CMN2ASIC_MAPPING_PWR,
886 smu->adev->pm.ac_power ?
887 SMU_POWER_SOURCE_AC :
888 SMU_POWER_SOURCE_DC);
889 if (power_src < 0)
890 return -EINVAL;
891
892 ret = smu_cmn_send_smc_msg_with_param(smu,
893 SMU_MSG_GetPptLimit,
894 power_src << 16,
895 power_limit);
896 if (ret)
897 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
898
899 return ret;
900}
901
2d1ac1cb
DP		 902int smu_v13_0_set_power_limit(struct smu_context *smu,
903 enum smu_ppt_limit_type limit_type,
904 uint32_t limit)
c05d1c40
KW		 905{
906 int ret = 0;
907
2d1ac1cb
DP		 908 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
909 return -EINVAL;
910
c05d1c40
KW		 911 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
912 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
913 return -EOPNOTSUPP;
914 }
915
2d1ac1cb 916 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
c05d1c40
KW		 917 if (ret) {
918 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
919 return ret;
920 }
921
2d1ac1cb 922 smu->current_power_limit = limit;
c05d1c40
KW		 923
924 return 0;
925}
926
927int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
928{
929 if (smu->smu_table.thermal_controller_type)
930 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
931
932 return 0;
933}
934
935int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
936{
937 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
938}
939
940static uint16_t convert_to_vddc(uint8_t vid)
941{
942 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
943}
944
945int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
946{
947 struct amdgpu_device *adev = smu->adev;
948 uint32_t vdd = 0, val_vid = 0;
949
950 if (!value)
951 return -EINVAL;
952 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
953 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
954 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
955
956 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
957
958 *value = vdd;
959
960 return 0;
961
962}
963
964int
965smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
966 struct pp_display_clock_request
967 *clock_req)
968{
969 enum amd_pp_clock_type clk_type = clock_req->clock_type;
970 int ret = 0;
971 enum smu_clk_type clk_select = 0;
972 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
973
974 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
975 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
976 switch (clk_type) {
977 case amd_pp_dcef_clock:
978 clk_select = SMU_DCEFCLK;
979 break;
980 case amd_pp_disp_clock:
981 clk_select = SMU_DISPCLK;
982 break;
983 case amd_pp_pixel_clock:
984 clk_select = SMU_PIXCLK;
985 break;
986 case amd_pp_phy_clock:
987 clk_select = SMU_PHYCLK;
988 break;
989 case amd_pp_mem_clock:
990 clk_select = SMU_UCLK;
991 break;
992 default:
993 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
994 ret = -EINVAL;
995 break;
996 }
997
998 if (ret)
999 goto failed;
1000
1001 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1002 return 0;
1003
1004 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1005
1006 if(clk_select == SMU_UCLK)
1007 smu->hard_min_uclk_req_from_dal = clk_freq;
1008 }
1009
1010failed:
1011 return ret;
1012}
1013
1014uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1015{
1016 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1017 return AMD_FAN_CTRL_MANUAL;
1018 else
1019 return AMD_FAN_CTRL_AUTO;
1020}
1021
1022 static int
1023smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1024{
1025 int ret = 0;
1026
1027 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1028 return 0;
1029
1030 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1031 if (ret)
1032 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1033 __func__, (auto_fan_control ? "Start" : "Stop"));
1034
1035 return ret;
1036}
1037
1038 static int
1039smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1040{
1041 struct amdgpu_device *adev = smu->adev;
1042
1043 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1044 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1045 CG_FDO_CTRL2, TMIN, 0));
1046 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1047 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1048 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1049
1050 return 0;
1051}
1052
1053 int
1054smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1055{
1056 struct amdgpu_device *adev = smu->adev;
1057 uint32_t duty100, duty;
1058 uint64_t tmp64;
1059
1060 if (speed > 100)
1061 speed = 100;
1062
1063 if (smu_v13_0_auto_fan_control(smu, 0))
1064 return -EINVAL;
1065
1066 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1067 CG_FDO_CTRL1, FMAX_DUTY100);
1068 if (!duty100)
1069 return -EINVAL;
1070
1071 tmp64 = (uint64_t)speed * duty100;
1072 do_div(tmp64, 100);
1073 duty = (uint32_t)tmp64;
1074
1075 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1076 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1077 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1078
1079 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1080}
1081
1082 int
1083smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1084 uint32_t mode)
1085{
1086 int ret = 0;
1087
1088 switch (mode) {
1089 case AMD_FAN_CTRL_NONE:
1090 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1091 break;
1092 case AMD_FAN_CTRL_MANUAL:
1093 ret = smu_v13_0_auto_fan_control(smu, 0);
1094 break;
1095 case AMD_FAN_CTRL_AUTO:
1096 ret = smu_v13_0_auto_fan_control(smu, 1);
1097 break;
1098 default:
1099 break;
1100 }
1101
1102 if (ret) {
1103 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1104 return -EINVAL;
1105 }
1106
1107 return ret;
1108}
1109
1110int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1111 uint32_t speed)
1112{
1113 struct amdgpu_device *adev = smu->adev;
1114 int ret;
1115 uint32_t tach_period, crystal_clock_freq;
1116
1117 if (!speed)
1118 return -EINVAL;
1119
1120 ret = smu_v13_0_auto_fan_control(smu, 0);
1121 if (ret)
1122 return ret;
1123
1124 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1125 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1126 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1127 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1128 CG_TACH_CTRL, TARGET_PERIOD,
1129 tach_period));
1130
1131 ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1132
1133 return ret;
1134}
1135
1136int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1137 uint32_t pstate)
1138{
1139 int ret = 0;
1140 ret = smu_cmn_send_smc_msg_with_param(smu,
1141 SMU_MSG_SetXgmiMode,
1142 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1143 NULL);
1144 return ret;
1145}
1146
1147static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1148 struct amdgpu_irq_src *source,
1149 unsigned tyep,
1150 enum amdgpu_interrupt_state state)
1151{
ebfc2533 1152 struct smu_context *smu = adev->powerplay.pp_handle;
c05d1c40
KW		 1153 uint32_t low, high;
1154 uint32_t val = 0;
1155
1156 switch (state) {
1157 case AMDGPU_IRQ_STATE_DISABLE:
1158 /* For THM irqs */
1159 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1160 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1161 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1162 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1163
1164 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1165
1166 /* For MP1 SW irqs */
1167 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1168 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1169 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1170
1171 break;
1172 case AMDGPU_IRQ_STATE_ENABLE:
1173 /* For THM irqs */
1174 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1175 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1176 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1177 smu->thermal_range.software_shutdown_temp);
1178
1179 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1180 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1181 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1182 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1183 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1184 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1185 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1186 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1187 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1188
1189 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1190 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1191 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1192 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1193
1194 /* For MP1 SW irqs */
1195 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1196 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1197 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1198 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1199
1200 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1201 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1202 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1203
1204 break;
1205 default:
1206 break;
1207 }
1208
1209 return 0;
1210}
1211
1212static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1213{
1214 return smu_cmn_send_smc_msg(smu,
1215 SMU_MSG_ReenableAcDcInterrupt,
1216 NULL);
1217}
1218
1219#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1220#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1221#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1222
1223static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1224 struct amdgpu_irq_src *source,
1225 struct amdgpu_iv_entry *entry)
1226{
ebfc2533 1227 struct smu_context *smu = adev->powerplay.pp_handle;
c05d1c40
KW		 1228 uint32_t client_id = entry->client_id;
1229 uint32_t src_id = entry->src_id;
1230 /*
1231 * ctxid is used to distinguish different
1232 * events for SMCToHost interrupt.
1233 */
1234 uint32_t ctxid = entry->src_data[0];
1235 uint32_t data;
1236
1237 if (client_id == SOC15_IH_CLIENTID_THM) {
1238 switch (src_id) {
1239 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1240 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1241 /*
1242 * SW CTF just occurred.
1243 * Try to do a graceful shutdown to prevent further damage.
1244 */
1245 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1246 orderly_poweroff(true);
1247 break;
1248 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1249 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1250 break;
1251 default:
1252 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1253 src_id);
1254 break;
1255 }
1256 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1257 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1258 /*
1259 * HW CTF just occurred. Shutdown to prevent further damage.
1260 */
1261 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1262 orderly_poweroff(true);
1263 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1264 if (src_id == 0xfe) {
1265 /* ACK SMUToHost interrupt */
1266 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1267 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1268 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1269
1270 switch (ctxid) {
1271 case 0x3:
1272 dev_dbg(adev->dev, "Switched to AC mode!\n");
ebfc2533 1273 smu_v13_0_ack_ac_dc_interrupt(smu);
c05d1c40
KW		 1274 break;
1275 case 0x4:
1276 dev_dbg(adev->dev, "Switched to DC mode!\n");
ebfc2533 1277 smu_v13_0_ack_ac_dc_interrupt(smu);
c05d1c40
KW		 1278 break;
1279 case 0x7:
1280 /*
1281 * Increment the throttle interrupt counter
1282 */
1283 atomic64_inc(&smu->throttle_int_counter);
1284
1285 if (!atomic_read(&adev->throttling_logging_enabled))
1286 return 0;
1287
1288 if (__ratelimit(&adev->throttling_logging_rs))
1289 schedule_work(&smu->throttling_logging_work);
1290
1291 break;
1292 }
1293 }
1294 }
1295
1296 return 0;
1297}
1298
1299static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1300{
1301 .set = smu_v13_0_set_irq_state,
1302 .process = smu_v13_0_irq_process,
1303};
1304
1305int smu_v13_0_register_irq_handler(struct smu_context *smu)
1306{
1307 struct amdgpu_device *adev = smu->adev;
1308 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1309 int ret = 0;
1310
1311 irq_src->num_types = 1;
1312 irq_src->funcs = &smu_v13_0_irq_funcs;
1313
1314 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1315 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1316 irq_src);
1317 if (ret)
1318 return ret;
1319
1320 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1321 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1322 irq_src);
1323 if (ret)
1324 return ret;
1325
1326 /* Register CTF(GPIO_19) interrupt */
1327 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1328 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1329 irq_src);
1330 if (ret)
1331 return ret;
1332
1333 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1334 0xfe,
1335 irq_src);
1336 if (ret)
1337 return ret;
1338
1339 return ret;
1340}
1341
1342int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1343 struct pp_smu_nv_clock_table *max_clocks)
1344{
1345 struct smu_table_context *table_context = &smu->smu_table;
1346 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1347
1348 if (!max_clocks || !table_context->max_sustainable_clocks)
1349 return -EINVAL;
1350
1351 sustainable_clocks = table_context->max_sustainable_clocks;
1352
1353 max_clocks->dcfClockInKhz =
1354 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1355 max_clocks->displayClockInKhz =
1356 (unsigned int) sustainable_clocks->display_clock * 1000;
1357 max_clocks->phyClockInKhz =
1358 (unsigned int) sustainable_clocks->phy_clock * 1000;
1359 max_clocks->pixelClockInKhz =
1360 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1361 max_clocks->uClockInKhz =
1362 (unsigned int) sustainable_clocks->uclock * 1000;
1363 max_clocks->socClockInKhz =
1364 (unsigned int) sustainable_clocks->soc_clock * 1000;
1365 max_clocks->dscClockInKhz = 0;
1366 max_clocks->dppClockInKhz = 0;
1367 max_clocks->fabricClockInKhz = 0;
1368
1369 return 0;
1370}
1371
1372int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1373{
1374 int ret = 0;
1375
1376 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1377
1378 return ret;
1379}
1380
c941e9fe
LL		 1381static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1382 uint64_t event_arg)
1383{
1384 int ret = 0;
1385
1386 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1387 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1388
1389 return ret;
1390}
1391
1392int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1393 uint64_t event_arg)
1394{
1395 int ret = -EINVAL;
1396
1397 switch (event) {
1398 case SMU_EVENT_RESET_COMPLETE:
1399 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1400 break;
1401 default:
1402 break;
1403 }
1404
1405 return ret;
1406}
1407
5c03e584
FX		 1408int smu_v13_0_mode2_reset(struct smu_context *smu)
1409{
e42569d0
LL		 1410 int ret;
1411
1412 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1413 SMU_RESET_MODE_2, NULL);
1414 /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
5c03e584
FX		 1415 if (!ret)
1416 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
e42569d0 1417
5c03e584
FX		 1418 return ret;
1419}
1420
c05d1c40
KW		 1421int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1422 uint32_t *min, uint32_t *max)
1423{
1424 int ret = 0, clk_id = 0;
1425 uint32_t param = 0;
1426 uint32_t clock_limit;
1427
1428 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1429 switch (clk_type) {
1430 case SMU_MCLK:
1431 case SMU_UCLK:
1432 clock_limit = smu->smu_table.boot_values.uclk;
1433 break;
1434 case SMU_GFXCLK:
1435 case SMU_SCLK:
1436 clock_limit = smu->smu_table.boot_values.gfxclk;
1437 break;
1438 case SMU_SOCCLK:
1439 clock_limit = smu->smu_table.boot_values.socclk;
1440 break;
1441 default:
1442 clock_limit = 0;
1443 break;
1444 }
1445
1446 /* clock in Mhz unit */
1447 if (min)
1448 *min = clock_limit / 100;
1449 if (max)
1450 *max = clock_limit / 100;
1451
1452 return 0;
1453 }
1454
1455 clk_id = smu_cmn_to_asic_specific_index(smu,
1456 CMN2ASIC_MAPPING_CLK,
1457 clk_type);
1458 if (clk_id < 0) {
1459 ret = -EINVAL;
1460 goto failed;
1461 }
1462 param = (clk_id & 0xffff) << 16;
1463
1464 if (max) {
1465 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1466 if (ret)
1467 goto failed;
1468 }
1469
1470 if (min) {
1471 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1472 if (ret)
1473 goto failed;
1474 }
1475
1476failed:
1477 return ret;
1478}
1479
1480int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1481 enum smu_clk_type clk_type,
1482 uint32_t min,
1483 uint32_t max)
1484{
c05d1c40
KW		 1485 int ret = 0, clk_id = 0;
1486 uint32_t param;
1487
1488 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1489 return 0;
1490
1491 clk_id = smu_cmn_to_asic_specific_index(smu,
1492 CMN2ASIC_MAPPING_CLK,
1493 clk_type);
1494 if (clk_id < 0)
1495 return clk_id;
1496
c05d1c40
KW		 1497 if (max > 0) {
1498 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1499 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1500 param, NULL);
1501 if (ret)
1502 goto out;
1503 }
1504
1505 if (min > 0) {
1506 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1507 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1508 param, NULL);
1509 if (ret)
1510 goto out;
1511 }
1512
1513out:
c05d1c40
KW		 1514 return ret;
1515}
1516
1517int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1518 enum smu_clk_type clk_type,
1519 uint32_t min,
1520 uint32_t max)
1521{
1522 int ret = 0, clk_id = 0;
1523 uint32_t param;
1524
1525 if (min <= 0 && max <= 0)
1526 return -EINVAL;
1527
1528 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1529 return 0;
1530
1531 clk_id = smu_cmn_to_asic_specific_index(smu,
1532 CMN2ASIC_MAPPING_CLK,
1533 clk_type);
1534 if (clk_id < 0)
1535 return clk_id;
1536
1537 if (max > 0) {
1538 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1539 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1540 param, NULL);
1541 if (ret)
1542 return ret;
1543 }
1544
1545 if (min > 0) {
1546 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1547 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1548 param, NULL);
1549 if (ret)
1550 return ret;
1551 }
1552
1553 return ret;
1554}
1555
1556int smu_v13_0_set_performance_level(struct smu_context *smu,
1557 enum amd_dpm_forced_level level)
1558{
1559 struct smu_13_0_dpm_context *dpm_context =
1560 smu->smu_dpm.dpm_context;
1561 struct smu_13_0_dpm_table *gfx_table =
1562 &dpm_context->dpm_tables.gfx_table;
1563 struct smu_13_0_dpm_table *mem_table =
1564 &dpm_context->dpm_tables.uclk_table;
1565 struct smu_13_0_dpm_table *soc_table =
1566 &dpm_context->dpm_tables.soc_table;
1567 struct smu_umd_pstate_table *pstate_table =
1568 &smu->pstate_table;
1569 struct amdgpu_device *adev = smu->adev;
1570 uint32_t sclk_min = 0, sclk_max = 0;
1571 uint32_t mclk_min = 0, mclk_max = 0;
1572 uint32_t socclk_min = 0, socclk_max = 0;
1573 int ret = 0;
1574
1575 switch (level) {
1576 case AMD_DPM_FORCED_LEVEL_HIGH:
1577 sclk_min = sclk_max = gfx_table->max;
1578 mclk_min = mclk_max = mem_table->max;
1579 socclk_min = socclk_max = soc_table->max;
1580 break;
1581 case AMD_DPM_FORCED_LEVEL_LOW:
1582 sclk_min = sclk_max = gfx_table->min;
1583 mclk_min = mclk_max = mem_table->min;
1584 socclk_min = socclk_max = soc_table->min;
1585 break;
1586 case AMD_DPM_FORCED_LEVEL_AUTO:
1587 sclk_min = gfx_table->min;
1588 sclk_max = gfx_table->max;
1589 mclk_min = mem_table->min;
1590 mclk_max = mem_table->max;
1591 socclk_min = soc_table->min;
1592 socclk_max = soc_table->max;
1593 break;
1594 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1595 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1596 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1597 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1598 break;
1599 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1600 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1601 break;
1602 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1603 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1604 break;
1605 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1606 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1607 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1608 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1609 break;
1610 case AMD_DPM_FORCED_LEVEL_MANUAL:
1611 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1612 return 0;
1613 default:
1614 dev_err(adev->dev, "Invalid performance level %d\n", level);
1615 return -EINVAL;
1616 }
1617
1618 mclk_min = mclk_max = 0;
1619 socclk_min = socclk_max = 0;
1620
1621 if (sclk_min && sclk_max) {
1622 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1623 SMU_GFXCLK,
1624 sclk_min,
1625 sclk_max);
1626 if (ret)
1627 return ret;
e943dd88
LL		 1628
1629 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1630 pstate_table->gfxclk_pstate.curr.max = sclk_max;
c05d1c40
KW		 1631 }
1632
1633 if (mclk_min && mclk_max) {
1634 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1635 SMU_MCLK,
1636 mclk_min,
1637 mclk_max);
1638 if (ret)
1639 return ret;
e943dd88
LL		 1640
1641 pstate_table->uclk_pstate.curr.min = mclk_min;
1642 pstate_table->uclk_pstate.curr.max = mclk_max;
c05d1c40
KW		 1643 }
1644
1645 if (socclk_min && socclk_max) {
1646 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1647 SMU_SOCCLK,
1648 socclk_min,
1649 socclk_max);
1650 if (ret)
1651 return ret;
e943dd88
LL		 1652
1653 pstate_table->socclk_pstate.curr.min = socclk_min;
1654 pstate_table->socclk_pstate.curr.max = socclk_max;
c05d1c40
KW		 1655 }
1656
1657 return ret;
1658}
1659
1660int smu_v13_0_set_power_source(struct smu_context *smu,
1661 enum smu_power_src_type power_src)
1662{
1663 int pwr_source;
1664
1665 pwr_source = smu_cmn_to_asic_specific_index(smu,
1666 CMN2ASIC_MAPPING_PWR,
1667 (uint32_t)power_src);
1668 if (pwr_source < 0)
1669 return -EINVAL;
1670
1671 return smu_cmn_send_smc_msg_with_param(smu,
1672 SMU_MSG_NotifyPowerSource,
1673 pwr_source,
1674 NULL);
1675}
1676
1677int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1678 enum smu_clk_type clk_type,
1679 uint16_t level,
1680 uint32_t *value)
1681{
1682 int ret = 0, clk_id = 0;
1683 uint32_t param;
1684
1685 if (!value)
1686 return -EINVAL;
1687
1688 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1689 return 0;
1690
1691 clk_id = smu_cmn_to_asic_specific_index(smu,
1692 CMN2ASIC_MAPPING_CLK,
1693 clk_type);
1694 if (clk_id < 0)
1695 return clk_id;
1696
1697 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1698
1699 ret = smu_cmn_send_smc_msg_with_param(smu,
1700 SMU_MSG_GetDpmFreqByIndex,
1701 param,
1702 value);
1703 if (ret)
1704 return ret;
1705
1706 /*
1707 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1708 * now, we un-support it
1709 */
1710 *value = *value & 0x7fffffff;
1711
1712 return ret;
1713}
1714
1715int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1716 enum smu_clk_type clk_type,
1717 uint32_t *value)
1718{
f41f8e08
LL		 1719 int ret;
1720
1721 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
2913b567
LG		 1722 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1723 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
f41f8e08
LL		 1724 ++(*value);
1725
1726 return ret;
c05d1c40
KW		 1727}
1728
1729int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1730 enum smu_clk_type clk_type,
1731 struct smu_13_0_dpm_table *single_dpm_table)
1732{
1733 int ret = 0;
1734 uint32_t clk;
1735 int i;
1736
1737 ret = smu_v13_0_get_dpm_level_count(smu,
1738 clk_type,
1739 &single_dpm_table->count);
1740 if (ret) {
1741 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1742 return ret;
1743 }
1744
1745 for (i = 0; i < single_dpm_table->count; i++) {
1746 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1747 clk_type,
1748 i,
1749 &clk);
1750 if (ret) {
1751 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1752 return ret;
1753 }
1754
1755 single_dpm_table->dpm_levels[i].value = clk;
1756 single_dpm_table->dpm_levels[i].enabled = true;
1757
1758 if (i == 0)
1759 single_dpm_table->min = clk;
1760 else if (i == single_dpm_table->count - 1)
1761 single_dpm_table->max = clk;
1762 }
1763
1764 return 0;
1765}
1766
1767int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1768 enum smu_clk_type clk_type,
1769 uint32_t *min_value,
1770 uint32_t *max_value)
1771{
1772 uint32_t level_count = 0;
1773 int ret = 0;
1774
1775 if (!min_value && !max_value)
1776 return -EINVAL;
1777
1778 if (min_value) {
1779 /* by default, level 0 clock value as min value */
1780 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1781 clk_type,
1782 0,
1783 min_value);
1784 if (ret)
1785 return ret;
1786 }
1787
1788 if (max_value) {
1789 ret = smu_v13_0_get_dpm_level_count(smu,
1790 clk_type,
1791 &level_count);
1792 if (ret)
1793 return ret;
1794
1795 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1796 clk_type,
1797 level_count - 1,
1798 max_value);
1799 if (ret)
1800 return ret;
1801 }
1802
1803 return ret;
1804}
1805
1806int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1807{
1808 struct amdgpu_device *adev = smu->adev;
1809
1810 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1811 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1812 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1813}
1814
1815int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1816{
1817 uint32_t width_level;
1818
1819 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1820 if (width_level > LINK_WIDTH_MAX)
1821 width_level = 0;
1822
1823 return link_width[width_level];
1824}
1825
1826int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1827{
1828 struct amdgpu_device *adev = smu->adev;
1829
1830 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1831 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1832 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1833}
1834
1835int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1836{
1837 uint32_t speed_level;
1838
1839 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1840 if (speed_level > LINK_SPEED_MAX)
1841 speed_level = 0;
1842
1843 return link_speed[speed_level];
1844}
1845
Linux 6.x block layer and io_uring tree(s)