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drm/amd/pm: correct the usage for 'supported' member of smu_feature structure
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu13 / smu_v13_0.c
CommitLineData
c05d1c40
KW		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/reboot.h>
27
28#define SMU_13_0_PARTIAL_PPTABLE
29#define SWSMU_CODE_LAYER_L3
30
31#include "amdgpu.h"
32#include "amdgpu_smu.h"
33#include "atomfirmware.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_atombios.h"
36#include "smu_v13_0.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "amdgpu_ras.h"
40#include "smu_cmn.h"
41
42#include "asic_reg/thm/thm_13_0_2_offset.h"
43#include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44#include "asic_reg/mp/mp_13_0_2_offset.h"
45#include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46#include "asic_reg/smuio/smuio_13_0_2_offset.h"
47#include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49/*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54#undef pr_err
55#undef pr_warn
56#undef pr_info
57#undef pr_debug
58
59MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60
61#define SMU13_VOLTAGE_SCALE 4
62
c05d1c40
KW		 63#define LINK_WIDTH_MAX 6
64#define LINK_SPEED_MAX 3
65
66#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
67#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
68#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
69#define smnPCIE_LC_SPEED_CNTL 0x11140290
70#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
71#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
72
dd67d7a6
AD		 73static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
74static const int link_speed[] = {25, 50, 80, 160};
c05d1c40
KW		 75
76int smu_v13_0_init_microcode(struct smu_context *smu)
77{
78 struct amdgpu_device *adev = smu->adev;
79 const char *chip_name;
80 char fw_name[30];
81 int err = 0;
82 const struct smc_firmware_header_v1_0 *hdr;
83 const struct common_firmware_header *header;
84 struct amdgpu_firmware_info *ucode = NULL;
85
4a1cac25
KW		 86 /* doesn't need to load smu firmware in IOV mode */
87 if (amdgpu_sriov_vf(adev))
88 return 0;
89
1d789535 90 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9 91 case IP_VERSION(13, 0, 2):
c05d1c40
KW		 92 chip_name = "aldebaran";
93 break;
94 default:
61b396b9 95 dev_err(adev->dev, "Unsupported IP version 0x%x\n",
1d789535 96 adev->ip_versions[MP1_HWIP][0]);
c05d1c40
KW		 97 return -EINVAL;
98 }
99
100 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
101
102 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
103 if (err)
104 goto out;
105 err = amdgpu_ucode_validate(adev->pm.fw);
106 if (err)
107 goto out;
108
109 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
110 amdgpu_ucode_print_smc_hdr(&hdr->header);
111 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
112
113 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
114 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
115 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
116 ucode->fw = adev->pm.fw;
117 header = (const struct common_firmware_header *)ucode->fw->data;
118 adev->firmware.fw_size +=
119 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
120 }
121
122out:
123 if (err) {
124 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
125 fw_name);
126 release_firmware(adev->pm.fw);
127 adev->pm.fw = NULL;
128 }
129 return err;
130}
131
132void smu_v13_0_fini_microcode(struct smu_context *smu)
133{
134 struct amdgpu_device *adev = smu->adev;
135
136 release_firmware(adev->pm.fw);
137 adev->pm.fw = NULL;
138 adev->pm.fw_version = 0;
139}
140
141int smu_v13_0_load_microcode(struct smu_context *smu)
142{
143#if 0
144 struct amdgpu_device *adev = smu->adev;
145 const uint32_t *src;
146 const struct smc_firmware_header_v1_0 *hdr;
147 uint32_t addr_start = MP1_SRAM;
148 uint32_t i;
149 uint32_t smc_fw_size;
150 uint32_t mp1_fw_flags;
151
152 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
153 src = (const uint32_t *)(adev->pm.fw->data +
154 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
155 smc_fw_size = hdr->header.ucode_size_bytes;
156
157 for (i = 1; i < smc_fw_size/4 - 1; i++) {
158 WREG32_PCIE(addr_start, src[i]);
159 addr_start += 4;
160 }
161
162 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
163 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
164 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
165 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
166
167 for (i = 0; i < adev->usec_timeout; i++) {
168 mp1_fw_flags = RREG32_PCIE(MP1_Public |
169 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
170 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
171 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
172 break;
173 udelay(1);
174 }
175
176 if (i == adev->usec_timeout)
177 return -ETIME;
178#endif
179 return 0;
180}
181
182int smu_v13_0_check_fw_status(struct smu_context *smu)
183{
184 struct amdgpu_device *adev = smu->adev;
185 uint32_t mp1_fw_flags;
186
187 mp1_fw_flags = RREG32_PCIE(MP1_Public |
188 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
189
190 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
191 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
192 return 0;
193
194 return -EIO;
195}
196
197int smu_v13_0_check_fw_version(struct smu_context *smu)
198{
6f072a84 199 struct amdgpu_device *adev = smu->adev;
c05d1c40 200 uint32_t if_version = 0xff, smu_version = 0xff;
82890466 201 uint8_t smu_program, smu_major, smu_minor, smu_debug;
c05d1c40
KW		 202 int ret = 0;
203
204 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
205 if (ret)
206 return ret;
207
82890466
ML		 208 smu_program = (smu_version >> 24) & 0xff;
209 smu_major = (smu_version >> 16) & 0xff;
c05d1c40
KW		 210 smu_minor = (smu_version >> 8) & 0xff;
211 smu_debug = (smu_version >> 0) & 0xff;
6f072a84
ML		 212 if (smu->is_apu)
213 adev->pm.fw_version = smu_version;
c05d1c40 214
9f952378 215 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9 216 case IP_VERSION(13, 0, 2):
c05d1c40
KW		 217 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
218 break;
61b396b9
AD		 219 case IP_VERSION(13, 0, 1):
220 case IP_VERSION(13, 0, 3):
21cf0293
XH		 221 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
222 break;
c05d1c40 223 default:
9f952378
ML		 224 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
225 adev->ip_versions[MP1_HWIP][0]);
c05d1c40
KW		 226 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
227 break;
228 }
229
0ff76b53
ML		 230 /* only for dGPU w/ SMU13*/
231 if (adev->pm.fw)
82890466
ML		 232 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
233 smu_program, smu_version, smu_major, smu_minor, smu_debug);
0ff76b53 234
c05d1c40
KW		 235 /*
236 * 1. if_version mismatch is not critical as our fw is designed
237 * to be backward compatible.
238 * 2. New fw usually brings some optimizations. But that's visible
239 * only on the paired driver.
240 * Considering above, we just leave user a warning message instead
241 * of halt driver loading.
242 */
243 if (if_version != smu->smc_driver_if_version) {
9f952378 244 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
82890466 245 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
c05d1c40 246 smu->smc_driver_if_version, if_version,
82890466 247 smu_program, smu_version, smu_major, smu_minor, smu_debug);
9f952378 248 dev_warn(adev->dev, "SMU driver if version not matched\n");
c05d1c40
KW		 249 }
250
251 return ret;
252}
253
254static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
255 uint32_t *size, uint32_t pptable_id)
256{
257 struct amdgpu_device *adev = smu->adev;
258 const struct smc_firmware_header_v2_1 *v2_1;
259 struct smc_soft_pptable_entry *entries;
260 uint32_t pptable_count = 0;
261 int i = 0;
262
263 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
264 entries = (struct smc_soft_pptable_entry *)
265 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
266 pptable_count = le32_to_cpu(v2_1->pptable_count);
267 for (i = 0; i < pptable_count; i++) {
268 if (le32_to_cpu(entries[i].id) == pptable_id) {
269 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
270 *size = le32_to_cpu(entries[i].ppt_size_bytes);
271 break;
272 }
273 }
274
275 if (i == pptable_count)
276 return -EINVAL;
277
278 return 0;
279}
280
4a1cac25 281static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
c05d1c40
KW		 282{
283 struct amdgpu_device *adev = smu->adev;
c05d1c40
KW		 284 uint16_t atom_table_size;
285 uint8_t frev, crev;
4a1cac25 286 int ret, index;
c05d1c40 287
4a1cac25
KW		 288 dev_info(adev->dev, "use vbios provided pptable\n");
289 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
290 powerplayinfo);
f1adbe03 291
4a1cac25
KW		 292 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
293 (uint8_t **)table);
294 if (ret)
295 return ret;
296
297 if (size)
298 *size = atom_table_size;
299
300 return 0;
301}
302
303static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
304 uint32_t pptable_id)
305{
306 const struct smc_firmware_header_v1_0 *hdr;
307 struct amdgpu_device *adev = smu->adev;
308 uint16_t version_major, version_minor;
309 int ret;
c05d1c40
KW		 310
311 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
4a1cac25
KW		 312 if (!hdr)
313 return -EINVAL;
314
315 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
316
c05d1c40
KW		 317 version_major = le16_to_cpu(hdr->header.header_version_major);
318 version_minor = le16_to_cpu(hdr->header.header_version_minor);
4a1cac25 319 if (version_major != 2) {
c94126c4 320 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
4a1cac25
KW		 321 version_major, version_minor);
322 return -EINVAL;
323 }
324
325 switch (version_minor) {
326 case 1:
327 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
328 break;
329 default:
330 ret = -EINVAL;
331 break;
332 }
333
334 return ret;
335}
336
337int smu_v13_0_setup_pptable(struct smu_context *smu)
338{
339 struct amdgpu_device *adev = smu->adev;
340 uint32_t size = 0, pptable_id = 0;
341 void *table;
342 int ret = 0;
c05d1c40 343
4a1cac25
KW		 344 /* override pptable_id from driver parameter */
345 if (amdgpu_smu_pptable_id >= 0) {
346 pptable_id = amdgpu_smu_pptable_id;
347 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
c05d1c40 348 } else {
4a1cac25 349 pptable_id = smu->smu_table.boot_values.pp_table_id;
c05d1c40
KW		 350 }
351
4a1cac25
KW		 352 /* force using vbios pptable in sriov mode */
353 if (amdgpu_sriov_vf(adev) || !pptable_id)
354 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
355 else
356 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
357
358 if (ret)
359 return ret;
360
c05d1c40
KW		 361 if (!smu->smu_table.power_play_table)
362 smu->smu_table.power_play_table = table;
363 if (!smu->smu_table.power_play_table_size)
364 smu->smu_table.power_play_table_size = size;
365
366 return 0;
367}
368
369int smu_v13_0_init_smc_tables(struct smu_context *smu)
370{
371 struct smu_table_context *smu_table = &smu->smu_table;
372 struct smu_table *tables = smu_table->tables;
373 int ret = 0;
374
375 smu_table->driver_pptable =
376 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
377 if (!smu_table->driver_pptable) {
378 ret = -ENOMEM;
379 goto err0_out;
380 }
381
382 smu_table->max_sustainable_clocks =
383 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
384 if (!smu_table->max_sustainable_clocks) {
385 ret = -ENOMEM;
386 goto err1_out;
387 }
388
389 /* Aldebaran does not support OVERDRIVE */
390 if (tables[SMU_TABLE_OVERDRIVE].size) {
391 smu_table->overdrive_table =
392 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
393 if (!smu_table->overdrive_table) {
394 ret = -ENOMEM;
395 goto err2_out;
396 }
397
398 smu_table->boot_overdrive_table =
399 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
400 if (!smu_table->boot_overdrive_table) {
401 ret = -ENOMEM;
402 goto err3_out;
403 }
404 }
405
406 return 0;
407
408err3_out:
409 kfree(smu_table->overdrive_table);
410err2_out:
411 kfree(smu_table->max_sustainable_clocks);
412err1_out:
413 kfree(smu_table->driver_pptable);
414err0_out:
415 return ret;
416}
417
418int smu_v13_0_fini_smc_tables(struct smu_context *smu)
419{
420 struct smu_table_context *smu_table = &smu->smu_table;
421 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
422
423 kfree(smu_table->gpu_metrics_table);
424 kfree(smu_table->boot_overdrive_table);
425 kfree(smu_table->overdrive_table);
426 kfree(smu_table->max_sustainable_clocks);
427 kfree(smu_table->driver_pptable);
428 smu_table->gpu_metrics_table = NULL;
429 smu_table->boot_overdrive_table = NULL;
430 smu_table->overdrive_table = NULL;
431 smu_table->max_sustainable_clocks = NULL;
432 smu_table->driver_pptable = NULL;
433 kfree(smu_table->hardcode_pptable);
434 smu_table->hardcode_pptable = NULL;
435
edd79420 436 kfree(smu_table->ecc_table);
c05d1c40
KW		 437 kfree(smu_table->metrics_table);
438 kfree(smu_table->watermarks_table);
edd79420 439 smu_table->ecc_table = NULL;
c05d1c40
KW		 440 smu_table->metrics_table = NULL;
441 smu_table->watermarks_table = NULL;
442 smu_table->metrics_time = 0;
443
444 kfree(smu_dpm->dpm_context);
445 kfree(smu_dpm->golden_dpm_context);
446 kfree(smu_dpm->dpm_current_power_state);
447 kfree(smu_dpm->dpm_request_power_state);
448 smu_dpm->dpm_context = NULL;
449 smu_dpm->golden_dpm_context = NULL;
450 smu_dpm->dpm_context_size = 0;
451 smu_dpm->dpm_current_power_state = NULL;
452 smu_dpm->dpm_request_power_state = NULL;
453
454 return 0;
455}
456
457int smu_v13_0_init_power(struct smu_context *smu)
458{
459 struct smu_power_context *smu_power = &smu->smu_power;
460
461 if (smu_power->power_context || smu_power->power_context_size != 0)
462 return -EINVAL;
463
464 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
465 GFP_KERNEL);
466 if (!smu_power->power_context)
467 return -ENOMEM;
468 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
469
470 return 0;
471}
472
473int smu_v13_0_fini_power(struct smu_context *smu)
474{
475 struct smu_power_context *smu_power = &smu->smu_power;
476
477 if (!smu_power->power_context || smu_power->power_context_size == 0)
478 return -EINVAL;
479
480 kfree(smu_power->power_context);
481 smu_power->power_context = NULL;
482 smu_power->power_context_size = 0;
483
484 return 0;
485}
486
487static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
488 uint8_t clk_id,
489 uint8_t syspll_id,
490 uint32_t *clk_freq)
491{
492 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
493 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
494 int ret, index;
495
496 input.clk_id = clk_id;
497 input.syspll_id = syspll_id;
498 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
499 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
500 getsmuclockinfo);
501
502 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
503 (uint32_t *)&input);
504 if (ret)
505 return -EINVAL;
506
507 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
508 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
509
510 return 0;
511}
512
513int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
514{
515 int ret, index;
516 uint16_t size;
517 uint8_t frev, crev;
518 struct atom_common_table_header *header;
3d01361c 519 struct atom_firmware_info_v3_4 *v_3_4;
c05d1c40
KW		 520 struct atom_firmware_info_v3_3 *v_3_3;
521 struct atom_firmware_info_v3_1 *v_3_1;
522
523 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
524 firmwareinfo);
525
526 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
527 (uint8_t **)&header);
528 if (ret)
529 return ret;
530
531 if (header->format_revision != 3) {
532 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
533 return -EINVAL;
534 }
535
536 switch (header->content_revision) {
537 case 0:
538 case 1:
539 case 2:
540 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
541 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
542 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
543 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
544 smu->smu_table.boot_values.socclk = 0;
545 smu->smu_table.boot_values.dcefclk = 0;
546 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
547 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
548 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
549 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
550 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
551 smu->smu_table.boot_values.pp_table_id = 0;
552 break;
553 case 3:
c05d1c40
KW		 554 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
555 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
556 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
557 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
558 smu->smu_table.boot_values.socclk = 0;
559 smu->smu_table.boot_values.dcefclk = 0;
560 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
561 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
562 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
563 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
564 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
565 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
e5a83213 566 break;
3d01361c
FX		 567 case 4:
568 default:
569 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
570 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
571 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
572 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
573 smu->smu_table.boot_values.socclk = 0;
574 smu->smu_table.boot_values.dcefclk = 0;
575 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
576 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
577 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
578 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
579 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
580 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
e5a83213 581 break;
c05d1c40
KW		 582 }
583
584 smu->smu_table.boot_values.format_revision = header->format_revision;
585 smu->smu_table.boot_values.content_revision = header->content_revision;
586
587 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
588 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
589 (uint8_t)0,
590 &smu->smu_table.boot_values.socclk);
591
592 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
593 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
594 (uint8_t)0,
595 &smu->smu_table.boot_values.dcefclk);
596
597 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
598 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
599 (uint8_t)0,
600 &smu->smu_table.boot_values.eclk);
601
602 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
603 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
604 (uint8_t)0,
605 &smu->smu_table.boot_values.vclk);
606
607 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
608 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
609 (uint8_t)0,
610 &smu->smu_table.boot_values.dclk);
611
612 if ((smu->smu_table.boot_values.format_revision == 3) &&
613 (smu->smu_table.boot_values.content_revision >= 2))
614 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
615 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
616 (uint8_t)SMU11_SYSPLL1_2_ID,
617 &smu->smu_table.boot_values.fclk);
618
619 return 0;
620}
621
f1adbe03 622
c05d1c40
KW		 623int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
624{
625 struct smu_table_context *smu_table = &smu->smu_table;
626 struct smu_table *memory_pool = &smu_table->memory_pool;
627 int ret = 0;
628 uint64_t address;
629 uint32_t address_low, address_high;
630
631 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
632 return ret;
633
c05d1c40
KW		 634 address = memory_pool->mc_address;
635 address_high = (uint32_t)upper_32_bits(address);
636 address_low = (uint32_t)lower_32_bits(address);
637
638 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
639 address_high, NULL);
640 if (ret)
641 return ret;
642 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
643 address_low, NULL);
644 if (ret)
645 return ret;
646 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
647 (uint32_t)memory_pool->size, NULL);
648 if (ret)
649 return ret;
650
651 return ret;
652}
653
654int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
655{
656 int ret;
657
658 ret = smu_cmn_send_smc_msg_with_param(smu,
659 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
660 if (ret)
661 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
662
663 return ret;
664}
665
666int smu_v13_0_set_driver_table_location(struct smu_context *smu)
667{
668 struct smu_table *driver_table = &smu->smu_table.driver_table;
669 int ret = 0;
670
671 if (driver_table->mc_address) {
672 ret = smu_cmn_send_smc_msg_with_param(smu,
673 SMU_MSG_SetDriverDramAddrHigh,
674 upper_32_bits(driver_table->mc_address),
675 NULL);
676 if (!ret)
677 ret = smu_cmn_send_smc_msg_with_param(smu,
678 SMU_MSG_SetDriverDramAddrLow,
679 lower_32_bits(driver_table->mc_address),
680 NULL);
681 }
682
683 return ret;
684}
685
686int smu_v13_0_set_tool_table_location(struct smu_context *smu)
687{
688 int ret = 0;
689 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
690
691 if (tool_table->mc_address) {
692 ret = smu_cmn_send_smc_msg_with_param(smu,
693 SMU_MSG_SetToolsDramAddrHigh,
694 upper_32_bits(tool_table->mc_address),
695 NULL);
696 if (!ret)
697 ret = smu_cmn_send_smc_msg_with_param(smu,
698 SMU_MSG_SetToolsDramAddrLow,
699 lower_32_bits(tool_table->mc_address),
700 NULL);
701 }
702
703 return ret;
704}
705
706int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
707{
708 int ret = 0;
709
710 if (!smu->pm_enabled)
711 return ret;
712
713 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
714
715 return ret;
716}
717
718
719int smu_v13_0_set_allowed_mask(struct smu_context *smu)
720{
721 struct smu_feature *feature = &smu->smu_feature;
722 int ret = 0;
723 uint32_t feature_mask[2];
724
1f2cf08a
EQ		 725 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
726 feature->feature_num < 64)
727 return -EINVAL;
c05d1c40
KW		 728
729 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
730
731 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
732 feature_mask[1], NULL);
733 if (ret)
1f2cf08a 734 return ret;
c05d1c40 735
1f2cf08a
EQ		 736 return smu_cmn_send_smc_msg_with_param(smu,
737 SMU_MSG_SetAllowedFeaturesMaskLow,
738 feature_mask[0],
739 NULL);
c05d1c40
KW		 740}
741
21cf0293
XH		 742int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
743{
744 int ret = 0;
745 struct amdgpu_device *adev = smu->adev;
746
1d789535 747 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9
AD		 748 case IP_VERSION(13, 0, 1):
749 case IP_VERSION(13, 0, 3):
21cf0293
XH		 750 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
751 return 0;
752 if (enable)
753 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
754 else
755 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
756 break;
757 default:
758 break;
759 }
760
761 return ret;
762}
763
c05d1c40
KW		 764int smu_v13_0_system_features_control(struct smu_context *smu,
765 bool en)
766{
767 struct smu_feature *feature = &smu->smu_feature;
2d282665 768 uint64_t feature_mask;
c05d1c40
KW		 769 int ret = 0;
770
771 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
772 SMU_MSG_DisableAllSmuFeatures), NULL);
773 if (ret)
774 return ret;
775
776 bitmap_zero(feature->enabled, feature->feature_num);
c05d1c40
KW		 777
778 if (en) {
2d282665 779 ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
c05d1c40
KW		 780 if (ret)
781 return ret;
782
783 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
784 feature->feature_num);
c05d1c40
KW		 785 }
786
787 return ret;
788}
789
790int smu_v13_0_notify_display_change(struct smu_context *smu)
791{
792 int ret = 0;
793
794 if (!smu->pm_enabled)
795 return ret;
796
797 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
798 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
799 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
800
801 return ret;
802}
803
804 static int
805smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
806 enum smu_clk_type clock_select)
807{
808 int ret = 0;
809 int clk_id;
810
811 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
812 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
813 return 0;
814
815 clk_id = smu_cmn_to_asic_specific_index(smu,
816 CMN2ASIC_MAPPING_CLK,
817 clock_select);
818 if (clk_id < 0)
819 return -EINVAL;
820
821 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
822 clk_id << 16, clock);
823 if (ret) {
824 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
825 return ret;
826 }
827
828 if (*clock != 0)
829 return 0;
830
831 /* if DC limit is zero, return AC limit */
832 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
833 clk_id << 16, clock);
834 if (ret) {
835 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
836 return ret;
837 }
838
839 return 0;
840}
841
842int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
843{
844 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
845 smu->smu_table.max_sustainable_clocks;
846 int ret = 0;
847
848 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
849 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
850 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
851 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
852 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
853 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
854
855 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
856 ret = smu_v13_0_get_max_sustainable_clock(smu,
857 &(max_sustainable_clocks->uclock),
858 SMU_UCLK);
859 if (ret) {
860 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
861 __func__);
862 return ret;
863 }
864 }
865
866 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
867 ret = smu_v13_0_get_max_sustainable_clock(smu,
868 &(max_sustainable_clocks->soc_clock),
869 SMU_SOCCLK);
870 if (ret) {
871 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
872 __func__);
873 return ret;
874 }
875 }
876
877 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
878 ret = smu_v13_0_get_max_sustainable_clock(smu,
879 &(max_sustainable_clocks->dcef_clock),
880 SMU_DCEFCLK);
881 if (ret) {
882 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
883 __func__);
884 return ret;
885 }
886
887 ret = smu_v13_0_get_max_sustainable_clock(smu,
888 &(max_sustainable_clocks->display_clock),
889 SMU_DISPCLK);
890 if (ret) {
891 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
892 __func__);
893 return ret;
894 }
895 ret = smu_v13_0_get_max_sustainable_clock(smu,
896 &(max_sustainable_clocks->phy_clock),
897 SMU_PHYCLK);
898 if (ret) {
899 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
900 __func__);
901 return ret;
902 }
903 ret = smu_v13_0_get_max_sustainable_clock(smu,
904 &(max_sustainable_clocks->pixel_clock),
905 SMU_PIXCLK);
906 if (ret) {
907 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
908 __func__);
909 return ret;
910 }
911 }
912
913 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
914 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
915
916 return 0;
917}
918
919int smu_v13_0_get_current_power_limit(struct smu_context *smu,
920 uint32_t *power_limit)
921{
922 int power_src;
923 int ret = 0;
924
925 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
926 return -EINVAL;
927
928 power_src = smu_cmn_to_asic_specific_index(smu,
929 CMN2ASIC_MAPPING_PWR,
930 smu->adev->pm.ac_power ?
931 SMU_POWER_SOURCE_AC :
932 SMU_POWER_SOURCE_DC);
933 if (power_src < 0)
934 return -EINVAL;
935
936 ret = smu_cmn_send_smc_msg_with_param(smu,
937 SMU_MSG_GetPptLimit,
938 power_src << 16,
939 power_limit);
940 if (ret)
941 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
942
943 return ret;
944}
945
2d1ac1cb
DP		 946int smu_v13_0_set_power_limit(struct smu_context *smu,
947 enum smu_ppt_limit_type limit_type,
948 uint32_t limit)
c05d1c40
KW		 949{
950 int ret = 0;
951
2d1ac1cb
DP		 952 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
953 return -EINVAL;
954
c05d1c40
KW		 955 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
956 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
957 return -EOPNOTSUPP;
958 }
959
2d1ac1cb 960 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
c05d1c40
KW		 961 if (ret) {
962 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
963 return ret;
964 }
965
2d1ac1cb 966 smu->current_power_limit = limit;
c05d1c40
KW		 967
968 return 0;
969}
970
971int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
972{
973 if (smu->smu_table.thermal_controller_type)
974 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
975
976 return 0;
977}
978
979int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
980{
981 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
982}
983
984static uint16_t convert_to_vddc(uint8_t vid)
985{
986 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
987}
988
989int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
990{
991 struct amdgpu_device *adev = smu->adev;
992 uint32_t vdd = 0, val_vid = 0;
993
994 if (!value)
995 return -EINVAL;
996 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
997 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
998 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
999
1000 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1001
1002 *value = vdd;
1003
1004 return 0;
1005
1006}
1007
1008int
1009smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1010 struct pp_display_clock_request
1011 *clock_req)
1012{
1013 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1014 int ret = 0;
1015 enum smu_clk_type clk_select = 0;
1016 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1017
1018 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1019 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1020 switch (clk_type) {
1021 case amd_pp_dcef_clock:
1022 clk_select = SMU_DCEFCLK;
1023 break;
1024 case amd_pp_disp_clock:
1025 clk_select = SMU_DISPCLK;
1026 break;
1027 case amd_pp_pixel_clock:
1028 clk_select = SMU_PIXCLK;
1029 break;
1030 case amd_pp_phy_clock:
1031 clk_select = SMU_PHYCLK;
1032 break;
1033 case amd_pp_mem_clock:
1034 clk_select = SMU_UCLK;
1035 break;
1036 default:
1037 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1038 ret = -EINVAL;
1039 break;
1040 }
1041
1042 if (ret)
1043 goto failed;
1044
1045 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1046 return 0;
1047
1048 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1049
1050 if(clk_select == SMU_UCLK)
1051 smu->hard_min_uclk_req_from_dal = clk_freq;
1052 }
1053
1054failed:
1055 return ret;
1056}
1057
1058uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1059{
1060 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1061 return AMD_FAN_CTRL_MANUAL;
1062 else
1063 return AMD_FAN_CTRL_AUTO;
1064}
1065
1066 static int
1067smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1068{
1069 int ret = 0;
1070
1071 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1072 return 0;
1073
1074 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1075 if (ret)
1076 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1077 __func__, (auto_fan_control ? "Start" : "Stop"));
1078
1079 return ret;
1080}
1081
1082 static int
1083smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1084{
1085 struct amdgpu_device *adev = smu->adev;
1086
1087 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1088 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1089 CG_FDO_CTRL2, TMIN, 0));
1090 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1091 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1092 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1093
1094 return 0;
1095}
1096
1097 int
1098smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1099{
1100 struct amdgpu_device *adev = smu->adev;
1101 uint32_t duty100, duty;
1102 uint64_t tmp64;
1103
1104 if (speed > 100)
1105 speed = 100;
1106
1107 if (smu_v13_0_auto_fan_control(smu, 0))
1108 return -EINVAL;
1109
1110 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1111 CG_FDO_CTRL1, FMAX_DUTY100);
1112 if (!duty100)
1113 return -EINVAL;
1114
1115 tmp64 = (uint64_t)speed * duty100;
1116 do_div(tmp64, 100);
1117 duty = (uint32_t)tmp64;
1118
1119 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1120 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1121 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1122
1123 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1124}
1125
1126 int
1127smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1128 uint32_t mode)
1129{
1130 int ret = 0;
1131
1132 switch (mode) {
1133 case AMD_FAN_CTRL_NONE:
1134 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1135 break;
1136 case AMD_FAN_CTRL_MANUAL:
1137 ret = smu_v13_0_auto_fan_control(smu, 0);
1138 break;
1139 case AMD_FAN_CTRL_AUTO:
1140 ret = smu_v13_0_auto_fan_control(smu, 1);
1141 break;
1142 default:
1143 break;
1144 }
1145
1146 if (ret) {
1147 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1148 return -EINVAL;
1149 }
1150
1151 return ret;
1152}
1153
1154int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1155 uint32_t speed)
1156{
1157 struct amdgpu_device *adev = smu->adev;
1158 int ret;
1159 uint32_t tach_period, crystal_clock_freq;
1160
1161 if (!speed)
1162 return -EINVAL;
1163
1164 ret = smu_v13_0_auto_fan_control(smu, 0);
1165 if (ret)
1166 return ret;
1167
1168 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1169 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1170 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1171 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1172 CG_TACH_CTRL, TARGET_PERIOD,
1173 tach_period));
1174
1175 ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1176
1177 return ret;
1178}
1179
1180int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1181 uint32_t pstate)
1182{
1183 int ret = 0;
1184 ret = smu_cmn_send_smc_msg_with_param(smu,
1185 SMU_MSG_SetXgmiMode,
1186 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1187 NULL);
1188 return ret;
1189}
1190
1191static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1192 struct amdgpu_irq_src *source,
1193 unsigned tyep,
1194 enum amdgpu_interrupt_state state)
1195{
ebfc2533 1196 struct smu_context *smu = adev->powerplay.pp_handle;
c05d1c40
KW		 1197 uint32_t low, high;
1198 uint32_t val = 0;
1199
1200 switch (state) {
1201 case AMDGPU_IRQ_STATE_DISABLE:
1202 /* For THM irqs */
1203 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1204 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1205 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1206 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1207
1208 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1209
1210 /* For MP1 SW irqs */
1211 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1212 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1213 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1214
1215 break;
1216 case AMDGPU_IRQ_STATE_ENABLE:
1217 /* For THM irqs */
1218 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1219 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1220 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1221 smu->thermal_range.software_shutdown_temp);
1222
1223 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1224 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1225 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1226 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1227 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1228 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1229 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1230 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1231 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1232
1233 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1234 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1235 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1236 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1237
1238 /* For MP1 SW irqs */
1239 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1240 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1241 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1242 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1243
1244 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1245 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1246 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1247
1248 break;
1249 default:
1250 break;
1251 }
1252
1253 return 0;
1254}
1255
1256static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1257{
1258 return smu_cmn_send_smc_msg(smu,
1259 SMU_MSG_ReenableAcDcInterrupt,
1260 NULL);
1261}
1262
1263#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1264#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1265#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1266
1267static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1268 struct amdgpu_irq_src *source,
1269 struct amdgpu_iv_entry *entry)
1270{
ebfc2533 1271 struct smu_context *smu = adev->powerplay.pp_handle;
c05d1c40
KW		 1272 uint32_t client_id = entry->client_id;
1273 uint32_t src_id = entry->src_id;
1274 /*
1275 * ctxid is used to distinguish different
1276 * events for SMCToHost interrupt.
1277 */
1278 uint32_t ctxid = entry->src_data[0];
1279 uint32_t data;
1280
1281 if (client_id == SOC15_IH_CLIENTID_THM) {
1282 switch (src_id) {
1283 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1284 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1285 /*
1286 * SW CTF just occurred.
1287 * Try to do a graceful shutdown to prevent further damage.
1288 */
1289 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1290 orderly_poweroff(true);
1291 break;
1292 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1293 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1294 break;
1295 default:
1296 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1297 src_id);
1298 break;
1299 }
1300 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1301 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1302 /*
1303 * HW CTF just occurred. Shutdown to prevent further damage.
1304 */
1305 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1306 orderly_poweroff(true);
1307 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1308 if (src_id == 0xfe) {
1309 /* ACK SMUToHost interrupt */
1310 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1311 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1312 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1313
1314 switch (ctxid) {
1315 case 0x3:
1316 dev_dbg(adev->dev, "Switched to AC mode!\n");
ebfc2533 1317 smu_v13_0_ack_ac_dc_interrupt(smu);
c05d1c40
KW		 1318 break;
1319 case 0x4:
1320 dev_dbg(adev->dev, "Switched to DC mode!\n");
ebfc2533 1321 smu_v13_0_ack_ac_dc_interrupt(smu);
c05d1c40
KW		 1322 break;
1323 case 0x7:
1324 /*
1325 * Increment the throttle interrupt counter
1326 */
1327 atomic64_inc(&smu->throttle_int_counter);
1328
1329 if (!atomic_read(&adev->throttling_logging_enabled))
1330 return 0;
1331
1332 if (__ratelimit(&adev->throttling_logging_rs))
1333 schedule_work(&smu->throttling_logging_work);
1334
1335 break;
1336 }
1337 }
1338 }
1339
1340 return 0;
1341}
1342
1343static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1344{
1345 .set = smu_v13_0_set_irq_state,
1346 .process = smu_v13_0_irq_process,
1347};
1348
1349int smu_v13_0_register_irq_handler(struct smu_context *smu)
1350{
1351 struct amdgpu_device *adev = smu->adev;
1352 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1353 int ret = 0;
1354
1355 irq_src->num_types = 1;
1356 irq_src->funcs = &smu_v13_0_irq_funcs;
1357
1358 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1359 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1360 irq_src);
1361 if (ret)
1362 return ret;
1363
1364 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1365 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1366 irq_src);
1367 if (ret)
1368 return ret;
1369
1370 /* Register CTF(GPIO_19) interrupt */
1371 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1372 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1373 irq_src);
1374 if (ret)
1375 return ret;
1376
1377 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1378 0xfe,
1379 irq_src);
1380 if (ret)
1381 return ret;
1382
1383 return ret;
1384}
1385
1386int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1387 struct pp_smu_nv_clock_table *max_clocks)
1388{
1389 struct smu_table_context *table_context = &smu->smu_table;
1390 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1391
1392 if (!max_clocks || !table_context->max_sustainable_clocks)
1393 return -EINVAL;
1394
1395 sustainable_clocks = table_context->max_sustainable_clocks;
1396
1397 max_clocks->dcfClockInKhz =
1398 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1399 max_clocks->displayClockInKhz =
1400 (unsigned int) sustainable_clocks->display_clock * 1000;
1401 max_clocks->phyClockInKhz =
1402 (unsigned int) sustainable_clocks->phy_clock * 1000;
1403 max_clocks->pixelClockInKhz =
1404 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1405 max_clocks->uClockInKhz =
1406 (unsigned int) sustainable_clocks->uclock * 1000;
1407 max_clocks->socClockInKhz =
1408 (unsigned int) sustainable_clocks->soc_clock * 1000;
1409 max_clocks->dscClockInKhz = 0;
1410 max_clocks->dppClockInKhz = 0;
1411 max_clocks->fabricClockInKhz = 0;
1412
1413 return 0;
1414}
1415
1416int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1417{
1418 int ret = 0;
1419
1420 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1421
1422 return ret;
1423}
1424
c941e9fe
LL		 1425static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1426 uint64_t event_arg)
1427{
1428 int ret = 0;
1429
1430 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1431 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1432
1433 return ret;
1434}
1435
1436int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1437 uint64_t event_arg)
1438{
1439 int ret = -EINVAL;
1440
1441 switch (event) {
1442 case SMU_EVENT_RESET_COMPLETE:
1443 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1444 break;
1445 default:
1446 break;
1447 }
1448
1449 return ret;
1450}
1451
5c03e584
FX		 1452int smu_v13_0_mode2_reset(struct smu_context *smu)
1453{
e42569d0
LL		 1454 int ret;
1455
1456 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1457 SMU_RESET_MODE_2, NULL);
1458 /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
5c03e584
FX		 1459 if (!ret)
1460 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
e42569d0 1461
5c03e584
FX		 1462 return ret;
1463}
1464
c05d1c40
KW		 1465int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1466 uint32_t *min, uint32_t *max)
1467{
1468 int ret = 0, clk_id = 0;
1469 uint32_t param = 0;
1470 uint32_t clock_limit;
1471
1472 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1473 switch (clk_type) {
1474 case SMU_MCLK:
1475 case SMU_UCLK:
1476 clock_limit = smu->smu_table.boot_values.uclk;
1477 break;
1478 case SMU_GFXCLK:
1479 case SMU_SCLK:
1480 clock_limit = smu->smu_table.boot_values.gfxclk;
1481 break;
1482 case SMU_SOCCLK:
1483 clock_limit = smu->smu_table.boot_values.socclk;
1484 break;
1485 default:
1486 clock_limit = 0;
1487 break;
1488 }
1489
1490 /* clock in Mhz unit */
1491 if (min)
1492 *min = clock_limit / 100;
1493 if (max)
1494 *max = clock_limit / 100;
1495
1496 return 0;
1497 }
1498
1499 clk_id = smu_cmn_to_asic_specific_index(smu,
1500 CMN2ASIC_MAPPING_CLK,
1501 clk_type);
1502 if (clk_id < 0) {
1503 ret = -EINVAL;
1504 goto failed;
1505 }
1506 param = (clk_id & 0xffff) << 16;
1507
1508 if (max) {
1509 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1510 if (ret)
1511 goto failed;
1512 }
1513
1514 if (min) {
1515 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1516 if (ret)
1517 goto failed;
1518 }
1519
1520failed:
1521 return ret;
1522}
1523
1524int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1525 enum smu_clk_type clk_type,
1526 uint32_t min,
1527 uint32_t max)
1528{
c05d1c40
KW		 1529 int ret = 0, clk_id = 0;
1530 uint32_t param;
1531
1532 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1533 return 0;
1534
1535 clk_id = smu_cmn_to_asic_specific_index(smu,
1536 CMN2ASIC_MAPPING_CLK,
1537 clk_type);
1538 if (clk_id < 0)
1539 return clk_id;
1540
c05d1c40
KW		 1541 if (max > 0) {
1542 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1543 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1544 param, NULL);
1545 if (ret)
1546 goto out;
1547 }
1548
1549 if (min > 0) {
1550 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1551 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1552 param, NULL);
1553 if (ret)
1554 goto out;
1555 }
1556
1557out:
c05d1c40
KW		 1558 return ret;
1559}
1560
1561int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1562 enum smu_clk_type clk_type,
1563 uint32_t min,
1564 uint32_t max)
1565{
1566 int ret = 0, clk_id = 0;
1567 uint32_t param;
1568
1569 if (min <= 0 && max <= 0)
1570 return -EINVAL;
1571
1572 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1573 return 0;
1574
1575 clk_id = smu_cmn_to_asic_specific_index(smu,
1576 CMN2ASIC_MAPPING_CLK,
1577 clk_type);
1578 if (clk_id < 0)
1579 return clk_id;
1580
1581 if (max > 0) {
1582 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1583 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1584 param, NULL);
1585 if (ret)
1586 return ret;
1587 }
1588
1589 if (min > 0) {
1590 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1591 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1592 param, NULL);
1593 if (ret)
1594 return ret;
1595 }
1596
1597 return ret;
1598}
1599
1600int smu_v13_0_set_performance_level(struct smu_context *smu,
1601 enum amd_dpm_forced_level level)
1602{
1603 struct smu_13_0_dpm_context *dpm_context =
1604 smu->smu_dpm.dpm_context;
1605 struct smu_13_0_dpm_table *gfx_table =
1606 &dpm_context->dpm_tables.gfx_table;
1607 struct smu_13_0_dpm_table *mem_table =
1608 &dpm_context->dpm_tables.uclk_table;
1609 struct smu_13_0_dpm_table *soc_table =
1610 &dpm_context->dpm_tables.soc_table;
1611 struct smu_umd_pstate_table *pstate_table =
1612 &smu->pstate_table;
1613 struct amdgpu_device *adev = smu->adev;
1614 uint32_t sclk_min = 0, sclk_max = 0;
1615 uint32_t mclk_min = 0, mclk_max = 0;
1616 uint32_t socclk_min = 0, socclk_max = 0;
1617 int ret = 0;
1618
1619 switch (level) {
1620 case AMD_DPM_FORCED_LEVEL_HIGH:
1621 sclk_min = sclk_max = gfx_table->max;
1622 mclk_min = mclk_max = mem_table->max;
1623 socclk_min = socclk_max = soc_table->max;
1624 break;
1625 case AMD_DPM_FORCED_LEVEL_LOW:
1626 sclk_min = sclk_max = gfx_table->min;
1627 mclk_min = mclk_max = mem_table->min;
1628 socclk_min = socclk_max = soc_table->min;
1629 break;
1630 case AMD_DPM_FORCED_LEVEL_AUTO:
1631 sclk_min = gfx_table->min;
1632 sclk_max = gfx_table->max;
1633 mclk_min = mem_table->min;
1634 mclk_max = mem_table->max;
1635 socclk_min = soc_table->min;
1636 socclk_max = soc_table->max;
1637 break;
1638 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1639 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1640 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1641 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1642 break;
1643 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1644 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1645 break;
1646 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1647 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1648 break;
1649 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1650 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1651 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1652 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1653 break;
1654 case AMD_DPM_FORCED_LEVEL_MANUAL:
1655 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1656 return 0;
1657 default:
1658 dev_err(adev->dev, "Invalid performance level %d\n", level);
1659 return -EINVAL;
1660 }
1661
1662 mclk_min = mclk_max = 0;
1663 socclk_min = socclk_max = 0;
1664
1665 if (sclk_min && sclk_max) {
1666 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1667 SMU_GFXCLK,
1668 sclk_min,
1669 sclk_max);
1670 if (ret)
1671 return ret;
e943dd88
LL		 1672
1673 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1674 pstate_table->gfxclk_pstate.curr.max = sclk_max;
c05d1c40
KW		 1675 }
1676
1677 if (mclk_min && mclk_max) {
1678 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1679 SMU_MCLK,
1680 mclk_min,
1681 mclk_max);
1682 if (ret)
1683 return ret;
e943dd88
LL		 1684
1685 pstate_table->uclk_pstate.curr.min = mclk_min;
1686 pstate_table->uclk_pstate.curr.max = mclk_max;
c05d1c40
KW		 1687 }
1688
1689 if (socclk_min && socclk_max) {
1690 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1691 SMU_SOCCLK,
1692 socclk_min,
1693 socclk_max);
1694 if (ret)
1695 return ret;
e943dd88
LL		 1696
1697 pstate_table->socclk_pstate.curr.min = socclk_min;
1698 pstate_table->socclk_pstate.curr.max = socclk_max;
c05d1c40
KW		 1699 }
1700
1701 return ret;
1702}
1703
1704int smu_v13_0_set_power_source(struct smu_context *smu,
1705 enum smu_power_src_type power_src)
1706{
1707 int pwr_source;
1708
1709 pwr_source = smu_cmn_to_asic_specific_index(smu,
1710 CMN2ASIC_MAPPING_PWR,
1711 (uint32_t)power_src);
1712 if (pwr_source < 0)
1713 return -EINVAL;
1714
1715 return smu_cmn_send_smc_msg_with_param(smu,
1716 SMU_MSG_NotifyPowerSource,
1717 pwr_source,
1718 NULL);
1719}
1720
1721int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1722 enum smu_clk_type clk_type,
1723 uint16_t level,
1724 uint32_t *value)
1725{
1726 int ret = 0, clk_id = 0;
1727 uint32_t param;
1728
1729 if (!value)
1730 return -EINVAL;
1731
1732 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1733 return 0;
1734
1735 clk_id = smu_cmn_to_asic_specific_index(smu,
1736 CMN2ASIC_MAPPING_CLK,
1737 clk_type);
1738 if (clk_id < 0)
1739 return clk_id;
1740
1741 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1742
1743 ret = smu_cmn_send_smc_msg_with_param(smu,
1744 SMU_MSG_GetDpmFreqByIndex,
1745 param,
1746 value);
1747 if (ret)
1748 return ret;
1749
1750 /*
1751 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1752 * now, we un-support it
1753 */
1754 *value = *value & 0x7fffffff;
1755
1756 return ret;
1757}
1758
1759int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1760 enum smu_clk_type clk_type,
1761 uint32_t *value)
1762{
f41f8e08
LL		 1763 int ret;
1764
1765 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1766 /* FW returns 0 based max level, increment by one */
1767 if (!ret && value)
1768 ++(*value);
1769
1770 return ret;
c05d1c40
KW		 1771}
1772
1773int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1774 enum smu_clk_type clk_type,
1775 struct smu_13_0_dpm_table *single_dpm_table)
1776{
1777 int ret = 0;
1778 uint32_t clk;
1779 int i;
1780
1781 ret = smu_v13_0_get_dpm_level_count(smu,
1782 clk_type,
1783 &single_dpm_table->count);
1784 if (ret) {
1785 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1786 return ret;
1787 }
1788
1789 for (i = 0; i < single_dpm_table->count; i++) {
1790 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1791 clk_type,
1792 i,
1793 &clk);
1794 if (ret) {
1795 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1796 return ret;
1797 }
1798
1799 single_dpm_table->dpm_levels[i].value = clk;
1800 single_dpm_table->dpm_levels[i].enabled = true;
1801
1802 if (i == 0)
1803 single_dpm_table->min = clk;
1804 else if (i == single_dpm_table->count - 1)
1805 single_dpm_table->max = clk;
1806 }
1807
1808 return 0;
1809}
1810
1811int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1812 enum smu_clk_type clk_type,
1813 uint32_t *min_value,
1814 uint32_t *max_value)
1815{
1816 uint32_t level_count = 0;
1817 int ret = 0;
1818
1819 if (!min_value && !max_value)
1820 return -EINVAL;
1821
1822 if (min_value) {
1823 /* by default, level 0 clock value as min value */
1824 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1825 clk_type,
1826 0,
1827 min_value);
1828 if (ret)
1829 return ret;
1830 }
1831
1832 if (max_value) {
1833 ret = smu_v13_0_get_dpm_level_count(smu,
1834 clk_type,
1835 &level_count);
1836 if (ret)
1837 return ret;
1838
1839 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1840 clk_type,
1841 level_count - 1,
1842 max_value);
1843 if (ret)
1844 return ret;
1845 }
1846
1847 return ret;
1848}
1849
1850int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1851{
1852 struct amdgpu_device *adev = smu->adev;
1853
1854 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1855 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1856 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1857}
1858
1859int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1860{
1861 uint32_t width_level;
1862
1863 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1864 if (width_level > LINK_WIDTH_MAX)
1865 width_level = 0;
1866
1867 return link_width[width_level];
1868}
1869
1870int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1871{
1872 struct amdgpu_device *adev = smu->adev;
1873
1874 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1875 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1876 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1877}
1878
1879int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1880{
1881 uint32_t speed_level;
1882
1883 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1884 if (speed_level > LINK_SPEED_MAX)
1885 speed_level = 0;
1886
1887 return link_speed[speed_level];
1888}
1889
Linux 6.x block layer and io_uring tree(s)