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drm/amdgpu: avoid to perform undesired clockgating operation
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu13 / smu_v13_0.c
CommitLineData
c05d1c40
KW		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/reboot.h>
27
28#define SMU_13_0_PARTIAL_PPTABLE
29#define SWSMU_CODE_LAYER_L3
30
31#include "amdgpu.h"
32#include "amdgpu_smu.h"
33#include "atomfirmware.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_atombios.h"
36#include "smu_v13_0.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "amdgpu_ras.h"
40#include "smu_cmn.h"
41
42#include "asic_reg/thm/thm_13_0_2_offset.h"
43#include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44#include "asic_reg/mp/mp_13_0_2_offset.h"
45#include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46#include "asic_reg/smuio/smuio_13_0_2_offset.h"
47#include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49/*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54#undef pr_err
55#undef pr_warn
56#undef pr_info
57#undef pr_debug
58
59MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
276c03a0 60MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
0c2a2d1c 61MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
c05d1c40 62
da1db031
AD		 63#define mmMP1_SMN_C2PMSG_66 0x0282
64#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
65
66#define mmMP1_SMN_C2PMSG_82 0x0292
67#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
68
69#define mmMP1_SMN_C2PMSG_90 0x029a
70#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
71
c05d1c40
KW		 72#define SMU13_VOLTAGE_SCALE 4
73
c05d1c40
KW		 74#define LINK_WIDTH_MAX 6
75#define LINK_SPEED_MAX 3
76
77#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
78#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
79#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
80#define smnPCIE_LC_SPEED_CNTL 0x11140290
81#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
82#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
83
dd67d7a6
AD		 84static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
85static const int link_speed[] = {25, 50, 80, 160};
c05d1c40 86
276c03a0
EQ		 87static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
88 uint32_t pptable_id);
89
c05d1c40
KW		 90int smu_v13_0_init_microcode(struct smu_context *smu)
91{
92 struct amdgpu_device *adev = smu->adev;
93 const char *chip_name;
94 char fw_name[30];
276c03a0 95 char ucode_prefix[30];
c05d1c40
KW		 96 int err = 0;
97 const struct smc_firmware_header_v1_0 *hdr;
98 const struct common_firmware_header *header;
99 struct amdgpu_firmware_info *ucode = NULL;
100
4a1cac25
KW		 101 /* doesn't need to load smu firmware in IOV mode */
102 if (amdgpu_sriov_vf(adev))
103 return 0;
104
1d789535 105 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9 106 case IP_VERSION(13, 0, 2):
276c03a0 107 chip_name = "aldebaran_smc";
c05d1c40
KW		 108 break;
109 default:
276c03a0
EQ		 110 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
111 chip_name = ucode_prefix;
c05d1c40
KW		 112 }
113
276c03a0 114 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
c05d1c40
KW		 115
116 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
117 if (err)
118 goto out;
119 err = amdgpu_ucode_validate(adev->pm.fw);
120 if (err)
121 goto out;
122
123 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
124 amdgpu_ucode_print_smc_hdr(&hdr->header);
125 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
126
127 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
128 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
129 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
130 ucode->fw = adev->pm.fw;
131 header = (const struct common_firmware_header *)ucode->fw->data;
132 adev->firmware.fw_size +=
133 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
134 }
135
136out:
137 if (err) {
138 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
139 fw_name);
140 release_firmware(adev->pm.fw);
141 adev->pm.fw = NULL;
142 }
143 return err;
144}
145
146void smu_v13_0_fini_microcode(struct smu_context *smu)
147{
148 struct amdgpu_device *adev = smu->adev;
149
150 release_firmware(adev->pm.fw);
151 adev->pm.fw = NULL;
152 adev->pm.fw_version = 0;
153}
154
155int smu_v13_0_load_microcode(struct smu_context *smu)
156{
157#if 0
158 struct amdgpu_device *adev = smu->adev;
159 const uint32_t *src;
160 const struct smc_firmware_header_v1_0 *hdr;
161 uint32_t addr_start = MP1_SRAM;
162 uint32_t i;
163 uint32_t smc_fw_size;
164 uint32_t mp1_fw_flags;
165
166 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
167 src = (const uint32_t *)(adev->pm.fw->data +
168 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
169 smc_fw_size = hdr->header.ucode_size_bytes;
170
171 for (i = 1; i < smc_fw_size/4 - 1; i++) {
172 WREG32_PCIE(addr_start, src[i]);
173 addr_start += 4;
174 }
175
176 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
177 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
178 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
179 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
180
181 for (i = 0; i < adev->usec_timeout; i++) {
182 mp1_fw_flags = RREG32_PCIE(MP1_Public |
183 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
184 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
185 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
186 break;
187 udelay(1);
188 }
189
190 if (i == adev->usec_timeout)
191 return -ETIME;
192#endif
276c03a0
EQ		 193
194 return 0;
195}
196
197int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
198{
199 struct amdgpu_device *adev = smu->adev;
200 struct amdgpu_firmware_info *ucode = NULL;
201 uint32_t size = 0, pptable_id = 0;
202 int ret = 0;
203 void *table;
204
205 /* doesn't need to load smu firmware in IOV mode */
206 if (amdgpu_sriov_vf(adev))
207 return 0;
208
209 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
210 return 0;
211
212 if (!adev->scpm_enabled)
213 return 0;
214
215 /* override pptable_id from driver parameter */
216 if (amdgpu_smu_pptable_id >= 0) {
217 pptable_id = amdgpu_smu_pptable_id;
218 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
219 } else {
220 pptable_id = smu->smu_table.boot_values.pp_table_id;
221
cbd3adae
KF		 222 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
223 pptable_id == 3667)
224 pptable_id = 36671;
225
226 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
227 pptable_id == 3688)
228 pptable_id = 36881;
276c03a0 229 /*
6fd69381
EQ		 230 * Temporary solution for SMU V13.0.0 with SCPM enabled:
231 * - use 36831 signed pptable when pp_table_id is 3683
232 * - use 36641 signed pptable when pp_table_id is 3664 or 0
233 * TODO: drop these when the pptable carried in vbios is ready.
276c03a0 234 */
6fd69381
EQ		 235 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
236 switch (pptable_id) {
237 case 0:
238 case 3664:
239 pptable_id = 36641;
240 break;
241 case 3683:
242 pptable_id = 36831;
243 break;
244 default:
245 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
246 return -EINVAL;
247 }
248 }
276c03a0
EQ		 249 }
250
251 /* "pptable_id == 0" means vbios carries the pptable. */
252 if (!pptable_id)
253 return 0;
254
255 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
256 if (ret)
257 return ret;
258
259 smu->pptable_firmware.data = table;
260 smu->pptable_firmware.size = size;
261
262 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
263 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
264 ucode->fw = &smu->pptable_firmware;
265 adev->firmware.fw_size +=
266 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
267
c05d1c40
KW		 268 return 0;
269}
270
271int smu_v13_0_check_fw_status(struct smu_context *smu)
272{
273 struct amdgpu_device *adev = smu->adev;
274 uint32_t mp1_fw_flags;
275
276 mp1_fw_flags = RREG32_PCIE(MP1_Public |
277 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
278
279 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
280 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
281 return 0;
282
283 return -EIO;
284}
285
286int smu_v13_0_check_fw_version(struct smu_context *smu)
287{
6f072a84 288 struct amdgpu_device *adev = smu->adev;
c05d1c40 289 uint32_t if_version = 0xff, smu_version = 0xff;
82890466 290 uint8_t smu_program, smu_major, smu_minor, smu_debug;
c05d1c40
KW		 291 int ret = 0;
292
293 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
294 if (ret)
295 return ret;
296
82890466
ML		 297 smu_program = (smu_version >> 24) & 0xff;
298 smu_major = (smu_version >> 16) & 0xff;
c05d1c40
KW		 299 smu_minor = (smu_version >> 8) & 0xff;
300 smu_debug = (smu_version >> 0) & 0xff;
6f072a84
ML		 301 if (smu->is_apu)
302 adev->pm.fw_version = smu_version;
c05d1c40 303
9f952378 304 switch (adev->ip_versions[MP1_HWIP][0]) {
61b396b9 305 case IP_VERSION(13, 0, 2):
c05d1c40
KW		 306 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
307 break;
276c03a0
EQ		 308 case IP_VERSION(13, 0, 0):
309 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
310 break;
113cc31d
CG		 311 case IP_VERSION(13, 0, 7):
312 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
313 break;
61b396b9
AD		 314 case IP_VERSION(13, 0, 1):
315 case IP_VERSION(13, 0, 3):
db090ff8 316 case IP_VERSION(13, 0, 8):
21cf0293
XH		 317 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
318 break;
a0219175
TH		 319 case IP_VERSION(13, 0, 4):
320 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
321 break;
068ea8bd
YZ		 322 case IP_VERSION(13, 0, 5):
323 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
324 break;
c05d1c40 325 default:
9f952378
ML		 326 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
327 adev->ip_versions[MP1_HWIP][0]);
c05d1c40
KW		 328 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
329 break;
330 }
331
0ff76b53
ML		 332 /* only for dGPU w/ SMU13*/
333 if (adev->pm.fw)
82890466
ML		 334 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
335 smu_program, smu_version, smu_major, smu_minor, smu_debug);
0ff76b53 336
c05d1c40
KW		 337 /*
338 * 1. if_version mismatch is not critical as our fw is designed
339 * to be backward compatible.
340 * 2. New fw usually brings some optimizations. But that's visible
341 * only on the paired driver.
342 * Considering above, we just leave user a warning message instead
343 * of halt driver loading.
344 */
345 if (if_version != smu->smc_driver_if_version) {
9f952378 346 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
82890466 347 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
c05d1c40 348 smu->smc_driver_if_version, if_version,
82890466 349 smu_program, smu_version, smu_major, smu_minor, smu_debug);
9f952378 350 dev_warn(adev->dev, "SMU driver if version not matched\n");
c05d1c40
KW		 351 }
352
353 return ret;
354}
355
276c03a0
EQ		 356static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
357{
358 struct amdgpu_device *adev = smu->adev;
359 uint32_t ppt_offset_bytes;
360 const struct smc_firmware_header_v2_0 *v2;
361
362 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
363
364 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
365 *size = le32_to_cpu(v2->ppt_size_bytes);
366 *table = (uint8_t *)v2 + ppt_offset_bytes;
367
368 return 0;
369}
370
c05d1c40
KW		 371static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
372 uint32_t *size, uint32_t pptable_id)
373{
374 struct amdgpu_device *adev = smu->adev;
375 const struct smc_firmware_header_v2_1 *v2_1;
376 struct smc_soft_pptable_entry *entries;
377 uint32_t pptable_count = 0;
378 int i = 0;
379
380 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
381 entries = (struct smc_soft_pptable_entry *)
382 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
383 pptable_count = le32_to_cpu(v2_1->pptable_count);
384 for (i = 0; i < pptable_count; i++) {
385 if (le32_to_cpu(entries[i].id) == pptable_id) {
386 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
387 *size = le32_to_cpu(entries[i].ppt_size_bytes);
388 break;
389 }
390 }
391
392 if (i == pptable_count)
393 return -EINVAL;
394
395 return 0;
396}
397
4a1cac25 398static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
c05d1c40
KW		 399{
400 struct amdgpu_device *adev = smu->adev;
c05d1c40
KW		 401 uint16_t atom_table_size;
402 uint8_t frev, crev;
4a1cac25 403 int ret, index;
c05d1c40 404
4a1cac25
KW		 405 dev_info(adev->dev, "use vbios provided pptable\n");
406 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
407 powerplayinfo);
f1adbe03 408
4a1cac25
KW		 409 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
410 (uint8_t **)table);
411 if (ret)
412 return ret;
413
414 if (size)
415 *size = atom_table_size;
416
417 return 0;
418}
419
420static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
421 uint32_t pptable_id)
422{
423 const struct smc_firmware_header_v1_0 *hdr;
424 struct amdgpu_device *adev = smu->adev;
425 uint16_t version_major, version_minor;
426 int ret;
c05d1c40
KW		 427
428 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
4a1cac25
KW		 429 if (!hdr)
430 return -EINVAL;
431
432 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
433
c05d1c40
KW		 434 version_major = le16_to_cpu(hdr->header.header_version_major);
435 version_minor = le16_to_cpu(hdr->header.header_version_minor);
4a1cac25 436 if (version_major != 2) {
c94126c4 437 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
4a1cac25
KW		 438 version_major, version_minor);
439 return -EINVAL;
440 }
441
442 switch (version_minor) {
276c03a0
EQ		 443 case 0:
444 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
445 break;
4a1cac25
KW		 446 case 1:
447 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
448 break;
449 default:
450 ret = -EINVAL;
451 break;
452 }
453
454 return ret;
455}
456
457int smu_v13_0_setup_pptable(struct smu_context *smu)
458{
459 struct amdgpu_device *adev = smu->adev;
460 uint32_t size = 0, pptable_id = 0;
461 void *table;
462 int ret = 0;
c05d1c40 463
4a1cac25
KW		 464 /* override pptable_id from driver parameter */
465 if (amdgpu_smu_pptable_id >= 0) {
466 pptable_id = amdgpu_smu_pptable_id;
467 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
c05d1c40 468 } else {
4a1cac25 469 pptable_id = smu->smu_table.boot_values.pp_table_id;
276c03a0
EQ		 470
471 /*
6fd69381
EQ		 472 * Temporary solution for SMU V13.0.0 with SCPM disabled:
473 * - use 3664 or 3683 on request
474 * - use 3664 when pptable_id is 0
475 * TODO: drop these when the pptable carried in vbios is ready.
276c03a0 476 */
6fd69381
EQ		 477 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
478 switch (pptable_id) {
479 case 0:
480 pptable_id = 3664;
481 break;
482 case 3664:
483 case 3683:
484 break;
485 default:
486 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
487 return -EINVAL;
488 }
489 }
c05d1c40
KW		 490 }
491
4a1cac25 492 /* force using vbios pptable in sriov mode */
276c03a0 493 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
4a1cac25
KW		 494 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
495 else
496 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
497
498 if (ret)
499 return ret;
500
c05d1c40
KW		 501 if (!smu->smu_table.power_play_table)
502 smu->smu_table.power_play_table = table;
503 if (!smu->smu_table.power_play_table_size)
504 smu->smu_table.power_play_table_size = size;
505
506 return 0;
507}
508
509int smu_v13_0_init_smc_tables(struct smu_context *smu)
510{
511 struct smu_table_context *smu_table = &smu->smu_table;
512 struct smu_table *tables = smu_table->tables;
513 int ret = 0;
514
515 smu_table->driver_pptable =
516 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
517 if (!smu_table->driver_pptable) {
518 ret = -ENOMEM;
519 goto err0_out;
520 }
521
522 smu_table->max_sustainable_clocks =
523 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
524 if (!smu_table->max_sustainable_clocks) {
525 ret = -ENOMEM;
526 goto err1_out;
527 }
528
529 /* Aldebaran does not support OVERDRIVE */
530 if (tables[SMU_TABLE_OVERDRIVE].size) {
531 smu_table->overdrive_table =
532 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
533 if (!smu_table->overdrive_table) {
534 ret = -ENOMEM;
535 goto err2_out;
536 }
537
538 smu_table->boot_overdrive_table =
539 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
540 if (!smu_table->boot_overdrive_table) {
541 ret = -ENOMEM;
542 goto err3_out;
543 }
544 }
545
276c03a0
EQ		 546 smu_table->combo_pptable =
547 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
548 if (!smu_table->combo_pptable) {
549 ret = -ENOMEM;
550 goto err4_out;
551 }
552
c05d1c40
KW		 553 return 0;
554
276c03a0
EQ		 555err4_out:
556 kfree(smu_table->boot_overdrive_table);
c05d1c40
KW		 557err3_out:
558 kfree(smu_table->overdrive_table);
559err2_out:
560 kfree(smu_table->max_sustainable_clocks);
561err1_out:
562 kfree(smu_table->driver_pptable);
563err0_out:
564 return ret;
565}
566
567int smu_v13_0_fini_smc_tables(struct smu_context *smu)
568{
569 struct smu_table_context *smu_table = &smu->smu_table;
570 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
571
572 kfree(smu_table->gpu_metrics_table);
276c03a0 573 kfree(smu_table->combo_pptable);
c05d1c40
KW		 574 kfree(smu_table->boot_overdrive_table);
575 kfree(smu_table->overdrive_table);
576 kfree(smu_table->max_sustainable_clocks);
577 kfree(smu_table->driver_pptable);
578 smu_table->gpu_metrics_table = NULL;
276c03a0 579 smu_table->combo_pptable = NULL;
c05d1c40
KW		 580 smu_table->boot_overdrive_table = NULL;
581 smu_table->overdrive_table = NULL;
582 smu_table->max_sustainable_clocks = NULL;
583 smu_table->driver_pptable = NULL;
584 kfree(smu_table->hardcode_pptable);
585 smu_table->hardcode_pptable = NULL;
586
edd79420 587 kfree(smu_table->ecc_table);
c05d1c40
KW		 588 kfree(smu_table->metrics_table);
589 kfree(smu_table->watermarks_table);
edd79420 590 smu_table->ecc_table = NULL;
c05d1c40
KW		 591 smu_table->metrics_table = NULL;
592 smu_table->watermarks_table = NULL;
593 smu_table->metrics_time = 0;
594
595 kfree(smu_dpm->dpm_context);
596 kfree(smu_dpm->golden_dpm_context);
597 kfree(smu_dpm->dpm_current_power_state);
598 kfree(smu_dpm->dpm_request_power_state);
599 smu_dpm->dpm_context = NULL;
600 smu_dpm->golden_dpm_context = NULL;
601 smu_dpm->dpm_context_size = 0;
602 smu_dpm->dpm_current_power_state = NULL;
603 smu_dpm->dpm_request_power_state = NULL;
604
605 return 0;
606}
607
608int smu_v13_0_init_power(struct smu_context *smu)
609{
610 struct smu_power_context *smu_power = &smu->smu_power;
611
612 if (smu_power->power_context || smu_power->power_context_size != 0)
613 return -EINVAL;
614
615 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
616 GFP_KERNEL);
617 if (!smu_power->power_context)
618 return -ENOMEM;
619 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
620
621 return 0;
622}
623
624int smu_v13_0_fini_power(struct smu_context *smu)
625{
626 struct smu_power_context *smu_power = &smu->smu_power;
627
628 if (!smu_power->power_context || smu_power->power_context_size == 0)
629 return -EINVAL;
630
631 kfree(smu_power->power_context);
632 smu_power->power_context = NULL;
633 smu_power->power_context_size = 0;
634
635 return 0;
636}
637
c05d1c40
KW		 638int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
639{
640 int ret, index;
641 uint16_t size;
642 uint8_t frev, crev;
643 struct atom_common_table_header *header;
3d01361c 644 struct atom_firmware_info_v3_4 *v_3_4;
c05d1c40
KW		 645 struct atom_firmware_info_v3_3 *v_3_3;
646 struct atom_firmware_info_v3_1 *v_3_1;
593a54f1
EQ		 647 struct atom_smu_info_v3_6 *smu_info_v3_6;
648 struct atom_smu_info_v4_0 *smu_info_v4_0;
c05d1c40
KW		 649
650 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
651 firmwareinfo);
652
653 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
654 (uint8_t **)&header);
655 if (ret)
656 return ret;
657
658 if (header->format_revision != 3) {
659 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
660 return -EINVAL;
661 }
662
663 switch (header->content_revision) {
664 case 0:
665 case 1:
666 case 2:
667 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
668 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
669 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
670 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
671 smu->smu_table.boot_values.socclk = 0;
672 smu->smu_table.boot_values.dcefclk = 0;
673 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
674 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
675 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
676 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
677 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
678 smu->smu_table.boot_values.pp_table_id = 0;
679 break;
680 case 3:
c05d1c40
KW		 681 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
682 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
683 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
684 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
685 smu->smu_table.boot_values.socclk = 0;
686 smu->smu_table.boot_values.dcefclk = 0;
687 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
688 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
689 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
690 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
691 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
692 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
e5a83213 693 break;
3d01361c
FX		 694 case 4:
695 default:
696 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
697 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
698 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
699 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
700 smu->smu_table.boot_values.socclk = 0;
701 smu->smu_table.boot_values.dcefclk = 0;
702 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
703 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
704 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
705 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
706 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
707 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
e5a83213 708 break;
c05d1c40
KW		 709 }
710
711 smu->smu_table.boot_values.format_revision = header->format_revision;
712 smu->smu_table.boot_values.content_revision = header->content_revision;
713
593a54f1
EQ		 714 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
715 smu_info);
716 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
717 (uint8_t **)&header)) {
276c03a0 718
593a54f1
EQ		 719 if ((frev == 3) && (crev == 6)) {
720 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
721
722 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
723 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
724 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
725 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
726 } else if ((frev == 4) && (crev == 0)) {
727 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
728
729 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
730 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
731 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
732 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
733 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
734 } else {
735 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
736 (uint32_t)frev, (uint32_t)crev);
737 }
738 }
c05d1c40
KW		 739
740 return 0;
741}
742
f1adbe03 743
c05d1c40
KW		 744int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
745{
746 struct smu_table_context *smu_table = &smu->smu_table;
747 struct smu_table *memory_pool = &smu_table->memory_pool;
748 int ret = 0;
749 uint64_t address;
750 uint32_t address_low, address_high;
751
752 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
753 return ret;
754
c05d1c40
KW		 755 address = memory_pool->mc_address;
756 address_high = (uint32_t)upper_32_bits(address);
757 address_low = (uint32_t)lower_32_bits(address);
758
759 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
760 address_high, NULL);
761 if (ret)
762 return ret;
763 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
764 address_low, NULL);
765 if (ret)
766 return ret;
767 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
768 (uint32_t)memory_pool->size, NULL);
769 if (ret)
770 return ret;
771
772 return ret;
773}
774
775int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
776{
777 int ret;
778
779 ret = smu_cmn_send_smc_msg_with_param(smu,
780 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
781 if (ret)
782 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
783
784 return ret;
785}
786
787int smu_v13_0_set_driver_table_location(struct smu_context *smu)
788{
789 struct smu_table *driver_table = &smu->smu_table.driver_table;
790 int ret = 0;
791
792 if (driver_table->mc_address) {
793 ret = smu_cmn_send_smc_msg_with_param(smu,
794 SMU_MSG_SetDriverDramAddrHigh,
795 upper_32_bits(driver_table->mc_address),
796 NULL);
797 if (!ret)
798 ret = smu_cmn_send_smc_msg_with_param(smu,
799 SMU_MSG_SetDriverDramAddrLow,
800 lower_32_bits(driver_table->mc_address),
801 NULL);
802 }
803
804 return ret;
805}
806
807int smu_v13_0_set_tool_table_location(struct smu_context *smu)
808{
809 int ret = 0;
810 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
811
812 if (tool_table->mc_address) {
813 ret = smu_cmn_send_smc_msg_with_param(smu,
814 SMU_MSG_SetToolsDramAddrHigh,
815 upper_32_bits(tool_table->mc_address),
816 NULL);
817 if (!ret)
818 ret = smu_cmn_send_smc_msg_with_param(smu,
819 SMU_MSG_SetToolsDramAddrLow,
820 lower_32_bits(tool_table->mc_address),
821 NULL);
822 }
823
824 return ret;
825}
826
827int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
828{
829 int ret = 0;
830
831 if (!smu->pm_enabled)
832 return ret;
833
834 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
835
836 return ret;
837}
838
c05d1c40
KW		 839int smu_v13_0_set_allowed_mask(struct smu_context *smu)
840{
841 struct smu_feature *feature = &smu->smu_feature;
842 int ret = 0;
843 uint32_t feature_mask[2];
844
1f2cf08a
EQ		 845 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
846 feature->feature_num < 64)
847 return -EINVAL;
c05d1c40
KW		 848
849 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
850
851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
852 feature_mask[1], NULL);
853 if (ret)
1f2cf08a 854 return ret;
c05d1c40 855
1f2cf08a
EQ		 856 return smu_cmn_send_smc_msg_with_param(smu,
857 SMU_MSG_SetAllowedFeaturesMaskLow,
858 feature_mask[0],
859 NULL);
c05d1c40
KW		 860}
861
21cf0293
XH		 862int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
863{
864 int ret = 0;
865 struct amdgpu_device *adev = smu->adev;
866
1d789535 867 switch (adev->ip_versions[MP1_HWIP][0]) {
276c03a0 868 case IP_VERSION(13, 0, 0):
61b396b9
AD		 869 case IP_VERSION(13, 0, 1):
870 case IP_VERSION(13, 0, 3):
33ef11cd 871 case IP_VERSION(13, 0, 4):
111aeed2 872 case IP_VERSION(13, 0, 5):
b4e7b0e8 873 case IP_VERSION(13, 0, 7):
d7709eb6 874 case IP_VERSION(13, 0, 8):
21cf0293
XH		 875 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
876 return 0;
877 if (enable)
878 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
879 else
880 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
881 break;
882 default:
883 break;
884 }
885
886 return ret;
887}
888
c05d1c40
KW		 889int smu_v13_0_system_features_control(struct smu_context *smu,
890 bool en)
891{
3c6591e9
EQ		 892 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
893 SMU_MSG_DisableAllSmuFeatures), NULL);
c05d1c40
KW		 894}
895
896int smu_v13_0_notify_display_change(struct smu_context *smu)
897{
898 int ret = 0;
899
900 if (!smu->pm_enabled)
901 return ret;
902
903 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
904 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
905 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
906
907 return ret;
908}
909
910 static int
911smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
912 enum smu_clk_type clock_select)
913{
914 int ret = 0;
915 int clk_id;
916
917 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
918 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
919 return 0;
920
921 clk_id = smu_cmn_to_asic_specific_index(smu,
922 CMN2ASIC_MAPPING_CLK,
923 clock_select);
924 if (clk_id < 0)
925 return -EINVAL;
926
927 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
928 clk_id << 16, clock);
929 if (ret) {
930 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
931 return ret;
932 }
933
934 if (*clock != 0)
935 return 0;
936
937 /* if DC limit is zero, return AC limit */
938 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
939 clk_id << 16, clock);
940 if (ret) {
941 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
942 return ret;
943 }
944
945 return 0;
946}
947
948int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
949{
950 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
951 smu->smu_table.max_sustainable_clocks;
952 int ret = 0;
953
954 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
955 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
956 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
957 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
958 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
959 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
960
961 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
962 ret = smu_v13_0_get_max_sustainable_clock(smu,
963 &(max_sustainable_clocks->uclock),
964 SMU_UCLK);
965 if (ret) {
966 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
967 __func__);
968 return ret;
969 }
970 }
971
972 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
973 ret = smu_v13_0_get_max_sustainable_clock(smu,
974 &(max_sustainable_clocks->soc_clock),
975 SMU_SOCCLK);
976 if (ret) {
977 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
978 __func__);
979 return ret;
980 }
981 }
982
983 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
984 ret = smu_v13_0_get_max_sustainable_clock(smu,
985 &(max_sustainable_clocks->dcef_clock),
986 SMU_DCEFCLK);
987 if (ret) {
988 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
989 __func__);
990 return ret;
991 }
992
993 ret = smu_v13_0_get_max_sustainable_clock(smu,
994 &(max_sustainable_clocks->display_clock),
995 SMU_DISPCLK);
996 if (ret) {
997 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
998 __func__);
999 return ret;
1000 }
1001 ret = smu_v13_0_get_max_sustainable_clock(smu,
1002 &(max_sustainable_clocks->phy_clock),
1003 SMU_PHYCLK);
1004 if (ret) {
1005 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
1006 __func__);
1007 return ret;
1008 }
1009 ret = smu_v13_0_get_max_sustainable_clock(smu,
1010 &(max_sustainable_clocks->pixel_clock),
1011 SMU_PIXCLK);
1012 if (ret) {
1013 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
1014 __func__);
1015 return ret;
1016 }
1017 }
1018
1019 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1020 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1021
1022 return 0;
1023}
1024
1025int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1026 uint32_t *power_limit)
1027{
1028 int power_src;
1029 int ret = 0;
1030
1031 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1032 return -EINVAL;
1033
1034 power_src = smu_cmn_to_asic_specific_index(smu,
1035 CMN2ASIC_MAPPING_PWR,
1036 smu->adev->pm.ac_power ?
1037 SMU_POWER_SOURCE_AC :
1038 SMU_POWER_SOURCE_DC);
1039 if (power_src < 0)
1040 return -EINVAL;
1041
1042 ret = smu_cmn_send_smc_msg_with_param(smu,
1043 SMU_MSG_GetPptLimit,
1044 power_src << 16,
1045 power_limit);
1046 if (ret)
1047 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1048
1049 return ret;
1050}
1051
2d1ac1cb
DP		 1052int smu_v13_0_set_power_limit(struct smu_context *smu,
1053 enum smu_ppt_limit_type limit_type,
1054 uint32_t limit)
c05d1c40
KW		 1055{
1056 int ret = 0;
1057
2d1ac1cb
DP		 1058 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1059 return -EINVAL;
1060
c05d1c40
KW		 1061 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1062 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1063 return -EOPNOTSUPP;
1064 }
1065
2d1ac1cb 1066 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
c05d1c40
KW		 1067 if (ret) {
1068 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1069 return ret;
1070 }
1071
2d1ac1cb 1072 smu->current_power_limit = limit;
c05d1c40
KW		 1073
1074 return 0;
1075}
1076
1077int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1078{
bb50bba9 1079 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
c05d1c40
KW		 1080}
1081
1082int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1083{
1084 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1085}
1086
1087static uint16_t convert_to_vddc(uint8_t vid)
1088{
1089 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1090}
1091
1092int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1093{
1094 struct amdgpu_device *adev = smu->adev;
1095 uint32_t vdd = 0, val_vid = 0;
1096
1097 if (!value)
1098 return -EINVAL;
1099 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1100 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1101 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1102
1103 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1104
1105 *value = vdd;
1106
1107 return 0;
1108
1109}
1110
1111int
1112smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1113 struct pp_display_clock_request
1114 *clock_req)
1115{
1116 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1117 int ret = 0;
1118 enum smu_clk_type clk_select = 0;
1119 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1120
1121 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1122 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1123 switch (clk_type) {
1124 case amd_pp_dcef_clock:
1125 clk_select = SMU_DCEFCLK;
1126 break;
1127 case amd_pp_disp_clock:
1128 clk_select = SMU_DISPCLK;
1129 break;
1130 case amd_pp_pixel_clock:
1131 clk_select = SMU_PIXCLK;
1132 break;
1133 case amd_pp_phy_clock:
1134 clk_select = SMU_PHYCLK;
1135 break;
1136 case amd_pp_mem_clock:
1137 clk_select = SMU_UCLK;
1138 break;
1139 default:
1140 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1141 ret = -EINVAL;
1142 break;
1143 }
1144
1145 if (ret)
1146 goto failed;
1147
1148 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1149 return 0;
1150
1151 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1152
1153 if(clk_select == SMU_UCLK)
1154 smu->hard_min_uclk_req_from_dal = clk_freq;
1155 }
1156
1157failed:
1158 return ret;
1159}
1160
1161uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1162{
1163 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1164 return AMD_FAN_CTRL_MANUAL;
1165 else
1166 return AMD_FAN_CTRL_AUTO;
1167}
1168
1169 static int
1170smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1171{
1172 int ret = 0;
1173
1174 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1175 return 0;
1176
1177 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1178 if (ret)
1179 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1180 __func__, (auto_fan_control ? "Start" : "Stop"));
1181
1182 return ret;
1183}
1184
1185 static int
1186smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1187{
1188 struct amdgpu_device *adev = smu->adev;
1189
1190 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1191 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1192 CG_FDO_CTRL2, TMIN, 0));
1193 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1194 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1195 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1196
1197 return 0;
1198}
1199
276c03a0
EQ		 1200int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1201 uint32_t speed)
c05d1c40
KW		 1202{
1203 struct amdgpu_device *adev = smu->adev;
1204 uint32_t duty100, duty;
1205 uint64_t tmp64;
1206
276c03a0 1207 speed = MIN(speed, 255);
c05d1c40
KW		 1208
1209 if (smu_v13_0_auto_fan_control(smu, 0))
1210 return -EINVAL;
1211
1212 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1213 CG_FDO_CTRL1, FMAX_DUTY100);
1214 if (!duty100)
1215 return -EINVAL;
1216
1217 tmp64 = (uint64_t)speed * duty100;
276c03a0 1218 do_div(tmp64, 255);
c05d1c40
KW		 1219 duty = (uint32_t)tmp64;
1220
1221 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1222 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1223 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1224
1225 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1226}
1227
1228 int
1229smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1230 uint32_t mode)
1231{
1232 int ret = 0;
1233
1234 switch (mode) {
1235 case AMD_FAN_CTRL_NONE:
276c03a0 1236 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
c05d1c40
KW		 1237 break;
1238 case AMD_FAN_CTRL_MANUAL:
1239 ret = smu_v13_0_auto_fan_control(smu, 0);
1240 break;
1241 case AMD_FAN_CTRL_AUTO:
1242 ret = smu_v13_0_auto_fan_control(smu, 1);
1243 break;
1244 default:
1245 break;
1246 }
1247
1248 if (ret) {
1249 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1250 return -EINVAL;
1251 }
1252
1253 return ret;
1254}
1255
1256int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1257 uint32_t speed)
1258{
1259 struct amdgpu_device *adev = smu->adev;
c05d1c40 1260 uint32_t tach_period, crystal_clock_freq;
276c03a0 1261 int ret;
c05d1c40
KW		 1262
1263 if (!speed)
1264 return -EINVAL;
1265
1266 ret = smu_v13_0_auto_fan_control(smu, 0);
1267 if (ret)
1268 return ret;
1269
1270 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1271 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1272 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1273 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1274 CG_TACH_CTRL, TARGET_PERIOD,
1275 tach_period));
1276
276c03a0 1277 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
c05d1c40
KW		 1278}
1279
1280int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1281 uint32_t pstate)
1282{
1283 int ret = 0;
1284 ret = smu_cmn_send_smc_msg_with_param(smu,
1285 SMU_MSG_SetXgmiMode,
1286 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1287 NULL);
1288 return ret;
1289}
1290
1291static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1292 struct amdgpu_irq_src *source,
1293 unsigned tyep,
1294 enum amdgpu_interrupt_state state)
1295{
ebfc2533 1296 struct smu_context *smu = adev->powerplay.pp_handle;
c05d1c40
KW		 1297 uint32_t low, high;
1298 uint32_t val = 0;
1299
1300 switch (state) {
1301 case AMDGPU_IRQ_STATE_DISABLE:
1302 /* For THM irqs */
1303 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1304 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1305 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1306 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1307
1308 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1309
1310 /* For MP1 SW irqs */
1311 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1312 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1313 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1314
1315 break;
1316 case AMDGPU_IRQ_STATE_ENABLE:
1317 /* For THM irqs */
1318 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1319 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1320 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1321 smu->thermal_range.software_shutdown_temp);
1322
1323 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1324 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1325 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1326 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1327 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1328 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1329 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1330 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1331 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1332
1333 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1334 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1335 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1336 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1337
1338 /* For MP1 SW irqs */
1339 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1340 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1341 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1342 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1343
1344 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1345 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1346 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1347
1348 break;
1349 default:
1350 break;
1351 }
1352
1353 return 0;
1354}
1355
1356static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1357{
1358 return smu_cmn_send_smc_msg(smu,
1359 SMU_MSG_ReenableAcDcInterrupt,
1360 NULL);
1361}
1362
1363#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1364#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1365#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1366
1367static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1368 struct amdgpu_irq_src *source,
1369 struct amdgpu_iv_entry *entry)
1370{
ebfc2533 1371 struct smu_context *smu = adev->powerplay.pp_handle;
c05d1c40
KW		 1372 uint32_t client_id = entry->client_id;
1373 uint32_t src_id = entry->src_id;
1374 /*
1375 * ctxid is used to distinguish different
1376 * events for SMCToHost interrupt.
1377 */
1378 uint32_t ctxid = entry->src_data[0];
1379 uint32_t data;
1380
1381 if (client_id == SOC15_IH_CLIENTID_THM) {
1382 switch (src_id) {
1383 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1384 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1385 /*
1386 * SW CTF just occurred.
1387 * Try to do a graceful shutdown to prevent further damage.
1388 */
1389 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1390 orderly_poweroff(true);
1391 break;
1392 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1393 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1394 break;
1395 default:
1396 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1397 src_id);
1398 break;
1399 }
1400 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1401 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1402 /*
1403 * HW CTF just occurred. Shutdown to prevent further damage.
1404 */
1405 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1406 orderly_poweroff(true);
1407 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1408 if (src_id == 0xfe) {
1409 /* ACK SMUToHost interrupt */
1410 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1411 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1412 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1413
1414 switch (ctxid) {
1415 case 0x3:
1416 dev_dbg(adev->dev, "Switched to AC mode!\n");
ebfc2533 1417 smu_v13_0_ack_ac_dc_interrupt(smu);
c05d1c40
KW		 1418 break;
1419 case 0x4:
1420 dev_dbg(adev->dev, "Switched to DC mode!\n");
ebfc2533 1421 smu_v13_0_ack_ac_dc_interrupt(smu);
c05d1c40
KW		 1422 break;
1423 case 0x7:
1424 /*
1425 * Increment the throttle interrupt counter
1426 */
1427 atomic64_inc(&smu->throttle_int_counter);
1428
1429 if (!atomic_read(&adev->throttling_logging_enabled))
1430 return 0;
1431
1432 if (__ratelimit(&adev->throttling_logging_rs))
1433 schedule_work(&smu->throttling_logging_work);
1434
1435 break;
1436 }
1437 }
1438 }
1439
1440 return 0;
1441}
1442
1443static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1444{
1445 .set = smu_v13_0_set_irq_state,
1446 .process = smu_v13_0_irq_process,
1447};
1448
1449int smu_v13_0_register_irq_handler(struct smu_context *smu)
1450{
1451 struct amdgpu_device *adev = smu->adev;
1452 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1453 int ret = 0;
1454
1455 irq_src->num_types = 1;
1456 irq_src->funcs = &smu_v13_0_irq_funcs;
1457
1458 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1459 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1460 irq_src);
1461 if (ret)
1462 return ret;
1463
1464 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1465 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1466 irq_src);
1467 if (ret)
1468 return ret;
1469
1470 /* Register CTF(GPIO_19) interrupt */
1471 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1472 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1473 irq_src);
1474 if (ret)
1475 return ret;
1476
1477 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1478 0xfe,
1479 irq_src);
1480 if (ret)
1481 return ret;
1482
1483 return ret;
1484}
1485
1486int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1487 struct pp_smu_nv_clock_table *max_clocks)
1488{
1489 struct smu_table_context *table_context = &smu->smu_table;
1490 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1491
1492 if (!max_clocks || !table_context->max_sustainable_clocks)
1493 return -EINVAL;
1494
1495 sustainable_clocks = table_context->max_sustainable_clocks;
1496
1497 max_clocks->dcfClockInKhz =
1498 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1499 max_clocks->displayClockInKhz =
1500 (unsigned int) sustainable_clocks->display_clock * 1000;
1501 max_clocks->phyClockInKhz =
1502 (unsigned int) sustainable_clocks->phy_clock * 1000;
1503 max_clocks->pixelClockInKhz =
1504 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1505 max_clocks->uClockInKhz =
1506 (unsigned int) sustainable_clocks->uclock * 1000;
1507 max_clocks->socClockInKhz =
1508 (unsigned int) sustainable_clocks->soc_clock * 1000;
1509 max_clocks->dscClockInKhz = 0;
1510 max_clocks->dppClockInKhz = 0;
1511 max_clocks->fabricClockInKhz = 0;
1512
1513 return 0;
1514}
1515
1516int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1517{
1518 int ret = 0;
1519
1520 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1521
1522 return ret;
1523}
1524
c941e9fe
LL		 1525static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1526 uint64_t event_arg)
1527{
1528 int ret = 0;
1529
1530 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1531 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1532
1533 return ret;
1534}
1535
1536int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1537 uint64_t event_arg)
1538{
1539 int ret = -EINVAL;
1540
1541 switch (event) {
1542 case SMU_EVENT_RESET_COMPLETE:
1543 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1544 break;
1545 default:
1546 break;
1547 }
1548
1549 return ret;
1550}
1551
c05d1c40
KW		 1552int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1553 uint32_t *min, uint32_t *max)
1554{
1555 int ret = 0, clk_id = 0;
1556 uint32_t param = 0;
1557 uint32_t clock_limit;
1558
1559 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1560 switch (clk_type) {
1561 case SMU_MCLK:
1562 case SMU_UCLK:
1563 clock_limit = smu->smu_table.boot_values.uclk;
1564 break;
1565 case SMU_GFXCLK:
1566 case SMU_SCLK:
1567 clock_limit = smu->smu_table.boot_values.gfxclk;
1568 break;
1569 case SMU_SOCCLK:
1570 clock_limit = smu->smu_table.boot_values.socclk;
1571 break;
1572 default:
1573 clock_limit = 0;
1574 break;
1575 }
1576
1577 /* clock in Mhz unit */
1578 if (min)
1579 *min = clock_limit / 100;
1580 if (max)
1581 *max = clock_limit / 100;
1582
1583 return 0;
1584 }
1585
1586 clk_id = smu_cmn_to_asic_specific_index(smu,
1587 CMN2ASIC_MAPPING_CLK,
1588 clk_type);
1589 if (clk_id < 0) {
1590 ret = -EINVAL;
1591 goto failed;
1592 }
1593 param = (clk_id & 0xffff) << 16;
1594
1595 if (max) {
276c03a0
EQ		 1596 if (smu->adev->pm.ac_power)
1597 ret = smu_cmn_send_smc_msg_with_param(smu,
1598 SMU_MSG_GetMaxDpmFreq,
1599 param,
1600 max);
1601 else
1602 ret = smu_cmn_send_smc_msg_with_param(smu,
1603 SMU_MSG_GetDcModeMaxDpmFreq,
1604 param,
1605 max);
c05d1c40
KW		 1606 if (ret)
1607 goto failed;
1608 }
1609
1610 if (min) {
1611 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1612 if (ret)
1613 goto failed;
1614 }
1615
1616failed:
1617 return ret;
1618}
1619
1620int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1621 enum smu_clk_type clk_type,
1622 uint32_t min,
1623 uint32_t max)
1624{
c05d1c40
KW		 1625 int ret = 0, clk_id = 0;
1626 uint32_t param;
1627
1628 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1629 return 0;
1630
1631 clk_id = smu_cmn_to_asic_specific_index(smu,
1632 CMN2ASIC_MAPPING_CLK,
1633 clk_type);
1634 if (clk_id < 0)
1635 return clk_id;
1636
c05d1c40
KW		 1637 if (max > 0) {
1638 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1639 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1640 param, NULL);
1641 if (ret)
1642 goto out;
1643 }
1644
1645 if (min > 0) {
1646 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1647 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1648 param, NULL);
1649 if (ret)
1650 goto out;
1651 }
1652
1653out:
c05d1c40
KW		 1654 return ret;
1655}
1656
1657int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1658 enum smu_clk_type clk_type,
1659 uint32_t min,
1660 uint32_t max)
1661{
1662 int ret = 0, clk_id = 0;
1663 uint32_t param;
1664
1665 if (min <= 0 && max <= 0)
1666 return -EINVAL;
1667
1668 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1669 return 0;
1670
1671 clk_id = smu_cmn_to_asic_specific_index(smu,
1672 CMN2ASIC_MAPPING_CLK,
1673 clk_type);
1674 if (clk_id < 0)
1675 return clk_id;
1676
1677 if (max > 0) {
1678 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1679 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1680 param, NULL);
1681 if (ret)
1682 return ret;
1683 }
1684
1685 if (min > 0) {
1686 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1687 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1688 param, NULL);
1689 if (ret)
1690 return ret;
1691 }
1692
1693 return ret;
1694}
1695
1696int smu_v13_0_set_performance_level(struct smu_context *smu,
1697 enum amd_dpm_forced_level level)
1698{
1699 struct smu_13_0_dpm_context *dpm_context =
1700 smu->smu_dpm.dpm_context;
1701 struct smu_13_0_dpm_table *gfx_table =
1702 &dpm_context->dpm_tables.gfx_table;
1703 struct smu_13_0_dpm_table *mem_table =
1704 &dpm_context->dpm_tables.uclk_table;
1705 struct smu_13_0_dpm_table *soc_table =
1706 &dpm_context->dpm_tables.soc_table;
276c03a0
EQ		 1707 struct smu_13_0_dpm_table *vclk_table =
1708 &dpm_context->dpm_tables.vclk_table;
1709 struct smu_13_0_dpm_table *dclk_table =
1710 &dpm_context->dpm_tables.dclk_table;
1711 struct smu_13_0_dpm_table *fclk_table =
1712 &dpm_context->dpm_tables.fclk_table;
c05d1c40
KW		 1713 struct smu_umd_pstate_table *pstate_table =
1714 &smu->pstate_table;
1715 struct amdgpu_device *adev = smu->adev;
1716 uint32_t sclk_min = 0, sclk_max = 0;
1717 uint32_t mclk_min = 0, mclk_max = 0;
1718 uint32_t socclk_min = 0, socclk_max = 0;
276c03a0
EQ		 1719 uint32_t vclk_min = 0, vclk_max = 0;
1720 uint32_t dclk_min = 0, dclk_max = 0;
1721 uint32_t fclk_min = 0, fclk_max = 0;
1722 int ret = 0, i;
c05d1c40
KW		 1723
1724 switch (level) {
1725 case AMD_DPM_FORCED_LEVEL_HIGH:
1726 sclk_min = sclk_max = gfx_table->max;
1727 mclk_min = mclk_max = mem_table->max;
1728 socclk_min = socclk_max = soc_table->max;
276c03a0
EQ		 1729 vclk_min = vclk_max = vclk_table->max;
1730 dclk_min = dclk_max = dclk_table->max;
1731 fclk_min = fclk_max = fclk_table->max;
c05d1c40
KW		 1732 break;
1733 case AMD_DPM_FORCED_LEVEL_LOW:
1734 sclk_min = sclk_max = gfx_table->min;
1735 mclk_min = mclk_max = mem_table->min;
1736 socclk_min = socclk_max = soc_table->min;
276c03a0
EQ		 1737 vclk_min = vclk_max = vclk_table->min;
1738 dclk_min = dclk_max = dclk_table->min;
1739 fclk_min = fclk_max = fclk_table->min;
c05d1c40
KW		 1740 break;
1741 case AMD_DPM_FORCED_LEVEL_AUTO:
1742 sclk_min = gfx_table->min;
1743 sclk_max = gfx_table->max;
1744 mclk_min = mem_table->min;
1745 mclk_max = mem_table->max;
1746 socclk_min = soc_table->min;
1747 socclk_max = soc_table->max;
276c03a0
EQ		 1748 vclk_min = vclk_table->min;
1749 vclk_max = vclk_table->max;
1750 dclk_min = dclk_table->min;
1751 dclk_max = dclk_table->max;
1752 fclk_min = fclk_table->min;
1753 fclk_max = fclk_table->max;
c05d1c40
KW		 1754 break;
1755 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1756 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1757 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1758 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
276c03a0
EQ		 1759 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1760 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1761 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
c05d1c40
KW		 1762 break;
1763 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1764 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1765 break;
1766 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1767 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1768 break;
1769 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1770 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1771 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1772 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
276c03a0
EQ		 1773 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1774 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1775 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
c05d1c40
KW		 1776 break;
1777 case AMD_DPM_FORCED_LEVEL_MANUAL:
1778 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1779 return 0;
1780 default:
1781 dev_err(adev->dev, "Invalid performance level %d\n", level);
1782 return -EINVAL;
1783 }
1784
276c03a0
EQ		 1785 /*
1786 * Unset those settings for SMU 13.0.2. As soft limits settings
1787 * for those clock domains are not supported.
1788 */
1789 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1790 mclk_min = mclk_max = 0;
1791 socclk_min = socclk_max = 0;
1792 vclk_min = vclk_max = 0;
1793 dclk_min = dclk_max = 0;
1794 fclk_min = fclk_max = 0;
1795 }
c05d1c40
KW		 1796
1797 if (sclk_min && sclk_max) {
1798 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1799 SMU_GFXCLK,
1800 sclk_min,
1801 sclk_max);
1802 if (ret)
1803 return ret;
e943dd88
LL		 1804
1805 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1806 pstate_table->gfxclk_pstate.curr.max = sclk_max;
c05d1c40
KW		 1807 }
1808
1809 if (mclk_min && mclk_max) {
1810 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1811 SMU_MCLK,
1812 mclk_min,
1813 mclk_max);
1814 if (ret)
1815 return ret;
e943dd88
LL		 1816
1817 pstate_table->uclk_pstate.curr.min = mclk_min;
1818 pstate_table->uclk_pstate.curr.max = mclk_max;
c05d1c40
KW		 1819 }
1820
1821 if (socclk_min && socclk_max) {
1822 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1823 SMU_SOCCLK,
1824 socclk_min,
1825 socclk_max);
1826 if (ret)
1827 return ret;
e943dd88
LL		 1828
1829 pstate_table->socclk_pstate.curr.min = socclk_min;
1830 pstate_table->socclk_pstate.curr.max = socclk_max;
c05d1c40
KW		 1831 }
1832
276c03a0
EQ		 1833 if (vclk_min && vclk_max) {
1834 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1835 if (adev->vcn.harvest_config & (1 << i))
1836 continue;
1837 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1838 i ? SMU_VCLK1 : SMU_VCLK,
1839 vclk_min,
1840 vclk_max);
1841 if (ret)
1842 return ret;
1843 }
1844 pstate_table->vclk_pstate.curr.min = vclk_min;
1845 pstate_table->vclk_pstate.curr.max = vclk_max;
1846 }
1847
1848 if (dclk_min && dclk_max) {
1849 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1850 if (adev->vcn.harvest_config & (1 << i))
1851 continue;
1852 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1853 i ? SMU_DCLK1 : SMU_DCLK,
1854 dclk_min,
1855 dclk_max);
1856 if (ret)
1857 return ret;
1858 }
1859 pstate_table->dclk_pstate.curr.min = dclk_min;
1860 pstate_table->dclk_pstate.curr.max = dclk_max;
1861 }
1862
1863 if (fclk_min && fclk_max) {
1864 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1865 SMU_FCLK,
1866 fclk_min,
1867 fclk_max);
1868 if (ret)
1869 return ret;
1870
1871 pstate_table->fclk_pstate.curr.min = fclk_min;
1872 pstate_table->fclk_pstate.curr.max = fclk_max;
1873 }
1874
c05d1c40
KW		 1875 return ret;
1876}
1877
1878int smu_v13_0_set_power_source(struct smu_context *smu,
1879 enum smu_power_src_type power_src)
1880{
1881 int pwr_source;
1882
1883 pwr_source = smu_cmn_to_asic_specific_index(smu,
1884 CMN2ASIC_MAPPING_PWR,
1885 (uint32_t)power_src);
1886 if (pwr_source < 0)
1887 return -EINVAL;
1888
1889 return smu_cmn_send_smc_msg_with_param(smu,
1890 SMU_MSG_NotifyPowerSource,
1891 pwr_source,
1892 NULL);
1893}
1894
276c03a0
EQ		 1895static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1896 enum smu_clk_type clk_type,
1897 uint16_t level,
1898 uint32_t *value)
c05d1c40
KW		 1899{
1900 int ret = 0, clk_id = 0;
1901 uint32_t param;
1902
1903 if (!value)
1904 return -EINVAL;
1905
1906 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1907 return 0;
1908
1909 clk_id = smu_cmn_to_asic_specific_index(smu,
1910 CMN2ASIC_MAPPING_CLK,
1911 clk_type);
1912 if (clk_id < 0)
1913 return clk_id;
1914
1915 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1916
1917 ret = smu_cmn_send_smc_msg_with_param(smu,
1918 SMU_MSG_GetDpmFreqByIndex,
1919 param,
1920 value);
1921 if (ret)
1922 return ret;
1923
c05d1c40
KW		 1924 *value = *value & 0x7fffffff;
1925
1926 return ret;
1927}
1928
276c03a0
EQ		 1929static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1930 enum smu_clk_type clk_type,
1931 uint32_t *value)
c05d1c40 1932{
f41f8e08
LL		 1933 int ret;
1934
1935 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
2913b567
LG		 1936 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1937 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
f41f8e08
LL		 1938 ++(*value);
1939
1940 return ret;
c05d1c40
KW		 1941}
1942
276c03a0
EQ		 1943static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1944 enum smu_clk_type clk_type,
1945 bool *is_fine_grained_dpm)
1946{
1947 int ret = 0, clk_id = 0;
1948 uint32_t param;
1949 uint32_t value;
1950
1951 if (!is_fine_grained_dpm)
1952 return -EINVAL;
1953
1954 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1955 return 0;
1956
1957 clk_id = smu_cmn_to_asic_specific_index(smu,
1958 CMN2ASIC_MAPPING_CLK,
1959 clk_type);
1960 if (clk_id < 0)
1961 return clk_id;
1962
1963 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1964
1965 ret = smu_cmn_send_smc_msg_with_param(smu,
1966 SMU_MSG_GetDpmFreqByIndex,
1967 param,
1968 &value);
1969 if (ret)
1970 return ret;
1971
1972 /*
1973 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1974 * now, we un-support it
1975 */
1976 *is_fine_grained_dpm = value & 0x80000000;
1977
1978 return 0;
1979}
1980
c05d1c40
KW		 1981int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1982 enum smu_clk_type clk_type,
1983 struct smu_13_0_dpm_table *single_dpm_table)
1984{
1985 int ret = 0;
1986 uint32_t clk;
1987 int i;
1988
1989 ret = smu_v13_0_get_dpm_level_count(smu,
1990 clk_type,
1991 &single_dpm_table->count);
1992 if (ret) {
1993 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1994 return ret;
1995 }
1996
276c03a0
EQ		 1997 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
1998 ret = smu_v13_0_get_fine_grained_status(smu,
1999 clk_type,
2000 &single_dpm_table->is_fine_grained);
2001 if (ret) {
2002 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2003 return ret;
2004 }
2005 }
2006
c05d1c40
KW		 2007 for (i = 0; i < single_dpm_table->count; i++) {
2008 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2009 clk_type,
2010 i,
2011 &clk);
2012 if (ret) {
2013 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2014 return ret;
2015 }
2016
2017 single_dpm_table->dpm_levels[i].value = clk;
2018 single_dpm_table->dpm_levels[i].enabled = true;
2019
2020 if (i == 0)
2021 single_dpm_table->min = clk;
2022 else if (i == single_dpm_table->count - 1)
2023 single_dpm_table->max = clk;
2024 }
2025
2026 return 0;
2027}
2028
2029int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2030 enum smu_clk_type clk_type,
2031 uint32_t *min_value,
2032 uint32_t *max_value)
2033{
2034 uint32_t level_count = 0;
2035 int ret = 0;
2036
2037 if (!min_value && !max_value)
2038 return -EINVAL;
2039
2040 if (min_value) {
2041 /* by default, level 0 clock value as min value */
2042 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2043 clk_type,
2044 0,
2045 min_value);
2046 if (ret)
2047 return ret;
2048 }
2049
2050 if (max_value) {
2051 ret = smu_v13_0_get_dpm_level_count(smu,
2052 clk_type,
2053 &level_count);
2054 if (ret)
2055 return ret;
2056
2057 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2058 clk_type,
2059 level_count - 1,
2060 max_value);
2061 if (ret)
2062 return ret;
2063 }
2064
2065 return ret;
2066}
2067
2068int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2069{
2070 struct amdgpu_device *adev = smu->adev;
2071
2072 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2073 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2074 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2075}
2076
2077int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2078{
2079 uint32_t width_level;
2080
2081 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2082 if (width_level > LINK_WIDTH_MAX)
2083 width_level = 0;
2084
2085 return link_width[width_level];
2086}
2087
2088int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2089{
2090 struct amdgpu_device *adev = smu->adev;
2091
2092 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2093 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2094 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2095}
2096
2097int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2098{
2099 uint32_t speed_level;
2100
2101 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2102 if (speed_level > LINK_SPEED_MAX)
2103 speed_level = 0;
2104
2105 return link_speed[speed_level];
2106}
2107
276c03a0
EQ		 2108int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2109 bool enable)
2110{
2111 struct amdgpu_device *adev = smu->adev;
2112 int i, ret = 0;
2113
2114 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2115 if (adev->vcn.harvest_config & (1 << i))
2116 continue;
2117
2118 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2119 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2120 i << 16U, NULL);
2121 if (ret)
2122 return ret;
2123 }
2124
2125 return ret;
2126}
2127
2128int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2129 bool enable)
2130{
2131 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2132 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2133 0, NULL);
2134}
93661c1d
EQ		 2135
2136int smu_v13_0_run_btc(struct smu_context *smu)
2137{
2138 int res;
2139
2140 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2141 if (res)
2142 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2143
2144 return res;
2145}
a5ffbfa0
EQ		 2146
2147int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2148 bool enablement)
2149{
2150 struct amdgpu_device *adev = smu->adev;
2151 int ret = 0;
2152
2153 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2154 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2155 if (ret) {
2156 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2157 return ret;
2158 }
2159 }
2160
2161 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2162 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2163 if (ret) {
2164 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2165 return ret;
2166 }
2167 }
2168
2169 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2170 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2171 if (ret) {
2172 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2173 return ret;
2174 }
2175 }
2176
2177 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2178 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2179 if (ret) {
2180 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2181 return ret;
2182 }
2183 }
2184
2185 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2186 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2187 if (ret) {
2188 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2189 return ret;
2190 }
2191 }
2192
2193 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2194 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2195 if (ret) {
2196 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2197 return ret;
2198 }
2199 }
2200
2201 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2202 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2203 if (ret) {
2204 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2205 return ret;
2206 }
2207 }
2208
2209 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2210 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2211 if (ret) {
2212 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2213 return ret;
2214 }
2215 }
2216
2217 return ret;
2218}
914b3087
EQ		 2219
2220int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2221 bool enablement)
2222{
2223 int ret = 0;
2224
2225 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2226 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2227
2228 return ret;
2229}
7c1fa0bf
EQ		 2230
2231bool smu_v13_0_baco_is_support(struct smu_context *smu)
2232{
2233 struct smu_baco_context *smu_baco = &smu->smu_baco;
2234
2235 if (amdgpu_sriov_vf(smu->adev) ||
2236 !smu_baco->platform_support)
2237 return false;
2238
2239 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2240 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2241 return false;
2242
2243 return true;
2244}
2245
2246enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2247{
2248 struct smu_baco_context *smu_baco = &smu->smu_baco;
2249
2250 return smu_baco->state;
2251}
2252
2253int smu_v13_0_baco_set_state(struct smu_context *smu,
2254 enum smu_baco_state state)
2255{
2256 struct smu_baco_context *smu_baco = &smu->smu_baco;
2257 struct amdgpu_device *adev = smu->adev;
2258 int ret = 0;
2259
2260 if (smu_v13_0_baco_get_state(smu) == state)
2261 return 0;
2262
2263 if (state == SMU_BACO_STATE_ENTER) {
2264 ret = smu_cmn_send_smc_msg_with_param(smu,
2265 SMU_MSG_EnterBaco,
2266 0,
2267 NULL);
2268 } else {
2269 ret = smu_cmn_send_smc_msg(smu,
2270 SMU_MSG_ExitBaco,
2271 NULL);
2272 if (ret)
2273 return ret;
2274
2275 /* clear vbios scratch 6 and 7 for coming asic reinit */
2276 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2277 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2278 }
2279
2280 if (!ret)
2281 smu_baco->state = state;
2282
2283 return ret;
2284}
2285
2286int smu_v13_0_baco_enter(struct smu_context *smu)
2287{
2288 int ret = 0;
2289
2290 ret = smu_v13_0_baco_set_state(smu,
2291 SMU_BACO_STATE_ENTER);
2292 if (ret)
2293 return ret;
2294
2295 msleep(10);
2296
2297 return ret;
2298}
2299
2300int smu_v13_0_baco_exit(struct smu_context *smu)
2301{
2302 return smu_v13_0_baco_set_state(smu,
2303 SMU_BACO_STATE_EXIT);
2304}
a0219175 2305
7101ab97
HR		 2306int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2307{
2308 uint16_t index;
2309
2310 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2311 SMU_MSG_EnableGfxImu);
2312
2313 return smu_cmn_send_msg_without_waiting(smu, index, 0);
2314}
2315
a0219175
TH		 2316int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2317 enum PP_OD_DPM_TABLE_COMMAND type,
2318 long input[], uint32_t size)
2319{
2320 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2321 int ret = 0;
2322
2323 /* Only allowed in manual mode */
2324 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2325 return -EINVAL;
2326
2327 switch (type) {
2328 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2329 if (size != 2) {
2330 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2331 return -EINVAL;
2332 }
2333
2334 if (input[0] == 0) {
2335 if (input[1] < smu->gfx_default_hard_min_freq) {
2336 dev_warn(smu->adev->dev,
2337 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2338 input[1], smu->gfx_default_hard_min_freq);
2339 return -EINVAL;
2340 }
2341 smu->gfx_actual_hard_min_freq = input[1];
2342 } else if (input[0] == 1) {
2343 if (input[1] > smu->gfx_default_soft_max_freq) {
2344 dev_warn(smu->adev->dev,
2345 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2346 input[1], smu->gfx_default_soft_max_freq);
2347 return -EINVAL;
2348 }
2349 smu->gfx_actual_soft_max_freq = input[1];
2350 } else {
2351 return -EINVAL;
2352 }
2353 break;
2354 case PP_OD_RESTORE_DEFAULT_TABLE:
2355 if (size != 0) {
2356 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2357 return -EINVAL;
2358 }
2359 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2360 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2361 break;
2362 case PP_OD_COMMIT_DPM_TABLE:
2363 if (size != 0) {
2364 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2365 return -EINVAL;
2366 }
2367 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2368 dev_err(smu->adev->dev,
2369 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2370 smu->gfx_actual_hard_min_freq,
2371 smu->gfx_actual_soft_max_freq);
2372 return -EINVAL;
2373 }
2374
2375 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2376 smu->gfx_actual_hard_min_freq,
2377 NULL);
2378 if (ret) {
2379 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2380 return ret;
2381 }
2382
2383 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2384 smu->gfx_actual_soft_max_freq,
2385 NULL);
2386 if (ret) {
2387 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2388 return ret;
2389 }
2390 break;
2391 default:
2392 return -ENOSYS;
2393 }
2394
2395 return ret;
2396}
2397
2398int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2399{
2400 struct smu_table_context *smu_table = &smu->smu_table;
2401
2402 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2403 smu_table->clocks_table, false);
2404}
da1db031
AD		 2405
2406void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2407{
2408 struct amdgpu_device *adev = smu->adev;
2409
2410 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2411 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2412 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2413}
Linux 6.x block layer and io_uring tree(s)